3-5 IEEE Asian Solid-State Circuits Conference

November 12-14, 2007 / Jeju, Korea

A CMOS Linear-in-dB High-Linearity Variable-

Gain Amplifier for UWB Receivers
Chan Tat Fu and Howard Luong
Department of Electronic and Computer Engineering
Hong Kong University of Science & Technology
Clear Water Bay, Hong Kong

Abstract — This paper presents a CMOS linear-in-dB
variable gain amplifier (VGA) that provides a variable gain
range over 90dB with 3dB bandwidth greater than 400MHz at
54dB gain. The maximum output 1dB compression point is 9dBm.
Maximum gain error is +/-2dB. It consumes total 22mW with
1.8V supply, including control circuit. This VGA is fabricated in
TSMC 0.18um CMOS process and demonstrate the performance
of the proposed dB-linear VGA.
Index Terms — VGA, UWB, linear in dB characteristics
I. INTRODUCTION
Variable gain amplifier (VGA) is an indispensable building
block in many wireless communication systems. The main
function of VGA is to maximize the dynamic range of system
by maintaining a fixed voltage output for different signal
inputs.
In wireless communication systems, the amplitude of received
signal in the transceiver varies by large amount. In order to
maintain constant settling time with different input signal
amplitude in automatic gain control (AGC) loop, the gain of
VGA should have exponential gain characteristic. Due to the
square-law characteristics of CMOS technology, it is difficult
to generate an exponential gain only base on VGA itself.
Therefore, there are many different exponential control
circuits were proposed recently. [1] Operating the transistors
in sub-threshold region has exponential characteristics; but it
suffered from noise, low frequency and process variation
effects. [2] Using pseudo-exponential function for modeling
the exponential property has a limited of gain control range
with gain error +/- 0.5dB. [3]Recently, people proposed using
diode-connected pair with gain control linear-in-dB
characteristics, although linear-in-dB is achieved, however, it
has unfavorable effect that associated with poor linearity in
1dB compression point at either highest gain or lowest gain, it
definitely degrades the gain range of VGA and not suitable for
high linearity’s system application such as UWB.
In this paper, a new control idea and circuit is proposed, which
can operate at high frequency application, wide tuning range
and high linearity with linear-in-dB gain characteristic.
II. Architecture of whole VGAs for UWB
UWB specification needs VGA to have 40dB dynamic range
from 10dB to 50dB with 3dB minimum frequency response
large than 260MHz and the output 1dB compression point
requires at least 7dBm in order to have enough signal strength
to drive ADC. The noise figure should be less than 15dB.
Basically, the gain requirement is not difficult to achieve.
However, the difficulties are the high frequency response and
high 1 dB linearity. Conventional linear-in-dB VGA design [3],
shown in Fig 1, the voltage gain is:
gm Mc1, Mc 2 (W / L )Mc1,Mc 2 I Mc1,Mc 2
Av = = (1)
gm Mc 3, Mc 4 (W / L )Mc 3,Mc 4 I Mc3,Mc 4
From the Eq. (1), the highest gain is achieved as the maximum
current of IMc1,Mc2 and minimum current of IMc3,Mc4. However,
the frequency response drops a lot at the maximum gain
because of the output impedance of VGA increases which is
equal to 1/gmMc3, Mc4. Even increasing the bias current also
cannot help the frequency response because the gain relation is
current ratio. Moreover, the linearity would be suffered at the
minimum gain because of minimum current of IMc1,Mc2 and
maximum current of IMc3,Mc4. When IMc3,Mc4 is maximum, due
to the diode-connected of Mc3 and Mc4, the over-drive voltage
of Mc3 and Mc4 increases also and thus decreases the overall
output swing. Since the output swing drops, the overall
linearity definitely is degraded.
Fig 1 Conventional linear-in-dB VGA

1-4244-1360-5/07/$25.00 2007 IEEE 103

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 III. Circuit implementation

Fig 2 Block diagram of overall implementation of VGAs for UWB

Due to the limitations of frequency response and linearity, in
this paper, the newly proposed linear-in-dB control circuit
implementations and architecture VGA for UWB would try to
address the problems. Figure 2 illustrates the proposed overall
implementation of VGA chain for UWB. The first two stages
are VGA and the last stage is a constant gain amplifier. The
VGA gain can be varied from 0-17dB and the fix gain for last
stage is 17dB. So, the overall gain can be altered from Fig 4 Core of VGA in current steering implementation
10-50dB.
A. Proposed VGA Amplifier
Fig. 4 shows a core of VGA. Vin+ and Vin- are the differential
Since the linearity is dominated by the last stage of cascade
input signal and Vr and Vc are the control voltage from control
amplifiers, good linearity amplifier should be put at the last
circuit Fig. 5. Vcm is the common mode feedback voltage from
stage. Three-stage VGA [1] cascade together may not fulfill
common mode feedback circuit Fig.7.
the linearity requirement. Since the more complexity
architecture of VGA, the linearity would be degraded
A current steering circuit Fig. 4 is adopted for high linearity
compared with a simple constant gain differential amplifier as
consideration and gain of this circuit is given by
shown Fig. 3a. In order to maintain high linearity, simple
differential amplifier at the last stage is proposed to use for
Av = ( 2α − 1) g m 5, 6 Rout (2)
UWB for high linearity because of low complexity and high
voltage headroom.
where α is the current gain, gm5,6 is transconductance of M5 or
M6 and Rout is output resistance at output. In order to have
Although the reduction complexity for simple differential
linear-in-dB control gain, 2α - 1should have an exponential
amplifier already minimizes parasitic capacitance, the miller
characteristic with linear control voltage Vcont. Since both
effect exists and significantly degrades the overall frequency
transistors M1 and M2 work in saturation region, the term
response. There are some techniques like negative resistive
2α - 1 can derived
load to enhance the frequency response [4], but the drawback
of voltage headroom and not suitable for low voltage supply. g m1
Therefore, neutralization technique is a good candidate for low 2α − 1 = 2 −1 (3)
g m1 + g m 2
power and low voltage supply in order to eliminate the miller
effect. Neutralization technique implementation is depicted in
Fig 3b. It is because Vin3+ and Vout- is in phase, so by setting
Where g m = 2 Iμ n C oxW / L and Eq. (3) can be
rewritten as
the capacitance value of Cneu1 and Cneu2 equals to the gate to
drain capacitance Cgd of M21 and M22 in such a way that the I1
net coupling is zero from Vout+ to vin3+ and cancel the miller =2 −1
capacitance. I1 + I 2

VGS1 − VGS2
≅ (4)
VGS1 + VGS2 − 2V t
Where I1 and I2 are drain current of M1 and M2
t t
Put VG1 and VG2 be C +C1e and C –C1e respectively in Eq.
(4), so Eq. (4) can be derived into Eq. (5)

C + C1e t - (C - C1e t )
= (5)
Fig3a Constant gain differential amplifier 3b.Neutralization technique C + C1e t + (C - C1e t ) - 2VS - 2V t

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 where VT=KT/q Vcont Vcont
2C1e t Vr = R(I r + βI S e VT
) = C + C1e VT (9)
=
2C - 2VS - 2Vt Vcont Vcont
(10)
Vc = VDD − R(I c + βI S e VT
) = C − C1 e VT

= ke t (6) where β is the gain factor from current mirror. From Eqs. (9)
where C and C1 are constant, Vt is threshold voltage and and (10), C=RIr=VDD-RIc and C1=βIS. The constant current Ir
t=(Vcont/VT). Given the constant sum of I1+I2, common source and Ic are used to set the initial voltage, C, of Vr and Vc, As the
voltage VS can be approximately equal to constant. Since C, voltage of Vcont increases, the current rises exponentially.
C1, Vt and VS are constant, the whole term 2α - 1 can be Therefore, Vr will rise and Vc will drop respected to the
t
equated to Eq. (6), and where K is constant and e is an increase of Vcont. The advantages of proposed exponential
exponential function. The gain of core VGA becomes: circuit are low cost and low power. By using a large value of R,
Vcont the power consuming by control circuit is significantly small.
Av = ke VT
g m5,6 Rout (7) C. DC offset cancellation
Fig 6 shows a DC offset cancellation circuit [7], Output
From the equation (7), the voltage gain of current steering
voltage is sensed by RC filter and filter out the high frequency
circuit is a function of an exponential Vcont function. By
component. M15 and M16 generate a differential signal and
changing the value of Vcont linearly, the exponential voltage
convert to voltage domain in Vf1 and Vf2, and then mirror to
gain can be obtained.
the core VGA by Md3 and Md4. Therefore, the corrected signal
VGA employed with current steering circuit is suffered from
cannel the mismatched current in the core of VGA.
phase inversion problem. In order to solve this problem, the
voltage value of Vr is always large than Vc. Initially, Vcont is
very small and BJT is in off state, voltage value of Vr is a little
bit large than Vc. As Vcont increases later on, Vr will always be
large than Vc as one grows up and one goes down. In such a
way that constant phase can be maintained through the whole
gain range.

B. Proposed Exponential Control Circuit for VGA

Fig 6 DC offset cancellation circuit

D. Common mode feedback circuit

Fig 7 depicts a common-mode feedback circuit. M9 and M12
are directly connected to the output of each stage VGA to
perform average, and M10 and M11 are used for comparison
with Vref. A high-gain amplifier is designed to compare the
difference between DC output of VGA and Vref, and to feed
back the outputs Vcm to the gates of M7 and M8.

Fig5 Proposed exponential control circuit using parasitic BJT

Fig. 5 shows a proposed exponential control circuit that used
t t
to generate the terms C +C1e and C - C1e which used in Eq.
(5). Where B1 is a NPN lateral BJT. The current and voltage
B

relationship of BJT is shown in Eq. (8). Vcont is the input of

control circuit and Vc and Vr are the outputs directly connect
to the VGA core. The parasitic bjt generates an exponential
characteristic current with Vcont. The exponential current will
flow through current mirror and copy the exponential
relationship current to the branch of Vc and Vr.
⎛ Vcont ⎞
⎜⎜ ⎟⎟
⎝ VT (8)
I E = ISe ⎠ Fig 7 Common mode feedback circuit

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 Reference [3] [6] This work
Technology 0.18um CMOS 0.25um 0.18um CMOS
Supply voltage 1.8V 3.3V 1.8V
Current dissipation 3.6mA 22.6mA 12.2mA
Gain Range (dB) -48 to 36 (two 8-48.3 -30-65
stages)
3dB Bandwidth 40M@36dB gain 6MHz@48dB 400MHz@54dB
gain gain
Fig. 8. Microphotograph of VGA chip
Output 1dB -6dBm N/A 9dBm@54dB
IV. Measurement results compression point gain
8dBm@8dB gain
The proposed VGA chain with one constant gain amplifier is
fabricated in 0.18 μ m TSMC CMOS technology with the OIP3 N/A 33dBm 19dBm@54dB
gain
supply voltages 1.8V while dissipating 12.2mA current.
17dBm@8dB
Although the UWB specification for voltage gain is from
gain
10-50dB, total variable gain of this design can alter from
Noise Figure N/A 8.6@48dB 13.8dB@54dB
-30dB to 65dB while Vcont is changed 0.7V to 0.9V.
gain gain
Fig 9 displays the measured gain versus with control voltage
Vcont. The dynamic linear-in-dB gain range over 90dB with Table 1 Summary and comparison performance table
maximum error less than +/-2dB. The 3dB bandwidth, 1dB V Conclusions
compression point, OIP3, and Noise Figure at 54dB gain is High linearity, large dynamic gain range, high frequency
400MHz, 9dBm, 19dBm, and 13.8dB, respectively. High response and linear in dB gain characteristics VGA has been
linearity is achieved with 1dB compression point at least demonstrated and alleviated the difficult with linear in dB gain
8dBm for the entire gain range of UWB. The overall VGA characteristics but poor in linearity. The newly proposed
performance is shown in Table 1. Figure 8 illustrates a control circuit using parasitic BJT in current steering VGA
microphotograph of the proposed cascade two stages VGA and core is demonstrated and that high linearity feature enable to
one constant gain stage chip. use in actual implementation of wireless system, like UWB. In
this the new proposed control method, a 95dB wide dynamic
Gain vs Vcont continuous tuning range and high linearity 9dBm output VGA
80
can be obtained. A wideband VGA with 3dB large than
60 400MHz at 54dB gain is achieved while drawing 22mW from
40
1.8V supply.
Gain in dB

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Fig. 10 Measured 11P3 at 54dB gain

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