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Analysis and Design of MOSFET based

Amplier in Dierent Congurations


Tarun Singh Yadav
1
, Paritosh Vyas
1
, Sunil Kumar
2
1
M.Tech Scholar, Department of Electronics and Communication, JIIT, Noida
2
M.Tech Scholar, Department of Electronics and Communication, Mewar University, Rajasthan
Email: tsyadav@hotmail.com, paritoshvyas@hotmail.com, sunilaec123@gmail.com
Abstract: This paper presents the design of am-
plier in three dierent congurations. i.e. Com-
mon Source, Common Drain, Common Gate. It also
presents their input output characteristics,time domain
analysis and frequency response of the amplier. The
voltage gain of a particular amplier is dened by choos-
ing appropriate value of V
GS
in saturation region in
the input output voltage characteristics. After choos-
ing that value we applied an input sinusoidal signal
and check the output waveform and compare it with
the theoretical results.
I. Introduction
Amplication is an essential function in most analog
(and many digital) circuits. We amplify an analog
or digital signal because it may be too small to drive
a load, overcome the noise of a subsequent stage, or
provide logical levels to a digital circuit. Amplication
also plays a critical role in feedback systems. In this
paper, we study the low-frequency behavior of single-
stage CMOS ampliers. Analyzing both large signal
and small signal characteristics of each circuit, we de-
velop intuitive techniques and models that prove useful
in understanding more complex systems. An impor-
tant part of designers job is to use proper approxima-
tions so as to create a simple metal picture of a com-
plicated circuit. We describe in this paper three types
of amplier congurations: Common Source, Common
Gate, Common Drain.
II. Common Source Amplifier
Figure 1: Schematic of CS Amplier.
The Common-source(CS) conguration is the most
widely used of all MOSFET amplier circuits. Ob-
serve that to establish a signal ground we have con-
nected a large capacitor, C
S
, between the source and
ground. This capacitor, usually in F range, is re-
quired to provide a very small impedance at signal
frequencies of interest. In this way, the signal current
passes through C
S
to ground and thus bypasses the
resistance R
S
, Hence C
S
is called bypass capacitor. A
common source amplier realized using the circuit of
Fig. 1.
In order not to disturb dc bias current and voltages,
the signal to be amplied, shown as voltage source
V
sig
with an internal resistance R
sig
, is connected to
the gate through a large capacitor C
C1
. Similarly, the
drain is also connected to load resistance R
L
via a large
capacitor C
C2
. These two capacitances are called cou-
pling capacitors. Note that R
L
can either be a load re-
sistor, to which the amplier is required to provide its
output voltage signal, or it can be the input impedance
of another amplifying stage. The resistances R
G1
and
R
G2
are used to provide a suitable dc bias to the tran-
sistor to make it operate in saturation region.
In this paper we will use TSpice tool to compute
the voltage gain and frequency response of the CS am-
plier. Here we connected source and body of the
MOSFET together to cancel the body eect. Also,
we used the 2-m CMOS technology and Spice level-1
parameters.
The expressions for volatage gain(A
V
) and Input
Impedance R
in
of CS amplier is given by
A
V
= g
m
(r
ds
||R
D
||R
L
) (1)
R
in
= R
G1
||R
G2
(2)
Firstly, we will draw voltage transfer characteris-
tics(VTC) of the amplier. We will observe the change
output voltage with respect to the change in input
voltage. This will gives us the insight of choosing ap-
propriate value of V
GS
(operating point) so that our
transistor works in saturation region and gives us max-
imum voltage swing.
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538
Figure 2: Voltage Transfer Characteristics(VTC)
A
of
CS Amplier.
Now, we will choose V
GS
as such that our transistor
works in saturation region. Here saturation region of
the transistor lies between 1V to 1.4V. So, we choose
V
GS
= 1.3V to ensure that our transistor works in sat-
uration region and acts as an amplier.
We applied an input signal of 1mV and frequency
1KHz. Our target is to amplify this signal 10 times, i.e
Amplier Gain should be 10. We assume that power
supply V
DD
= 3.5V and maximum power consumption
P=1.5mW. We will also assume a signal source resis-
tance R
sig
= 10k, a load resistance of R
L
= 50k
and bypass and coupling capacitors of 10 F. With a
3.5V power supply, drain current of MOSFET is lim-
ited to
I
D
=
P
V
DD
=
1.5mW
3.5V
= 0.42mA (3)
The equation of I
D
in saturation is given by
I
D
=
1
2

n
C
ox
W
L
eff
V
2
ov
(1 +V
DS
) (4)

n
C
ox
= 3 10
5
(Spice Level-1 parameter)
Overdrive,V
ov
=0.3 (Typical Value)
=0.02 (Spice Level-1 parameter)
V
DS
=
V
DD
3
(For maximum Voltage Swing)
V
DS
= 1.16V
By solving equation (4) for
W
Leff
W
L
eff
=
2I
D

n
C
ox
V
2
ov
(1 +V
DS
)
(5)
After putting all the values in eq. (5) we get
W
L
eff
= 305 (6)
Here, L = 2m as per 2-m CMOS technology node.
L
eff
= L 2L
D
= 0.4m, L
D
= 0.8 (7)
Therefore,
W = 305 L
eff
= 305 0.4m = 122m (8)
Now, we will nd drain to source resistance r
ds
, which
is given by
r
ds
=
1
I
D
= 119.04K (9)
The transconductance g
m
of the amplier is given by
g
m
=

2
n
C
ox
W
L
I
D
= 2.7mS (10)
By using equation (1) we will nd the value of R
D
, as
A
V
=10 is given
A
V
= g
m
(r
ds
||R
D
||R
L
) (11)
Using all the values given, R
D
calculated as
R
D
= 4.13K (12)
Output voltage V
O
is given by
V
O
= V
DD
I
D
R
D
= 3.5 (0.42 4.13) = 1.76V (13)
Source Resistance R
S
can be written as
R
S
=
V
O

V
DD
3
I
D
= 1.42K (14)
For nding Gate voltage V
G
we apply KVL at the in-
put loop which gives
V
G
= I
D
R
S
+V
OV
+V
th
= 1.89V (15)
We use hit and trail method for nding R
G1
and R
G2
so it can satises this equation
V
G
=
R
G2
R
G1
+R
G2
V
DD
(16)
Which gives,
R
G1
= 2M (17)
R
G2
= 2.35M (18)
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538
With the help of above results we design CS ampli-
er on TSpice tool. After doing its transient analysis
we get the output signal waveform with respect to in-
put signal. Also the input signal is amplied 10 times
as shown in Fig 2. We have applied the input signal
Figure 3: Output Voltage with respect to Input
Voltage
B
of 2mV P-P and get the output votage of 20.23mV.
i. e
V
in
= 2mV (P P) (19)
V
O
= 20.23mV (P P) (20)
Therefore, Voltage Gain A
V
is
A
V
= 10.11(Practical) (21)
We get our pactical gain of 10.11 as our theoretical
gain is 10. Therefore, % error is given by
%error =
A
V
(Th.) A
V
(Pr.)
A
V
(Th.)
100 (22)
%error =
10 10.11
10
100 = 1.1 (23)
Next, to measure the midband gain A
M
and the 3-
dB frequencies f
L
and f
H
, we apply a 1-V ac voltage
at the input, perform an ac analysis simulation, and
plot the output voltage magnitude versus frequency as
shown in Fig. 4.
Figure 4: Frequency response of CS amplier with By-
pass capacitor
C
.
This corresponds to the magnitude response of CS
amplier because we chose a 1-V input signal. Ac-
cordingly, the midband gain A
M
=10.11 and the 3-dB
frequencies are f
L
= 50.92Hz and f
H
= 119.68MHz.
Therefore, bandwidth(BW) is
BW = f
H
f
L
119.68MHz 120MHz (24)
The eect of bypass capacitor C
S
is seen clearly from
the graph. Because gain is attens at very low fre-
quency, i.e 10Hz. This attening of gain is due to
capacitor C
S
and resistor R
S
. Now, we will see the
eect of unbypassed resistor R
S
, i.e C
S
=0. This will
reduce the gain of the amplier by a factor of 1 +
g
m
R
S
and increase the bandwidth(BW) of the ampli-
er. The eective reduction of gain and increment of
bandwidth(BW) is shown in Fig. 5.
A
V 1
= g
m
(r
ds
||R
D
||R
L
)
1 +g
m
R
S
(25)
1 +g
m
R
S
= 4.834 (26)
A
V 1
= g
m
(r
ds
||R
D
||R
L
)
4.834
(27)
A
V 1
Gain without bypass capacitor C
S
.
Figure 5: Frequency response of CS amplier without
Bypass capacitor
D
.
The midband gain in this case is A
M
= 2.09 and
the 3-dB frequencies are f
L
= 0.29Hz and f
H
= 415.86MHz.
Therefore, bandwidth(BW) is
BW = f
H
f
L
415.86MHz 416MHz (28)
So, we can see clearly that the bandwidth is increased
by three fold and gain is reduced by a factor of 4.8.
Therefore, the source degeneration resistor R
S
pro-
vides negative feedback, which allows us to trade o
gain for wider bandwidth.
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538
III. Common Drain Amplifier
A common drain amplier, also known as a source
follower, is one of three basic single-stage eld eect
transistor (FET) amplier topologies, typically used as
a voltage buer. In this circuit the gate terminal of the
transistor serves as the input, the source is the output,
and the drain is common to both (input and output),
hence its name. In addition, this circuit is used to
transform impedances. For example, the Thevenin re-
sistance of a combination of a voltage follower driven
by a voltage source with high Thevenin resistance is
reduced to only the output resistance of the voltage
follower, a small resistance. That resistance reduction
makes the combination a more ideal voltage source.
Conversely, a voltage follower inserted between a driv-
ing stage and a high load (ie a low resistance) presents
an innite resistance (low load) to the driving stage, an
advantage in coupling a voltage signal to a large load.
A common drain amplier realized using the circuit of
Fig. 6.
Figure 6: Schematic of CD Amplier.
In order not to disturb dc bias current and voltages,
the signal to be amplied, shown as voltage source
V
sig
with an internal resistance R
sig
, is connected to
the gate through a large capacitor C
1
. Similarly, the
source is also connected to load resistance R
L
via a
large capacitor C
2
. These two capacitances are called
coupling capacitors. Note that R
L
can either be a
load resistor, to which the amplier is required to pro-
vide its output voltage signal, or it can be the input
impedance of another amplifying stage. The resis-
tances R
1
and R
2
are used to provide a suitable dc
bias to the transistor to make it operate in saturation
region.
In this paper we will use TSpice tool to compute
the voltage gain and frequency response of the CD
amplier. Here we connected source and body of the
MOSFET together to cancel the body eect. Also, we
used the 2-m CMOS technology and Spice level-1 pa-
rameters.
The expressions for volatage gain(A
V
) and Input
Impedance R
in
of CD amplier is given by
A
V
=
g
m
(r
ds
||R
L
||R
S
)
1 +g
m
(r
ds
||R
L
||R
S
)
(29)
R
in
= R
1
||R
2
(30)
Firstly, we will draw voltage transfer characteris-
tics(VTC) of the amplier. We will observe the change
output voltage with respect to the change in input
voltage. This will gives us the insight of choosing ap-
propriate value of V
GS
(operating point) so that our
transistor works in saturation region and gives us max-
imum voltage swing.
Figure 7: Voltage Transfer Characteristics(VTC)
E
of
CD Amplier.
Now, we will choose V
GS
as such that our transistor
works in saturation region. Here saturation region of
the transistor lies between 1V to 2.9V. So, we choose
V
GS
= 1.5V to ensure that our transistor works in sat-
uration region and acts as an amplier.
We applied an input signal of 1mV and frequency
1KHz. This is a CD amplier or Source follower, i.e
Amplier Gain should be approximately 1. We assume
that power supply V
DD
= 3.5V and maximum power
consumption P=1.5mW. We will also assume a signal
source resistance R
sig
= 10k, a load resistance of
R
L
= 50k and bypass and coupling capacitors of
10 F. With a 3.5V power supply, drain current of
MOSFET is limited to
I
D
=
P
V
DD
=
1.5mW
3.5V
= 0.42mA (31)
The equation of I
D
in saturation is given by
I
D
=
1
2

n
C
ox
W
L
eff
V
2
ov
(1 +V
DS
) (32)

n
C
ox
= 3 10
5
(Spice Level-1 parameter)
Overdrive,V
ov
=0.3 (Typical Value)
=0.02 (Spice Level-1 parameter)
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538
V
DS
=
V
DD
3
(For maximum Voltage Swing)
V
DS
= 1.16V
By solving equation (32) for
W
Leff
W
L
eff
=
2I
D

n
C
ox
V
2
ov
(1 +V
DS
)
(33)
After putting all the values in eq. (33) we get
W
L
eff
= 305 (34)
Here, L = 2m as per 2-m CMOS technology node.
L
eff
= L 2L
D
= 0.4m, L
D
= 0.8 (35)
Therefore,
W = 305 L
eff
= 305 0.4m = 122m (36)
Now, we will nd drain to source resistance r
ds
, which
is given by
r
ds
=
1
I
D
= 119.04K (37)
The transconductance g
m
of the amplier is given by
g
m
=

2
n
C
ox
W
L
I
D
= 2.7mS (38)
By using equation (29) we will nd the value of R
S
,
as A
V
=1
A
V
=
g
m
(r
ds
||R
L
||R
S
)
1 +g
m
(r
ds
||R
L
||R
S
)
(39)
Using all the values given, R
S
calculated as
R
S
5K (40)
For nding Gate voltage V
G
we apply KVL at the in-
put loop which gives
V
G
= I
D
R
S
+V
OV
+V
th
= 2.8V (41)
We use hit and trail method for nding R
G1
and R
G2
so it can satises this equation
V
G
=
R
G2
R
G1
+R
G2
V
DD
(42)
Which gives,
R
G1
= 2M (43)
R
G2
= 2.6M (44)
With the help of above results we design CD ampli-
er on TSpice tool. After doing its transient analysis
we get the output signal waveform with respect to in-
put signal as shown in Fig 8.
Figure 8: Output Voltage with respect to Input
Voltage
F
We have applied the input signal of 2mV P-P and
get the output votage of 20.23mV.
i. e
V
in
= 2mV (P P) (45)
V
O
= 1.57mV (P P) (46)
Therefore, Voltage Gain A
V
is
A
V
= 0.785(Practical) (47)
We get our pactical gain of 0.785 as our theoretical
gain is 1. Therefore, % error is given by
%error =
A
V
(Th.) A
V
(Pr.)
A
V
(Th.)
100 (48)
%error =
1 0.785
1
100 = 21.5 (49)
Next, to measure the midband gain A
M
and the 3-
dB frequencies f
L
and f
H
, we apply a 1-V ac voltage
at the input, perform an ac analysis simulation, and
plot the output voltage magnitude versus frequency as
shown in Fig. 9.
Figure 9: Frequency response of CD amplier
G
.
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538
This corresponds to the magnitude response of CD
amplier because we chose a 1-V input signal. Accord-
ingly, the midband gain A
M
=0.78 and the 3-dB fre-
quencies are f
L
= 0.32Hz and f
H
= 1.27GHz. There-
fore, bandwidth(BW) is
BW = f
H
f
L
1.27GHz (50)
IV. Common Gate Amplifier
A Common-Gate Amplier typically used as a cur-
rent buer or voltage amplier. In this circuit the
source terminal of the transistor serves as the input,
the drain is the output and the gate is common to
both, hence its name. It is useful in, for example,
CMOS RF receivers, especially when operating near
the frequency limitations of the FETs, it is desirable
because of the ease of impedance matching and po-
tentially has lower noise. A common gate amplier
realized using the circuit of Fig. 10.
Figure 10: Schematic of CG Amplier.
In order not to disturb dc bias current and voltages,
the signal to be amplied, shown as voltage source
V
i
n is connected to the source through a large capac-
itor C
3
. Similarly, the drain is also connected to load
resistance R
L
via a large capacitor C
2
. These two ca-
pacitances are called coupling capacitors. Note that
R
L
can either be a load resistor, to which the ampli-
er is required to provide its output voltage signal, or
it can be the input impedance of another amplifying
stage. The resistances R
1
and R
2
are used to provide
a suitable dc bias to the transistor to make it operate
in saturation region.
In this paper we will use TSpice tool to compute
the voltage gain and frequency response of the CG
amplier. Here we connected source and body of the
MOSFET together to cancel the body eect. Also, we
used the 2-m CMOS technology and Spice level-1 pa-
rameters.
The expression for volatage gain(A
V
) of CG am-
plier is given by
A
V
=
(1 +g
m
r
ds
)(R
D
||R
L
)
r
ds
+ (R
D
||R
L
)
(51)
Firstly, we will draw voltage transfer characteris-
tics(VTC) of the amplier. We will observe the change
output voltage with respect to the change in input
voltage. This will gives us the insight of choosing ap-
propriate value of V
GS
(operating point) so that our
transistor works in saturation region and gives us max-
imum voltage swing.
Figure 11: Voltage Transfer Characteristics(VTC)
H
of
CG Amplier.
Now, we will choose V
in
as such that our transistor
works in saturation region. Here saturation region of
the transistor lies between 0.5V to 0.8V. So, we choose
V
in
= 0.6V to ensure that our transistor works in sat-
uration region and acts as an amplier.
We applied an input signal of 1mV and frequency
1KHz. Our target is to amplify this signal 10 times, i.e
Amplier Gain should be 10. We assume that power
supply V
DD
= 5V and maximum power consumption
P=1.5mW. We will also assume a load resistance of
R
L
= 50k is connected at the output and bypass and
coupling capacitors are of 10 F. With a 5V power
supply, drain current of MOSFET is limited to
I
D
=
P
V
DD
=
1.5mW
5V
= 0.3mA (52)
The equation of I
D
in saturation is given by
I
D
=
1
2

n
C
ox
W
L
eff
V
2
ov
(1 +V
DS
) (53)

n
C
ox
= 3 10
5
(Spice Level-1 parameter)
Overdrive,V
ov
=0.3 (Typical Value)
=0.02 (Spice Level-1 parameter)
V
DS
=
V
DD
3
(For maximum Voltage Swing)
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538
V
DS
= 1.66V
By solving equation (53) for
W
L
W
L
=
2I
D

n
C
ox
V
2
ov
(1 +V
DS
)
(54)
After putting all the values in eq. (54) we get
W
L
eff
= 215 (55)
Here, L = 2m as per 2-m CMOS technology node.
Therefore,
W = 215 L = 305 2m = 430m (56)
Now, we will nd drain to source resistance r
ds
, which
is given by
r
ds
=
1
I
D
= 166.66K (57)
The transconductance g
m
of the amplier is given by
g
m
=

2
n
C
ox
W
L
I
D
= 2mS (58)
By using equation (51) we will nd the value of
R
D
, as A
V
=10
A
V
=
(1 +g
m
r
ds
)(R
D
||R
L
)
r
ds
+ (R
D
||R
L
)
(59)
Using all the values given, R
D
calculated as
R
D
= 5.13K (60)
Output voltage V
O
is given by
V
O
= V
DD
I
D
R
D
= 5 (0.3 5.13) = 3.46V (61)
Source Resistance R
S
can be written as
R
S
=
V
O

V
DD
3
I
D
= 6K (62)
For nding Gate voltage V
G
we apply KVL at the in-
put loop which gives
V
G
= I
D
R
S
+V
OV
+V
th
= 3.1V (63)
We use hit and trail method for nding R
1
and R
2
so
it can satises this equation
V
G
=
R
2
R
1
+R
2
V
DD
(64)
Which gives,
R
1
= 3.3M (65)
R
2
= 2M (66)
With the help of above results we design CG amplier
on TSpice tool. After doing its transient analysis we
get the output signal waveform with respect to input
signal as shown in Fig 12.
Figure 12: Output Voltage with respect to Input
Voltage
I
We have applied the input signal of 2mV P-P and
get the output votage of 17.60mV P-P.
i. e
V
in
= 2mV (P P) (67)
V
O
= 17.60mV (P P) (68)
Therefore, Voltage Gain A
V
is
A
V
= 8.8(Practical) (69)
We get our pactical gain of 0.68 as our theoretical gain
is 1. Therefore, % error is given by
%error =
A
V
(Th.) A
V
(Pr.)
A
V
(Th.)
100 (70)
%error =
10 8.8
10
100 = 12 (71)
Next, to measure the midband gain A
M
and the 3-
dB frequencies f
L
and f
H
, we apply a 1-V ac voltage
at the input, perform an ac analysis simulation, and
plot the output voltage magnitude versus frequency as
shown in Fig. 13.
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538
Figure 13: Frequency response of CG amplier
J
.
This corresponds to the magnitude response of CG
amplier because we chose a 1-V input signal. Ac-
cordingly, the midband gain A
M
=8.8 and the 3-dB
frequencies are f
L
= 31.84Hz and f
H
= 946.41MHz.
Therefore, bandwidth(BW) is
BW = f
H
f
L
946.41MHz (72)
V. Conclusion
In this report, we accomplished the goal of learning
and designing of the diernt types of ampliers. i.e
common source, common drain, common gate using
T-Spice tool. We have seen their frequency response
to check in which frequency range our amplier gives
the optimal gain. We also seen the eect of dierent
biasing and feedback resistors on gain and drawn their
plots.
VI. References
[1] Design of Analog CMOS Integrated Circuits by Be-
hzad Razavi, Tata McGraw Hill Publication.
[2] Microelectronic Circuits by Adel S. Sedra & Ken-
neth C. Smith, Oxford University Press.
[3] Operation and Modeling of The MOS Transistor
by Yannis Tsividis, Oxford University Press.
[4] Analysis and Design Of Analog Integrated Circuits
by Paul R. Gray, Paul J. Hurst, Stephen H. Lewis &
Robert G. Meyer, John Wiley & Sons,INC.
[5] MOSFET Modeling For VLSI Design by Narain
Arora, World Scientic.
VII. Appendix(A)
A. T-spice code for Fig 2.
CS amplifier
M1 1 4 6 6 csamp w=122u l=2u
.model csamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rd 1 2 4.13k
Rsig 3 5 10k
Rl 7 0 50k
vdd 2 0 3.5v
vgs 4 6
R1 4 2 2Meg
R2 4 0 2.35Meg
Rs 6 0 1.42k
cci 4 3 10u
cco 1 7 10u
.dc vgs 0 5 0.01
.plot v(1,0)
B. T-spice code for Fig 3.
CS amplifier
M1 1 4 6 6 csamp w=122u l=2u
.model csamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rd 1 2 4.13k
Rsig 3 5 10k
Rl 7 0 50k
vdd 2 0 3.5v
vgs 4 6
R1 4 2 2Meg
R2 4 0 2.35Meg
Rs 6 0 1.42k
cci 4 3 10u
cco 1 7 10u
cs 6 0 10u
v1 5 0 SIN (0 1m 1k)
.tran 0.001 2m start=0
.print V(5,0)
.plot v(7,0)
C. T-spice code for Fig 4.
CS amplifier
M1 1 4 6 6 csamp w=122u l=2u
.model csamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rd 1 2 4.13k
Rsig 3 5 10k
Rl 7 0 50k
vdd 2 0 3.5v
vgs 4 6
R1 4 2 2Meg
R2 4 0 2.35Meg
Rs 6 0 1.42k
cci 4 3 10u
cco 1 7 10u
cs 6 0 10u
v1 5 0 AC 1
.ac dec 10 10m 1G
.plot v(7,0)
D. T-spice code for Fig 5.
CS amplifier
M1 1 4 6 6 csamp w=122u l=2u
.model csamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rd 1 2 4.13k
Rsig 3 5 10k
Rl 7 0 50k
vdd 2 0 3.5v
vgs 4 6
R1 4 2 2Meg
R2 4 0 2.35Meg
cci 4 3 10u
cco 1 7 10u
v1 5 0 AC 1
.ac dec 10 10m 1G
.plot v(7,0)
E. T-spice code for Fig 7.
CD amplifier
M1 1 4 2 0 cdamp w=86u l=2u
.model cdamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rs 2 0 5k
R1 4 1 2Meg
R2 4 0 2.6Meg
Rin 5 3 10k
Rl 6 0 50k
vdd 1 0 5v
c2 2 6 10u
c1 4 5 10u
vgs 4 2
.op
.dc vgs 0 5 0.1
.plot V(1,0)
F. T-spice code for Fig 8.
CD amplifier
M1 1 4 2 0 cdamp w=86u l=2u
.model cdamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rs 2 0 5k
R1 4 1 2Meg
R2 4 0 2.6Meg
Rin 5 3 10k
Rl 6 0 50k
vdd 1 0 5v
c2 2 6 10u
c1 4 5 10u
vin 3 0 SIN (0 1m 1k)
.op
.tran 0.001 5m start=0
.print V(3,0)
.plot V(6,0)
G. T-spice code for Fig 9.
CD amplifier
M1 1 4 2 0 cdamp w=86u l=2u
.model cdamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rs 2 0 5k
R1 4 1 2Meg
R2 4 0 2.6Meg
Rin 5 3 10k
Rl 6 0 50k
vdd 1 0 5v
c2 2 6 10u
c1 4 5 10u
v1 3 0 ac 1
.op
.ac dec 10 10m 10G
.plot V(6,0)
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538
H. T-spice code for Fig 11.
CG amplifier
M1 1 4 2 0 cgamp w=430u l=2u
.model cgamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rd 1 3 5.13k
Rs 2 0 6k
R1 4 3 3.3Meg
R2 4 0 2Meg
Rl 6 0 50k
vdd 3 0 5v
c1 4 0 10u
c2 1 6 10u
cin 2 7 10u
cs 2 0 10u
vin 2 0
.op
.dc vin 0 5 0.001
.plot V(1,0)
I. T-spice code for Fig 12.
CG amplifier
M1 1 4 2 0 cgamp w=430u l=2u
.model cgamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rd 1 3 5.13k
Rs 2 0 6k
R1 4 3 3.3Meg
R2 4 0 2Meg
Rl 6 0 50k
vdd 3 0 5v
c1 4 0 10u
c2 1 6 10u
cin 2 7 10u
cs 2 0 10u
vin 7 0 SIN (0 1m 1k)
.op
.tran 0.001 5m start=0
.print V(7,0)
.plot V(6,0)
J. T-spice code for Fig 13.
CG amplifier
M1 1 4 2 0 cgamp w=430u l=2u
.model cgamp nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
Rd 1 3 5.13k
Rs 2 0 6k
R1 4 3 3.3Meg
R2 4 0 2Meg
Rl 6 0 50k
vdd 3 0 5v
c1 4 0 10u
c2 1 6 10u
cin 2 7 10u
cs 2 0 10u
v1 7 0 ac 1
.op
.ac dec 10 1 100G
.plot V(6,0)
2
nd
National Conference in Intelligent Computing & Communication
Organized by Dept. of IT, GCET Greater Noida, INDIA
ISBN: 9788175157538