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W.

Kucewicz VLSICirciuit Design 1


3.0
CMOS Transitors
3.0
CMOS Transitors
W.Kucewicz VLSICirciuit Design 2
CMOS Transistor CMOS Transistor
CMOS Transistor
Cross
Cross
-
-
section of NMOS Transistor
section of NMOS Transistor
Bulk (Body)
Source Drain
Gate
p
n+
W
W
L
L
G
S D
B
G
S D
NMOS transistor symbol NMOS transistor symbol
W W width of gate width of gate
L L - - length of gate length of gate
W.Kucewicz VLSICirciuit Design 3
CMOS Transistor CMOS Transistor
CMOS Transistor
Cross
Cross
-
-
section of PMOS Transistor
section of PMOS Transistor
Bulk (Body)
Source Drain
Gate
n
p+
G
S D
B
G
S D
PMOS transistor symbol PMOS transistor symbol
W.Kucewicz VLSICirciuit Design 4
Threshold Voltage
Threshold Voltage
W.Kucewicz VLSICirciuit Design 5
CMOS Transistor CMOS
CMOS
Transistor
Transistor
Bulk
Source
Drain
Gate
p
n+
- VGS +
n+
n n channel channel
W.Kucewicz VLSICirciuit Design 6
The Threshold Voltage The Threshold Voltage
The Threshold Voltage
Bulk
Source
Drain
Gate
p
n+
- VGS +
n+
n
n
-
-
channel
channel
W.Kucewicz VLSICirciuit Design 7
The Threshold Voltage The Threshold Voltage
The Threshold Voltage
The Threshold Voltage The Threshold Voltage is function of several components: oxide thickness, is function of several components: oxide thickness,
Fermi voltage, charge of impurities trapped at the surface, dosa Fermi voltage, charge of impurities trapped at the surface, dosage of ge of
implanted ions, etc. implanted ions, etc.
V
V
T T
= V
= V
T0 T0
+
+

(
(

|
|
-
-
2
2

F F
+ V
+ V
SB SB
|
|
-
-

|
|
-
-
2
2

F F
|)
|)
where where
V V
T0 T0
is the is the threshold voltage at V threshold voltage at V
SB SB
= 0 = 0 and is mostly a and is mostly a function of the manufacturing process function of the manufacturing process

F F
= = - -
T T
ln(N ln(N
A A
/n /n
i i
) ) is the is the Fermi potential Fermi potential

T T
= kT/q = 26mV at = kT/q = 26mV at 300K is the thermal voltage; N 300K is the thermal voltage; N
A A
is the acceptor ion concentration; is the acceptor ion concentration; n n
i i

1.5x10 1.5x10
10 10
cm cm
- -3 3
at 300K is the intrinsic carrier concentration in at 300K is the intrinsic carrier concentration in pure silicon) pure silicon)

= = (2q (2q
si si
N N
A A
)/C )/C
ox ox
is the is the body body- -effect coefficient effect coefficient (impact of (impact of changes in V changes in V
SB SB
) )

si si
= = 1.053x10 1.053x10
- -10 10
F/m is the permittivity of silicon; F/m is the permittivity of silicon;
C C
ox ox
= =
ox ox
/t /t
ox ox
is the gate oxide capacitance with is the gate oxide capacitance with
ox ox
= = 3.5x10 3.5x10
- -11 11
F/m F/m
W.Kucewicz VLSICirciuit Design 8
The Body Effect The
The
Body
Body
Effect
Effect
V V
BS BS
(V) (V)
V V
T T
(V) (V)

V
V
SB SB
is the substrate
is the substrate
bias
bias
voltage (normally
voltage (normally
positive
positive
for n
for n
-
-
channel
channel
devices with
devices with
the body
the body
tied to ground)
tied to ground)

A negative bias
A negative bias on the
substrate
causes V
causes V
T T
to
to
increase
increase
from 0.45V to
from 0.45V to
0.85V
0.85V
W.Kucewicz VLSICirciuit Design 9
Characteristics
Characteristics
W.Kucewicz VLSICirciuit Design 10
Transistor in Linear Mode Transistor in Linear Mode
Transistor in Linear Mode
n+
n+
Source
Drain
Gate
p
- VGS +
VDS +
I
D
Bulk
- V(x) +
x
V
GS
> V
T
V
V
GS GS
> V
> V
T T
W.Kucewicz VLSICirciuit Design 11
Transistor in Linear Mode Transistor in Linear Mode
Transistor in Linear Mode
For long
For long
-
-
channel devices (L > 0.25 micron)
channel devices (L > 0.25 micron)
When V
When V
DS DS

V
V
GS GS

V
V
T T
I
I
D D
= k
= k
n n
W/L [(V
W/L [(V
GS GS

V
V
T T
)V
)V
DS DS

V
V
DS DS
2 2
/2]
/2]
where
where
k
k
n n
=
=

n n
C
C
ox ox
=
=

n n

ox ox
/t
/t
ox ox
= is the
= is the
process
process
transconductance
transconductance
parameter
parameter
(
(

n n
is the carrier mobility
is the carrier mobility
(m
(m
2 2
/Vsec))
/Vsec))
k
k
n n
= k
= k
n n
W/L is the
W/L is the
gain factor
gain factor
of the device
of the device
For small V
For small V
DS DS
, there is a linear dependence between V
, there is a linear dependence between V
DS DS
and I
and I
D D
, hence the name
, hence the name
resistive
resistive
or
or
linear
linear
region
region
W.Kucewicz VLSICirciuit Design 12
Transistor in Saturation Mode Transistor in Saturation Mode
Transistor in Saturation Mode
n+
n+
Source
Drain
Gate
p
- V
GS
+
+
I
D
Bulk
V
DS
> V
GS-
V
T
V
GS
- V
T
=V
DS
Pinch Pinch- -off off
W.Kucewicz VLSICirciuit Design 13
Transistor in Saturation Mode Transistor in Saturation Mode
Transistor in Saturation Mode
For long channel devices
For long channel devices
When V
When V
DS DS

V
V
GS GS

V
V
T T
I
I
D D
= k
= k
n n
/2 W/L [(V
/2 W/L [(V
GS GS

V
V
T T
)
)
2 2
]
]
since the voltage difference over the induced channel
since the voltage difference over the induced channel
(from the
(from the
pinch
pinch
-
-
off
off
point to the source) remains fixed at
point to the source) remains fixed at
V
V
GS GS

V
V
T T
However, the effective length of the conductive channel
However, the effective length of the conductive channel
is modulated by the applied V
is modulated by the applied V
DS DS
, so
, so
I
I
D D
= I
= I
D D
(1 +
(1 +

V
V
DS DS
)
)
where
where

is the
is the
channel
channel
-
-
length modulation
length modulation
(varies with the
(varies with the
inverse of the channel length)
inverse of the channel length)
W.Kucewicz VLSICirciuit Design 14
I
D
Current Parameters I
I
D D
Current Parameters
Current Parameters
For a fixed V
For a fixed V
DS DS
and V
and V
GS GS
(> V
(> V
T T
), I
), I
DS DS
is a function of
is a function of

the distance between the source and drain


the distance between the source and drain

L
L

the channel width


the channel width

W
W

the threshold voltage


the threshold voltage

V
V
T T

the thickness of the SiO


the thickness of the SiO
2 2

t
t
ox ox

the dielectric of the gate insulator (SiO


the dielectric of the gate insulator (SiO
2 2
)
)

ox ox

the carrier mobility


the carrier mobility
for for NMOS NMOS: :
n n
= 500 cm = 500 cm
2 2
/Vsec /Vsec
for for PMOS PMOS: :
p p
= 180 cm = 180 cm
2 2
/Vsec /Vsec
W.Kucewicz VLSICirciuit Design 15
Short channel
effect
Short channel
effect
W.Kucewicz VLSICirciuit Design 16
Short Channel Effects Short Channel Effects
Short Channel Effects
Behavior of short channel device mainly due to
Behavior of short channel device mainly due to
Velocity saturation
Velocity saturation
the velocity of the carriers the velocity of the carriers
saturates due to scattering saturates due to scattering
(collisions suffered by the carriers) (collisions suffered by the carriers)
- - the velocity can be express by the velocity can be express by: :
Constant Constant
velocity velocity
Constant mobility Constant mobility
(slope = (slope = ) )
For an NMOS device with L of 1
For an NMOS device with L of 1

m, only a couple of volts


m, only a couple of volts
difference between D and S are needed to reach velocity
difference between D and S are needed to reach velocity
saturation
saturation

c c

=
=

/(1+
/(1+

/
/

c c
)
)

c c

=
=

Sat Sat
=
=

c c
/2
/2
W.Kucewicz VLSICirciuit Design 17
Velocity saturation Velocity saturation
Velocity saturation
For short channel devices
For short channel devices
Linear: When V Linear: When V
DS DS
V V
GS GS
V V
T T
I
I
D D
= k(V
= k(V
DS DS
) k
) k
n n
W/L [(V
W/L [(V
GS GS

V
V
T T
)V
)V
DS DS

V
V
DS DS
2 2
/2]
/2]
where where
k(V) = 1/(1 + (V/ k(V) = 1/(1 + (V/
c c
L)) is a measure of the degree of L)) is a measure of the degree of velocity saturation velocity saturation
Saturation: When V Saturation: When V
DS DS
= V = V
DSat DSat
= = L L
c c
= = 2L 2L
Sat Sat
/ /
I
I
DSat DSat
=
=

Sat Sat
C
C
ox ox
W [V
W [V
GS GS

V
V
T T

V
V
Dsat Dsat
/2
/2
]
]
W.Kucewicz VLSICirciuit Design 18
Velocity Saturation Effect Velocity Saturation Effect
Velocity Saturation Effect
For short channel devices
For short channel devices
and large enough V
and large enough V
GS GS

V
V
T T

V
V
DSat DSat
< V
< V
GS GS

V
V
T T
so
so
the
the
device enters
device enters
saturation
saturation
before
before
V
V
DS DS
reaches V
reaches V
GS GS

V
V
T T
and
and
operates more often in
operates more often in
saturation
saturation

I
I
DSat DSat
has a
has a
linear dependence
linear dependence
in function of V
in function of V
GS GS
so a
so a
reduced amount of current is delivered for a given control
reduced amount of current is delivered for a given control
voltage
voltage
W.Kucewicz VLSICirciuit Design 19
Long Channel NMOS Long Channel
Long Channel
NMOS
NMOS
Linear Linear Saturation Saturation
I I
D D
[A] [A]
Q
u
a
d
Q
u
a
d
r
a
t
i
c
r
a
t
i
c
d
e
p
e
n
d
e
n
c
e
d
e
p
e
n
d
e
n
c
e
Cut Cut- -off off
V V
DS DS
[V] [V]
NMOS transistor, 0.25um, NMOS transistor, 0.25um, L L
d d
= 10um = 10um, W/L = 1.5, V , W/L = 1.5, V
DD DD
= 2.5V, V = 2.5V, V
T T
= 0.4V = 0.4V
W.Kucewicz VLSICirciuit Design 20
Short channel NMOS Short channel
Short channel
NMOS
NMOS
I I
D D
[ [A A] ]
L
i
n
e
a
r
L
i
n
e
a
r
d
e
p
e
n
d
e
n
c
e
d
e
p
e
n
d
e
n
c
e
V V
DS DS
[ [V V] ]
NMOS transistor, 0.25um, NMOS transistor, 0.25um, L L
d d
= 0.25um = 0.25um, W/L = 1.5, V , W/L = 1.5, V
DD DD
= 2.5V, V = 2.5V, V
T T
= 0.4V = 0.4V
W.Kucewicz VLSICirciuit Design 21
I
D
vs. V
GS
Characteristics I
I
D D
vs
vs
. V
. V
GS GS
Characteristics
Characteristics
Linear (short
Linear (short
-
-
channel)
channel)
versus quadratic (long
versus quadratic (long
-
-
channel)
channel)
dependence of
dependence of
I
I
D D
on V
on V
GS GS
in saturation
in saturation

Velocity
Velocity
saturation
saturation
causes the short
causes the short
-
-
channel
channel
device to
device to
saturate at
saturate at
substantially
substantially
smaller
smaller
values of V
values of V
DS DS
resulting in
resulting in
a substantial
a substantial
drop in
drop in
current drive
current drive
(for V (for V
DS DS
= 2.5V, = 2.5V, W/L = 1.5) W/L = 1.5)
0 0.5 1 1.5 2 2.5
V V
GS GS
[ [V V] ]
I I
D D
[m [mA A] ]
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0.0 0.0
W.Kucewicz VLSICirciuit Design 22
Short channel PMOS Short channel
Short channel
PMOS
PMOS
All polarities of all voltages and currents are reversed
All polarities of all voltages and currents are reversed
V V
DS DS
[ [V V] ]
I I
D D
[ [A A] ]
Due to the smaller
Due to the smaller
mobility, the maximum
mobility, the maximum
current is
current is
only 42%
only 42%
of
of
what is achieved by a
what is achieved by a
similar
similar
NMOS transistor.
NMOS transistor.
P PMOS transistor, 0.25um, MOS transistor, 0.25um, L L
d d
= 0.25um = 0.25um, W/L = 1.5, V , W/L = 1.5, V
DD DD
= = - -2.5V, V 2.5V, V
T T
= = - -0.4V 0.4V
W.Kucewicz VLSICirciuit Design 23
Subthreshold Conductance Subthreshold Conductance
Subthreshold Conductance

Transition from ON
Transition from ON
to OFF
to OFF
is gradual
is gradual
(decays
(decays
exponentially)
exponentially)

Current roll
Current roll
-
-
off is
off is
also
also
affected by
affected by
increase in
increase in
temperature
temperature

Has repercussions in
Has repercussions in
dynamic circuits and for
dynamic circuits and for
power
power
consumption
consumption
W.Kucewicz VLSICirciuit Design 24
MOS Models
MOS Models
W.Kucewicz VLSICirciuit Design 25
MOS transistor First Order Model MOS
MOS
transistor First
transistor First
Order Model
Order Model
The I
The I
ds ds
current SPICE caclulation is based
current SPICE caclulation is based
on 6
on 6
parameters
parameters
:
:
0.25m 0.25m MOS channel length L
0.5-40m 0.5-20m MOS channel width W
0.4 V
0.5
0.4 V
0.5
Bulk threshold parameter GAMMA ()
0.3V 0.3V Surface potential at strong inversion PHI ()
120A/V
2
300A/V
2
Transconductance coefficient KP (K
P
)
-0.4V 0.4V Theshold voltage VTO (V
TO
)
pMOS nMOS
TYPICAL VALUE 0.25m
DEFINITION PARAMETER
W.Kucewicz VLSICirciuit Design 26
MOS transistor First Order Model MOS
MOS
transistor First
transistor First
Order Model
Order Model
Long channel Long channel ( (10 10 m m) )
Measured
Simulated
Simulation results of Simulation results of nMOS nMOS transistor using transistor using model 1 model 1
The MOS model 1 works
The MOS model 1 works
fine in
fine in
micron technology
micron technology
W.Kucewicz VLSICirciuit Design 27
MOS transistor First Order Model MOS
MOS
transistor First
transistor First
Order Model
Order Model
Simulation results of Simulation results of nMOS nMOS transistor using transistor using model 1 model 1
Short channel Short channel (0. (0.25 25 m m) )
Measured
Simulated
150% error 150% error
The
The
MOS model 1
MOS model 1
is
is
far a
far a
way in submicron technology
way in submicron technology
W.Kucewicz VLSICirciuit Design 28
MOS transistor Third Order Model MOS
MOS
transistor Third
transistor Third
Order Model
Order Model
The I
The I
ds ds
current SPICE cal
current SPICE cal
c
c
ulation take into account a set
ulation take into account a set
of physical limitations in semi
of physical limitations in semi
-
-
empirical way:
empirical way:
0.07 V
-1
0.07 V
-1
Substhreshold factor NSS
0.3 V
-1
0.3 V
-1
Mobility degradation factor THETA
100Km/s 150Km/s Maximum drift velocity VMAX
0.01 V
-1
0.01 V
-1
Saturation field factor KAPPA
0.01m 0.01m Lateral diffusion into channel LD
pMOS nMOS
TYPICAL VALUE 0.25m
DEFINITION PARAMETER
W.Kucewicz VLSICirciuit Design 29
MOS transistor Third Order Model MOS
MOS
transistor Third
transistor Third
Order Model
Order Model
Simulation results of Simulation results of nMOS nMOS transistor 10x0 transistor 10x0. .25 25 m m
using using model 3 model 3
MOS level 3 includes short channel limitation effects
MOS level 3 includes short channel limitation effects
W.Kucewicz VLSICirciuit Design 30
BSIM4 Berkeley MOS Model BSIM
BSIM
4
4
Berkeley
Berkeley
MOS Model
MOS Model
B
Berkeley
S
Short-channel
I
IGFET
M
Model
20 Basic
20 Basic
parameters
parameters
60 secondary
60 secondary
parameters
parameters
2
2
20 fitting
20 fitting
parameters
parameters
W.Kucewicz VLSICirciuit Design 31
BSIM4 Berkeley MOS Model BSIM
BSIM
4
4
Berkeley
Berkeley
MOS Model
MOS Model

BSIM4 has been introduced


BSIM4 has been introduced
in
in
2000
2000

Provides
Provides
a
a
perfect
perfect
continuity between lenear
continuity between lenear
ans
ans
saturated regions
saturated regions

Model gourous
Model gourous

Model is becoming a service


Model is becoming a service
Achieve good fit with static measurements using
Achieve good fit with static measurements using
a wide set of tricks and internal arrangements
a wide set of tricks and internal arrangements
W.Kucewicz VLSICirciuit Design 32
MOS Model MOS Model
MOS Model
BSIM4 threshold
BSIM4 threshold
voltage
voltage
model
model
DIBL NULD SCE s s
Vt Vt Vt Vbs K Vbs K VTHO vth + + + + = . 2 ) ( . 1
Short
channel
effects
Vth (V)
Channel length
(m)
W.Kucewicz VLSICirciuit Design 33
MOS Model MOS Model
MOS Model
BSIM4
BSIM4
I
I
DS DS
model
model
)
L
V
(1
V
)
4.vt) (2V
V A
(1 V

eff
Leff
Weff
Ids0
eff sat
dseff
dseff
gsteff
dseff bulk
gsteff
r 0
+
+
=
TOXE
Ids
Vgs (V)
Ids (Log)
Vds (V)
W.Kucewicz VLSICirciuit Design 34
MOS transistor BSIM4 Model MOS
MOS
transistor BSIM4
transistor BSIM4
Model
Model
Simulation results of Simulation results of nMOS nMOS transistor 10x0 transistor 10x0. .12 12 m using different models m using different models
Model1 Model1 Model3 Model3 BSIM4 BSIM4
W.Kucewicz VLSICirciuit Design 35
MOS Model MOS Model
MOS Model
Poor fit
Poor fit
Width (m)
100.0
10.0
0.0
2.5
5.0 10
1.0
7.5
The MOS model is reliable within its optimized range
The MOS model is reliable within its optimized range
Good fit
Good fit
Length
(m)
W.Kucewicz VLSICirciuit Design 36
The MOS Current Source Model The
The
MOS
MOS
Current Source
Current Source
Model
Model
I I
D D
= 0 for V = 0 for V
GS GS
V V
T T
0 0
I I
D D
= k W/L [(V = k W/L [(V
GS GS
V V
T T
)V )V
min min
V V
min min
2 2
/2](1+ /2](1+ V V
DS DS
) )
for V for V
GS GS
V V
T T
0 0
with V with V
min min
= min(V = min(V
GS GS
V V
T T
, V , V
DS DS
, V , V
DSat DSat
) )

Determined by the voltages at the four terminals
Determined by the voltages at the four terminals
and
and
a set of five device parameters
a set of five device parameters
0.25 0.25 m m
W.Kucewicz VLSICirciuit Design 37
The MOS Model as a Switch The
The
MOS Model as a
MOS Model as a
Switch
Switch

Resistance inversely
Resistance inversely
proportional to W/L (doubling
proportional to W/L (doubling
W halves R
W halves R
on on
)
)

For V
For V
DD DD
>>V
>>V
T T
+V
+V
DSat DSat
/2, R
/2, R
on on
independent of V
independent of V
DD DD

Once V
Once V
DD DD
approaches V
approaches V
T T
,
,
R
R
on on
increases dramatically
increases dramatically
Modeled as a switch with
Modeled as a switch with
infinite off resistance and a
infinite off resistance and a
finite on resistance, R
finite on resistance, R
on on
W.Kucewicz VLSICirciuit Design 38
Switch Model of nMOS Transistor Switch
Switch
Model
Model
of
of
nMOS
nMOS
Transistor
Transistor
W.Kucewicz VLSICirciuit Design 39
Switch Model of nMOS Transistor Switch
Switch
Model
Model
of
of
nMOS
nMOS
Transistor
Transistor
Input Logic signal
Output Logic signal
Switch
The
The
nMOS
nMOS
drives well
drives well
O but
O but
poorly high voltage
poorly high voltage
(
(
V
V
DD DD
-
-
V
V
T T
)
)
W.Kucewicz VLSICirciuit Design 40
Switch Model of pMOS Transistor Switch
Switch
M
M
o
o
del
del
of
of
pMOS
pMOS
Transistor
Transistor
W.Kucewicz VLSICirciuit Design 41
Switch Model of pMOS Transistor Switch
Switch
Model
Model
of
of
pMOS
pMOS
Transistor
Transistor
Input Logic signal
Output Logic signal
Switch
The
The
pMOS
pMOS
drives well high voltage
drives well high voltage
but
but
poorly
poorly
zero (
zero (
V
V
T T
)
)
W.Kucewicz VLSICirciuit Design 42
MOS Capacitances
MOS Capacitances
W.Kucewicz VLSICirciuit Design 43
MOS Gate Capacitances MOS
MOS
Gate Capacitances
Gate Capacitances
Capacitance of Gate Capacitance of Gate to to Channel Channel
C
C
G G
=
=
C
C
GC GC
+
+
C
C
GS0 GS0
+
+
C
C
GD0 GD0
=
=
C
C
GC GC
+
+
2C
2C
ox ox
x
x
d d
W
W
C
C
GC GC
=
=
C
C
GCB GCB
+
+
C
C
GCS GCS+ +
C
C
GCD GCD
where where
C C
ox ox
= =
ox ox
/ /t t
ox ox
C C
GCB GCB
cap. cap. gate gate to body to body
C C
GCS GCS
cap. cap. gate gate to to source source
C C
GCD GCD
cap. cap. gate gate to to drain drain
W.Kucewicz VLSICirciuit Design 44
MOS Gate Capacitances MOS
MOS
Gate Capacitances
Gate Capacitances
Cut Cut- -off off Linear Linear Saturation Saturation
W.Kucewicz VLSICirciuit Design 45
MOS Gate Capacitances MOS
MOS
Gate Capacitances
Gate Capacitances
Cut Cut- -off off
2 C
ox
WL/3 + 2 C
ox
x
d
W
2 C
ox
WL/3 0 2 C
ox
WL/3 0 Saturation Saturation
C
ox
WL + 2 C
ox
x
d
W
C
ox
WL C
ox
WL/2 C
ox
WL/2 0 Linear Linear
C
ox
WL + 2 C
ox
x
d
W C
ox
WL 0 0 C
ox
WL Cutoff Cutoff
C C
G G
C C
GC GC
C C
GCD GCD
C C
GCS GCS
C C
GCB GCB
Operation Operation
region region
Linear Linear Saturation Saturation
W.Kucewicz VLSICirciuit Design 46
MOS Structure Capacitances MOS
MOS
Structure Capacitances
Structure Capacitances
Junction Capacitances
Junction Capacitances
C
C
diff diff
=
=
C
C
bottom bottom
+
+
C
C
side walls side walls
=
=
C
C
j j
L
L
S S
W
W
+
+
C
C
jsw jsw
(
(
2L
2L
S S
+W)
+W)
W.Kucewicz VLSICirciuit Design 47
MOS Structure Capacitances MOS
MOS
Structure Capacitances
Structure Capacitances
MOSFET capacitance model.
MOSFET capacitance model.
C
C
GS GS
=
=
C
C
GCS GCS
+
+
C
C
GS0 GS0
C
C
GD GD
=
=
C
C
GCD GCD
+
+
C
C
GD0 GD0
C
C
GB GB
=
=
C
C
GCB GCB
C
C
SB SB
=
=
C
C
Sdiff Sdiff
C
C
DB DB
=
=
C
C
Ddiff Ddiff
W.Kucewicz VLSICirciuit Design 48
MOS Structure Capacitances MOS
MOS
Structure Capacitances
Structure Capacitances
Consider an NMOS transistor with
the following parameters:
t
ox
= 6 nm, L = 0.24 m, W = 0.36 m,
L
D
= L
S
= 0.625 m, C
O
= 3 x10
10
F/m,
C
j0
= 2 x10
3
F/m
2
,
C
jsw0
= 2.75 x10
10
F/m.
Determine the zero-bias value of all
relevant capacitances.
C
C
GB GB
=
ox
LW/t
ox
=
0.5fF
0.5fF
C
C
GS GS
= C
= C
GD GD
= C
0
W =
0.1
0.1
fF
fF
C
C
SB SB
= C
= C
DB DB
= C
j0
WL
S,D
+C
jsw0
(W+2L
D,S
)=0.45fF+0.44fF=
0.89
0.89
fF
fF
0.25 0.25 m m
W.Kucewicz VLSICirciuit Design 49
MOS Source-Drain Resistance MOS
MOS
Source
Source
-
-
Drain Resistance
Drain Resistance
W.Kucewicz VLSICirciuit Design 50
Other effects
Other effects
W.Kucewicz VLSICirciuit Design 51
Other Submicron MOS Transistor
Concerns
Other Submicron
Other Submicron
MOS
MOS
Transistor
Transistor
Concerns
Concerns

Velocity saturation
Velocity saturation

Subthreshold conduction
Subthreshold conduction
Transistor is already partially conducting for voltages below V Transistor is already partially conducting for voltages below V
T T

Parasitic resistances
Parasitic resistances
- - resistances associated with the resistances associated with the source source
and drain contacts and drain contacts
W.Kucewicz VLSICirciuit Design 52
Other Submicron MOS Transistor
Concerns
Other Submicron
Other Submicron
MOS
MOS
Transistor
Transistor
Concerns
Concerns

Threshold variations
Threshold variations
- - In long In long- -channel devices, the threshold is a function of the length channel devices, the threshold is a function of the length
(for low V (for low V
DS DS
) )
- - In short In short- -channel devices, there is a drain channel devices, there is a drain- -induced threshold induced threshold
barrier lowering at the upper end of the V barrier lowering at the upper end of the V
DS DS
range (for low L) range (for low L)
W.Kucewicz VLSICirciuit Design 53
Other Submicron MOS Transistor
Concerns
Other Submicron
Other Submicron
MOS
MOS
Transistor
Transistor
Concerns
Concerns

Latch
Latch
-
-
up.
up.
The The combination of wells and substrates combination of wells and substrates results in the formation of results in the formation of
parasitic n parasitic n- -p p- -n n- -p p structures structures ( (thyristor thyristor !!) !!)
T To avoid latchup, the o avoid latchup, the resistances resistances R R
nwell nwell
and and R R
psubs psubs
should be minimized. should be minimized.
This can be achieved by providing This can be achieved by providing numerous well and substrate contacts, numerous well and substrate contacts,
placed close to the source connections of the placed close to the source connections of the NMOS/PMOS devices. NMOS/PMOS devices.
W.Kucewicz VLSICirciuit Design 54
Other Submicron MOS Transistor
Concerns
Other Submicron
Other Submicron
MOS
MOS
Transistor
Transistor
Concerns
Concerns

Hot
Hot
-
-
Carrier Effects
Carrier Effects
Cause the Cause the I I- -V V Characteristics of an Characteristics of an NMOS NMOS transistor transistor to to degrade degrade
from extensive usage from extensive usage
W.Kucewicz VLSICirciuit Design 55
Conclusions Conclusions
Conclusions
The MOS(FET) transistor is a voltage-controlled
device, where the controlling gate terminal is insulated
from the conducting channel by a SiO
2
capacitor.
Based on the value of the gate-source voltage with
respect to a threshold voltage V
T
, three operation
regions have been identified: cut-off, linear, and
saturation.
The MOS transistor, approximates a voltage-
controlled switch: when the control voltage is low, the
switch is nonconducting (open); for a high control
voltage, a conducting channel is formed, and the switch
can be considered closed. This two-state operation
matches the concepts of binary digital logic.
W.Kucewicz VLSICirciuit Design 56
Conclusions Conclusions
Conclusions
The continuing reduction of the device dimensions to
the submicron range has introduced some substantial
deviations from the traditional long-channel MOS
transistor model.
The most important one is the velocity saturation
effect, which changes the dependence of the transistor
current with respect to the controlling voltage from
quadratic to linear.
One particular effect that is gaining in importance is
the sub-threshold conduction, which causes devices to
conduct current even when the control voltage drops
below the threshold.
W.Kucewicz VLSICirciuit Design 57
Conclusions Conclusions
Conclusions
The dynamic operation of the MOS transistor is
dominated by the device capacitors. The main
contributors are the gate capacitance and the
capacitance formed by the depletion regions of the
source and drain junctions. The minimization of these
capacitances is the prime requirement in high-
performance MOS design.
The MOS transistor is expected to dominate the
digital integrated circuit scene for the next decade.
Continued scaling will lead to device sizes of
approximately 0.07 micron by the year 2010, and logic
circuits integrating more than 1 billion transistors on a
die.