Cliff Tsai , cliff.tsai@xilinx.

com, 02-81761006
Channel FAE Manager
June.2012
Xilinx Motor Solutions
Copyright 2012 Xilinx
Xilinx 28nm 7-series FPGA
Vivado and High Level Synthesis(C/C++/SystemC to RTL)
FPGA Motor Solutions
Zynq and Motor Solutions
ADI FMC cards for Xilinx Platforms
Agenda
ADI FMC cards for Xilinx Platforms
Page 2
Copyright 2012 Xilinx
Xilinx 28nm Platforms
Copyright 2012 Xilinx
Page 3
7 Series Power Efficiency Focus
from Every Angle 50% Lower Total Power
BRAM
High performance,
low power process
Transistor choice
optimization
Config
Memory
V
CCAUX
Reduced from
2.5V to 1.8V
Reducing
Static Power
5
th
gen. partial
reconfiguration
Additional
Power Saving
Features
Integrated Analog Front End
Unused BRAM
Power Savings
Out
In
Pad
-
+
V
CCO
IO Design &
User Power
Saving Modes
Reducing
I/O Power
Process
Shrink
Reducing
Dynamic Power
Optimized
Hard
Blocks
Fine grain clock and logic gating
Lower device
core voltage
-2L
Xilinx
7 Series
FPGAs
Before After
reconfiguration
Scalable Optimized Architecture Boosts Design
Productivity -Accelerating Design Creation, Debug and Simplifying Reuse
XST
ngdbuild
map
par
trce
bitgen
Coregen
EDK
SysGen
3
rd
party
Rodin
Pre-verified
IP
assembly
tool
Unified SW Architecture
AXI4 (data)
AXI4
Streaming
AXI4
AXI4 Lite
AXI4 Lite
AXI4 Lite
AXI4
AXI4 Lite
Processor
AXI
Interconnect
Block
AXI DDR3
Mem Ctrl
DMA
Timer
IntCtrl.
Flash Int.
TEMAC
AXI
Interconnect
Block
Plug & Play IP
3 party
Plug & Play Boards
Solving Next Generation Design Challenges
For All Market Segments
Agile Mixed Signal Technology
Customized Applications
Motor Control/Power Conversion Touch Control (HMI)
System Management Sensor Interface
FPGA Leadership at 28nm
Lowest Total Power FPGAs
HPL process proven 50% lower over alternative
Highest Productivity FPGAs
Unified, plug and play with extensive Ecosystem
Agile Mixed Signal (AMS) providing analog capability in all 7 series family members
Fastest cost reduction path with EasyPath-7 (Kintex-7 7K355T-7K480T, all Virtex-7 FPGAs)
Highest Performance FPGAs
Largest capacity: 2M logic cells (XC7V2000T) Largest capacity: 2M logic cells (XC7V2000T)
Largest transceiver count: 96 (XC7VX1140T)
100x better connectivity/watt: Stacked Silicon Interconnect Technology
Fastest memory interface: 1,866 Mb/s (Kintex-7 and Virtex-7 FPGAs)
Largest Block RAM capacity: 68 Mb (XC7VX1140T)
Highest DSP performance: 5,335 GMACS - symmetric mode (XC7VX980T)
Innovative Architecture Breaks the Rules
Extensible Processing Platform (Zynq-7000 EPP family)
Industrys Most Capable Programmable Offering
Vivado and High Level Synthesis
Copyright 2012 Xilinx
Page 9
Why Now?
Programmable Logic Devices
Enables Programmable
Logic
ALL Programmable Devices
Enables Programmable
Systems Integration
Page 10 Page 10
Bottlenecks are Shifting
System Integration Bottlenecks
Design and IP reuse
Integrating algorithmic and RTL level IP
Mixing DSP, embedded, connectivity, logic
Implementation Bottlenecks
Hierarchical chip planning
Multi-domain and multi-die physical optimization
Predictable design vs. timing closure
Late ECOs and rippling effect of changes
Mixing DSP, embedded, connectivity, logic
Verification of blocks and systems
Page 11 Page 11
Vivado: Accelerating Productivity up to 4X
Accelerating
Integration
IP & System IP & System--centric centric
Integration with Fast Integration with Fast
Verification Verification
up to
4X
Vivado Next Vivado Next
Generation Generation
Design System Design System
Accelerating
Implementation
Fast, Hierarchical and Fast, Hierarchical and
Deterministic Closure Deterministic Closure
Automation w/ ECO Automation w/ ECO
RTL to Bit RTL to Bit--stream with stream with
Iterative Approach Iterative Approach
1X
1X up to 4X
Page 12 Page 12
ESL Algorithm
IP-Centric Integration with Fast Verification
Processor
System
PCIe
Memory
Interface
User IP Xilinx IP 3
rd
Party IP
Display
Processing Datapath
Embedded Interconnect
Memory Interfaces
Hand-coded
VHDL
Vivado HLS
C
Design Time
(weeks)
12 1
Latency
(ms)
37 21
Memory
(RAMB18E1)
134 (16%) 10 (1%)
Memory
(RAMB36E1)
273 (65%) 138 (33%)
Registers 29686 (9%) 14263 (4%)
LUTs 28152 (18%) 24257 (16%)
IP & System IP & System--centric centric
Integration with Fast Integration with Fast
Verification Verification
IP Assembly
ESL Algorithm
IP Synthesis
IP & HW-SW
Integrator
Stds Based
IP Reuse
Fast Simulation & HW Co-Sim
ISim Vivado
R
u
n
t
i
m
e
w/ HW Co-sim
Tcl SDC
Page 13 Page 13
Package Designs into System-Level IP for Reuse
IP Packager
Source (C, RTL, IP, etc)
Simulation Models
Documentation
Example Designs
Test Bench
Vivado IP Integrator
Standardized IP-XACT
representation
Xilinx IP Xilinx IP
3 3
rd rd
Party IP Party IP
User IP User IP
Share IP within your team, project or company
3
rd
party IP delivered with a common look and feel
Reuse IP at any point in the implementation process
Source, placed, or placed and routed
Reuse in different designs
Reuse multiple times
Page 14
Vivado IP Integrator
A graphical design environment to enable rapid and accurate
connection of complex IP
Connections made at the interface level, not the individual signal level
Automatic setting and propagation of IP parameters
Automated generated of RTL
Page 15
Full support for arbitrary levels of design hierarchy
Capable of processor-based or non-processor based design creation
Tight integration with Vivado IP Packager flow for rapid IP and
subsystem reuse
Vivado HLS C Development
CDT based
Simplified for HLS user
Windows
MinGW/msys included
Linux
SystemC libraries included
Page 16
SystemC libraries included
Video/Image functional verification:
10000x speed versus RTL simulation
Standard Input
Design Specification
Superior language support
C Easy, familiar
C++ Methodical
SystemC Standard
Directives
Tcl Efficient Exploration
Pragma Self-documenting
Structured Programming
Object Oriented Programming (OOP)
System Modeling
C
(C99)
CPP
(Standard C++)
OSCI SystemC
(IEEE 1666-2005)
Function Class
Template (STL)
Module/Port
Arbitrary precision
Parallel process
Time (Simulation
Kernel)
Abstraction (TLM)
Page 17
DSP Applications
Arbitrary Precision
C
Simulation and Synthesis
C++
Rounding and Saturation
void yuv2rgb (
pixel_t *in,
pixel_t *out
) {
uint8 R, G, B;
void yuv2rgb (
pixel_t *in,
pixel_t *out
) {
hls_ufixed8,8,!"#_R$%,!"#_#&'( R, G, B;
hls_fixed8,8,!"#_R$%,!"#_#&'( ), *, +;
,onst -p_fixed..,2,!"#_R$%( /yuv012012 3 {
{., 4, .5.16817,
{.,845169:;,845;84:7,
{., 25412.., 47,
7;
) 3 in8(,ol.;
* 3 in8(,ol2;
Page 18
uint8 R, G, B;
int6 <, %, =, ), *, +;
,onst int.. /yuv012012 3 {
{268, 4, 9467,
{268, 8.44, 82487,
{268, ;.:, 47,
7;
) 3 in8(,ol.;
* 3 in8(,ol2;
+ 3 in8(,ol1;
< 3 ) 8 .:;
% 3 * 8 .28;
= 3 + 8 .28;
R 3 <">?(( /yuv042042 * < @ /yuv042022 * = @ .28) (( 8);
G 3 <">?(( /yuv0.2042 * < @ /yuv0.20.2 * % @ /yuv0.2022 * = @ .28) (( 8);
B 3 <">?(( /yuv022042 * < @ /yuv0220.2 * % @ .28) (( 8);
out8(,ol. 3 R;
out8(,ol2 3 G;
out8(,ol1 3 B;
7
* 3 in8(,ol2;
+ 3 in8(,ol1;
R 3 /yuv042042 * ) @ /yuv042022 * +;
G 3 /yuv0.2042 * ) @ /yuv0.20.2 * * @ /yuv0.2022 * +;
B 3 /yuv022042 * ) @ /yuv0220.2 * * ;
out8(,ol. 3 R;
out8(,ol2 3 G;
out8(,ol1 3 B;
7
DSP Applications
Page 19
HPC Applications
Floating-Point
Performance
Latency
Ain,lude Bfir5hB
IEEE 754
Compliance
Full
Allocated
Vectorization
Page 20
d-t-_t fir(d-t-_t x) {
,onst ,oef_t ,0$2 3 {
Ain,lude Bfir5in,B
7;
CC %el-y line h-s extr- del-y -t input
st-ti, d-t-_t D0$2;
-,,_t -,, 3 4;
int i,E;
t-psF for (i 3 $8.; i (3 4; i88) {
D0i2 3 (i334) G x F D0i8.2;
-,, @3 D0i2 * ,0i2;
7
return -,,;
7
typedef flo-t ,oef_t;
typedef flo-t d-t-_t;
typedef flo-t -,,_t;
Full
Vectorization
FPGA Motor Solutions
Copyright 2012 Xilinx
Page 21
Different Electrical Motors
Brushless DC (BLDC)
Permanent Magnet Synchronous Motor
Stepper Motors (hybrid)
Xilinx solution today
DC motors
uC easy play
Induction Motor Reluctance
Xilinx additional solution in future
Xilinx Motor Control Reference Design
Features
Networking support
Industrial Ethernet, CAN and other protocols
Zero impact on motor control performance
Resource efficient, high resolution space vector modulation
Any custom modulation for high efficiency and high performance
Switching of modulation waveforms on the fly
Scalable solution for
DC, BLDC, PMSM and Stepper motors
Supports up to four DC, two BLDCs/PMSMs or two Stepper motors per
daughter card
Number of motors only limited by FPGA size
Xilinx Motor Control Platforms
Hardware Configurations Supported
Base board hosting maintenance and communication function
Xilinx Spartan-6 LX45 Development Kit (SP605) or
Xilinx Spartan-3A DSP 3400A Development Platform Kit or
Avnet Spartan-6 LX150T Development Kit
Qdesys FMC daughter card implementing motor control Qdesys FMC daughter card implementing motor control
functions
2 Full H-Power Bridges,
2 Ethernet Physical Layer interfaces @ 10/100/1000 Megabits
5 Sigma-Delta high speed analog to digital converter and Sinc3 filter,
8 Digital Output with insulation capability @ 24Volts,
8 Digital Inputs @ 24 Volts,
2 Incremental Encoder Interfaces,
Spartan-XC3S50AN interface device
Base Board Design
Block Diagram
FMC FMC
Interrupt
Controller
Timer/
Counter
MicroBlaze
MPMC
UART
Ethernet MAC
DDR2 DDR2
P
L
B
Ethernet MAC
SPARTAN
XC6SLX45
FMC
Connector
FMC
Connector
Serial Link Serial Link
CAN
USB
Xilinx Motor
Control IP
Xilinx Motor
Control IP
USB
Transceiver
USB
Transceiver
= Xilinx standard IP library
= dedicated motor control IP library
Xilinx Motor
Control IP
Xilinx Motor
Control IP
CAN
NETMOT Daughter Card
System Block Diagram
RS485
Transceiver
RS485
Transceiver
10/100/1000
Transceiver
10/100/1000
Transceiver
-
ADC
H bridge
Current
measurement
-
H bridge
FMC
-
ADC
Ethernet
RS485
DC_Link
MotorCoil
MotorCoil
High Speed Serial
Link
ADI strong position
CAN
Transceiver
CAN
Transceiver
8 Digital
Output @24V
8 Digital
Inputs
@24V
SPARTAN
XC3S50AN
-
ADC
Current
measurement
-
ADC
H bridge
Current
measurement
-
ADC
H bridge
Current
measurement
Connector
Encoer 1 Encoer !
MotorCoil
MotorCoil
CAN Bus
Incremental
Encoders
Field I/O
8
LED
Xilinx Motor Control Reference Design
FOC for PMSM (Permanent Magnet Synchronous Motor) and BLDC
Ethernet
PHY
Interrupt
Controller
T
i
m
e
r

C
o
u
n
t
e
r
MicroBla!e
processor
"
a
t
c
h

D
o
#
P
L
B
I
/
F
C
l
o
c
$
P
L
B

B
U
S
MPMC
DDR DDR2
F
%
C
F
%
C
Control
Ethernet
PHY
P L B B U S
TEM&C
TEM&C
Bri'#e
P
"
M
Bri'#e
P
"
M
ADI strong position
Crystal
Oscillator
DCM
clock
management
"
a
t
c
h

D
o
#
DC_Bus oltage
C&(
!
D
C
s

C
o
n
t
r
o
l
l
e
r

Sinc
"
Acquisition
Stator
Current
Stator
Current

Sinc
"

Sinc
"

Sinc
"

Sinc
"
Stator
Current
Stator
Current
Enco'er Filter X#$ !ccumulator
Filter X#$ !ccumulator
Enco'er
Position and Angle
PHY
RS)*+
Digital I/O Filter
Di#ital %utput
Di#ital
Input
I/O
U!%&
C!'
Networking
P
"
M
Base board
Daughter
card
Xilinx Motor Control Reference Design
FOC for STEPPER allows finer Torque Control
H, Bri'#e
P
"
M
H, Bri'#e
P
"
M
H, Bri'#e
P
"
M
Ethernet
PHY
Interrupt
Controller
T
i
m
e
r

C
o
u
n
t
e
r
MicroBla!e
processor
"
a
t
c
h

D
o
#
P
L
B
I
/
F
C
l
o
c
$
P
L
B

B
U
S
MPMC
DDR DDR2
F
%
C
F
%
C
Control
Ethernet
PHY
P L B B U S
TEM&C
TEM&C
ADI strong position
Page 28
H, Bri'#e
P
"
M
Crystal
Oscillator
DCM
clock
management
"
a
t
c
h

D
o
#
C&(
!
D
C
s

C
o
n
t
r
o
l
l
e
r

Sinc
"
Acquisition
Stator
Current
Stator
Current

Sinc
"

Sinc
"

Sinc
"

Sinc
"
Stator
Current
Stator
Current
Enco'er Filter X#$ !ccumulator
Filter X#$ !ccumulator
Enco'er
Position and Angle
PHY
RS)*+
Digital I/O Filter
Di#ital %utput
Di#ital
Input
I/O
U!%&
C!'
Networking
Base board
Daughter
card
DC_Bus oltage
Xilinx Motor Control IP Library
FOC (field oriented control) HDL Block Diagram 5us full loop @50Mhz a 15x of uC
Id
Iq
V a,b,c
QDESYS NETMOT
Daughter Card
Features
Two 10/100/1000 Ethernet interfaces
Multi-channel Analog Sigma Delta acquisition
Measurement of stators currents and motors bus voltage
Sinc3 filter and high speed data link.
Device DNA unique identifier
Motor identifier for remote maintenance. Motor identifier for remote maintenance.
Isolation barrier between the power and the control
Two power bridges supporting permanent magnet motors
(PMSM, BLDC, Stepper)
Legacy communication like Profibus or RS485 and CAN.
Supports multiple hardware platforms
AVNET Xilinx Spartan-6 IEK
Spartan-6 FPGA SP605 Kit
Spartan-3 VSK
Price 860Euro
XILINX MOTOR CONTROL LIBRARY
The LEGO concept an extensible pipeline
Basic Building Blocks
15 Control Functions
Every function stand-alone
DSP48 centric
Dynamic operation
Minimum foot-print
Start/Finish Legomechanism Start/Finish Legomechanism
Allos simple rappin!
E"tensi#le concept
Full parallelism
Full DSP48 precision
48#it operations
18#it precisions
$nterpolated Sin%Cos%Atan&
15 Times aster than u!
Freescale' 55us()*M+,
-ilin"-.DES/S $P 5us(50M+,
FOC PID CLARK PARK PWM-
SVM
ATAN2
SIN/COS
Rect2Pol Encoder IIR
FULLY DOCUMENTED IP
Customer can know, understand, estimate and use
IP USE MODEL
A start / finish pipeline mechanism allows full parallelism and extension
x_in
y_in
start
finish
x_out
y_out
CLARK
x_in
y_in
start
finish
x_out
y_out
PARK
x_in
y_in
start
finish
x_out
y_out
Atan2
Pipelined
Inputs Outputs
x_in x_out
Wrapper
x_in
y_in
start
finish
x_out
y_out
Rect2Pol
Parallel
FULL SOFTWARE STACK
The Application is controlled as layered oriented model in S/W
Microblaze (no O.S.)
RS232 Back Door UDP/IP -100Mb
Storae B!""er
UDP/IP -100Mb
#$ la%er &ro"ile ' co((!nication- )(l inter&reter
*M+ Databa,e Data entr%
-UI .ational In,tr!(ent, +ab St!/io
S
o
f
t
w
a
r
e
P
C
Microblaze UDP/IP Agent
House-keeping
Initialization
IP Registers mapping
IP Registers I/O
HAL (Hardware Abstraction Layer)
Multiple IP instances
Consistent S/W view
2
3
Page 33
01
01 Dri2er, (I/O)
Motor control IP block,
03+ (4ar/1are ab,traction la%er)
H
D
L
Consistent S/W view
Easy Migration to Zynq
Realtime Signal Acquisition
Current, Voltages, Angles
Allow Re/Im display realtime
Allow Postprocessing
Observers
New Algorithms
XML Database
Motors description
Board calibration
FULL S/W STACK & Labview GUI
1
2
1-2-3 = Source code Software on board with UDP/IP Agent
SOFTWARE STACK AS PLUG-IN
Easy plug-in all modules decoupled MC performances unaffected
Motor control IP block,
03+ (4ar/1are ab,traction la%er)
Microblaze
RS232 Back Door #3.
Storae B!""er
H
D
L
Software
Customer can strip the GUI
Bare bone application
Plug the I/F (example CAN)
Field bus adaptation layer
MC performances unaffected
Page 34
01
01 Dri2er, (I/O)
H
D
L
Testing in new environment
MOTOR CONTROL IP ZYNQ FRIENDLY
The layered architecture allows the exploitation of the Zynq environment
DM3
#55 la%er &ro"ile ' co((!nication- )(l inter&reter
*M+ Databa,e Data entr%
-UI 6t
S
o
f
t
w
a
r
e
Z
y
n
q
L
I
N
U
X
#3.
A
C
P
7t4ernet
Zynq can open to new applications
Motor Control fully independent
Acceleration profile via S/W
Motion Control
NURBS
Neon processor
Up to 16 axis
CNC
Page 35
01
01 Dri2er, (I/O)
Motor control IP block,
03+ (4ar/1are ab,traction la%er)
DM3
H
D
L
Z
y
n
q
01 01 01 01 01 01
Motor
2
Motor
3
Motor
8
Motor
9
Motor
:
Motor
;
Motor
2
CNC
RS274NGC language
GUI with Labstudio
Netmot V2.0 and AVNET-AES-FMC-MC1-G
ON-LINE DOCUMENTATION
2 MODALITIES
DEMO beginner
EXPERT full control
AQUISITION MODE
Currents, Voltage, Angles
On-the-fly switch On-the-fly switch
SVM Sinusoidal
PWM RPFM
PWM frequency
RPFM repetition
Vector Space Display
Diagnosis
Tuning
FFT for noise measurement
Demonstration hardware Block Diagram
SP605*
LX$(&
SP605
Power
Supply
Bri'#e
M
o
'
-
C
t
r
l

Stator Current
Enco'er F
M
C
Motors
SD_CARD
Interrupt
Controller T
im
e
r

C
o
u
n
t
e
r
MicroBla!e
processor
MPMC
U&RT
P
.
B
Enco'er
Bri'#e
M
o
'
-
C
t
r
l

Stator Current
Enco'er
NETMOT
Power
Supply
9Vdc
F
M
C
Motors
Power
Supply
24Vdc
)&*
)&*
"
S
(
+
!
'
FOC
P,M/SP,M
Current
Serial Link
I
/
O
* Could also be Avnet LX150T Industrial Ethernet kit
Zynq and Motor Control Solution
Zynq-7000 Family Highlights
Complete ARM-based Processing System
Dual ARM Cortex-A9 MPCore, processor centric
Integrated memory controllers & peripherals
Fully autonomous to the Programmable Logic
Tightly Integrated Programmable Logic
Used to extend Processing System
7 Series
Programmable
Logic
Processing
System
Memory
Interfaces
Used to extend Processing System
High performance AXI based Interface
Scalable density and performance
Flexible Array of I/O
Wide range of external multi-standard I/O
High performance integrated serial transceivers
Analog-to-Digital Converter inputs
Software & Hardware Programmable
Common
Peripherals
Custom
Peripherals
Common Accelerators
Custom Accelerators
Common
Peripherals
ARM

Dual Cortex-A9
MPCore System
Zynq-7000 Industrial Motor Control Application
Embedded World Demos Part 1
HD Video Processing HD Video Processing
SW vs. HW SW vs. HW Sobel Sobel Filter Filter
PONG PONG
Real Time Control Loop Real Time Control Loop
with Video Object Tracking with Video Object Tracking
Ubuntu Ubuntu Linux with Linux with
Medical Image Acceleration Medical Image Acceleration
(SW vs. HW algorithm) (SW vs. HW algorithm)
with Video Object Tracking with Video Object Tracking
Cadence Virtual Platform Cadence Virtual Platform
Medical Image Acceleration demo Medical Image Acceleration demo
Embedded World Demos Part 2
ARM DS ARM DS--5 Tools 5 Tools
Multi Multi--processor Debug and Trace processor Debug and Trace
Lauterbach Lauterbach Trace32 Tools Trace32 Tools
Linux + FreeRTOS Linux + FreeRTOS
PetaLogix Linux SDK with FreeRTOS PetaLogix Linux SDK with FreeRTOS
Lauterbach Lauterbach Trace32 Tools Trace32 Tools
AMP and SMP Trace AMP and SMP Trace
iVeia iVeia Android 2.3 Android 2.3
Image Processing Application Image Processing Application
Zynq-7000 Extensible Processing Platform Summary
New Scalable Family of Devices
Zynq-7000 EPP device portfolio
Four devices for a broad range of applications
Industry Standard Design Environments
Well defined SW programming model
Familiar HW design flow
Flexible accelerators and IP Flexible accelerators and IP
Standard AMBA

AXI interfaces
Broad and Expanding Ecosystem
Tools, OSs, IP
Middleware, codecs
Availability
Z-7020 Sampling Now
Production 2H CY2012
Page 43
ZYNQ AND FPGA DELIVERS MODULAR
PLATFORMS
I
n
d
.
N
e
t
.
I
n
d
.
N
e
t
.
U
S
B
.
D
V
I
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
CPU
Module
DVI
Module
Analog
Module
I/O
Module
I/O
Module
MEMS
Module
M
o
t
o
r
M
o
t
o
r
Motor
Control
P
r
o
c
e
s
s

C
o
n
t
r
o
l
l
e
r
Page 44
Z
Y
N
Q
A
R
T
I
X
A
R
T
I
X
A
R
T
I
X
A
R
T
I
X
DVI
SDC
Eth
Eth
High Speed Link
Analog Input
@24V
Output
@24V
Mems
Z
Y
N
Q
Motor
Contr.
S
D
C
A
R
D
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
M
o
t
o
r
USB
Zero latency with Gigabit backplane
P
r
o
c
e
s
s

C
o
n
t
r
o
l
l
e
r
Performance
Personality
Platform
Zynq =
ZYNQ THE PROCESSING ACCELERATOR
A9 Cortex
d
e
b
u
g
A9 Cortex
FPU & NEON FPU & NEON
M
M
U
M
M
U
32K I- cache
32K D-cache
32K I- cache
32K D-cache
Snoop Control Unit (SCU)
Application Processing Unit
SDC
Q-SPI
1,2,4,8 bit
Parallel 8-bit
NOR/SRAM
NAND 8,16-bit
GPIOx54, x64
UART
UART
USB
USB
GigE
GigE
SDC Controller
Eth.
USB.
ZYNQ
Stable Platform
Page 45
DDR2
DDR Controller
L2 Cache On Chip Memory
AXGM# x 2
General Purpose
32-bit AXI Master
AXGS# x 2
General Purpose
32-bit AXI Slave
AXDS# x 4
AXI Data
32/64-bit Slave
AXCS
AXI Coherent
64-bit Slave
Memory Switch
UART
SPI
SPI
I2C
I2C
CAN
CAN
TTC/WDT
Core Switch
DMA
8 ch
Comm Backplane
High Speed Channels 14
Process Data
IEC61131-3 Acceleration
Industrial Networking
Personality
Diagnostic Data
MEMS Acceleration
HMI
Field
IF
Custom
Platform
ZYNQ AND FPGA DELIVERS MODULAR PLATFORMS
I
n
d
.
N
e
t
.
I
n
d
.
N
e
t
.
S
D
C
A
R
D
U
S
B
.
D
V
I
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
CPU
Module
DVI
Module
Analog
Module
I/O
Module
I/O
Module
MEMS
Module
M
o
t
o
r
M
o
t
o
r
Motor
Control
S
D
C
A
R
D
Process Control
Platform Modular I/O with Personality
Motor Control
backplane
Overall Xilinx Strategy vs. MCU
MCU Only
Advantages
MCU Only
Disadvantages
Stuck with drive and
decoding logic from
MCU vendor
Corresponding
Xilinx Strength
Flexibility in
optimizing algorithms
Low cost (~$5)
Legacy code & tools
Page 47
Limited performance
Limited connectivity
No CAN / Ethernet
combo
May require multiple
peripheral chips
SW botttlenecks go
away in HW
We have both!
Integration,
Integration,
Integration!
Likely to have on-chip
Flash and ADC
No FPGA tools or
experience required
Many CPU architectures
to choose from
The "orl' .ea'er in Hi#h Per/ormance Si#nal Processin# Solutions
ADI FMC cards for Xilinx Platforms
xCOMM FMC Simplified Block Diagram
Frequency
ADL5375 ADL5602
AD9548 AD9523-1
ADF4351
L
P
C

(
3
2

D
a
t
a

+

3

C
L
K

L
V
D
S
)

F
M
C

C
o
n
n
e
c
t
o
r


(
5
0
0
M
H
z
)
X
i
l
i
n
x

D
e
v
e
l
o
p
m
e
n
t

P
l
a
t
f
o
r
m
RF
Out
DAC
16-bit
1250MSPS
AD9122
Modulator
400 6000MHz
20dB Fixed Gain
50 4000MHz
ADL5605/6
700 - 1000MHz
1800 2700MHz

Master Clock Out
16 + 1 LVDS
Pair @
1000 Mbps
500MHz (DDR)
S
S
50MHz
Ref Clock
I2C / USB
to SPI
SPI
SPI SPI SPI
5V @
500mA
Tx
RF output power control is
accomplished by
adjusting baseband data
Optional Front end
2
0dB 0dB
49
Clock
Generator /
Sync
Clock
distribution
Frequency
Synthesizer
ADL5380 AD8366 AD9643
AD9548 AD9523-1
L
P
C

(
3
2

D
a
t
a

+

3

C
L
K

L
V
D
S
)

F
M
C

C
o
n
n
e
c
t
o
r


(
5
0
0
M
H
z
)
D
e
v
e
l
o
p
m
e
n
t

P
l
a
t
f
o
r
m
RF
In`
Slave Clock In
Sync In
ADC
14-bit
250MSPS
0.25dB Step Size
600MHz Bandwidth
Demodulator
400 6000MHz
Output: 1 1000MHz Input: 1 Hz - 750MHz
Output: 35 - 4400MHz
Frequency
Synthesizer
16 + 1 LVDS
Pair @
500 Mbps
250MHz DDR
Pi network
Solder bump jumper S
S
S
1 LVDS
Pair
SMA connector
SPI SPI SPI
SPI
SPI
SPI
Power
ADL5523
400MHz to 4000MHz
Low Noise Amplifier
Tuned for frequency

Rx
Optional Front end
2
-9dB
Non-SMA connector
ADI proided !locks
!DC
!DC
I-
Mo.
I-
Demo.
D!C
A
D
I

D
e
v
e
l
o
p
e
d
H
D
L

(
V
e
r
i
l
o
g
)
FMCCOMMS1-EBZ Board
HDL for connectivity (AXI Master which can source/sink data) + dual tone DDS
Linux IIO drivers for HDL (data path) and each part on the FMCCOMMS1-EBZ Board (control)
Linux userspace application, to provide basic example of how to use everything
All released as source (schematics, HDL, C Source) under open license, for others to build on
No optional / custom front ends (can use pre-existing evaluation boards for PA, LNA, etc)
50
Mo.
D!C
ADI "DMI# $ot %&st color !ars
on '()*+++ Xilinx Deelopment Boards
Xilinx boards
Artix EVB
ADI HDMI Tx ADV7511
Kintex EVB
KC705 ADI HDMI Tx: ADV7511
Virtex EVB
ADI HDMI Tx and Rx: ADV7511 and
$ot %&st Color Bars#
Xilinx AD "DMI test pattern in em!edded ,OM
a commercial s-ips .it- eer/ !oard
ADI HDMI Tx and Rx: ADV7511 and
ADV7611
Zynq EVB
ADI HDMI Tx & Rx ADV7511 and ADV7611
Zed Board
ADI HDMI Tx ADV7511 and ADI Audio
ADAU1761
51
Reference Design Features Reference Design Benefit
High image quality Compliant to HDMI 1.4,
HEAC (ARC), and 3D video
Audio 8-channel Supports stereo or 7.1
surround audio up to 768
kHz., compressed audio
including Dolby Digital,
DTS, and THX.
Proven Reference Design,
HDL, Linux Drivers provided
Reduced Risk: Support for
the ADV7511 and ADV7611
integrated into Xilinx Tools
and support package for ease
of use and drives ADI
preference
KC705
Sec&rit/ Camera Design
L
P
C

(
3
2

D
a
t
a

+

3

C
L
K

L
V
D
S
)

F
M
C

C
o
n
n
e
c
t
o
r


(
5
0
0
M
H
z
)
X
i
l
i
n
x

D
e
v
e
l
o
p
m
e
n
t

P
l
a
t
f
o
r
m
Comp
Out
VDAC
Low Power, Chip Scale
10-Bit SD/HD Video Encoder
ADV7393
16 + 2
Single ended
I2C
MEMS Omni Directional Mic
Digital Output
ADMP421
Motor Control for
Pan/Tilt
ADuM5230
Reference
Design Features
Reference
Design Benefit
Standard Linux running on
52
L
P
C

(
3
2

D
a
t
a

+

3

C
L
K

L
V
D
S
)

F
M
C

C
o
n
n
e
c
t
o
r


(
5
0
0
M
H
z
)
D
e
v
e
l
o
p
m
e
n
t

P
l
a
t
f
o
r
m
1
Power
MIC
Lens Driver
For Zoom/Focus
AD5808
I2C
AR0331 - 3.1-megapixel, 1/3-inch
Aptina CMOS Sensor
3 Axis inclinometer
ADXL345
I2C
16-Bit Temp Sensor
ADT7410
I2C
Standard
software, open
source camera
control
application
Linux running on
Zynq
Proven
Reference
Design, HDL,
Linux Drivers
provided and
supported on
Web
Risk reduction
example software
defined radio
including high
performance
analog and RF
design capable of
Tx and Rx
Lots of ADI parts Allows for
multiple
distributor
registration
opportunities
AD0120A FMC Board
Application Segments
Broadband
communications
systems
CMTS/VOD
Xilinx ML605 + AD9739A FMC
CMTS/VOD
Cellular infrastructure
Point-to-point wireless
Instrumentation,
automatic test equipment
Radar, avionics
53
Reference Design Feature s Reference Design Benefit
Proven Reference Design,
HDL, Linux Drivers provided
Customer is provided
standard software production
ready HDL, Linux device
drivers for integration into
projects
A dual-port interface with
double data rate (DDR) LVDS
data receivers supports the
maximum conversion rate of
2500 MSPS.
Lowers total power
consumption for high data
rate transfer
Runs on Standard Xilinx
ML605 and Series 7 boards
FMC connection allows for
FAE demos with latest ADI
and Xilinx parts distributor
Registration opportunities
AD0(31 FMC Board
Application Segments
Wireless Infrastructure
Emphasis on developing
common radio platforms
serving worldwide 4G
deployment
Xilinx ML605 + AD9467A FMC
Test Equipment (Spectrum
Analysis)
High performance over broader
bandwidths
More bits and more speed
Defense and Aerospace
Improved dynamic range
supports different radar modes
of detection and response
54
Reference Design Feature s Reference Design Benefit
Proven Reference Design,
HDL, Linux Drivers provided
Customer is provided
standard software production
ready HDL, Linux device
drivers for integration into
projects
Proven Reference Design,
HDL, Linux Drivers provided
Reduced Risk: Support for
the ADV7511 and ADV7611
integrated into Xilinx Tools
and support package for ease
of use and drives ADI
preference
FMC Interposers
High Speed DAC and ADC Interposer Benefits SDP FMC Interposer Interposer Benefits
Xilinx ML605 FMC Interposer and AD9649 Eval Board
SDP-FMC Interposer
Xilinx KC705
AD5415 Eval Board
55
High Speed DAC and ADC
Interposer Features
Interposer Benefits
Proven Reference Design,
HDL, Linux Drivers and
sample applications provided
and supported on Web
Customer is provided
standard software production
ready HDL, Linux device
drivers for integration into
projects
Connects High Speed DACs
and ADC evaluation boards
to Xilinx Development boards
Connects to over 140 ADI
evaluation boards allowing for
rapid development of
customers applications
Runs on Standard Xilinx
ML605 and Series 7 boards
FMC connection allows for
FAE demos with latest ADI
and Xilinx parts
Lots of Demos Multiple Registration
opportunities
SDP FMC Interposer
Features
Interposer Benefits
Standard software, open
source application demo and
examples
Linux running on Zynq (Arm)
or MicroBlaze Includes tested
interface HDL, device drivers
Connects ADI Precision
Evaluation boards that have
SDP connector
Connects to all new SDP
boards (estimate 50 new
boards/year) allowing FAEs
to demonstrate ADI products
connected to Xilinx platform
Runs on Standard Xilinx
ML605 and Series 7 boards
FMC connection allows for
FAE demos with latest ADI
and Xilinx parts
Lots of Demos Multiple Registration
opportunities
All /o& can do.nload from .iki4analog4com
56