Computer Organisation

Part-Processor

[This paper deals with the study of computers organization from a programmerss
point of view rather than an architectural point.Basically it is about the relationship
among the processor,memory and I/O devices.

2014
Abhinab Das
College Of Engineering And Technology,BBSR
7/12/2014
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Advance Material Research Vols 234-235
Online Available Since 12/07/2014 at www.scribd.com
Scribd publications,California,United States
PROCESSOR,MEMORY,I/O DEVICES RELATIONSHIP
Abhinab Das
College Of Engineering And Technology,Ghatikia,Bhubaneswar,Odisha,India-751003
Email-abhinabrohit@gmail.com

Keywords: Memory, Processor, I/O Devices, State Machine, Data Path Architecture
Abstract:
The relationship among processor,memory & I/O Devices has been reviewed in this
study.But before going into the topic,few contents of Computer Organisation has been
overviewed to make the study of processor,memory & I/O Devices a little easier.It has
been started with the introduction to computing,software,hardware,processors
activites,processor as a state machine,Data Path Architecture,controller,state machine
design,controller design-microprogrammed & hardwired,microinstructions,memory
hierarchy.Before studying the I/O Devices let me clear it that I/O Devices are nothing
but extended memory.so we will basically deal with the memory.
Introduction:
1. Introduction To Computing
Data Path
Numbers Data Control
Computers
Processing Memory
Storage

Processor Memory I/O (extended memory)
(processing) (stores numbers)
The CPU deals with the I/O in the same way as it deals with the memory.
Memory
CPU
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One should not confuse Computer Organisation with Computer Architecture.
Organisation is considered usually from a users point of view whereas architecture is
considered from a designers point of view (i.e) organization is more often considered
from software opinion whereas architecture is considered from hardware point.For
instance for an instruction set MULTIPLIER-what is the program to be written is
regarded from an organizational view but how it is implemented will be looked on from
architectural view.
Application
1 bit 4 8 16 32 ----------------------------

Control(Electrical eng.) Data Processing(CS)

Special Pupose General Purpose
ROM RAM
Hardware Software

An application usually goes through the above phase starting from control(1-bit) to
Data processing end.In between the transition phase a microprocessor is
introduced.The control part is basically handled by an electrical engineer whereas the
Data processing end is mastered by a Computer Science engineer.Control part is usually
for special purpose,has ROM & is from hardware point of view.Data Processing part is
usually for general purpose,has RAM and is from software point of view.
Earlier a system was used for either computing or communication

COMPUTING COMMUNICATION

Processing Storing Voice Digitisation
Data
Numeric Processing + Symbolic Processing Coded Data
(Arithmetic) (Logic)
These two processing constitute the Arithmentic Logical Unit(ALU),the core of the CPU.
m.p
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TEXT AUDIO,VEDIO-
The symbolic Processing can be GRAPHICS Unstructured Data
which are called as multimedia AUDIO (as it cant be changed)
VEDIO


Software The hardware is nothing but layers and
layers of softwares.


MACHINE CODE
0 1 1 0 0 1 1 0 0_ _ _ _ _ _ _ _ _ _ _ _ _
Operation Operand
(Op.code) (data)
ADD A,B
Mnemonic code X=Y+Z(Statement)

A Machine Code is usually divided into an operation code and operand(data). When the
instruction is fetched,the operation code is the one which is decoded first.It is decrypted
to assembly language which is known as mnemonic code.Operand is actually the data
which can be any variable.Then to make it user-friendly,the assembly language is
usually converted to a statement which is known as High-Level-Language(HLL) which
indeed is written in a language(FORTRAN,BASIC,PASCAL).So,to undergo the change in
transition from any of the machine(m/c) code,assembly code,HLL we need a translator.
2.Introduction To Software

CPU
Software Hardware Memory
I/O
H/W

H/W
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If we want to go to the core of the hardware from users point of view,we need to come
across several layers of softwares.
ASSEMBLER
TRANSLATOR
H/W-Machine Codes
Assembler Codes COMPILER
Statements-HLL Codes INTERPRETER
We have seen that in the machine code we have converted it into a high level language
using FORTRAN,BASIC or PASCAL.Now the program to be written in HLL is considered
to be from the organisational point of view but to understand the machine code(Op.
Code & operand),it is seen from the architectural point of view.
But we have to keep in mind that the system will execute an output only if the input is
fed in machine code i.e binary code not in HLL or assembler codes.So,for converting
assembler to machine code or HLL code to machine code we need a translator which
can be an assembler or compiler or an interpreter.
It is not only possible for a user to translate from HLL to assembler then to M/C code
but it can also be directly translated from HLL to M/C.

Assembly language to M/C code Assembler
HLL code to M/C code Compiler/Interpreter

With the use of the word translator we are slowly graduating from MACHINE to
SYSTEM i.e we have taken one step away from the core hardware.
The system not only includes the basic core CPU,memory,I/O hardwares,but also this
kind of translators which are part and parcel of the entire system.

sin
we can create library of programs which can be saved as a part of system.
For I/O hardwares we need programs,for example in case of keyboard we need
keyboard routines.For display we need display routines.Thesse can be utilities.
If we have a dot matrix printer,a dot matrix routine and an interface will be needed.
P
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Any user is not bothered about the inner hardware but it comes to an O/S(Operating
System).
We can have a hardware and have set of softwares
to come up with an OS and we can have the same
hardware and have different set of softwares to come
up with a different OS.
For instance let us say we have Intel 5486 system O/S
or a Pentium and layers and layers of softwares can
be added to get a DOS OS.

Machine Code Object Code

Translated
Language Code Source Code(Source Listing)
The software which is part and parcel of the sytem is known as system software.
Application software is a part of software which deals with the user.
Previously we had different types of computers as mentioned below:-
1.Batch Processing:-
The details of operating system will vary depending upon the kind of system one has.
Before,in all the computer centres all these hardware resources CPU,memory,I/O
devices were all centrally located in one place and the jobs were processed from
different users according to the precedence.The user is not able to interact with the
system
JCL-Job Command Language
2.Time Sharing:-
The user may be able to interact with the system.If the user is online then this will be
called on-line time sharing system.
3.Process Control:-
All the signals will be coming to a particular system and the process will be controlled.
4.Real-Time Processing:-
We are not only taking signals from the external real world,we may also take the signals,
H/W
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process them and return the processed information back to the system in real time.The
system waits for some time,within that time if the processed information comes back
then its called real time.
A system is usually of two types distributed system and networked system.The code
which the programmer feeds is the source code and which indeed gets converted as the
machine friendly code is called as object code.
more time
Running the object code will be the fastest. shell like less time
Farther from the core or the hardware,slower
will be the response.So there is no point in
adding layers and layers if ultimately the system user
response is slow.
(Application)
Hierarchial Manner:-

Software

System Application

Translator OS wordstav _ _ _ _ _ _ _ d-base
Compiler Interpreter _ _ _ _ _File handling

FORTRAN C PASCAL

Hardware:- (from users point of view)
Keyboard CPU Board
Display Memory Board
Printer I/O Board
Interface
H/W
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We have different hardware devices like keyboard,display,printer and boards such as
CPU,memory,I/O board.So,for these I/O devices to execute and perform we need an
interface to connect them to the I/O board which is usually called as bus.

BUS




master of slave usually slave
the bus




Fig(1.0)

Bus is the set of signal lines.CPU is secernated as the master of the bus.memory is the
slave and I/O usually may act as slave.
There may be situation when CPU demands to memory or I/O and they have to respond
being slaves.But there can also be situation where I/O will demand and CPU will be
responding for a short while.
Depending on the keyboard the appropriate interface is needed.In our case we use the
ASCII (American Standard Code For Information Interchange) interface keyboard i.e
while pressing a key,the corresponding ASCII code is generated which makes it
perceivable by the I/O board.Similarly is the case in display and printers where we need
an appropriate interface depending on the display or printer.In display we may have
RASTER SCAN or RANDOM SCAN.


CPU Memory I/O
keyboard
printer
display
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3.Introduction To Hardware

Keyboard:-ASCII code Display:-Raster Scan
Printer:-Dot matrix Random Scan
Laser Point Plot 52ms time
Daisy wheel Calligraphic
Inkjet Vector Display

Raster Scan:-
It has poor or less Resolution because picture definition is stored as a intensity value.
Electron Beam is directed from top to bottom and one row at a time on screen, but
electron beam is directed to whole screen. Zig Zag line is produced because plotted
value are discrete.
Random Scan,Point Plot Calligraphit,Vector Display are usually similar.
Random Scan has High Resolution because it stores picture definition as a set of line
commands. Electron Beam is directed to only that part of screen where picture is
required to be drawn, one line at a time so also called Vector Display. Smooth line is
produced because directly the line path is followed by electron beam .
Now we have earlier discussed that the CPU board has two ends i.e control part and
data processing part. Here we will study the memory hierarchy system where we will
come across three terms cost,size,speed. And even before we learnt that the core is
hardware in case of processor but here its CPU in case of memory hierarchy.And
cost,speed,size all will be proportional to each other.
Speed Cost 1/Size
That means as the speed increases,the cost will increase but the size will be decreased
in case of the memory hierarchy system.The study of the hierarchy system will also be
the same shell-like structure which we have come across before.



-----------------
-----------------
-----------------
-

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Memory Hierarchy:-

Cost/bit Cache
DRAM(main memory)
Secondary Storage
(magnetic disk)
Decreasing speed &
Cost, increasing size REAL WORLD

From the figure we can see that we have several layers,starting from cache to DRAM
which is the main memory then to the secondary storage(magnetic disk) and atlast it is
the real world outside the memory.The response of each layer goes on slower and
slower as it moves away from the CPU.
(i.e) response of the Real World < Secondary storage < DRAM < Cache

Cache DRAM Storage

Cost -------- -------- ----------


Size Kilobytes Mega bytes 100s of megabytes


Speed 10ns 100ns z-10ms


The size of cache is usually in kilobytes,DRAM is in megabytes and that of secondary
storage is in 100s of megabytes.
The speed of cache cache is around 10ns,DRAM is 100 ns and that of secondary storage
is z-10 ms.RAM is basically of two types i.e static RAM and Dynamic RAM out of which
the former is the faster one.
CPU
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Storage

Floppy diskette Hard disk


O/S - I/O routines
There will be atleast one device driver for each disk system i.e the driver will provide a
software interface to the disk sytem enabling the operating system to access the
hardware device(disk system) without knowing the precise details of the hardware
being used.
Computers are of two types:
1.Stand-Alone-single user ask respond
2.Networked computers


The networked computers are used to establish communication,share
resources,remote,access.
Program memory
location address
Instruction data/operand

A program usually contains instruction which the CPU can process and the data which
the memory holds.


........................
.......................
.........................
.......................
........................
........................
...........................
...........................
Bus
Interface
Disk System
CPU
memory
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Major Phases:-
Fetch the instruction Execute(data)

Any program will undergo two major phases i.e fetching the instruction and executing
the data.The processor will execute the data not the memory.Now both the two phases
will constitute an instruction cycle.There will be several instruction cycles for
program.An instruction cycle will have several machine cycles and each machine cycle
thenafter will have various low level state activities.
Fetch Interpreter Execute
Decoder
The particular instruction code must be understood and should be unique to the
processor which is carried out by the Interpreter.After the CPU gets the instruction and
the required data,then it will be executed.

Fetch the instruction Execute(data)
bus activity

machine cycle

Fetching may also be carried on with several steps i.e the data/instruction can also be
on different memory locations.In such case the CPU has to fetch the data from the
location one by one.
The program is executed by taking instructions after instructions,the instructions cycle
consists of machine cycle which has some bus activity and each machine cycle consists
of some small steps of activity.Each one of the activity is known as the state of the
processor.
The state level activity of the processor is described in the next chapter where there will
be an introduction to the term Clock Period.



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4.Processor Activities

fetch execute
Instruction cycle
machine cycle

Bus activity
State of the processor

State small steps of activity


The processor is nothing but the study of
the state.State is the study of clock period.
Clock period
We cannot study the activity of CPU,memory,I/O in isolation.Some kind of relation has
to be there.The processor executes program.
Program

Instruction Data
(Stored Program Digital Computer)
(VON NEUMANN ARCHITECTURE):-90-95% of the computers are based on this
architechture.
The CPU may address to the location in memory and the CPU may also fetch
address(location) from the memory for data access.
Bus activity is essential for fetching an instruction or data since the CPU is looked
as a state machine.
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register

n-bit word


memory
For n-bit word it is meaningful to have n-bit register in CPU to store the
data/instruction.
CPU holds the data in the register.If the CPU doesnt have the data itself,then only it has
to ask from the memory.
When we say that the execution of a program has three machine cycles that means the
CPU accesses the bus 3 times.


m


Instruction Fetch(coded form) Decode Execute
The program is executed by the CPU in this manner.



Instruction Format
After the instruction is fetched the decoding will be started from Operation Code side.
Operand can be single operand,double operand or no operand.
So while decoding the processor has to know what kind of operand it is.
Another familiar term which we come across is 8-bit CPu,16-bit CPU,32-bit _ _ _ _ _ _ _ _
and so on.

n







Op.Code Operand
n-bit
Bus(m)
CPU Memory I/O
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What it actually means is:-
8-bit CPU The data being internally processed by the CPU is of 8-bit.
16-bit CPU The data being internally processed by the CPU is of 16-bit.
Processing Byte
(ALU) Byte-organised
memory
arithmetic logical

memory
8-bit CPU = 8-bit ALU
16-bit CPU = 16-bit ALU
Either it is a 8-bit CPU or a 16-bit CPU , it is actually the 8-bit ALU and 16-bit ALU
respectively.
CPU

ALU For one set of instruction,it will be
one data path and one control path
Data Path Data Path(control aspects) aspects.

AL Circuits Control circuits

The basic activity takes place on the register which is known as the Register-Transfer-
Level(RTL) activity.
For one clock period,register-transfer-level takes place.



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0 1






State by state figure as per some given algorithm:-
1-OUTPUT Function
2-NEXT STEP Function
MACHINE CYCLE:-

1-CPU addresses the memory i.e it fetches the instruction.
2-CPU generates the control(read) signal.It tells the memory to read the content of the
address which is an instruction.CPU addresses the data from the bus.
3-Memory must place the data on the bus.
In case of instruction fetch,the data is nothing but an instruction.
4-CPU reads in the instruction(data) which has been placed by memory on the bus in
response to CPUs request.



OUT1
INP1
----------------
-
----------------
-
----
---
----
---
a
b
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bus Address register from CPU
bus Read signal from CPU Inst. register Data bus
bus Data from memory
The address register from CPU sends the instruction address to the bus.Read signal
from CPU is then generated on the bus.The data from the memory is fetched to the
bus.So there arises a situation where the data from the data bus goes into the
instruction register in the CPU.

5.Processor As A State Machine






Address READ Addr. Ready
Data







m/c cycle



T1 T2 T3 T4
BUS











CPU











memory
C
O
N
T
R
O
L
Address
register
Inst.register
Decode
Control
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T1:-Address bus Address(CPU)
CPU places the address on the address part of the bus.

T2:-Control bus Read Control(CPU)
The read part is done on the control part of the bus.
T3:-Data bus Data/Instruction(Memory)
Data is transferred from the memory on the data part of the bus.
T4:-Inst. Register Data bus(CPU)
In case of OPERAND/DATA , the data fetched will go to some data register in the CPU.
In case of 8-bit CPU it is meaningful to have 8-bit long data part of the bus but strictly
not necessary.
Memory Access Time:-
Memory Access Time is the time taken by the memory to acces the data and put in on
the bus.
As soon as the memory gets the address(T1) and the read signal(T2),the memory will
generate not ready signal if the memory doesnt have fast memory access time.So in
such a case it is the responsibility of the CPU to introduce one more state.



T1 T2 T3

Tw(wait state)

Algorithmic State-Machine Chart(ASM):-
There must be a controllers output to be placed on the address register which the
address register indeed places it on the bus i.e the address register itself doesnt place
the instruction on the instruction part of the bus but rather the controller in the CPU
apprises the inst. Register to fetch the instruction on the data bus.


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1 0







1 0


State machine cycle is one cycle which goes through several steps and in each state it
generates an output . Whenever necessary it must demand for required output and then
it decides the next state.The starting point of a CPU design is the instruction cycle.For
each instruction cycle work out the machine cycles and for each machine cycle workout
the register-transfer-level activity(RTL).
CPU In this case the data it handles
Data Path Data Path Control is the address.
State M/C

Bus Add.reg

Bus Read sig.
Ready

Bus Data mem.

wait state

Inst.register D.Bus

READY
T1
T2
T3
T4
Tw
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From the above figure,we have figured out that the state machine cycle goes through
several RTL activities.
In the state T1 the controllers output is placed on the address register in the CPU which
is then placed on the address part of the bus.
In the state T2 the read signal is generated from to CPU on the bus .
After state T2 the memory has to generate ready or not ready signal depending on
the Memory Access Time of the memory.If the memory access time is not fast enough
then the memory will send 0 signal to the CPU to demand for a wait state.
Now if the memory is ready , it will send 1 signal to move forward to the next state.
In the state T3 the data from memory will be fetched on the data part of the bus.
And at the last state T4 the data bus will fetch the instruction/data on the
instruction/data register in the CPU which is then executed by the processor.
We have to go into the architecture of the CPU to further understand.There will be
different registers to handle instruction , data or address.
The part of the address register which gives the instruction address is known as the
Program Counter.
Now the an instruction consists of micro-instructions.
When a programmer can develop a program in the micro-instructions level then he is
known as a microprogrammer.
So the whole chahracter of the CPU is altered when a program is developed at micro-
instruction level.
If we use micro-programmed controller then its called Firmware.
Micro-instruction:-
In computer central processing units, micro-operations (also known as a micro-ops or
ops) are detailed low-level instructions used in some designs to implement complex
machine instructions.
A single instruction in microcode. It is the most elementary instruction in the computer,
such as moving the contents of a register to the arithmetic logic unit (ALU). It takes
several microinstructions to carry out one complex machine instruction (CISC).


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6.Data Path Architecture

Highest level:-Program * Data Path(architecture)


Low level:-State RTL activity * Data Control(ALU & register)

The highest level activity is the program and the low level is the small register-tranfer-
level activity.
MULTIPLEXER(MUX):-

Data A
Inputs OUTPUT(Z) MUX Z
B


Control Inputs Control
The above figure is a multiplexer , basically known as MUX. A multiplexer (or MUX) is a
device that selects one of several analog or digital input signals and forwards the
selected input into a single line OUTPUT.The one which selects are the control inputs. A
multiplexer of 2
n
inputs has n Control inputs , which are used to select which input line
to send to the output.
Conversely, a demultiplexer (or demux) is a device taking a single input signal and
selecting one of many data-output-lines, which is connected to the single input. A
multiplexer is often used with a complementary demultiplexer on the receiving end.
A 2-to-1 multiplexer has a boolean equation where and are the two inputs , is the
control input, and is the output.

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Arithmetic Logic Unit(ALU):-
For example:-
A
8-Arithmetic function 16 functions 4 4-bit OUT
8-logical function ALU
B
4

In this case there are total of 16 arithmentic and logical functions to be performed by
the ALU.Since 2
4
= 16 , the ALU will be a 4-bit code which will uniquely identify which
code it is and the two inputs will be of 4-bit code.
MUX only passes out the data whereas ALU will be carrying out some functions.
Engineers can design an arithmetic logic unit to calculate most operations. The more
complex the operation, the more expensive the ALU is, the more space it uses in the
processor, and the more power it dissipates. Therefore, engineers compromise. They
make the ALU powerful enough to make the processor fast, yet not so complex as to
become prohibitive.
The symbols for a MUX and an ALU are almost identical and easily mixed up. The ALU
symbol has a little triangle piece removed between the 2 inputs, while the mux symbol
is a simple quadrilateral.
A multiplexer would select one of both inputs, in an ALU both inputs may be used
simultaneously, depending on the pending operation.
All in all an ALU can perform several logical operations, like adding, shifting, clearing,
etc. It's a rather complex piece of logic which works on the operands on the inputs and
the operation code.
Operations like "clear A" are simple, but "multiply A and B" requires lots of gates.
An ALU could be given a multiplexer function as one of it's features if desired. i.e a
multiplexer's capabilities may be a small subset of an ALU's capabilities.
In a typical implementation, both have two inputs and one output.
But the multiplexer carries out only an either/or selection between the two inputs.
The ALU could do this plus addition, OR, AND, XOR, Add, Subtract, ...



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Data Bus

Address Bus


A MUX
ALU M
1

B 0/1
A
C
1
C
2
C
3
C
4
C
5
MUX
B
0/1
IN OUT M
0

T1:- Address Bus Program Counter(PC)
The dotted line is the Data Path.
T2:- Control Bus Read Signal
PC PC + 1. i.e PC is incremented by one and replaced.
T3:- Data Bus Data Memory
T4:- Inst.register Data Bus
Symbol:-
Data Signal

Conrol Signal
Inst. Register
Addr. Register
D
1
Register
Program counter
D
2
Register
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From the above figure we can see that the dotted line is the Data Path.The controller
instructs the address register i.e the Program Counter to fetch the instruction,the IN and
OUT port of the Program Counter must be enabled for the instruction to be fetched.In
the next step the control input to the MUX(M0) will be in such a way that the B INPUT
will be executed as the OUTPUT.Then the OUTPUT of ALU will be in such a way that B
input of ALU is taken for carrying out functions.The control input of MUX(M0) will be
either 0 or 1 depending on the fact that the INPUT which is the OUTPUT of the ALU will
be executed as the OUTPUT of the MUX(M0).Then the instruction will go to any one:-
Program Counter,D1 Register,D2 Register,Address Register,Instruction Register which
IN and OUT port must be enabled.
Once the instruction register gets the instruction it passes on to the controller for
execution.

I.reg D
1
reg D
2
reg A.reg PC MUX(M
0
) MUX(M
1
) ALU

0 0 1 1 1 1 0 0 1 1 0 1 0 1

The controller generates this type of code during T1.
Similarly it generates different codes for T2 , T3 and T4 in a machine cycle.




Inst. Register

(Instruction
Decoder)


Controller
IN OUT IN OUT IN OUT IN OUT IN OUT 0 1 0 1 0 0 1 0 1
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MICRO WORD REEGISTER

T1:-

What are the inputs to be tested for the given sate.
The address from the bus will be decoded by the address decoder in the memory which
will be sent to the memory ROM to access the address but it can only read the memory,
but not manipulate.It will be sent to the MICRO WORD REGISTER for data path control.
In the state T1, the instruction will be processed through 3 phases.Firstly it will be
tested,then it would move to the NEXT state and would be executed by controller
OUTPUT.





1 0




ADDRESS
DECODER
Memory(CROM)
Data Path Control Word
TEST NEXT CONTROLLER OUT
-------------
-------------
-
Ready
--------
-----
--------
--
T
2
T
2
T
3
T
4
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9.Data Path Controller:- Microprogrammed










1 0




T
1
:- Address Bus Program Counter These 4 microinstructions can
T
2
:- Control Bus READ form micro routine.
PC PC+1 Sets of micro routine will form
T
3
:- Data Bus Data Memory the routine required for
T
4
:- Inst.register Data Bus executing one instruction.

Generalised State Machine Model:-

INPUT

I NEXT STATE PRESENT
g FUNCTION STATE f
State input Clock
------------------
------------------
--------------
Input
a
b c

Input Logic
Memory Output
Logic
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Let us understand the figure. Let the memory is in state A. Some input must be
tested.Depending on the input the next state of the memory may be B or C. In that state
it generates an OUTPUT. In state A it checks the INPUT and decides what will be the
next state.
The OUTPUT not only depends on the PRESENT STATE but also the INPUT.
Sometimes the OUTPUT is only the function of the PRESENT STATE.
O = f (X , I) (MEALY MACHINE CODE)
When there is no INPUT function then
O = f ( X ) (MOORE MACHINE MODEL)
NEXT = g (X , I)
For instance , for 52 states we need 2
6
= 64 i.e 6-bit code.
Before going forward let us be familiar with the term FLIP-FLOP.
FLIP-FLOP:-
FLIP-FLOP is the smallest building block or the basic element of a sequential circuit that
can be made using logic gates and is available in IC form. The circuit can be made to
change state by signals applied to one or more control inputs and will have one or two
outputs. A flip-flop or latch is a circuit that has two stable states and can be used to store
state information.
Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or
edge-triggered); the simple ones are commonly called latches. The word latch is mainly
used for storage elements, while clocked devices are described as flip-flops. A latch is
level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it
becomes transparent, while a flip flop's output only changes on a single type (positive
going or negative going) of clock edge.
Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay), T
("toggle"), and JK types are the common ones. The behavior of a particular type can be
described by what is termed the characteristic equation, which derives the "next" (i.e.,
after the next clock pulse) output, Qnext in terms of the input signal(s) and/or the current
output, .



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STATE


One of 2
6
OUTPUT



CLOCK

Checking
Checking only F T
Inputs
0/1 MUX 6-bit
Ready code




As long as we have the code , the memory is frozen (i.e) we dont change anything . The
behaviour of the machine doesnt change . When one changes the behaviour of the
machine , it is called FIRMWARE but the hardware components remain the same.



1 0


FF
0



FF
5


ADDRESS
DECODER
CROM(MEMORY)
TEST NEXT OUTPUT
(6)
TEST
LOGIC
------------
------------
---------
---------
--------
T
2
T
3
T
w
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Now let us study the figure.
Firstly the address from the address bus will enter the FLIP-FLOP. In this case the FLIP-
FLOP would send a 6-bit OUTPUT to decode the address in the ADDRESS DECODER.
Then any one of the 2
6
code will be the OUTPUT. The code will be tested in the TEST
LOGIC which indeed will be sent as a signal in 0/1 when the control input is READY. The
OUTPUT of the TEST LOGIC will be considered to be the control input of MUX. In the
NEXT phase the two possibilities (i.e) F or T will be the INPUTS for the
MULTIPLEXER whose OUTPUT will be anyone of them. At last anyone of F or T will
be the OUTPUT for the MUX which will be fetched to the FLIP-FLOP which is also know
as the state generator.
FLIP-FLOP:-
We will study the master slave J-K FLIP-FLOP here
INPUT OUTPUT This is the general format
YJ HZERO Effect of K is to reset
YK HONE Effect of J is to set
YC(CLOCK) Y & H is for naming convention.






















INPUTS PRESENT NEXT
J K STATE STATE
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0


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8.State Machine Deisgn

Master Slave J-K FLIP-FLOP

YJ HZERO
JC
JK HONE

Synchronous System:-If input changes , the OUTPUT may not change.
Asynchronous System:-As soon as input changes , the OUTPUT changes , the state also
may change.
The term Master-Slave is linked with the CLOCK.
1
YC(CLOCK)
0

In the rising edge of the clock the inputs J & K are sensed.Internally FLIP_FLOP will go
through some state change.
In the falling edge of that clock the OUTPUT will be generated.
Master Slave Principle:-
During the rising edge of the CLOCK the inputs are sensed and the systems
OUTPUT is prepared and actually affect the change in OUTPUT during edge of
the CLOCK.





FLIP-FLOP
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Algorithmic State Machine(ASM) chart:-
There must be a controllers OUTPUT to be placed on the address register which the
address register indeed places it on the bus.

AB
00 11



0 0

1 1
01 10



1 0 0 1

1
YJ
0

YC
T1 T2 T3
HONE

HZERO a b

HZERO HONE
YJ.YC
HZERO
YK.YC
HONE
YC YC
a
b
c
d
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Let us study the J-K FLIP-FLOP table. In the table for the PRESENT STATE 0 we can see
that when J is 1 and K is 0 then the NEXT STATE will be 1. And even when J is 1 and K is
1 then also the NEXT STATE will be 1. So the INPUT K doesnt matter for the state
change when the PRESENT STATE is 0. It only depends on the INPUT J.
When the PRESENT STATE is 1 we can see that there is no state change when J is 0 & K
is 0 and when J is 1 and K is 0 . But when J is 0 and K is 1 then the NEXT STATE will be
0. And even when J is 1 & K is 1 then also the NEXT STATE will be 0. So the INPUT J
doesnt matter for the PRESENT STATE 1. IT only depends on the INPUT K.
So in the ASM chart let us assign 2 state variables A and B. Let for the PRESENT STATE
HZERO the two state variables are (00) . Now when YJ and YC both are 0,there will
be no state change. When YJ is 1 and YC is also 1 i.e for the rising edge of the CLOCK,
the INPUTS are sensed and internally there will be some state change. But the state will
remain as HZERO when the two state variables are (01). Next only YC will be checked.
If YC = 1 then it will remain in the same state but when YC = 0 there will be a state
change to HONE.
Now let the 2 state variables are in (11) for the state HONE. We have to check only YK &
YC in this case. As long as both are 0 there will be no state change internally. When YK =
1 and YC = 1 then the INPUTS are sensed and prepared for the OUTPUT but with no
state change. So for state d let the state variables be (10). Only YC will be checked. If
its 1 then it will be on the same state but if its 0 then the state will again be changed to
HZERO.
LINK PATH :-

:- OUTPUT TEST
HZERO YJ.YC
HONE YK.YC




a a a
a b
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9.Controller Design Microprogrammed & Hardwired

Table:-

PRESENT TEST NEXT STATE OUTPUT
STATE YJ YK YC TRUE FALSE HZERO HONE

00 1 0 1 01 00 1 0
01 0 0 1 00 11 1 0
11 0 1 1 10 11 0 1
10 0 0 1 10 00 0 1

CROM

1 of 4


CLOCK
HZERO

HONE
T F YJ
MUX YK
YC
2 (FIRMWARE IMPLEMENTATION)
ADDRESS
DECODER
A
B
TEST NEXT OUT
TEST
LOGIC
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The 2-bit code will go inside the address decoder and one out of the 2
2
= 4 will be
selected in CROM. In the TEST phase there will be 3 control inputs for the TEST LOGIC
and 3 INPUTS which are YJ , YK and YC whose OUTPUT will considered as the control
INPUT for the MUX. In the NEXT phase T & F will be the INPUTS for MUX whose
OUTPUT(2-bit) will depend on the condition of the PRESENT STATE. And the OUTPUT
will be again sent to the state variable CLOCK A & B.
As long as the code is the same, the behaviour will be the same. If we put another code,
the behaviour will be different. Hence it is called as FIRMWARE IMPLEMENTATION.
HARDWARE IMPLEMENTATION:-
Lets study a NAND GATE first.

INPUT OUTPUT
X Y X 1
0 0 1 y True
0 1 1
1 0 1 A Compliment
1 1 0 B
0/1 1/0
(S R Latch)

If X and B both are 1 , then we cant decide.
If both the inputs are not ZERO , then the OUTPUT will act as complement of each other.
But if both the inputs are ZERO , then the OUTPUT will not act as complement of each
other.
S Q

(S R Latch)
R Q
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State Assignment Map:-

B
A 0 1
A - S
A
R
A
Latch
0 B - S
B
R
B
Latch
1


S
A
MAP R
A
MAP S
B
MAP R
B
MAP

B B B B
A 0 1 A 0 1 A 0 1 A 0 1
0 0 YC 0 0 0 YJ.YC 0 0 0
1 0 1 YC 0 1 0 0 1 YK.YC


map-entered vaiable
Link Path:-

:- A : 0 0 :- A : 0 0 :- A : 1 1
0 0 0 1 if Yc=0 1 0
or Yc=1 if YC=0
:- A : 1 1 or YC=1
1 1
Lets study the state variable A in the State Assignment Map. In state a the state
variable A never gets set for both the link paths. So in S
A
it will be 0 and in R
A
it doesnt
matter which is denoted by . In state b the S
A
is set when YC = 0 or YC = 1 and R
A
=
0.
a b
d c
a b
c
d
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Next in state c the state variable A is never reset for both the link paths and S
A

doesnt matter because its already set which is denoted by . Next in state d, S
A
= 0
and R
A
is reset when YC = 0 or YC = 1.
Similarly we can find out for the state variable B.
But we can see that there is a variable YC in the map which is very uncommon in a map.
So to understand the variable in a map we need to understand a Karnaugh map.
Karnaugh Map:-
f(A,B,C) = ABC + ABC + ABC

BC
A 00 01 11 10 AC + BC
0 0 1 1 0 If we fold the map from the central axis,then
1 0 0 1 0 B vanishes which is called as reduced K-map.

B field B field

C
A 0 1
0 0 1 (reduced K-map) same as the above K-map.
1 0 B

f = AC + BC
So from this figure we can find out the state assignment maps SA , RA , SB , RB.

S
A
= Y
C
B
R
A
= Y
C
B
S
B
= Y
J
Y
C
A
R
B
= Y
K
Y
C
A
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The user is not concerned about the states that the states that the processor
undergoes.He is only concerned about the inputs (Y
J
, Y
K
, Y
C
) and the outputs
(HZERO & HONE). It is actually the designer who is concerned about the 4 states
mainly because having state by state approach he will be able to deisgn the system.
Using De-Morgans Law
S
A
= Y
C
.B S
B
= Y
J
.Y
c
.A
S
A
= Y
C
+ B S
B
= Y
J
+ Y
C
+ A
R
A
= Y
C
.B R
B
= Y
K
.Y
C
.A
R
A
= Y
C
+ B R
B
= Y
K
+ YC + A

NAND GATE SYNTHESIS:-

A A . B = A + B NAND gate act as OR GATE
B with its input complemented.

A A . B = A + B
B

A A . B A . B
B

2 1
(EVEN) (ODD)

A NAND GATE which is 2 levels away act as a AND GATE with its input TRUE(not as a
complement).
So a NAND GATE can act as AND , OR , NOT GATE depending on the level.

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The NAND GATE which is ODD levels away from the OUTPUT will act as OR GATE and is
complement of the INPUT.
The NAND GATE which is EVEN levels away from the OUTPUT will act as AND GATE and
is TRUE of the INPUT.
So for S
A
Y
C
Y
C
+ B
B


B
Y
C

Y
C
S
A
HONE

Y
C

B

R
A
HZERO



Y
J

Y
C
S
B

A


R
A


A
Y
K
Y
C
A
A
(NEXT STEP FUNCTION)(DIGITAL SYSTEM ONLY WITH NAND GATE)
A


A
B


B
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The above figure is a digital system with only NAND GATE which is actually a NEXT
STEP FUNCTION. A is usually slave and B is usually master and so is given master-slave
flip-flop name. The OUTPUT of A and A is determined from the INPUTS of B and B .
HONE is generated from A and HZERO is generated from A .

S.A. MAP:- HONE MAP:-

B B
A 0 1 A 0 1
0 0 0 0
1 1 1 1

HZERO MAP:- HONE = A

B
A 0 1
0 1 1 HZERO = A
1 0 0
(From Boolean expression)








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This paper is a clear, comprehensive, and up-to-date presentation of the
organization and architecture of modern day systems mainly on the processors
including some memory and I/O parts. Beside emphasizing the fundamental
principles and the critical role of performance in driving computer design, the
paper also covers Data Path Architecture,Controller,state machine
design,controllers designs-microprogrammed and hardwired.The paper uses
running examples from number of different ,achiness to clarify an reinforce the
concepts being presented.It also includes digitals circuits using only NAND
GATES and Karnaughs maps.
The paper is strictly based on professor S.Ramans (IIT Madras) concepts and
systematic representated notes from NPTEL(National Programme On Technical
Enhanced Learning).
Distinguishing Key Features
Broad , unified description of modern computer systems.
Detailed treatment of bus organistion and micro-programmed
implementation.
Numerous examples of processors activities.
Focuses on processors activities,functions ; stresses the interation of I/O
modules with outside world and the CPU.
The entire paper is devoted to Processor.
Extended and updated treatment of optical memory,CPU.
Companion website.
http://www.nptel.ac.in provides supported material for students and
instructors.





To learn more about memory and I/O Devices please visit the next edition paper.



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