Design Contest Report - FPGA Climatic 2

FPGA Climatic FPGA Climatic
Design Report Design Report

www.digilentdesigncontest.com
FPGA Climatic
Oana Valentina Rusu
rusu_valentina_oana@yahoo.ro
Submitted for the 2014 Digilent Design Contest
Cluj Napoca, Romania
17 May 2014
Advisor: Lecturer eng. Adrian-Vasile Duka PhD
Petru Maior University of Tirgu Mures, Romania
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FPGA Climatic Design Report
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Contents
1.Introduction................................................................................................................................................................ 5
1.1. Abstract...........................................................................................................................................................................5
1.2. Objectives........................................................................................................................................................................5
1.3. Project Summary.............................................................................................................................................................5
1.4. Digilent Products Reuired.............................................................................................................................................!
1.5. "ools Reuired.................................................................................................................................................................!
1.!. Design Status...................................................................................................................................................................#
1.#. $%y t%is &roject' Analysis o( e)isting designs and contributions broug%t....................................................................#
1.*. Re(erence materials.......................................................................................................................................................*
2. Design........................................................................................................................................................................ 9
2.1. Design Overvie+..............................................................................................................................................................,
2.2. -D. Design....................................................................................................................................................................11
2.2.1. A-/0.ite So1 system..............................................................................................................................................12
2.2.1.1. A-/0.ite 2aster 3 AR2 1orte) 24 Processor...............................................................................................1!
2.2.1.2. A-/0.ite Slaves...............................................................................................................................................1!
2.2.1.2. A-/0.ite Decoder and 2ulti&le)er. 2emory 2a&&ing.................................................................................1,
2.2.2. P2od"m& 2odule.................................................................................................................................................1,
2.2.3. 5R Receiver 2odule................................................................................................................................................21
2.2.4. P$2 2odule.........................................................................................................................................................23
2.2.5. "em&6#seg6dis&lay 2odule..................................................................................................................................24
2.3. So(t+are Design............................................................................................................................................................2#
2.3.1. "%e menu dis&lay (unctions...................................................................................................................................2#
2.3.2. "%e -eating Algorit%m...........................................................................................................................................2*
2.3.3. "%e 1ooling Algorit%m and P5D controller.............................................................................................................2,
2.3.4. 7851. 5nterru&t -andling.......................................................................................................................................34
3. Discussions.............................................................................................................................................................. 32
3.1. Problems 9ncountered..................................................................................................................................................32
3.2. 9ngineering Resources :sed ........................................................................................................................................32
3.3. 2ar;etability.................................................................................................................................................................35
3.4. 1ommunity <eedbac; ...................................................................................................................................................35
3.5. 1onclusions ...................................................................................................................................................................35
4. References............................................................................................................................................................... 36
Appendix A : Xilinx Proect ! "D# Design P$rt ! %erilog &odules.................................................................................. 3'
Appendix ( : Xilinx Proect ! "D# Design P$rt ! )c*e+$tics .......................................................................................... 6'
Appendix , : -eil u%ision Proect ! )oft.$re Design P$rt ............................................................................................. 69
Appendix D : #ist .it* Design /lo. ,*$rts.................................................................................................................... 00
Appendix 1 : /P2A ,li+$tic 3o$rd description.............................................................................................................. 09
Abbreviations
FPGA Field Programmable Gate Array ;
HDL Hardware Description Language ;
AC Air Conditioning ;
AX Advanced eXtensible nter!ace;
AP" Advanced Perip#eral "us;
A$" Advanced $race "us;
AH" Advanced Hig# Per!ormance "us ;
A%"A Advanced %icrocontroller "us Arc#itecture ;
&oC &ystem on C#ip ;
' in!rared ;
P(% Pulse (idt# %odulation ;
PD% Pulse Distance %odulation;
uC microcontroller ;
P ntellectual Property ;
PD Proportional ntegrative Derivative ;
'C" 'elay Control "oard ;
PC" Printed Circuit "oard ;
)GA )ideo Grap#ics Array;
*" +eyboard ;
,A'$ - universal async#ronous receiver.transmitter ;
'/ nterrupt 'e/uest;
F&% Finite &tate %ac#ine;
AGC Automatic Gain Control;
1. Introduction
1.1. Abstract
(e live in a dynamic world w#ere tec#nology is developing very !ast0 "ut even a simple device can
ma+e our daily lives easier0
$#e 1FPGA Climatic2 pro3ect is actually a climate control plat!orm based on FPGA0 t would replace
t#e two devices used to control t#e #eating and cooling system 4t#e t#ermostat and t#e AC remote
control5 in our #omes0 Furt#ermore6 it will provide an easier way to control everyt#ing since all t#e
available commands and menus will be s#own on a screen0
1.2. Objectives
$#e main ob3ective o! t#is pro3ect was to create a device w#ic# could be used in our daily lives0
$ec#nically spea+ing6 #ad t#e !ollowing ob3ectives7
Designing t#e #ardware plat!orm and HDL design in )erilog7
ntegrating t#e A'% Corte8 %9 P Core in a &oC system wit# AH"-Lite Perip#erals;
Creating custom &oC system to suite our needs 4 adding and creating custom AH"
perip#eral modules 5;
%odi!ying t#e AH"-Lite )GA module to allow cursor repositioning and screen clearing;
Creating a module !or t#e temperature sensor 4P%od$mp5;
Creating t#e ' receiver module;
Creating a P(% !an control module;
Creating a : segment display module 4 displaying t#e temperature on ;e8ys <=s :
segment display 5;
Designing t#e so!tware part and controlling algorit#ms7
Handling t#e ' receiver interrupt wit# Assembly and C code;
Creating t#e design part 7 s#owing t#e menus on t#e screen and ot#er options;
Creating t#e #eating and cooling control algorit#m;
1.. Project !ummar"

$#e design o! t#is pro3ect is complete and !ully !unctional0 t #as been p#ysically tested in all
conditions0
$#is pro3ect is divided in two parts7
>0 $#e Hardware parts and HDL design w#ic# includes t#e !ollowing )erilog modules 7 t#e A'%
Corte8 %9 Core6 t#e AH"-Lite &oC and custom made )erilog modules 4 !or temperature
sensor6 ' receiver6 P(% control6 : segment display 5;
?0 $#e &o!tware part w#ic# includes t#e menu design and #eating.cooling system control
algorit#ms0
Furt#ermore6 t#is pro3ect design can be applied in practice0 t can be used6 wit# small modi!ications
in modern #ouses6 to replace t#e t#ermostat.air conditioning control0 t could be use as a part or be
e8tended to an 1ntelligent House1 pro3ect0 ,sually6 a basic ntelligent House pro3ect is very e8pensive
and includes t#e !ollowing7 *;X &ystem6 Lig#t control6 Lig#t dim control6 $emperature control6 window
control0 'elative c#eap components were used to prove t#at t#is system can be a!!ordable !or
ordinary people too0
At t#e same time6 it #as to be #ig#lig#ted t#at in t#is pro3ect was designed only t#e control part6 not
t#e cooling or #eating system itsel!0 $#e above mentioned systems will be replaced wit# simple
components6 w#ic# could simulate t#e real ones0
1.#. Digilent Products Re$uired
$#e Digilent products re@uired are7
Product %uantit" Description
;e8ys < &partan-A FPGA4XCALX>A-C&<?B5 > As %ain "oard
Pmod$mp > For measuring t#e temperature
1.&. 'ools Re$uired
Ct#er #ardware products re@uired !or our pro3ect7
Product %uantit" Description
>99 (att incandescent Lig#t "ulb > 'epresenting t#e #eating system
P(% D? mm PC !an > 'epresenting t#e cooling system
'elay PC"s or Grid PC"s ? $o design relay control boards
$&CP BE<E ' 'eceiver <E *HF > As t#e ' receiver
' 'emote Control > ' Control Device
G/X->HF 'elay > For t#e #eating system control
Leg-H 'elay > For t#e cooling system control
?;<D9B ;P; $ransistor ? For 'elay Control "oard
>;B>BE Diode ? For 'elay Control "oard
LID ? For 'elay Control "oard
> * o#ms resistors B For 'elay Control "oard
>9 * o#ms resistors ? For 'elay Control "oard
H9 8 >99 mm breadboard > For an easy circuit trace
>? ) A99 mA power supply > For t#e PC !an
H ) A99 mA power supply > For relays
(ires6 cables6 screws6 lig#t bulb soc+et6 plywood - For t#e rest o! t#e design
Laptop PC > $o load !iles to FPGA
Cn t#e so!tware part t#e re@uirements were7
'ool (sage
Xilin8 &I Design &uite >B0? $o design t#e &oC &ystem and )erilog %odules
*eil u)ision H $o program t#e control algorit#ms6 menu design
!unctionalities and interrupt #andling
Digilent Adept &uite ?0>H0< $o load con!iguration !iles on FPGA board
A'% Corte8 %9 Design &tart %icroprocessor Core
1.). Design !tatus
All !eatures o! t#is pro3ect #ave been implemented and tested in di!!erent situations0 Any problems
w#ic# occurred during t#e implementation and possible improvement will be discussed in a later
section0
n addition6 most o! t#e source code #as been commented and structured0 n some paragrap#s o!
t#is pro3ect report will appear some code se@uences w#ic# will represent t#e illustration !or my
concepts or e8planations0
%oreover6 #ave tried to !it in t#e time-limit wit# t#is pro3ect design0 Future implementations could
be7
t#e possibility to control t#e system !rom distance t#roug# an internet connection 4 consider
using a 'aspberry pi as a web server6 it would be more e!!icient 5;
t#e e8tension o! t#is design to an ntelligent House Pro3ect0
>0:0 *+" '+is Project, Anal"sis o- e.isting designs and contributions broug+t
$#ere were a !ew reasons #ave c#osen to start t#is pro3ect0 First o! all6 wanted to learn
somet#ing new by doing my !irst FPGA pro3ect0 And wanted to discover t#e usage and capabilities o!
an FPGA starting !rom simple to comple8 pro3ects0
&econdly6 designing a use!ul plat!orm !or everyday usage was anot#er goal too0 (it# some small
c#anges we can replace t#e #eating.cooling system !rom our pro3ect board wit# a real #eating system
and an Air Conditioning device available in our #omes0
Furt#ermore6 to #ig#lig#t t#e reasons !or c#oosing to wor+ wit# t#e ;e8ys < board and integrating
t#e A'% Corte8 %9 core to it6 will illustrate t#e pros and cons to using a microcontroller or FPGA
arc#itecture !or developing micro-systems0
>0 FPGA 7
Focuses on parallel e8ecution 4 ideal !or time sensitive processes 5 7 you can #ave numerous
Finite &tate %ac#ines 4 F&% 5 ;
$#e possibility to design your own digital circuits;
$#e possibility to integrate a so!t core in it 4 %icrocontrollers 5;
Hig# cloc+ !re@uency;
Pins can be swappable;
Can connect a lot o! devices and perip#eral to it 4 more t#an <? digital pins6 )GA 6 It#ernet 6
,&" 6 ,&"- ,A'$ communication 5;
Possibility to reprogram t#e con!iguration !ile a!ter a power loss wit#out reloading it;
Power consumption 7 t#ey use more power t#an an usual microcontroller do;
Hard to design circuits;
?0 %icrocontroller 7
Iasy to program 4 in C 6 CJJ 5;
$#ey are low-cost;
Possibility to re-run t#e loaded pro3ect a!ter a power loss wit#out re-loading it;
For comple8 pro3ects6 you need e8pansion s#ields w#ic# can be e8pensive;
Low !re@uency cloc+ 4 it ta+es more processor cycles to process a !ew instructions5;
&imilar designs #ave already been developed and implemented6 despite t#e !act t#at t#ey #ave
several !aults in many o! t#eir aspects0 $#e 1FPGA Climatic2 pro3ect aims to improve t#e e8isting
!eatures and add some new ones at t#e same time0
$#e most common problems !ound at previous designs were7
&low data processing;
Poorly designed ,ser nter!ace;
n!le8ibility and limitations in controlling options;
nability to add more !eatures to t#e design;
n comparison to previous designs and di!!erences between two di!!erent devices 4FPGA vs0 uC56
t#e decision to use a FPGA board !or implementing a %icroprocessor Core P and a &oC were7
Creating comple8 circuits in )erilog 4converting.reading temperature module6 decode.encode
in!rared signal module6 P(% control module6 s#ow at t#e same time t#e current temperature
on t#e :segment display56 so data could be parallel processed0 Cn a microcontroller would be
very complicated to do suc# t#ings6 because instructions on a uC are e8ecuted se@uentially
and would re@uest more time !or processing;
$#e possibility to integrate on t#e FPGA a &oC system;
Iasiness to connect muc# more perip#erals comparing to an ordinary %icrocontroller;
n-"uilt perip#eral devices 7 leds6 switc#es6 : segment display6 )GA6 ,&" and It#ernet ports;
As a novice could program comple8 algorit#ms in C and #andle interrupts wit# a !ew lines o!
code written in Assembly;

$#e !ollowing new improvements were broug#t t#roug# t#is pro3ect7
A practical user inter!ace;
Parallel data processing;
;ew controlling options;
Capability to add new !eatures or devices to t#is plat!orm0
1./. Re-erence 0aterial
$#ere were several boo+s6 datas#eets and articles w#ic# #elped me develop t#e pro3ect7
;e8ys < 'e!erence %anual 7
#ttps7..www0digilentinc0com.Data.Products.;IXK&<.;e8ys<LrmL)?0pd! ;
$&CP BE<E Datas#eet 7 #ttp7..www0vis#ay0com.docs.E?BHD.tsopBE0pd! ;
Pmod$mp 'e!erence %anual;
D&>A?A Datas#eet;
Leg-H 'elay Datas#eet 7 #ttp7..www0punc#lig#t0com.!iles.relayLIG-HLdatas#eet0pd!M
PHP&I&&DNb:Be:ea9c9Abd?9c9a:DHcAADe?caBA> ;
G/X->HF 4 $D9 5 'elay Datas#eet 7 #ttp7..www0c#inarelay0com.yFl.upload.!ile.?9><9H?9.pcb-
relay-$D90pd! ;
FPGA Prototyping by )erilog I8amples - Pong P0 C#u;
A'% Assembly Language- Fundamentals and $ec#ni@ues;
#ttp7..soc0mit0edu.resources0#tml website;
#ttp7..wi+ipedia0org website;
#ttp7..in!ocenter0arm0com.#elp. website ;
#ttp7..www0vis#ay0com.docs. website;
#ttp7..www0arm0com.support.university.ip.inde80p#p website;
2. Design
2.1. Design Overvie1

$#e design o! t#is pro3ect is @uite simple0 $#e ;e8ys < FPGA board is t#e main component0 t is
used !or data processing and to connect ot#er components on it0
As input devices we #ave t#e temperature sensor 4Pmod$%P5 !rom w#ic# we will read t#e
temperature6 and t#e $&CPBE<E ' 'eceiver w#ic# receives t#e signal !rom our remote control0
(e #ave a )GA output device on w#ic# we display t#e menu and control options o! t#e plat!orm0 t
can be any )GA compatible device 4a $) or monitor display56 pre!erable wit# a native resolution
4E998A996 >9?B8:AE etc50
Furt#ermore6 we will #ave some control outputs !or t#e #eating and cooling system0 $#e #eating
system will #ave two states7 C; or CFF0 $#ese states will be set by a relay control board connected
to it0 $#e relay control signal is sent by t#e FPGA board0
For t#e cooling system two control options are provided0 Cne is based on a relay control board w#ic#
turns on and o!! t#e system5 and t#e ot#er one uses P(% control signal 4initially calculated by a
simple PD algorit#m50
n t#e !igures below it will be illustrated t#e !ollowing7 t#e design bloc+ diagram6 t#e wiring diagram
and 'C"=s 4relay control board5 sc#eme0
Figure 1 - The FPGA Climatic Block Diagram
Figure 2 Wiring Scheme of the proect !e"ign
0
Figure # - $ela% Control Boar! Scheme
n t#e ne8t sections it will be discussed in detail t#e HDL design part and so!tware part0
2.2. 2D3 Design
$#e HDL design part contains t#e !ollowing modules7
A2453ite5!oC t#e &oC system based on AH"-Lite protocol; t#is represents t#e
microcontroller component in w#ic# t#e A'% Corte8 %9 core is integrated; t#is module
processes t#e program loaded to control t#e #eating and cooling system w#ic# is
presented as t#e so!tware design part;
irreceiver t#e modules w#ic# decodes t#e received signal and encodes t#e desired
+eys;
Pmod'0P it converts and reads t#e temperature !rom t#e temperature sensor;
temp56seg5displa" displays t#e temperature read !rom t#e sensor on a : segment
display;
P*0 a module w#ic# #andle t#e P(% signal generation 4 it receives a value !rom
t#e PD controller5;

$#e structure 4illustrated in !igure B5 and implementation details o! t#ese components are presented
in t#e !ollowing paragrap#s0 $#ese modules operate in parallel0 $#e FPGA permits t#at operations li+e
decoding t#e ' signal6 converting and reading t#e temperature or displaying t#e temperature on a
:segment display to be processed at t#e same time0 $#e &oC system can receive data 4w#ic# is
already processed5 !rom e8ternal modules 4irreceiver6 Pmod'0P !or e8ample5 at any time0
Figure & 'D( De"ign Top (e)el Structure
?0?0>0 A2473ite !oC !"stem

A2453ite5!oC represents t#e integrated microcontroller arc#itecture in our HDL design part0 t
#as t#e !ollowing inputs and outputs7
's'8 ,sb-'&?<? 'eceive line;
's$8 ,sb-'&?<? $ransmit line;
LID Led ;
relayLout relay output6 controls t#e #eating system 4turns it on.o!!5;
relayLout? relay output6 it is a part o! t#e cooling system control 4turn t#e system on.o!!5;
#sync #oriFontal sync#roniFation signal 4)GA output5;
vsync vertical sync#roniFation signal 4)GA output5;
vgaLred4?7956 vgaLgreen4?7956 vgaLblue4?795 'G" color signals 4)GA output5;
outputLspeed4H795 PD control Abit output value;
temperature4:795 Ebit temperature input value;
remoteLcode4<795 Bbit remote code input value;
ir@Lremote remote control '/ input;
sw> switc# 4 !or AH"-Lite &oC global reset 5;
sw? switc# 4 !las# at Oero signal 5;
ps?d P&? data signal;
ps?c P&? cloc+ signal;
'amC&6 Flas#C&6 %em('6%emCI6 'am,"6 'amL"6 'amCre6 'amAdv6 'amCl+6 Flas#'p6
%emAdr4?A7>56 %emD"4>H7956 'am(ait memory.'A%.!las# control and data signals;

n today=s embedded processors a protocol called A%"A 4Advanced %icrocontroller "us
Arc#itecture5 P>Q is being used as t#e on-c#ip bus !or &oC designs0 ;owadays it is used in a wide
range o! &oC designs6 including application processors used in smartp#ones0 $#is protocol 4wit# its
versions5 is today a standard !or embedded processors because t#ey are well documented and can
be used wit#out royalties0 Also6 it can be considered as a good solution !or t#e modules to inter!ace
wit# eac# ot#er0
$#e A%"A speci!ication ob3ectives7
!acilitate rig#t-!irst-time development o! embedded microcontrollers;
tec#nology independency; it allows to reuse P cores and perip#erals;
!acilitate t#e modular system design;
supports #ig# per!ormance and low power-on-c#ip communication;
$#e A%"A < speci!ication de!ines !our inter!aces7 AX v>096 AP"< v>096 A$" v>096 AH"-Lite v>09;
AH" P?Q is a bus protocol w#ic# #as been introduced in A%"A v?0 t #as t#e !ollowing !eatures7
single edge cloc+ protocol;
split transactions;
several bus masters;
burst trans!ers;
pipelined operations;
single-cycle bus master #andover;
non tristate implementation;
large bus-widt#s;
A simple transaction on t#e AH" bus consists in only two bus cycles7 an address p#ase and a
subse@uent data p#ase0 Access to t#e target device is controlled t#roug# a %,X 4non-tristate56
admitting bus-access to one bus-master at a time0
n our pro3ect design was used t#e A2473ite protocol0 t is a subset o! AH" !ormally de!ined in t#e
A%"A < standard0 $#is subset simpli!ies t#e design !or a bus wit# a single master0 $#e main reason
!or using t#is protocol was to easily integrate t#e Corte8 %9 Core and create or add simple perip#eral
slaves0
$#e main components o! an AH"-Lite &oC based are7
%aster Component;
&lave Components ;
An address decoder;
A multiple8or;
"elow are illustrated t#e !ollowing bloc+ sc#emes7
AH"-Lite %aster &c#eme 4Figure H5;
AH"-Lite &lave &c#eme 4Figure A5;
AH"-Lite generic &oC 4Figure :5;
FPGA Climatic AH"-Lite &oC 4Figure E5;
Figure H s#ows t#e bloc+ arc#itecture o! a %aster controller and t#e inter!acing signals 4trans!er
response6 address and control6 data and global signals56 as described in t#e speci!ication o! AH"-Lite
A%"A < standard0 $#is pro3ect uses as AH"-Lite %aster t#e AR0 Corte. 08 Design !tart core0 $#is
core is connected to several slave modules0 According to AH"-Lite speci!ication6 t#e general
arc#itecture o! t#e slaves is presented in Figure A0 "ased on t#is arc#itecture several slaves #ave
been developed0
Figure : represents a general AH"-Lite &oC arc#itecture6 wit# one %aster module and several
slave modules0 t also illustrates t#e connection between t#em and connection wit# an address
decoder and slave multiple8er0
Figure * - A'B-(ite ma"ter component an! "ignal"
Figure +- A'B-(ite Sla)e component an! "ignal"
Figure , an generic A'B-(ite SoC
Figure - - FPGA Climatic A'B-(ite Soc
"ased on t#e arc#itecture illustrated in !igure :6 t#e &oC s#own in !igure E #as been developed !or
t#is pro3ect0 t is a microcontroller arc#itecture in w#ic# A'% Corte8 %9 #as been integrated0 $#is
&oC system was re@uired to !acilitate some data processing suc# as7
%enu display !unctionalities;
Heating system control algorit#ms;
Cooling system control algorit#ms;
Discrete PD controller calculations;
$#is &oC includes t#e !ollowing slave modules7
AH"?C$'L ;
AH";P,$ ;
)GA Controller ;
%emory Controller it controls t#e P&'A% and FLA&H memories ;
P&?-*" +eyboard controller;
$imer can be used as counter;
,A'$ - communication between FPGA and anot#er device t#roug# ,A'$;
$#e *eyboard6 $imer and ,A'$ modules are optional because currently t#ey are not used in t#e
pro3ect design0 $#ey were included in case o! pro3ect upgrades 4adding control !rom +eyboard or
,A'$6 using timer based !unctions6 etc50 $#ese perip#eral modules were included !rom t#e A'%
Corte8 %9 Design&tart I8ample Design *it 4ID*50 $#e AH"-Lite Decoder6 %ultiple8er and )GA
controller were modi!ied to correspond to pro3ect speci!ication0 A242C'R3 and nputs 4A24I9P('5
represent own creation0 $#ey will be e8plained in section ?0?0>0?0
2.2.1.1. A2473ite 0aster : Arm Corte. 08 Processor

An AH"-Lite master provides address and control in!ormation to initiate read and write
operations0 $#e A'% Corte8 %9 P core PBQ represents t#e %aster Component in t#e AH"-Lite
&oC0 t #as a !ew particularities comparing to ot#er P cores7
t does not generate ",'&$ transaction 4 H",'&$P?79Q will be always <=b999 5;
t never generates loc+ed transactions 4 H%A&$LCC* is always >=b9 5;
All transactions issued are non-se@uential trans!ers 4 H$'A;&P>79Q is ?=b99 idle or ?=b>9
;on &e@uential 5;
t #as a >A line ;)C 4 ;ested )ector nterrupt Controller5 w#ic# is tig#tly coupled wit#
processor core ;
Priority o! t#e '/ can be modi!ied in t#e interrupt vector7
a""ign .$/011223444454444544446 7A$T5.$/6 .8P7TS5.$/6 9B5.$/6 T.:;$5.$/<=
'/ can be #andled by writing code in Assembly or C;

2.2.1.2. A2473ite !laves

An AH"-Lite slave responds to trans!ers initiated by masters in t#e system0 $#e &lave uses t#e
H&IL8 select signal !rom t#e decoder to control w#en it responds to a bus trans!er0
AH"?C$'L and AH";P,$& are two AH"-Lite slave modules created !or data processing0 Cne o!
t#e modules included in t#e )GA controller was modi!ied to improve some !eatures0

A242C'R3 it is a slave module w#ic# receives data !rom t#e master module and assigns it to
outputs7 t#e relays control bits 4relayLout6relayLout?5 and PD controller=s output value
4outputLspeedPH79Q50 &o6 it will receive data on t#e !irst byte o! t#e H(DA$A line o! t#e data trans!er
p#ase 7
always @(posedge HCLK or negedge HRESETn)
begin
if(!HRESETn)
rCTRL <= 8b!!!!"!!!!#
else if(rHSEL $ rH%R&TE $ rHTR'(S)*+)
rCTRL <= H%,'T')-.!+#
$#is slave will send a trans!er response to t#e A'% processor 7 assign HRE',/01T = *b*#
and received value will be assigned to output wires 7 assign CTRL = rCTRL#
$#e number o! controlled outputs can be modi!ied by c#anging t#e rC$'L register6 C$'L output
widt#s0
A24I9P('! it is a slave module w#ic# reads data !rom inputs and sends t#em to t#e processor0
As input lines we #ave7 t#e remote control interrupt line 4ir@Lremote56 t#e remote code data bus
4remoteLcodeP<79Q56 and temperature data bus4temperatureP:79Q5;
$#e inputLdata port is being updates wit# new values7
always @(posedge HCLK2 negedge HRESETn)
begin
if(!HRESETn)
inp34"da4a <= *56!!!!#
else
inp34"da4a <= &(71TS&(#
end
w#ic# will be sent to t#e processor t#roug# H'DA$A line7 assign HRDATA[15:0]=input_data;
Furt#ermore6 t#e interrupt signal is assigned 7 assign inp34s"ir8= &(71TS&()*9+#
$#e number o! input lines can be modi!ied by c#anging t#e inputLdata widt#0
;GA controller it is an AH"-Lite perip#eral w#ic# is responsible !or )GA display0 t contains t#e
!ollowing modules7
vgas"nc module;
vga5console module;
vga5image module;

A )GA port #as !ive active signals 7 #sync6 vsync 6 and 'G" signals0
$#e vgas"nc module PHQ represents t#e sync#roniFation circuit0 t generates timing and
sync#roniFations signals0 Hsync and vsync signals are connected to t#e )GA monitor to control t#e
#oriFontal and vertical scans0 $#e signals are decoded !rom t#e internal counters6 w#ose outputs are
t#e pi8elL8 and pi8elLy signals0$#ese signals indicate t#e relative positions o! t#e scans6 and speci!y
t#e location o! t#e current pi8el0
$#e vgaLconsole module is our interest actually0 t is t#e module representing t#e te8t generation
circuit0 Here we can modi!y7
t#e screen tiles7 lo:alpara; <'="= = >!# ??(3;ber of 6ori@on4al
4iles
lo:alpara; <'="/ = *!# ??(3;ber of 4ile rows
assign color !or te8t 7
assign fon4"rgb = (fon4"bi4) A 8b******** . 8b!!!!!!!!#
??w6i4e.bla:B
assign fon4"inC"rgb=(fon4"bi4)A 8b!!!!!!! . 8b!!!!!!!!#
??bla:B.bla:B
add or edit pressed-+ey logic;
cursor positioning;
n t#is module #ave made t#e !ollowing modi!ications7
#ave developed an invisible cursor;
#ave provided custom cursor repositioning7 in t#e cursor and pi8el &tate %ac#ine anot#er
condition was added0 ! we #ave to display t#e ><
t#
c#aracter !rom t#e -ont5rom module 4 Rr
carriage return5 it will automatically reposition t#e cursor at t#e initial position 496957
//State Machine f! cu!s! and pi"e# $uffe!
a#%a&s ' (psedge c#)* negedge !esetn+
$egin
if(,!esetn+
$egin
cu!_"_!eg -= 0;
cu!_&_!eg -= 0;
end
e#se if(din==./$0001101+ // if %e ha0e cha!acte! 11 ( ca!!iage !etu!n
+ t disp#a&
$egin
cu!_"_!eg -= 0;
cu!_&_!eg -= 0;
end

e#se
$egin
cu!_"_!eg -= cu!_"_ne"t;
cu!_&_!eg -= cu!_&_ne"t;
pi"e#_"1 -= pi"e#_";
pi"e#_"2 -= pi"e#_"1;
pi"e#_&1 -= pi"e#_&;
pi"e#_&2 -= pi"e#_&1;
end
end
$#e dual5port5memor" ram is t#e memory w#ic# contains t#e te8t to display on t#e screen0
$#e -ont5rom module contains t#e >?E c#aracters o! t#e A&C code0 n our case t#e used !ont is
E-by->A 4 E tiles 6 >A rows 57
//cde "02
11/h020: data = 3/$00000000; //
11/h021: data = 3/$00000000; //
11/h022: data = 3/$01111110; // 444444
11/h021: data = 3/$11111111; // 44444444
11/h025: data = 3/$11011011; // 44 44 44
11/h025: data = 3/$11111111; // 44444444
11/h026: data = 3/$11111111; // 44444444
11/h02.: data = 3/$11000011; // 44 44
11/h023: data = 3/$11100111; // 444 444
11/h027: data = 3/$11111111; // 44444444
11/h02a: data = 3/$11111111; // 44444444
11/h02$: data = 3/$01111110; // 444444
11/h02c: data = 3/$00000000; //
11/h02d: data = 3/$00000000; //
11/h02e: data = 3/$00000000; //
11/h02f: data = 3/$00000000; //

$#e above mentioned modi!ications were re@uired in t#e vga5console module !or a better
appearance and t#e implementation o! t#e clear5screen<= !unction0 $#e logic be#ind t#is !unction is
t#e !ollowing7 w#en t#e ><
t#
A&C -ont5rom c#aracter is displayed t#e cursor is repositioned to its
initial position0 $#en t#e dualLport vga memory will be 1rewritten1 wit# empty c#aracters 4spaces5 and
t#en t#e cursor will be repositioned again by displaying again t#e ><
t#
c#aracter0 $#e !unction is being
implemented in t#e so!tware part6 but it=s code is s#own below7
0id c#ea!_sc!een(+8
p!intf(9:c9*11+;
f!(i=0;i-3;i;;+
p!intf(9
9+;
p!intf(9:c9*11+;
<
$#e vga5image module is use!ul i! we want to draw an image to t#e screen0 Also6 it #as a
dual5port5ram memory module too0

2.2.1.. A2473ite Decoder and 0ultiple.er. 0emor" 0apping
$#e decoder is t#e component w#ic# decodes t#e address o! eac# trans!er between t#e master
and a slave0 t provides a select signal !or t#e slave t#at is involved in t#e trans!er0 Furt#ermore6 it
provides a control signal to t#e multiple8er0 A decoder is always re@uired i! we #ave more t#an one
slave in our &oC design0 $#e multiple8or is re@uired to multiple8 read data bus and response signals
!rom slaves to master0
%emory mapping !or eac# perip#eral it is done according to t#e table >0
!lave 9ame !tart Address >nd Address !i?e Interrupt
Capabilit"
0emor" 989999L9999 9899FFLFFFF >A %" ;C
A242C'R3 98H999L9999 98H9FFLFFFF >A %" ;C
(AR' 98H>99L9999 98H>FFLFFFF >A %" KI&
A24I9P('! 98H?99L9999 98H?FFLFFFF >A %" KI&
;GA 98H<99L9999 98H<FFLFFFF >A %" ;C
A24@4 98HB99L9999 98HBFFLFFFF >A %" KI&
'imer 98HH99L9999 98HEFFLFFFF >A %" KI&
Ta3le 1 Peripheral :emor% :apping
2.2.2. Pmod'mp module
Pmodtmp module reads t#e temperature !rom t#e sensor0 t #as
t#e !ollowing inputs and outputs7
cloc+ cloc+ signal !rom >99%HF cl+;
cloc+Lconv a cloc+ signal !or t#e sensor w#ic# is manually
generated t#roug# eac# state o! t#e sensor state mac#ine
4see !igure >?5;
rstLn reset pin6 it is active on logic 192;
d@ bidirectional wire 4 it sends t#e commands to t#e sensor
and receives t#e temperature bits 5;
tempLout4:795 Ebit temperature output;
$#e Pmod$mp PAQ perip#eral is an inter!ace board !or t#e Dallas &emiconductor D&>A?A <-wire
digital t#ermometer and t#ermostat0 $#is sensor is capable o! transmitting t#e temperature wit# a >?-
bit resolution between -HH and J>?H degrees Celsius0 For t#is pro3ect only E bits are used !rom t#e
temperature register0 "it >> 4t#e sign bit5 and bits 96 >6 ? 4w#ic# correspond to ?6 < and B decimal part5
are not used0 &ince t#e pro3ect is intended !or domestic use6 it is assumed t#at t#e measured
temperature is always positive6 lower t#an >99 degrees and only one decimal part 4e0g0 ?<0H C5 is
re@uired0 n t#e !ollowing !igure t#e red rectangle mar+s t#e used bits 4!igure >957
Figure 14 DS1+2+ temperature regi"ter
Figure > Pmo!T:P Block
During a temperature read cycle we will send two con!iguration registers on t#e d@ wire 4w#ic# is a
tri-state in-out pin50 $#ese con!iguration register 4> byte long5 corresponds to t#e !ollowing commands7
start convert 498AA5 and read temperature 498H>50$#ese are serial transmitted starting wit# L&"0 $#e
con!iguration register P:Q #as t#e !ollowing structure 4!igure >>57
Figure 11 Configuration regi"ter

All communication wit# t#e D&>A?A are initiated by driving n'&$ signal #ig#0 Driving n'&$ low
terminates communications and causes D/ to go to a #ig#-impedance state0 n'&$ must be toggled
low a!ter every communication se@uence to ensure t#at subse@uent commands are recogniFed by t#e
sensor0 (#en writing to t#e D&>A?A data must be valid during rising edge o! t#e cloc+0 Data !rom
D&>A?A can be read on !alling edge o! cloc+ signal and it remains valid t#roug# t#e !ollowing rising
edge0
$#e n'&$ will be #ig# and t#en we will set t#e con!iguration register to &tart Convert 4H>#5 t#roug#
d@ line0 t remains in #ig# impedance until we send t#e 'ead $emperature command0 'ig#t a!ter t#at
we will start to read t#e temperature on eac# !alling edge o! t#e cloc+ signal0 For a better
understanding6 see !igure >? 4describes <-wire communication timing diagrams !rom t#e D&>A?A
re!erence manual5 and !igure >< 4w#ic# represents t#e generic &tate %ac#ine !or our module50
$#is module per!orms only one conversion and read temperature cycle once0 (e #ave to drive reset
#ig# a!ter eac# cycle0 $#at is t#e reason #ave implemented an autoreset module0 $#e autoreset
module 4included in pmodtmp module5 creates a 90H HF cloc+ signal 4a period o! ? seconds50
Figure 12 # ?ire communication timing !iagram
Figure 1# Pmo!T:P State :achine
2.2.. IR receiver module
$#e irreceiver module decodes t#e ' signal received !rom t#e
remote control0 t #as t#e !ollowing inputs and outputs7
cloc+ >99 %HF cloc+ signal ;
remoteLin remote signal;
reset reset input ;
ir@Lsignal it sends an '/ signal to t#e &oC system;
remoteLout4<795 sends an B bit code to t#e output
4represents t#e +ey code5;
$#e ' receiver used in t#e pro3ect design is a $&CPBE<E <E
+HF ' receiver0 $&CPBE<E is a AGC? legacy receiver6 used !or
long burst remote controls0 t is not so recommended because it can deliver poor results in some
environments0
Figure 1& irrecei)er 3lock
$#e code w#ic# is sent !rom t#e remote control #as t#e ;IC ' !ormat0 $#e ;IC !ormat PEQ uses
PD% 4Pulse Distance %odulation5 tec#ni@ue0 t is based on varying t#e pulse duty cycle !or logic 1>2
and 192 w#ile +eeping t#e pulse active period constant0 $#e period !or eac# logical state7 logic 192-
>0>? ms and logic 1>2 ?0?H ms0
$#e ;IC protocol PDQ uses an E-bit command and an E-bit address lengt# !or eac# trans!er0 $#e
command and address bits are trans!erred a second time wit# all bits inverted !or increased reliability0
&o6 t#e code transmitted by remote control s#ould contain7 a Dms #eader code6 a B0H ms o!! code6 an
E-bit address code6 an E-bit inverse address code6 an E-bit data code and anot#er E-bit inverse data
code0 $#e ;IC !ormat code is described in t#e !ollowing sc#eme 4!igure >H57

Figure 1* 8;C .$ format

$&CPBE<E inverts t#e input signal6 so it will be active in t#e low logic state0 (e #ave to e8amine
w#en it goes down to logic low state0 ! it is6 we #ave to e8amine Dms later to see i! t#e logic state is
low 4we will return bac+ to t#e monitoring state50 Ilse we will e8amine B0H ms later and i! we #ave
logic #ig# state we will return to monitoring state6 ot#erwise we will start reading t#e address bits6 data
bits and inverse data bits0
$wo logic states o! data bits can be distinguis#ed7 i! t#e signal is logic low and >0? ms later t#e
signal will be low6 t#en data bit will be 90 Ilse6 data bit will be >0 n t#at case6 we #ave to e8amine t#e
line ?0? ms later because a!ter >0? ms t#e line will be low every time6 eac# logic state starts wit# logic
low0 A state mac#ine was implemented !or decoding t#e remote code 4see !igure >A50
$#e address bits and data bits are essential in +ey assigning0 Address bits actually represents t#e
Device Address and command code represents one o! t#e +eys pressed0 Iac# +ey #as assigned a B
bit code0 $#e !ollowing table contains t#e address bits6 data bits and assignment code !or eac# remote
control +ey 4table ?57
@e" 9ame Address Code Data Code ;alue Assigned
Cn.C!! >>>>9>>>9999>999 999>>9>> : 49>>>5
A >>>>9>>>9999>999 999>>>>> > 4999>5
" >>>>9>>>9999>999 999>>>>9 ? 499>95
C >>>>9>>>9999>999 999>>9>9 < 499>>5
C >>>>9>>>9999>999 99999>99 H 49>9>5
,p >>>>9>>>9999>999 99999>9> A 49>>95
Down >>>>9>>>9999>999 99999999 B 49>995
Le!t >>>>9>>>9999>999 9999>999 E 4>9995
'ig#t >>>>9>>>9999>999 9999999> D 4>99>5
Ta3le 2 9e% a""igning
Figure 1+ irrecei)er State :achine
2.2.#. P*0 module
$#is module is responsible !or generating a P(% signal
!or our PC !an0 t #as t#e !ollowing inputs and outputs7
cloc+ input cloc+ signal 4>99%HF5;
inputLspeed4H795 input speed received !rom t#e
AH"-Lite &oC0 $#is value it is calculated by a discrete
PD controller programmed in C0
pwmLout P(% signal output;
outputLled4H795 displays on leds t#e value received
!rom t#e PD controller;
"e!ore generating t#e P(% signal we #ad t#e !ollowing considerations7 de!ining t#e signal period
and duty cycle;
Figure 1, PW: 3lock
(e #ave to determine t#e period wit# t#e !ollowing !ormula7
P 0 t @ fpga5freAuenc%= B1C
?here P - the perio! 6 t time=
n our case6 ;e8ys<=s !re@uency cloc+ is >99 %HF and c#ose to #ave an > ms period7
P 0 4D441@144 444 444 0 144 444= B2C
During t#e > ms period o! t#e P(% signal t#e signal will #ave a logic > on period proportional to
duty cycle 0 $#e duty cycle we will #ave two parameters7 stepLdelay and inputLspeed0nputLspeed is
a variable parameter0 t is a value on a Abit bus received !rom t#e AH"-Lite &oC 4an output value
computed by a discrete PD controller50 &tepLdelay is a constant0 ts value represents t#e ratio
between signal period 4P5 and t#e ma8imum values we can #ave as input value0
"tep5!ela% 0 PESC 4<5
&o6
"tep5!ela%0144 444 E +& 0F1*+4= B&C
For our signal period we need a register counter w#ose siFe can be determined so7
counter5?i!th0log2BPC 0logB144 444C F 1, 3it" B*C
$#e signal itsel! will be determined so7 t#e pwmLout signal will be logic #ig# state as long as our
counter reac#es t#e stepLdelaySinputLspeed value0 $#en it will drive low until t#e counter reac#es
>999990

2.2.&. 'emp56seg5displa"

t is use!ul to display t#e current temperature on t#e ;e8ys<=s :segment display0 t #as t#e !ollowing
inputs and outputs7
tempLin4:795 E bit temperature value;
cl+ cloc+ signal 4>99%HF5;
segout4A795 6 point 6 an4<795 : segment display outputs;
Figure 1- - temp5,"eg5!i"pla% 3lock "cheme
$#is module wor+s independently to processor control0 t is based on a time-multiple8ed seven-
segment display0 Furt#ermore t#e !ollowing modules were built !or t#is !unctionality7
temp5value receives t#e current temperature !rom an Ebit line and it divides it in tens6 units
and decimal parts0 $#e binary code is trans!ormed in a "CD value 4see Figure >D5; Cnly t#e
units and tens value are calculated so0 $#e decimal part and degree sign are assigned as
s#own by t#e !ollowing code7
a#%a&s '4 $egin
case (te=p_in[0]+
1/$0: $egin
deci=a#=5/$0000; // >e!
end
1/$1: $egin
deci=a#=5/$0101; // fi0e
end
endcase
end
assign deg!ee=5/$1100; // deg!ee sign (?+
Figure 1> B.8 to BCD output
digitmu. is a module w#ic# receives an input value 4tens6 units6 decimal part or degree sign5
and will transmit at once only one digit to output P>9Q0
$#e digits will be s#own on t#e : segment display wit# an : segment decoder 4 represented by
displa"6seg module5 ;
digitselcounter represents a module w#ic# generates a cloc+ signal wit# ? cascaded
counters and sends as output B values w#ic# corresponds to eac# individual :seg digit 4?=b99
!or t#e !irst digit6 ?=b9> !or t#e second6 ?=b>9 !or t#e t#ird and ?=b>> !or t#e last one50
mu.select6seg module allows to display one digit at a time 4see !igure ?957
a#%a&s '4
$egin
case(se#ectin+
2/$00 : an = 5/$1110;
2/$01 : an = 5/$1101;
2/$10 : an = 5/$1011;
2/$11 : an = 5/$0111;
defau#t : an = 5/$0000;
endcase
end
!urt#ermore6 we #ave to display a point between t#e units and decimal part digits 7
a#%a&s '4
$egin
case(se#ectin+
2/$10 : pint =1/$0;
defau#t : pint =1/$1;
endcase
end
Figure 24 Time multipleGe! "e)en-"egment !i"pla%
2.. !o-t1are Design
$#e so!tware parts are written in two programming languages7 A;& C and A'% Assembly0
$#e pro3ect itsel! contains B !iles7
C%9-D&0# #eader !ile 6 it contains t#e perip#eral memory map ;
retarget0c contains t#e implementation o! some !unctions used to display t#e te8t;
cm9dsasm0s contains t#e instructions w#ic# #andle t#e interrupt vector;
%yProgram0c - contains !unctions used !or menu display6 #eating.cooling algorit#ms
described in t#e !ollowing sections;
2..1. '+e menu displa" -unctions
n t#is part we #ave !our !unctions w#ic# deal wit# displaying a interactive menu on t#e screen7
void s#owLmenu45 displays t#e main menu wit# a cursor inline wit# t#e selected option;
void optionsLmenu45 displays t#e 1Cptions2 menu; i! we navigate on t#ose lines t#e menu will
be 1repainted2 by calling t#e s#owLoptionsLmenu45 !unction0 ! we want to increase or
decrease a value at t#e selected option 6 t#e menu will be repainted by calling t#e
optionLmenuLmodi!ied 4int increase5 !unction;
n !igure ?> we #ave some screen captures0

Figure 21 Screen capture"
A distinct !unction is called w#en entering cooling.#eating mode 4#eatingLmode45 or coolingLmode45
!unctions57 setLmode450 $#is !unction dispays t#e current temperature and #elps t#e user to set a
desired temperature0 $#e system waits !or t#e user to press a button0 $#e desired temperature will be
increased.decreased by pressing up.down +eys0 ! we press t#e o+ button it will call t#e correspondent
control !unction7 applyLcooling45 or applyL#eating450 ! t#e on.o!! button was pressed6 it will abort t#e
current operation and return to t#e main menu0 &ome !lowc#arts submitted in t#e A-lo1c+arts !older
can be analyFed !or a better understanding0
2..2. 2eating Algorit+m
(#en t#e #eating mode is selected6 t#e current temperature is s#own on t#e screen and a new
setpoint 4desired temperature5 can be introduced0 A!ter t#at it will call t#e applyL#eating45 !unction
w#ic# contains t#e #eating algorit#m 4see !igure ?? !or t#e program diagram50
n t#e #eating process we #ave < states7
acti)e5heating it compares t#e current temperature wit# t#e setpoint0 ! current temperature
is lower t#an t#e setpoint6 it will turn on t#e #eating system; ot#erwise it will turn o!! t#e #eating
system and enter t#e pauseL#eating state;
pau"e5heating it bac+ground compares t#e current temperature wit# t#e setpoint0 ! t#e
current temperature is t#res#oldLvalue degrees lower t#an t#e setpoint 6 it will enter t#e
activeL#eating state;
eGit5heating w#et#er we are in activeL#eating or pauseL#eating states6 we can abort t#e
#eating process at any time by pressing t#e on.o!! button0 t will return to t#e main menu;
$#e t#res#old value !or eac# mode is set at ? by de!ault0 $#ese values can be modi!ied by entering
t#e options menu0 $#ey are s#own as Heating %ode $#res#old and Cooling %ode $#res#old on t#e
screen 4see !igure ?>5;
Figure 22 'eating algorithm
2... Cooling Algorit+m. PID controller.
$#is !unctionality be#ave opposite to t#e #eating process 4see !igure ?<50 $#e algorit#m is similar6
t#e only di!!erence is t#at we #ave a PD controller too0
Cooling process states7
activeLcooling it compares t#e current temperature wit# t#e setpoint0 ! current temperature
is #ig#er t#an t#e setpoint6 it will turn on t#e cooling system; ot#erwise it will turn o!! t#e
cooling system and enter t#e pauseLcooling state;
pauseLcooling it bac+ground compares t#e current temperature wit# t#e setpoint0 ! t#e
current temperature is t#res#oldLvalue degrees #ig#er t#an t#e setpoint 6 it will enter t#e
activeLcooling state;
e8itLcooling w#et#er we are in activeLcooling or pauseLcooling states6 we can abort t#e
cooling process at any time by pressing t#e on.o!! button0 t will return to t#e main menu;
Figure 2# Cooling Algorithm

A PD controller P>>Q is a control loop !eedbac+ mec#anism 4controller5 widely used in industrial
control systems0 t calculates an error value as t#e di!!erence between a measured process variable
and a desired setpoint0 $#e controller attempts to minimiFe t#e error in outputs by ad3usting t#e
process control inputs0
$#e PD controller algorit#m contains t#ree main bloc+s7
Proportional bloc+ 4P5 depends on t#e present error;
ntegral bloc+ 45 t#e accumulation o! past errors;
Derivative bloc+ 4D5 a prediction on !uture errors6 based on current rate o! c#ange;
$#e weig#ted sum o! t#ese t#ree actions is used to ad3ust t#e process via a control element 4!an
speed in our case57
(#ere7
- e error 4 di!!erence between setpoint and current temperature5;
- t time;
- *p proportional gain;
- *i integral gain;
- *d derivative gain;
- - variable o! integration 4 ta+es on values !rom time 9 to t#e present t 5;
n our design6 a discrete PD controller was implemented0 $#e PD parameters 4*p6*i6*d5 were set
manually0 $#e values were determined e8perimentally 4*p >96 *i 90>6 *d >50 'easons !or
c#oosing t#ese values7
$#e proportional gain #as a #ig#er value because t#e !an speed must be proportional wit# t#e
temperature di!!erence 4error5 in a temperature interval;
n a time interval t#e current temperature may remain constant and could not reac# so easy
t#e setpoint0 $#e proportional gain will increase in time t#e speed value;
$#e derivative gain is #as a small value to #ave slig#t decrease o! t#e !an speed0 $#is bloc+ is
not as important as t#e ot#er ones0
2..#. 9;IC. Interrupt 2andling.
Corte8 %9 Design &tart supports seven e8ception types7
'eset Processor reset input is asserted;
HardFault e8ception can be any type o! !ault occurred 4e0g0 bus !ault or unde!ined
instruction5;
;% ;on-%as+able nterrupt occurred;
'/ '/ nterrupts occurred;
Pend&) &o!tware Generated interrupt;
&)Call e8ecution o! a &)C instruction;
&ys$ic+ internal system timer caused interrupt;
Iac# e8ception #as associated an e8ception number6 vector address and priority level0
;)C 4;ested )ector nterrupt Controller5 is t#e &oC interrupt controller0 t #as a ;% 4;on
%as+able nterrupt5 and >A prioritiFed interrupt lines0 ;)C is tig#tly coupled wit# our processor
core 4Corte8 %950
n !igure ?B6 we #ave a sc#eme o! t#e )ector $able and e8ception #andling P>?Q0$#e vector table
contains t#e Handler vector addresses and initial value o! t#e %ain &tac+ Pointer 4%&P50 n t#e
case o! an e8ception t#e core will read t#e vector #andler address !or t#e e8ception !rom t#e
vector table and branc#es to t#e #andler0

Figure 2& 'an!ler Hector
n our pro3ect design we use t#e '/ received !rom t#e remote control by pressing t#e C;.CFF
button0 t is represented by ;P,$&L'/ in t#e AH"LLiteL&oc system and it is t#e t#ird '/ !rom t#e
'/ vector6 rig#t a!ter t#e +eyboard '/0 n t#e )ector $able ;P,$&L'/=s #andler #as address
98BE 4corresponds to nterrupt T? Handler )ector entry50
$o add and #andle t#is interrupt we #ad to !ollow !our steps7
Assigning an entry in t#e '/ bus !rom t#e AH"LLiteL&oC module7
assign &RD = E*9b!!!!"!!!!"!!!!21'RT"&RD2INPUTS_IRQ2KF"&RD2T&<ER"&RDG#
Adding an entry to t#e )ector $able 4in cm9dsasm0s Assembly !ile50 ;ote7 t#e entry must
correspond wit# t#e entry !rom t#e '/ bus mentioned earlier0 &o6 our interrupt will #ave
nterrupt T? Handler )ector entry6 rig#t a!ter +eyboard '/ 7
,C, SysTi:B"Handler
,C, Ti;er"Handler
,C, KF"Handler
DCD Input_Handler
,C, 1'RT"Handler
,C, !
,C, !
(riting t#e interrupt #andler 7

&np34"Handler 7R0C
E=70RT &np34"Handler
&<70RT &(71T"&SR
71SH ER!2LRG
FL &(71T"&SR
707 ER!27CG
E(,7
(riting t#e C code !or t#e &' 4nterrupt &ervice 'outine5 !unction6 w#ic# is in our case is
;P,$L&'450 t #elps us initialiFe t#e climate control system and turn it on.o!!7
Coid &(71T"&SR()E
if((ir":ode)==-)E
on"off=!on"off#
if(on"off==4r3e)
43rn"on"f3n:4ion()#
else if(on"off==false)
43rn"off"f3n:4ion()#
end()#
G
G
. Discussion
.1. Problems >ncountered

During t#e pro3ect implementation6 #ave encountered a !ew minor problems w#ic# #ave been
solved @uic+ly0 %ost o! t#em were caused by lac+ o! e8perience and documentation0
.2. >ngineering Resources (sed
For t#e pro3ect implementation6 t#ere was no need !or ot#er resources ot#er t#an t#e resources
mentioned in section >0H0
For documentation part were used7
$inyCAD 7 !or designing t#e 'C" s+etc#;
P#otos#op C&H evaluation 7 !or certain diagrams;
spent about <99 #ours to develop t#e pro3ect and t#is interval includes7
Learning )erilog basics;
Learning #ow to integrate AR0 Corte. 08 IP core and creating a custom A2473ite !oC
system;
Creating AH"-Lite Perip#erals 7 A24I9P(' and A242C'R3;
Developing t#e ot#er )erilog speci-ic modules 4!or reading t#e temperature 6 decoding '
signal 6 generating P(% signal 6 displaying temperature on a : segment display5;
Developing t#e so!tware part in C 4cooling and +eating algorit+ms 6 user inter-ace
-unctions5 and Assembly 4interrupt +andling5;
Hardware component design and assembling;
%a+ing t#e pro3ect documentation;
Ct#er improvements;
n t#e !ollowing table will be provided some design summary o! t#e FPGA usage0
Device (tili?ation !ummar" B7C
!lice 3ogic (tili?ation (sed Available (tili?ation 9ote<s=
;umber o! &lice 'egisters >6B:E >E6??B EU
;umber used as Flip Flops >6BAD
;umber used as Latc#es E
;umber used as Latc#-t#rus 9
;umber used as A;D.C' logics >
;umber o! &lice L,$s H6?EE D6>>? HEU
;umber used as logic B6H:> D6>>? H9U
;umber using CA output only <6E>>
;umber using CH output only ??A
;umber using CH and CA H<B
;umber used as 'C% 9
;umber used as %emory A:< ?6>:A <9U
;umber used as Dual Port 'A% AAB
;umber using CA output only AH?
;umber using CH output only 9
;umber using CH and CA >?
;umber used as &ingle Port 'A% 9
;umber used as &#i!t 'egister D
;umber using CA output only ?
;umber using CH output only 9
;umber using CH and CA :
;umber used e8clusively as route-t#rus BB
;umber wit# same-slice register load <B
;umber wit# same-slice carry load >9
;umber wit# ot#er load 9
;umber o! occupied &lices >6E?< ?6?:E E9U
;ummber o! %,XCKs used <D? B6HHA EU
;umber o! L,$ Flip Flop pairs used H6H<9
;umber wit# an unused Flip Flop B6>HD H6H<9 :HU
;umber wit# an unused L,$ ?B? H6H<9 BU
;umber o! !ully used L,$-FF pairs >6>?D H6H<9 ?9U
;umber o! uni@ue control sets >AD
;umber o! slice register sites lost
to control set restrictions
:E< >E6??B BU
;umber o! bonded C"s D: ?<? B>U
;umber o! LCCed C"s D: D: >99U
;umber o! 'A%">A"(I's <? <? >99U
;umber o! 'A%"E"(I's 9 AB 9U
;umber o! ",FC?.",FC?L?CL*s 9 <? 9U
;umber o! ",FC?F".",FC?F"L?CL*s 9 <? 9U
;umber o! ",FG.",FG%,Xs < >A >EU
;umber used as ",FGs <
;umber used as ",FG%,X 9
;umber o! DC%.DC%LCL*GI;s 9 B 9U
;umber o! LCGC?.&I'DI&?s 9 ?BE 9U
;umber o! CDILAK?.CD'P?.CD'P?L%C"s 9 ?BE 9U
;umber o! CLCGC?.C&I'DI&?s 9 ?BE 9U
;umber o! "&CA;s 9 B 9U
;umber o! ",FHs 9 >?E 9U
;umber o! ",FPLLs 9 E 9U
;umber o! ",FPLLL%C"s 9 B 9U
;umber o! D&PBEA>s 9 <? 9U
;umber o! CAPs 9 > 9U
;umber o! %C"s 9 ? 9U
;umber o! PCLCGC&Is 9 ? 9U
;umber o! PLLLAD)s 9 ? 9U
;umber o! P%)s 9 > 9U
;umber o! &$A'$,Ps 9 > 9U
;umber o! &,&PI;DL&K;Cs 9 > 9U
Average Fanout o! ;on-Cloc+ ;ets H0>?
Ta3le # FPGA 7"age Stati"tic"
.. 0arDetabilit"
$#is system could be easily integrated in a real-li!e system wit# minor modi!ications 4besides some
so!tware twea+s6 t#e lig#t bulb and PC !an will be replaced by a #eating unit6 respectively AC unit50
.#. Communit" FeedbacD
#ave posted on t#e !ollowing !orums7
!orums08ilin80com6
eevblog0com.!orum.6
!orums0#ac+aday0 com6
community0arm0com6
did not receive a solid !eedbac+ !rom t#e community6 maybe because t#e pro3ect t#eme is
common in everyday li!e use0 Cn t#e eevblog site #ave received a !ew answers0 &ome members
recommended to use a microcontroller instead o! FPGA0 Cne user went !urt#er and suggested a
speci!ic microcontroller 4Paralla8 Propeller P><Q - a power!ul microcontroller6 wit# eig#t <?-bit '&C
CP, cores6 w#ic# #as some special Vvideo registersV !or use in generating PAL6 ;$&C6 )GA6 servo-
control6 or ot#er timing signals 50 Anot#er recommendation was to use a $&CP<BB<E or $&CPBB<E
instead o! my $&CPBE<E ' 'eceiver0 $#e $&CPBE<E ' receiver is an AGC? legacy receiver and
could cause trouble in some +ind o! environments0
Cn t#e ot#er #and6 #ave received positive !eedbac+ !rom persons w#o #ad a !ace-to-!ace contact
wit# my pro3ect design0 #ad t#e !ollowing recommendations 4w#ic# #ave implemented57
Finding a met#od to 1erase2 t#e te8t !rom t#e screen 4creating a clear screen !unction w#ic#
#ave e8plained it in section ?0?0>0?50
Displaying an interactive menu w#ere could navigate wit# arrows6 wit#out entering in a
mode wit# A6 " or ot#er +ey buttons; in t#e initial p#ase could enter in #eating or cooling
mode by pressing A or " button0
Adding t#res#old values to an option menu; a t#res#old value in our case represents a value
at w#ic# t#e #eating.cooling system will start0 For e8ample6 i! t#e t#res#old value set !or t#e
#eating system is <6 t#e #eating process will e8it passive and enter active state w#en t#e
current temperature is < degrees lower t#an t#e setpoint0 $#e cooling process be#aves
similarly 4it will enter t#e active state w#en t#e current temperature is < degrees #ig#er t#an
t#e setpoint50 Iac# mode #as its own t#res#old value; t#is remains valid until turning o!! t#e
w#ole system 4it will reset t#res#old values to initial values50
Displaying continuously t#e current temperature on t#e ;e8ys<=s :segment display; !or a
general user6 it is very #elp!ul to see t#e current temperature at all time6 wit#out entering t#e
menu displayed on t#e )GA monitor0
.&. Conclusions
FPGA climatic is a pro3ect t#at can be easily implemented in our daily lives0 #ave demonstrated
t#e reason !or c#oosing ;e8ys < FPGA board and implementing t#e Corte8 %9 Core P0
$#e !ollowing goals #ave been ac#ieved7
Learning )erilog basics;
ntegrate A'% Corte8 %9 Design &tart P core and creating a custom AH"-Lite &oC system
wit# perip#erals;
Developing ot#er )erilog speci!ic modules 4 !or temperature measuring and display6 '
decode6 P(% signal generation5;
Developing clearLscreen45 !unction !or C so!tware;
Creating t#e cooling.#eating algorit#ms in C;
Handling remote control '/ in )erilog and Assembly;
Developing interactive user inter!ace in C;
Hardware component design and assembling ;
Ct#er improvements ;
#. Re-erences
P>Q #ttp7..en0wi+ipedia0org.wi+i.AdvancedL%icrocontrollerL"usLArc#itectureTAdva
ncedLHig#-per!ormanceL"usL0?EAH"0?D
P?Q #ttp7..en0wi+ipedia0org.wi+i.AdvancedL%icrocontrollerL"usLArc#itecture
P<Q #ttp7..in!ocenter0arm0com.#elp.inde803spMtopicN.com0arm0doc0i#i99<<a.inde80#tml
PBQ #ttp7..www0#ipeac0net.system.!iles.cm9dsL>L90pd!
PHQ FPGA Prototyping by )erilg I8amples Pong P0 C#u page <>?
PAQ Pmod$%PW 'e!erence %anual page >
P:Q D&>A?A 'e!erence %anual - page D
PEQ #ttp7..www0ti0com.lit.an.swra<?<.swra<?<0pd!
PDQ 111. vis+a" .comAdocsA/8861Adata-orm.pd-
P>9Q ;e8ys< 'e!erence %anual page >D
P>>Q #ttp7..en0wi+ipedia0org.wi+i.PDLcontroller
P>?Q #ttp7..web0mit0edu.clar+ds.www.Files.slides>0 pd!
P><Q +ttp:AAen.1iDipedia.orgA1iDiAParalla.5Propeller
Appendi. A: Eilin. Project F 2D3 Design Part F ;erilog 0odules
Here is t#e structure and t#e source !iles o! t#e HDL Design 4 source !iles o! t#e )erilog modules
w#ic# are not own production or not modi!ied were not included in t#is pro3ect documentation; source
!iles w#ic# are not own P and were modi!ied are included #ere wit# a 1modi!ied2 mention 50 A part o!
t#e modules were included !rom t#e C%9D&-Design*it and t#ey #ave a copyrig#t #eader in t#e
pro3ect !ile0
Figure 2* IilinG Proect Structure
A2453ite5!oC.v :
;od3le 'HF"Li4e"SoC(
?? :lo:B
inp34 wire CLK2
?? ;e;ory
ino34 wire )*H.!+ <e;,F2
o34p34 wire )95.*+ <e;'dr2
o34p34 wire Ra;CS2
o34p34 wire Ilas6CS2
o34p34 wire <e;%R2
o34p34 wire <e;0E2
o34p34 wire Ra;1F2
o34p34 wire Ra;LF2
o34p34 wire Ra;Cre2
o34p34 wire Ra;'dC2
o34p34 wire Ra;ClB2
inp34 wire Ra;%ai42
o34p34 wire Ilas6Rp2
?? 1'RT
inp34 wire RsRJ2
o34p34 wire RsTJ2
?? board led
o34p34 wire LE,2

??(eJys Foard &np34s
inp34 wire sw*2
inp34 wire sw92
?? 7;odT;p inp34s
inp34 wire )-.!+ 4e;pera43re2
?? &R re:eiCer inp34s
inp34 wire )K.!+ re;o4e":ode2
inp34 wire ir8"re;o4e2
?? 7%< o34p34s
o34p34 wire )H.!+ o34p34"speed2
?? Relays o34p34
o34p34 wire relay"o342
o34p34 wire relay"o3492
?? LM' &?0
o34p34 wire )9.!+ Cga"red2
o34p34 wire )9.!+ Cga"green2
o34p34 wire )*.!+ Cga"bl3e2
o34p34 wire 6syn:2
o34p34 wire Csyn:2
??7S9 &?0
inp34 wire ps9d2
inp34 wire ps9:
)#
?? 'HFNLi4e ;as4er o34p34 signals
wire HCLK#
wire HRESETn#
wire )K*.!+ H',,R#
wire )K*.!+ H%,'T'#
wire H%R&TE#
wire )*.!+ HTR'(S#
wire )9.!+ HF1RST#
wire H<'STL0CK#
wire )K.!+ H7R0T#
wire )9.!+ HS&OE#
wire L0CK17#
wire T=EL#
wire SLEE7&(M#
wire )*H.!+ &RD#
??'HFNLi4e ;as4er inp34 signals
wire )K*.!+ HR,'T'#
wire HRES7#
wire HRE',/#
?? sele:4 signals
wire )K.!+ <1="SEL#
wire HSEL"<E<#
wire HSEL"CTRL#
wire HSEL"1'RT#
wire HSEL"&(71TS#
wire HSEL"LM'#
wire HSEL"KF#
wire HSEL"T&<ER#
??slaCe read da4a
wire )K*.!+ HR,'T'"<E<#
wire )K*.!+ HR,'T'"CTRL#
wire )K*.!+ HR,'T'"1'RT#
wire )K*.!+ HR,'T'"&(71TS#
wire )K*.!+ HR,'T'"LM'#
wire )K*.!+ HR,'T'"KF#
wire )K*.!+ HR,'T'"T&<ER#
wire HRE',/01T"<E<#
wire HRE',/01T"CTRL#
wire HRE',/01T"1'RT#
wire HRE',/01T"&(71TS#
wire HRE',/01T"LM'#
wire HRE',/01T"KF#
wire HRE',/01T"T&<ER#
??S/STE< ME(ER'TES (0 ERR0R RES70(SE
assign HRES7 = *b!#
?? Cor4eJ <! in4err3p4 signals
assign &RD =
E*9b!!!!"!!!!"!!!!21'RT"&RD2&(71TS"&RD2KF"&RD2T&<ER"&RDG#
assign LE, = L0CK17#
?? :lo:B diCider and rese4
reg rCLK#
always @(posedge CLK)
rCLK <= PrCLK#
assign HCLK = rCLK#
assign HRESETn = !sw*#
?? :or4eJ <! ,SN ;as4er
C0RTE=<!,S 3":or4eJ;!ds (
QHCLK (HCLK)2
QHRESETn (HRESETn)2
QH',,R (H',,R)K*.!+)2
QHF1RST (HF1RST)9.!+)2
QH<'STL0CK (H<'STL0CK)2
QH7R0T (H7R0T)K.!+)2
QHS&OE (HS&OE)9.!+)2
QHTR'(S (HTR'(S)*.!+)2
QH%,'T' (H%,'T')K*.!+)2
QH%R&TE (H%R&TE)2
QHR,'T' (HR,'T')K*.!+)2
QHRE',/ (HRE',/)2
QHRES7 (HRES7)2
Q(<& (*b!)2
Q&RD (&RD)*H.!+)2
QT=EL ()2
QR=EL (*b!)2
QL0CK17 (L0CK17)2
QS/SRESETRED ()2
QSLEE7&(M ()
)#
?? 'HFNLi4e 'dress ,e:oder
'HF,C, 3'HF,C, (
QH',,R(H',,R)K*.!+)2
QHSEL"S!(HSEL"<E<)2
QHSEL"S*(HSEL"CTRL)2
QHSEL"S9(HSEL"1'RT)2
QHSEL"SK(HSEL"&(71TS)2
QHSEL"S>(HSEL"LM')2
QHSEL"SH(HSEL"KF)2
QHSEL"S5(HSEL"T&<ER)2
QHSEL"(0<'7(HSEL"(0<'7)2
Q<1="SEL(<1="SEL)K.!+)
)#
?? 'HFNLi4e SlaCe 4o <as4er <3li4pleJor
'HF<1= 3'HF<1= (
QHCLK(HCLK)2
QHRESETn(HRESETn)2
Q<1="SEL(<1="SEL)K.!+)2
QHR,'T'"S!(HR,'T'"<E<)2
QHR,'T'"S*(HR,'T'"CTRL)2
QHR,'T'"S9(HR,'T'"1'RT)2
QHR,'T'"SK(HR,'T'"&(71TS)2
QHR,'T'"S>(HR,'T'"LM')2
QHR,'T'"SH(HR,'T'"KF)2
QHR,'T'"S5(HR,'T'"T&<ER)2
QHR,'T'"(0<'7(K96,E',FEEI)2
QHRE',/01T"S!(HRE',/01T"<E<)2
QHRE',/01T"S*(HRE',/01T"CTRL)2
QHRE',/01T"S9(HRE',/01T"1'RT)2
QHRE',/01T"SK(HRE',/01T"&(71TS)2
QHRE',/01T"S>(HRE',/01T"LM')2
QHRE',/01T"SH(HRE',/01T"KF)2
QHRE',/01T"S5(HRE',/01T"T&<ER)2
QHRE',/01T"(0<'7(*b*)2
QHR,'T'(HR,'T')K*.!+)2
QHRE',/(HRE',/)
)#
?? 'HFNLi4e <e;ory Con4roller
'HF9SR'<ILSH 3'HF9SR'<ILSH (
QHCLK(HCLK)2
QHRESETn(HRESETn)2
QH',,R(H',,R)K*.!+)2
QHSEL(HSEL"<E<)2
QHRE',/(HRE',/)2
QHS&OE(HS&OE)9.!+)2
QHTR'(S(HTR'(S)*.!+)2
QH%,'T'(H%,'T')K*.!+)2
QH%R&TE(H%R&TE)2
QHR,'T'(HR,'T'"<E<)K*.!+)2
QHRE',/01T(HRE',/01T"<E<)2
QIlas6'4Oero(sw9)2
Q<e;,F(<e;,F)2
Q<e;'dr(<e;'dr)95.*+)2
QRa;CS(Ra;CS)2
QIlas6CS(Ilas6CS)2
Q<e;%R(<e;%R)2
Q<e;0E(<e;0E)2
QRa;1F(Ra;1F)2
QRa;LF(Ra;LF)2
QRa;Cre(Ra;Cre)2
QRa;'dC(Ra;'dC)2
QRa;ClB(Ra;ClB)2
QRa;%ai4(Ra;%ai4)2
QIlas6Rp(Ilas6Rp)
)#

?? 'HFNLile slaCe o34p34 :on4rol perip6eral
'HF9CTRL 3'HF9CTRL (
QHCLK(HCLK)2
QHRESETn(HRESETn)2
QHSEL(HSEL"CTRL)2
QHRE',/(HRE',/)2
QH%,'T'(H%,'T')K*.!+)2
QH%R&TE(H%R&TE)2
QHR,'T'(HR,'T'"CTRL)2
QHRE',/01T(HRE',/01T"CTRL)2
QCTRL(Erelay"o342relay"o3492o34p34"speed)H.!+G)
)#
??'HFNLi4e slaCe 1'RT :on4roller
wire 1'RT"&RD#
'HF1'RT 3'HF1'RT(
QHCLK(HCLK)2
QHRESETn(HRESETn)2
QH',,R(H',,R)K*.!+)2
QH%,'T'(H%,'T')K*.!+)2
QH%R&TE(H%R&TE)2
QHRE',/(HRE',/)2
QHRE',/01T(HRE',/01T"1'RT)2
QHR,'T'(HR,'T'"1'RT)K*.!+)2
QHSEL(HSEL"1'RT)2
QRsRJ(RsRJ)2
QRsTJ(RsTJ)2
Q3ar4"ir8(1'RT"&RD)
)#
??'HFNLi4e slaCe &(71TS
wire &(71TS"&RD#
'HF&(71T 3'HF&(71TS(
QHCLK(HCLK)2
QHRESETn(HRESETn)2
QH',,R(H',,R)K*.!+)2
QH%R&TE(H%R&TE)2
QH%,'T'(H%,'T')K*.!+)2
QHTR'(S(HTR'(S)2
QHSEL(HSEL"&(71TS)2
QHRE',/(HRE',/)2
Q&(71TS&((EKb!!!!2ir8"re;o4e2re;o4e":ode)K.!+24e;pera43re)-.!+G)2
QHRE',/01T(HRE',/01T"&(71TS)2
QHR,'T'(HR,'T'"&(71TS)K*.!+)2
Qinp34s"ir8(&(71TS"&RD)
)#
??'HFNLi4e LM' :on4roller
'HFLM' 3'HFLM'(
QHCLK(HCLK)2
QHRESETn(HRESETn)2
QH',,R(H',,R)K*.!+)2
QH%R&TE(H%R&TE)2
QH%,'T'(H%,'T')K*.!+)2
QHSEL(HSEL"LM')2
QHRE',/(HRE',/)2
QHRE',/01T(HRE',/01T"LM')2
QHR,'T'(HR,'T'"LM')K*.!+)2
Qrgb(ECga"red2Cga"green2Cga"bl3eG)2
Q6syn:(6syn:)2
QCsyn:(Csyn:)
)#
??'HFNLi4e Keyboard Con4roller
wire KF"&RD#
'HFKF 3'HFKF(
QHCLK(HCLK)2
QHRESETn(HRESETn)2
QH',,R(H',,R)K*.!+)2
QH%R&TE(H%R&TE)2
QH%,'T'(H%,'T')K*.!+)2
QHSEL(HSEL"KF)2
QHRE',/(HRE',/)2
QHRE',/01T(HRE',/01T"KF)2
QHR,'T'(HR,'T'"KF)K*.!+)2
Qps9d(ps9d)2
Qps9:(ps9:)2
QBb"ir8(KF"&RD)
)#
?? 'HFNLi4e 4i;er
wire T&<ER"&RD#
'HFT&<ER 3'HFT&<ER(
QHCLK(HCLK)2
QHRESETn(HRESETn)2
QH',,R(H',,R)K*.!+)2
QH%,'T'(H%,'T')K*.!+)2
QH%R&TE(H%R&TE)2
QHRE',/(HRE',/)2
QHRE',/01T(HRE',/01T"T&<ER)2
QHR,'T'(HR,'T'"T&<ER)K*.!+)2
QHSEL(HSEL"T&<ER)2
Q4i;er"ir8(T&<ER"&RD)
)#
end;od3le
A24DCD.v <modi-ied=:
;od3le 'HF,C,(
inp34 wire )K*.!+ H',,R2
o34p34 wire HSEL"S!2
o34p34 wire HSEL"S*2
o34p34 wire HSEL"S92
o34p34 wire HSEL"SK2
o34p34 wire HSEL"S>2
o34p34 wire HSEL"SH2
o34p34 wire HSEL"S52
o34p34 wire HSEL"(0<'72
o34p34 reg )K.!+ <1="SEL
)#

reg )*H.!+ de:#
?? ??<E<0R/ <'7 NNR ST'RT ',,R E(, ',,R S&OE
assign HSEL"S! = de:)!+# ??<E<0R/ <'7 NNR !J!!!!"!!!! 4o !J!!II"IIII *5<F
assign HSEL"S* = de:)*+# ??<E<0R/ <'7 NNR !JH!!!"!!!! 4o !JH!II"IIII *5<F
assign HSEL"S9 = de:)9+# ??<E<0R/ <'7 NNR !JH*!!"!!!! 4o !JH*II"IIII *5<F
assign HSEL"SK = de:)K+# ??<E<0R/ <'7 NNR !JH9!!"!!!! 4o !JH9II"IIII *5<F
assign HSEL"S> = de:)>+# ??<E<0R/ <'7 NNR !JHK!!"!!!! 4o !JHKII"IIII *5<F
assign HSEL"SH = de:)H+# ??<E<0R/ <'7 NNR !JH>!!"!!!! 4o !JH>II"IIII *5<F
assign HSEL"S5 = de:)5+# ??<E<0R/ <'7 NNR !JHH!!"!!!! 4o !JHHII"IIII *5<F
assign HSEL"(0<'7 = de:)*H+# ??REST 0I REM&0( (0T C0LERE, 'F0LE
always@S
begin
:ase(H',,R)K*.9>+)
86!!. ??<E<0R/ <'7 NNR !J!!!!"!!!! 4o !J!!II"IIII *5<F
begin
de: = *5b!!!!"!!!!"!!!!!!!*#
<1="SEL = >b!!!!#
end
86H!. ??<E<0R/ <'7 NNR !JH!!!"!!!! 4o !JH!II"IIII *5<F
begin
de: = *5b!!!!"!!!!"!!!!"!!*!#
<1="SEL = >b!!!*#
end
86H*. ??<E<0R/ <'7 NNR !JH*!!"!!!! 4o !JH*II"IIII *5<F
begin
de: =*5b!!!!"!!!!"!!!!"!*!!#
<1="SEL = >b!!*!#
end
86H9. ??<E<0R/ <'7 NNR !JH>!!"!!!! 4o !JH9II"IIII *5<F
begin
de: = *5b!!!!"!!!!"!!!!"*!!!#
<1="SEL = >b!!**#
end
86HK. ??<E<0R/ <'7 NNR !JHK!!"!!!! 4o !JHKII"IIII *5<F
begin
de: = *5b!!!!"!!!!"!!!*"!!!!#
<1="SEL = >b!*!!#
end
86H>. ??<E<0R/ <'7 NNR !JH>!!"!!!! 4o !JH>II"IIII *5<F
begin
de: = *5b!!!!"!!!!"!!*!"!!!!#
<1="SEL = >b!*!*#
end
86HH. ??<E<0R/ <'7 NNR !JHH!!"!!!! 4o !JHHII"IIII *5<F
begin
de: = *5b!!!!"!!!!"!*!!"!!!!#
<1="SEL = >b!**!#
end
defa3l4. ??(0<'7
begin
de: = *5b*!!!"!!!!"!!!!!!!!#
<1="SEL = >b****#
end
end:ase
end
end;od3le
A240(E.v <modi-ied=:
;od3le 'HF<1=(
??ML0F'L CL0CK $ RESET
inp34 wire HCLK2
inp34 wire HRESETn2
??<1= SELECT IR0< ',,RESS ,EC0,ER
inp34 wire )K.!+ <1="SEL2
??RE', ,'T' IR0< 'LL THE SL'LES
inp34 wire )K*.!+ HR,'T'"S!2
inp34 wire )K*.!+ HR,'T'"S*2
inp34 wire )K*.!+ HR,'T'"S92
inp34 wire )K*.!+ HR,'T'"SK2
inp34 wire )K*.!+ HR,'T'"S>2
inp34 wire )K*.!+ HR,'T'"SH2
inp34 wire )K*.!+ HR,'T'"S52
inp34 wire )K*.!+ HR,'T'"(0<'72
??RE',/01T IR0< 'LL THE SL'LES
inp34 wire HRE',/01T"S!2
inp34 wire HRE',/01T"S*2
inp34 wire HRE',/01T"S92
inp34 wire HRE',/01T"SK2
inp34 wire HRE',/01T"S>2
inp34 wire HRE',/01T"SH2
inp34 wire HRE',/01T"S52
inp34 wire HRE',/01T"(0<'72
??<1LT&7LE=E, HRE',/ $ HR,'T' T0 <'STER
o34p34 reg HRE',/2
o34p34 reg )K*.!+ HR,'T'
)#

reg )K.!+ '7H'SE"<1="SEL#
always@ (posedge HCLK or negedge HRESETn)
begin
if(!HRESETn)
'7H'SE"<1="SEL <= >6!#
else if(HRE',/) ?? (0TE. 'LL THE C0(TR0L S&M('LS 'RE L'L&, 0(L/ &I
HRE',/ = *b*
'7H'SE"<1="SEL <= <1="SEL#
end
always@S
begin
:ase('7H'SE"<1="SEL)
>b!!!!. begin ?? SELECT SL'LE! RES70(SE $ ,'T' &I 7REL&01S '7H'SE %'S
I0R S!
HR,'T' = HR,'T'"S!#
HRE',/ = HRE',/01T"S!#
end
>b!!!*. begin
HR,'T' = HR,'T'"S*#
HRE',/ = HRE',/01T"S*#
end
>b!!*!. begin
HR,'T' = HR,'T'"S9#
HRE',/ = HRE',/01T"S9#
end
>b!!**. begin
HR,'T' = HR,'T'"SK#
HRE',/ = HRE',/01T"SK#
end
>b!*!!. begin
HR,'T' = HR,'T'"S>#
HRE',/ = HRE',/01T"S>#
end
>b!*!*. begin
HR,'T' = HR,'T'"SH#
HRE',/ = HRE',/01T"SH#
end
>b!**!. begin
HR,'T' = HR,'T'"S5#
HRE',/ = HRE',/01T"S5#
end
defa3l4. begin
HR,'T' = HR,'T'"(0<'7#
HRE',/ = HRE',/01T"(0<'7#
end
end:ase
end
end;od3le
A242C'R3.v :
;od3le 'HF9CTRL(
??'HFL&TE &(TERI'CE
??SlaCe Sele:4 Signals
inp34 wire HSEL2
??Mlobal Signal
inp34 wire HCLK2
inp34 wire HRESETn2
??'ddress2 Con4rol $ %ri4e ,a4a
inp34 wire HRE',/2
inp34 wire )*.!+ HTR'(S2
inp34 wire H%R&TE2
inp34 wire )9.!+ HS&OE2
inp34 wire )K*.!+ H%,'T'2
?? Transfer Response $ Read ,a4a
o34p34 wire HRE',/01T2
o34p34 wire )K*.!+ HR,'T'2
?? Con4roled 034p34
o34p34 wire )-.!+ CTRL
)#
??'ddress 76ase Sa;pling Regis4ers
reg rHSEL#
reg )K*.!+ rH',,R#
reg )*.!+ rHTR'(S#
reg rH%R&TE#
reg )9.!+ rHS&OE#
reg )-.!+ rCTRL#
??'ddress 76ase Sa;pling
begin
if(!HRESETn)
begin
rHSEL <= *b!#
rH',,R <= K96!#
rHTR'(S <= 9b!!#
rH%R&TE <= *b!#
rHS&OE <= Kb!!!#
end
else if(HRE',/)
begin
rHSEL <= HSEL#
rH',,R <= H',,R#
rHTR'(S <= HTR'(S#
rH%R&TE <= H%R&TE#
rHS&OE <= HS&OE#
end
end
??,a4a 76ase da4a 4ransfer
begin
if(!HRESETn)
rCTRL <= 8b!!!!"!!!!#
else if(rHSEL $ rH%R&TE $ rHTR'(S)*+)
rCTRL <= H%,'T')-.!+#
end
??Transfer Response
assign HRE',/01T = *b*#

??Read ,a4a
assign HR,'T' = E9>6!!!!"!!2rCTRLG#

?? 'ssign Cal3e 4o o34p34
assign CTRL = rCTRL#
end;od3le
A24I9P('.v :
;od3le 'HF&(71T(
inp34 wire HCLK2
inp34 wire HRESETn2
inp34 wire )*.!+ HTR'(S2
inp34 wire )K*.!+ H%,'T'2
inp34 wire H%R&TE2
inp34 wire HSEL2
inp34 wire HRE',/2
inp34 wire )*H.!+ &(71TS&(2

??034p34
o34p34 wire HRE',/01T2
o34p34 wire )K*.!+ HR,'T'2
o34p34 wire inp34s"ir8
)#

??lo:alpara; )-.!+ inp34"da4a"addr = 86!!#

reg )*H.!+ inp34"da4a#
reg )*H.!+ inp34"da4a"neJ4#
reg )K*.!+ las4"H',,R#
reg )*.!+ las4"HTR'(S#
reg las4"H%R&TE#
reg las4"HSEL#

in4eger i#

assign HRE',/01T = *b*#

?? Se4 Regis4ers fro; address p6ase
always @(posedge HCLK)
begin
if(HRE',/)
begin
las4"H',,R <= H',,R#
las4"HTR'(S <= HTR'(S#
las4"H%R&TE <= H%R&TE#
las4"HSEL <= HSEL#
end
end

?? 1pda4e inp34"da4a por4s
always @(posedge HCLK2 negedge HRESETn)
begin
if(!HRESETn)
inp34"da4a <= *56!!!!#
else
inp34"da4a <= &(71TS&(#
end

assign HR,'T')*H.!+ = inp34"da4a#
assign inp34s"ir8= &(71TS&()*9+#
end;od3le
vga5console.v < modi-ied = :
;od3le Cga":onsole(
inp34 wire :lB2
inp34 wire rese4n2
inp34 wire Cideo"on2
inp34 wire )T.!+ piJel"J2
inp34 wire )T.!+ piJel"y2

inp34 wire fon4"we2 ??fon4 wri4e
inp34 wire )-.!+ fon4"da4a2 ??inp34 -Nbi4 as:ii Cal3e

o34p34 reg )-.!+ 4eJ4"rgb2 ??o34p34 :olor
o34p34 reg s:roll ??signals s:rolling
)#
??S:reen 4ile para;e4ers
lo:alpara; <'="= = >!# ??(3;ber of 6ori@on4al 4iles
lo:alpara; <'="/ = *!# ??(3;ber of 4ile rows

??Ion4 R0<
wire )*!.!+ ro;"addr#
wire )5.!+ :6ar"addr#
wire )K.!+ row"addr#
wire )9.!+ bi4"addr#
wire )-.!+ fon4"word#
wire fon4"bi4#

??,3al por4 R'<
wire )**.!+ addr"r#
wire )**.!+ addr"w#
wire )5.!+ din#
wire )5.!+ do34#

??C3rsor
reg )5.!+ :3r"J"reg#
wire )5.!+ :3r"J"neJ4#
reg )>.!+ :3r"y"reg#
wire )>.!+ :3r"y"neJ4#
wire :3rsor"on#

??piJel b3ffers
reg )T.!+ piJel"J*#
reg )T.!+ piJel"J9#
reg )T.!+ piJel"y*#
reg )T.!+ piJel"y9#

wire )-.!+ fon4"rgb# ??:olor for 4eJ4
wire )-.!+ fon4"inC"rgb# ??:olor for 4eJ4 wi46 :3rsor on 4op

reg :3rren4"s4a4e#
reg neJ4"s4a4e#

wire re43rn"Bey# ??:arriage re43rn or Un
wire new"line# ??;oCe :3rsor 4o neJ4 line

??reg s:roll#
reg s:roll"neJ4#
reg )>.!+ yn# ??row :o3n4
reg )>.!+ yn"neJ4#
reg )5.!+ Jn# ??6ori@on4al :o3n4
reg )5.!+ Jn"neJ4#

wire Cerify":6ar#

??<od3le &ns4an4ia4ion
fon4"ro; 3fon4"ro;(
Q:lB(:lB)2
Qaddr(ro;"addr)2
Qda4a(fon4"word)
)#

d3al"por4"ra;"syn:
V(Q',,R"%&,TH(*9)2 Q,'T'"%&,TH(-))
3Cideo"ra;
( Q:lB(:lB)2
Qwe(we)2
Qaddr"a(addr"w)2
Qaddr"b(addr"r)2
Qdin"a(din)2
Qdo34"a()2
Qdo34"b(do34)
)#

??S4a4e <a:6ine for :3rsor and piJel b3ffer
always @ (posedge :lB2 negedge rese4n)
begin
if(!rese4n)
begin
:3r"J"reg <= !#
:3r"y"reg <= !#
end
else if(din==-b!!!**!*) ?? if we 6aCe :6ara:4er *K ( :arriage re43rn ) 4o
display
begin
:3r"J"reg <= !#
:3r"y"reg <= !#
end

else
begin
:3r"J"reg <= :3r"J"neJ4#
:3r"y"reg <= :3r"y"neJ4#
piJel"J* <= piJel"J#
piJel"J9 <= piJel"J*#
piJel"y* <= piJel"y#
piJel"y9 <= piJel"y*#
end
end

??Ion4 R0< '::ess
assign row"addr = piJel"y)K.!+# ??row Cal3e
assign ro;"addr = E:6ar"addr2row"addrG# ??as:ii Cal3e and row of :6ara:4er
assign bi4"addr = piJel"J9)9.!+# ??delayed
assign fon4"bi4 = fon4"word)Pbi4"addr+# ??o34p34 fro; fon4 ro;

??Re43rn Bey fo3nd
assign re43rn"Bey = (din == 5b!!**!* WW din == 5b!!*!*!) $$ Ps:roll# ?? Re43rn
WW XUnX

??Fa:Bspa:e
assign ba:B"spa:e = (din == 5b!!*!!!)#

??(ew line logi:
assign new"line = fon4"we $$ ((:3r"J"reg == <'="=N*) WW re43rn"Bey)#

??(eJ4 C3rsor 7osi4ion logi:
assign :3r"J"neJ4 = (new"line) A ! .
(ba:B"spa:e $$ :3r"J"reg) A :3r"J"reg N * .
(fon4"we $$ Pba:B"spa:e $$ Ps:roll) A :3r"J"reg Y * .
:3r"J"reg#

assign :3r"y"neJ4 = (:3r"y"reg == <'="/N*) A :3r"y"reg .
((new"line) A :3r"y"reg Y * . :3r"y"reg )#
??Color Menera4ion
assign fon4"rgb = (fon4"bi4) A 8b******** . 8b!!!!!!!!# ??w6i4e.bla:B
assign fon4"inC"rgb = (fon4"bi4) A 8b!!!!!!! . 8b!!!!!!!!# ??bla:B.bla:B

??,isplay logi: for :3rsor
assign :3rsor"on = (piJel"J9)T.K+ == :3r"J"reg) $$ (piJel"y9)8.>+ == :3r"y"reg)#

??R'< %ri4e Enable
assign we = fon4"we WW s:roll#

??,isplay :o;bina4ional logi:
always @S
begin
if(PCideo"on)
4eJ4"rgb = 86!!#
else
if(:3rsor"on)
4eJ4"rgb = fon4"inC"rgb#
else
4eJ4"rgb = fon4"rgb#
end

??Console s4a4e ;a:6ine
always @(posedge :lB2 negedge rese4n)
if(!rese4n)
begin
s:roll <= *b!#
yn <= Hb!!!!!#
Jn <= -b!!!!!!!#
:3rren4"s4a4e <= *b!#
end
else
begin
s:roll <= s:roll"neJ4#
yn <= yn"neJ4#
Jn <= Jn"neJ4#
:3rren4"s4a4e <= neJ4"s4a4e#
end

??Console neJ4 s4a4e logi:
always @S
begin
s:roll"neJ4 = s:roll#
Jn"neJ4 = Jn#
yn"neJ4 = yn#
neJ4"s4a4e = :3rren4"s4a4e#
:ase(:3rren4"s4a4e)
*b!. ??%ai4s for a new line and 46e :3rsor on 46e las4 line of 46e s:reen
if(new"line $$ (:3r"y"reg == <'="/N*))
begin
s:roll"neJ4 = *b*#
neJ4"s4a4e = *b*#
yn"neJ4 = !#
Jn"neJ4 = -b*******# ??,elayed by one :y:le
end
else
s:roll"neJ4 = *b!#
*b*. ??Co3n4s 46ro3g6 eCery 4ile and refres6es
begin
if(Jn"neJ4 == <'="=)
begin
Jn"neJ4 = -b*******# ??,elayed by one :y:le
yn"neJ4 = yn Y *b*#
if(yn"neJ4 == <'="/)
begin
neJ4"s4a4e = *b!#
s:roll"neJ4 = !#
end
end
else
Jn"neJ4 = Jn Y *b*#

end
end:ase
end

??R'< %ri4e
assign addr"w = (s:roll) A Eyn2JnG . E:3r"y"reg2 :3r"J"regG#
assign din = (s:roll) A do34 . fon4"da4a)5.!+#
??R'< Read
assign addr"r =(s:roll) A EynY*b*2Jn"neJ4G . EpiJel"y)8.>+2piJel"J)T.K+G#
assign :6ar"addr = do34#
end;od3le
temp5value.v :
;od3le 4e;p"Cal3e(4e;p"in2degree2de:i;al23ni424ens)#
inp34 )-.!+ 4e;p"in#
o34p34 )K.!+ degree#
o34p34 )K.!+ de:i;al#
reg )K.!+ de:i;al#
o34p34 )K.!+ 3ni4#
o34p34 )K.!+ 4ens#
wire )K.!+ :*2:92:K2:>2:H2:52:-#
wire )K.!+ d*2d92dK2d>2dH2d52d-#
wire )-.!+ Cal3e#
assign Cal3e=E*b!24e;p"in)-.*+G#
assign d* = E*b!2Cal3e)-.H+G#
assign d9 = E:*)9.!+2Cal3e)>+G#
assign dK = E:9)9.!+2Cal3e)K+G#
assign d> = E:K)9.!+2Cal3e)9+G#
assign dH = E:>)9.!+2Cal3e)*+G#
assign d5 = E*b!2:*)K+2:9)K+2:K)K+G#
assign d- = E:5)9.!+2 :>)K+G#
addK ;* (d*2:*)#
addK ;9 (d92:9)#
addK ;K (dK2:K)#
addK ;> (d>2:>)#
addK ;H (dH2:H)#
addK ;5 (d52:5)#
addK ;- (d-2:-)#
assign 3ni4=E:H)9.!+2Cal3e)!+G#
assign 4ens=E:-)9.!+2:H)K+G#
always @S begin
:ase (4e;p"in)!+)
*b!. begin
de:i;al=>b!!!!#
end
*b*. begin
de:i;al=>b!*!*#
end
end:ase
end
assign degree=>b**!!#
end;od3le
dcd6seg.v :
;od3le d:d-seg( 6eJ:ode2sego34 )#
inp34 )K.!+ 6eJ:ode#
o34p34 )5.!+ sego34#
reg )5.!+ sego34#
always @S
begin
:ase(6eJ:ode)
>b!!!* . sego34 = -b****!!*#
>b!!*! . sego34 = -b!*!!*!!#
>b!!** . sego34 = -b!**!!!!#
>b!*!! . sego34 = -b!!**!!*#
>b!*!* . sego34 = -b!!*!!*!#
>b!**! . sego34 = -b!!!!!*!#
>b!*** . sego34 = -b****!!!#
>b*!!! . sego34 = -b!!!!!!!#
>b*!!* . sego34 = -b!!*!!!!#
>b**!! . sego34 = -b*!!!**!#
defa3l4 . sego34 = -b*!!!!!!#
end:ase
end
end;od3le
mu.select6seg.v :
;od3le ;3Jsele:4-seg(sele:4ion2an2poin4 )#
inp34 )*.!+ sele:4ion#
o34p34 )K.!+ an#
reg )K.!+ an#
o34p34 poin4#
reg poin4#
always @S
begin
:ase(sele:4ion)
9b!! . an = >b***!#
9b!* . an = >b**!*#
9b*! . an = >b*!**#
9b** . an = >b!***#
defa3l4 . an = >b!!!!#
end:ase
end
always @S
begin
:ase(sele:4ion)
9b*! . poin4 =*b!#
defa3l4 . poin4 =*b*#
end:ase
end
end;od3le
;od3le digi4;3J(degree2de:i;al23ni424ens2o34"Cal3e2sele:4ion
)#
inp34 )K.!+ degree#
inp34 )K.!+ de:i;al#
inp34 )K.!+ 3ni4#
inp34 )K.!+ 4ens#
inp34 )*.!+ sele:4ion#
o34p34 )K.!+ o34"Cal3e#
reg )K.!+ o34"Cal3e#

always @S
begin
:ase(sele:4ion)
9b!! . o34"Cal3e = degree#
9b!* . o34"Cal3e = de:i;al#
9b*! . o34"Cal3e = 3ni4#
defa3l4 . o34"Cal3e = 4ens#
end:ase
end
end;od3le
pmodtmp.v :
;od3le p;od4;p(
ino34 d82 ?? d8 N we send :o;;ands 4o 46e
sensor and read 46e 4e;pera43re
inp34 :lo:B2 ?? (eJys :lo:B inp34
o34p34 reg :lo:B":onC2 ?? :lo:B o34p34 3sed for 7;odT;p
o34p34 reg rs4"n2 ?? rese4 pin
o34p34 reg )-.!+ 4e;p"o34 ?? o34p34 8Nbi4 4e;pera43re
)#
?S '34orese4 ;od3le N we 3se i4 4o rese4 46e sensor a4 eCery * se:ond2
in order 4o :onCer4 and read a new Cal3eQ
S?
a34orese4 a34orese4 (
Q:lo:B(:lo:B)2
Qrese4(rese4)
)#
reg )**.!+ 4e;p# ?? 4e;p regis4er ( we s4ore 46e *9bi4
4e;pera43re reading in i4 )
reg )-.!+ da4a"o34# ?? :o;;and regis4er
reg )9.!+ s4a4e#
reg )K.!+ bi4":o3n4# ?? :o3n4s bi4s sen4 and re:eiCed
reg )9.!+ :lB":o3n4#
reg :o;;and"by4e# ?? ! or *2depending on w6i:6 by4e :o;;and is sen4

reg ;ode# ?? ;ode de4er;ines 4rans;i4?re:eiCe ;ode
para;e4er Tr = *b*# ?? 4rans;i4 para;e4er
para;e4er Re: = *b!# ?? re:eiCe para;e4er
?S s4a4e para;e4ers S?
para;e4er )9.!+ ST'RT = Kb!!!#
para;e4er )9.!+ L0',",'T' = Kb!!*#
para;e4er )9.!+ Tr"F/TE = Kb!*!#
para;e4er )9.!+ Re:"TE<7 = Kb!**#
para;e4er )9.!+ ST07 = Kb*!!#
?? :o;;and para;e4ers ( :onCer4 ? read 4e;pera43re )
para;e4er )-.!+ read"4e;p":o;;and = 86''#
para;e4er )-.!+ s4ar4":onC":o;;and = 86H*#
reg )**.!+ 4e;pera43re"reading = !#
reg 4e;p"ready#
reg )5.!+ 8#
?? :o3n4er logi:
always @(posedge :lo:B2 posedge rese4) begin
if(rese4) 8 <= !#
else 8 <= 8Y*#
end
wire Cir43al":lB#
assign Cir43al":lB = 8)5+# ?? :lB9H5
?? Te;pera43re S4a4e <a:6ine
always @ (posedge Cir43al":lB or posedge rese4) begin
if (rese4)
begin
rs4"n <= !#
:lo:B":onC <= *#
:o;;and"by4e <= !#
bi4":o3n4 <= !#
:lB":o3n4 <= !#
4e;p"ready <= !#
s4a4e <= ST'RT#
4e;pera43re"reading <= !#
4e;p <= !#
end
else if (*) ?? if rese4 is !
begin
?? s4a4e :ase ??
:ase (s4a4e)
?S
S4ar4 s4a4e .
S?
ST'RT. begin
rs4"n <= *#
;ode <= Tr# ?? 4rans;i4 ;ode
s4a4e <= L0',",'T'# ?? Z3;p 4o L0',",'T' s4a4e
end
?S
Load ,a4a s4a4e
S?
L0',",'T'. begin
?S
&f :o;;and"by4e is ! 46en we will send 46e :onCer4
:o;;and
else we will send 46e 4e;pera43re read :o;;and
S?
:ase(:o;;and"by4e)
!. begin
da4a"o34 <= s4ar4":onC":o;;and# ??
firs4 i4 will be sen4 46e s4ar4 :onCer4 :o;;and
end
*. begin
da4a"o34 <= read"4e;p":o;;and# ?? and
af4er 46a4 46e read 4e;pera43re :o;;and
end
end:ase
s4a4e <= Tr"F/TE# ?? Z3;p 4o neJ4 s4a4e
end
?S
Trans;i4 Fy4e S4a4e
S?
Tr"F/TE. begin
:ase(:lB":o3n4)
!. begin
:lo:B":onC <= !#
:lB":o3n4 <= :lB":o3n4 Y *#
end
*. begin ?? R&S&(M E,ME CL0CK
if (bi4":o3n4 R !) begin
da4a"o34 <= E*b!2 da4a"o34)-.*+G#
?? 4rans;i44ing :o;;and
end
:lB":o3n4 <= :lB":o3n4 Y *#
end
9. begin
:lo:B":onC <= *#
:lB":o3n4 <= :lB":o3n4 Y *#
end
K. begin
if (bi4":o3n4 < -) begin
s4a4e <= Tr"F/TE# ?? re43rn 4o
4rans;i4 by4e s4a4e if we s4ill 6aCe 4o 4rans;i4 bi4s
bi4":o3n4 <= bi4":o3n4 Y *#
:lB":o3n4 <= !#
end
else if (!:o;;and"by4e) begin
s4a4e <= ST07#
bi4":o3n4 <= !#
:lB":o3n4 <= !#
end
else begin
s4a4e <= Re:"TE<7#
bi4":o3n4 <= !#
;ode <= Re:#
:lB":o3n4 <= 9#
end
end
end:ase
end
?S
Re:eiCe 4e;pera43re s4a4e
S?
Re:"TE<7. begin
:ase(:lB":o3n4)
!. begin
:lo:B":onC <= *#
4e;pera43re"reading <= Ed82
4e;pera43re"reading)**.*+G# ?? re:eiCe 4e;pera43re
:lB":o3n4 <= :lB":o3n4 Y *#
end
*. begin
:lB":o3n4 <= :lB":o3n4 Y *#
end
9. begin
:lo:B":onC <= !#
:lB":o3n4 <= :lB":o3n4 Y *#
end
K. begin ?? I'LL&(M E,ME 0I THE CL0CK S&M('L
:lB":o3n4 <= !#
if (bi4":o3n4 < *9) begin ?? if we 6aCe
in:o;ing da4a
s4a4e <= Re:"TE<7# ?? re43rn 4o
re:eiCe 4e;pera43re s4a4e
bi4":o3n4 <= bi4":o3n4 Y *#
end
else begin
s4a4e <= ST07# ?? Z3;p 4o s4op
s4a4e if we don4 6aCe any in:o;ing da4a
bi4":o3n4 <= !#
end
end
end:ase
end
?S
S4op s4a4e
S?
ST07. begin
rs4"n <= !#
if (!:o;;and"by4e) begin
s4a4e <= ST'RT#
:o;;and"by4e <= :o;;and"by4e Y *#
end
else begin
s4a4e <= ST'RT#
4e;p"ready <= *#
if(4e;p"ready)begin
4e;p <= 4e;pera43re"reading#
4e;p"ready <= !#
end
:lB":o3n4 <= !#
:lo:B":onC <= *#
end
?? Te;pera43re assign;en4 ( posi4iCe 4e;pera43re 2 wi46 only one
de:i;al par4 . bi4s *! 4o K)#
4e;p"o34)!+=4e;p)K+#
4e;p"o34)*+=4e;p)>+#
4e;p"o34)9+=4e;p)H+#
4e;p"o34)K+=4e;p)5+#
4e;p"o34)>+=4e;p)-+#
4e;p"o34)H+=4e;p)8+#
4e;p"o34)5+=4e;p)T+#
4e;p"o34)-+=4e;p)*!+#
end
end:ase
end
end
assign d8 = (;ode) A da4a"o34)!+ . *b@#
end;od3le
autoreset.v :
;od3le a34orese4(:lo:B2rese4)#
?S
&np34s and o34p34s
S?
inp34 :lo:B#
o34p34 rese4#
reg rese4#
?S
7ara;e4ers
S?
para;e4er period = 9!!!!!!!!# ?? 9 se:onds for o3r *!! <H@ :lo:B
para;e4er 6alfperiod = period ? 9# ?? 6alf period
reg )K*.!+ :o3n4Cal3e#
always@(posedge :lo:B)
begin
if(:o3n4Cal3e==periodN*)
begin
:o3n4Cal3e =! #
rese4 =!#
end
else
:o3n4Cal3e=:o3n4Cal3eY*#
if(:o3n4Cal3e==6alfperiod)
rese4 =*#
end
end;od3le
irreceiver.v :
;od3le irre:eiCer(
inp34 :lo:B2
inp34 re;o4e"in2
inp34 rese42
o34p34 reg )K.!+ re;o4e"o342
o34p34 reg ir8"signal
)#

?S
7ara;e4ers and regis4ers
S?

reg )*K.!+ 4i;er = !#
reg )9.!+ s4a4e"reg = !# ?? s4a4e regis4er
reg )9.!+ neJ4"s4a4e = !#
reg da4a = !#
reg )-.!+ bi4"4i;er = *#

reg )T.!+ 8 = !#
wire Cir43al":lB#

reg )H.!+bi4":o3n4er = K>#
reg )K*.!+ da4a"reading = !#
wire )9K.!+ da4a"in#

para;e4er %'&T = Kb!!!# ?? wai4 s4a4e
para;e4er HE',ER = Kb!!*# ?? 6eader s4a4e ( 6earder :ode )
para;e4er 0II = Kb!*!# ?? off s4a4e ( off :ode )
para;e4er ,'T' = Kb!**# ?? da4a s4a4e
para;e4er ,'T'"0II = Kb*!!# ??da4a off
para;e4er ,'T'"(E=T = Kb*!*#

?? s4a4e IS<
always @(posedge :lo:B)
if(rese4)
s4a4e"reg <= %'&T#
else
s4a4e"reg <= neJ4"s4a4e#

?? :o3n4er logi:
always @(posedge :lo:B)begin
if(Cir43al":lB WW rese4)
8 <= !#
else
8 <= 8 Y *#
end
assign Cir43al":lB = (8==TTT)#
?S
S4a4es
S?
always @(S)
:ase(s4a4e"reg)
%'&T. begin ?? wai4 s4a4e
if(re;o4e"in == !) ?? if we 6aCe 46e firs4 low logi:
signal NR Z3;p 4o neJ4 s4a4e ( HE',ER )
neJ4"s4a4e <= HE',ER#
else ?? else we will re;ain in %'&T s4a4e
neJ4"s4a4e <= %'&T#
end
HE',ER. begin ?? 6eader :ode 2 we 6aCe 4o eJa;ine af4er T ;s
re;o4e"in signal
if(4i;er == TT!! $$ re;o4e"in == *)begin
neJ4"s4a4e <= 0II# ?? Z3;p 4o neJ4 s4a4e
end
else if(4i;er == TT!! $$ re;o4e"in == !)
neJ4"s4a4e <= %'&T# ?? Z3;p 4o wai4 s4a4e
else
neJ4"s4a4e <= HE',ER#
end
0II. begin ?? off :ode
if(4i;er == T>-! $$ re;o4e"in == !)begin
neJ4"s4a4e <= ,'T'# ?? s4ar4 reading da4a
end
else if(4i;er == T>-! $$ re;o4e"in == *)
neJ4"s4a4e <= %'&T# ?? Z3;p 4o wai4 s4a4e
else
neJ4"s4a4e <= 0II# ?? Z3;p ba:B 4o off s4a4e
end
?? ,'T' 2 ,'T'"0II and ,'T'"(E=T s4a4es are 3sed 4o de4er;ine
46e * and ! logi: s4a4es
,'T'. begin
if(4i;er == K9!! $$ re;o4e"in == *)begin
neJ4"s4a4e <= ,'T'"0II#
end
else if(4i;er == K9!! $$ re;o4e"in == !)begin
neJ4"s4a4e <= %'&T#
end
else
neJ4"s4a4e <= ,'T'#
end
,'T'"0II. begin
if(4i;er == ! $$ re;o4e"in == *)begin
neJ4"s4a4e <= %'&T#
end
else if(4i;er == ! $$ re;o4e"in == !)
neJ4"s4a4e <= ,'T'"(E=T#
else
neJ4"s4a4e <= ,'T'"0II#
end
,'T'"(E=T. begin
if(4i;er < H! $$ re;o4e"in == !)begin
neJ4"s4a4e <= ,'T'"(E=T#
end
else if(4i;er == ! $$ re;o4e"in == *)
neJ4"s4a4e <= %'&T#
else
neJ4"s4a4e <= ,'T'"(E=T#
end
end:ase
?? 4i;er logi:
always @(posedge :lo:B) begin
if(rese4) begin
4i;er <= *!8H!#
end
else
:ase(s4a4e"reg)
%'&T. begin
if(re;o4e"in == !) begin
4i;er <= *!8H!#
end
end
HE',ER. begin
if(Cir43al":lB)
4i;er <= 4i;er N *#
end
0II. begin
if(Cir43al":lB)
4i;er <= 4i;er N *#
end
,'T'. begin
if(Cir43al":lB)
4i;er <= 4i;er N *#
end
,'T'"0II. begin
if(Cir43al":lB)
4i;er <= 4i;er N *#
end
,'T'"(E=T. begin
if(4i;er < H! $$ re;o4e"in == !) begin
4i;er <= *!8H!#
end
else if (Cir43al":lB $$ 4i;er R !)
4i;er <= 4i;er N *#
end
end:ase
end
?? ,a4a reading logi:
always @(posedge :lo:B) begin
if(rese4) begin
bi4"4i;er <= *#
bi4":o3n4er <= K>#
end
else if(s4a4e"reg == ,'T' $$ Cir43al":lB) begin
bi4"4i;er <= bi4"4i;er N *#
if(bi4"4i;er == ! $$ re;o4e"in == ! $$ bi4":o3n4er R !)
begin
bi4"4i;er <= ***# ?? *2*9 ;s
da4a <= !#
bi4":o3n4er <= bi4":o3n4er N *#
da4a"reading <= Eda4a2 da4a"reading)K*.*+G#
end
else if (bi4"4i;er == ! $$ re;o4e"in == * $$ bi4":o3n4er R
!) begin
bi4"4i;er <= 99K# ?? 929> ;s
da4a <= *#
bi4":o3n4er <= bi4":o3n4er N *#
da4a"reading <= Eda4a2 da4a"reading)K*.*+G#
end
else if(bi4"4i;er == ! $$ re;o4e"in == * $$ bi4":o3n4er ==
!) begin
bi4"4i;er <= *#
end
end
else if(s4a4e"reg == ,'T'"(E=T WW s4a4e"reg == ,'T'"0II)
bi4":o3n4er <= !#
else if(s4a4e"reg == %'&T)
bi4":o3n4er <= K>#
end
assign da4a"in = (bi4":o3n4er == ! ) A da4a"reading)9K.!+ .
9>b!!!!"!!!!"!!!!"!!!!"!!!!"!!!!#
?? Bey assign;en4
always @S begin
:ase (da4a"in)
9>b!!!**!******!***!!!!*!!!. begin ?? on?off Bey
re;o4e"o34 = >b!***#
ir8"signal = *#
end
9>b!!!*********!***!!!!*!!!. re;o4e"o34 = >b!!!*# ?? ' Bey
9>b!!!****!****!***!!!!*!!!. re;o4e"o34 = >b!!*!# ?? F Bey
9>b!!!**!*!****!***!!!!*!!!. re;o4e"o34 = >b!!**# ?? C Bey
9>b!!!!*!!!****!***!!!!*!!!. re;o4e"o34 = >b*!!!# ?? lef4 Bey
9>b!!!!!*!!****!***!!!!*!!!. re;o4e"o34 = >b!*!*# ??oB Bey
9>b!!!!!!!*****!***!!!!*!!!. re;o4e"o34 = >b*!!*# ?? rig64 Bey
9>b!!!!!*!*****!***!!!!*!!!. re;o4e"o34 = >b!**!# ??3p Bey
9>b!!!!!!!!****!***!!!!*!!!. re;o4e"o34 = >b!*!!# ??down Bey
9>b!!!!!!!!!!!!!!!!!!!!!!!!. begin
re;o4e"o34 = >b!!!!# ?? o46er :ase
ir8"signal = !#
end
end:ase
end
end;od3le
P*0.v :
;od3le 7%<(:lo:B2inp34"speed2o34p34"led2pw;"o34
)#

?? &np34s 2 o34p34s
inp34 :lo:B# ?? :lo:B signal
inp34 )H.!+ inp34"speed# ?? 5 bi4 inp34 Cal3e fro; SoC sys4e;
o34p34 )H.!+ o34p34"led# ?? o34p34 of 46e 5 bi4 Cal3e
o34p34 pw;"o34# ?? pw; signal o34p34
reg pw;"o34#

?? 7ara;e4ers
para;e4er s4ep"delay = *H5!# ?? ( P*!!!!!?5>)
reg )*5.!+ :o3n4er =!#

assign o34p34"led=inp34"speed#

?? i4 genera4es 46e * ;s pw; signal
always @(posedge :lo:B)
begin
:o3n4er=:o3n4erY*#
if(:o3n4er <= inp34"speedSs4ep"delay) ?? d34y :y:le
pw;"o34 = *#
else
pw;"o34 = !#
if(:o3n4erR=*!!"!!!)
:o3n4er = !# ?? :o3n4er rese4
end
end;od3le
AR0!OC5!).uc- :
(e4 XCLKX L0C=L*! #
(e4 XIlas6CSX L0C = L*- #
(e4 XIlas6RpX L0C = T> #
(e4 X<e;'dr<*RX L0C = K*8 #
(e4 X<e;'dr<9RX L0C = K*- #
(e4 X<e;'dr<KRX L0C = [*8 #
(e4 X<e;'dr<>RX L0C = [*5 #
(e4 X<e;'dr<HRX L0C = M*8 #
(e4 X<e;'dr<5RX L0C = M*5 #
(e4 X<e;'dr<-RX L0C = H*5 #
(e4 X<e;'dr<8RX L0C = H*H #
(e4 X<e;'dr<TRX L0C = H*> #
(e4 X<e;'dr<*!RX L0C = H*K #
(e4 X<e;'dr<**RX L0C = I*8 #
(e4 X<e;'dr<*9RX L0C = I*- #
(e4 X<e;'dr<*KRX L0C = K*K #
(e4 X<e;'dr<*>RX L0C = K*9 #
(e4 X<e;'dr<*HRX L0C = E*8 #
(e4 X<e;'dr<*5RX L0C = E*5 #
(e4 X<e;'dr<*-RX L0C = M*K #
(e4 X<e;'dr<*8RX L0C = H*9 #
(e4 X<e;'dr<*TRX L0C = ,*8 #
(e4 X<e;'dr<9!RX L0C = ,*- #
(e4 X<e;'dr<9*RX L0C = M*> #
(e4 X<e;'dr<99RX L0C = I*> #
(e4 X<e;'dr<9KRX L0C = C*8 #
(e4 X<e;'dr<9>RX L0C = C*- #
(e4 X<e;'dr<9HRX L0C = I*5 #
(e4 X<e;'dr<95RX L0C = I*H #
(e4 X<e;,F<!RX L0C = R*K #
(e4 X<e;,F<*RX L0C = T*> #
(e4 X<e;,F<9RX L0C = L*> #
(e4 X<e;,F<KRX L0C = 1H #
(e4 X<e;,F<>RX L0C = LH #
(e4 X<e;,F<HRX L0C = RK #
(e4 X<e;,F<5RX L0C = TK #
(e4 X<e;,F<-RX L0C = RH #
(e4 X<e;,F<8RX L0C = (H #
(e4 X<e;,F<TRX L0C = 75 #
(e4 X<e;,F<*!RX L0C = 7*9 #
(e4 X<e;,F<**RX L0C = 1*K #
(e4 X<e;,F<*9RX L0C = L*K #
(e4 X<e;,F<*KRX L0C = 1*! #
(e4 X<e;,F<*>RX L0C = R8 #
(e4 X<e;,F<*HRX L0C = T8 #
(e4 X<e;0EX L0C = L*8 #
(e4 X<e;%RX L0C = <*5 #
(e4 XRa;'dCX L0C = H*8 #
(e4 XRa;%ai4X L0C = L> #
(e4 XRa;ClBX L0C = R*! #
(e4 XRa;CSX L0C = L*H #
(e4 XRa;CreX L0C = <*8 #
(e4 XRa;1FX L0C = K*H #
(e4 XRa;LFX L0C = K*5 #
VV Leds
(e4 XLE,X L0C = T** #
VV Swi4:6es
(e4 Xrese4X L0C = LT #
(e4 Xsw*X L0C = T*!#
(e4 Xsw9X L0C = TT #
V 1sbNRS9K9 in4erfa:e
(e4 XRsRJX L0C = (*- W 71LL17#
(e4 XRsTJX L0C = (*8 #
VV LM' Conne:4or
(ET XCga"red<!RX L0C = 1- #
(ET XCga"red<*RX L0C = L- #
(ET XCga"red<9RX L0C = (- #
(ET XCga"green<!RX L0C = 78 #
(ET XCga"green<*RX L0C = T5 #
(ET XCga"green<9RX L0C = L5 #
(ET XCga"bl3e<!RX L0C = R- # V
(ET XCga"bl3e<*RX L0C = T- #
(ET X6syn:X L0C = (5 #
(ET XCsyn:X L0C = 7- #
VV7i: 1SFNH&, in4erfa:e
(e4 Xps9dX L0C = [*K W 71LL17#
(e4 Xps9:X L0C = L*9 W 71LL17#
VV &np34 and o34p34 pins
(ET Xre;o4e"inX L0C = KH#
(ET Xrelay"o34X L0C = MK#
(ET Xrelay"o349X L0C = [5#
(ET Xpw;"o34X L0C = HK#
(e4 Xd8X Lo:=L*9#
(e4 X:lo:B":onCX Lo:=7**#
(e4 Xrs4"nX Lo:=T*9#
Vled o34p34s
(ET Xo34p34"led<!RX L0C=1*5#
(ET Xo34p34"led<*RX L0C=L*5#
(ET Xo34p34"led<9RX L0C=1*H#
(ET Xo34p34"led<KRX L0C=L*H#
(ET Xo34p34"led<>RX L0C=<**#
(ET Xo34p34"led<HRX L0C=(**#
V- seg;en4 display o34p34s
(ET Xpoin4X Lo:=<*K#
(e4 Xsego34<!RX Lo:=T*-#
(e4 Xsego34<*RX Lo:=T*8#
(e4 Xsego34<9RX Lo:=1*-#
(e4 Xsego34<KRX Lo:=1*8#
(e4 Xsego34<>RX Lo:=<*>#
(e4 Xsego34<HRX Lo:=(*>#
(e4 Xsego34<5RX Lo:=L*>#
(e4 Xan<!RX Lo:=(*5#
(e4 Xan<*RX Lo:=(*H#
(e4 Xan<9RX Lo:=7*8#
(e4 Xan<KRX Lo:=7*-#
Appendi. 4: Eilin. Project F 2D3 Design Part F !c+ematics
Figure 2+ - temp5,"eg5!i"pla% "chematic"
Figure 2, - !igit"elcounter "chematic"
Figure 2- !i"pla%,"eg "chematic"
Appendi. C: @eil u;ision Project F !o-t1are Design Part
$#is part contains t#e ot#er part o! t#e pro3ect design0 $#e
retarget0c !ile and t#e part o! t#e )ector $able %ap and '/
#andlers !rom cm9dsasm0s are not part o! my own wor+0 $#ey
re used !rom t#e Corte8 %9 Design &tart - ID*0
C087D!.+:
?? Sys4e; ;e;ory
Vdefine R'<"S&OE !J*!!!!!! ?? *5 <F of 7SR'< on
,igilen4 Foard
Vdefine R'<"ST'RT !J!
Vdefine R'<"E(, R'<"ST'RT Y R'<"S&OE
?? 7erip6eral ;e;ory ;ap ??
Vdefine 'HF"CTRL"F'SE !JH!!!!!!!
Vdefine 'HF"1'RT"F'SE !JH*!!!!!!
Vdefine 'HF"&(71T"F'SE !JH9!!!!!!
Vdefine 'HF"LM'"F'SE !JHK!!!!!!
Vdefine 'HF"KE/F0'R,"F'SE !JH>!!!!!!
Vdefine 'HF"T&<ER"F'SE !JHH!!!!!!
retarget.c:
Vin:l3de <s4dioQ6R
Vin:l3de <4i;eQ6R
Vin:l3de <r4";is:Q6R
Vin:l3de XQ?C<!N,SQ6X
Vprag;a i;por4(""3se"no"se;i6os4ing)
?? &;ple;en4 a si;ple s4r3:43re for Cs I&LE 6andle and
?? define 46e lo:a4ion of 46e o34p34 :onsole (LM')
?? define 46e lo:a4ion of 46e inp34 (KF)
s4r3:4 ""I&LE E
3nsigned :6ar S p4r#
G#
I&LE ""s4do34 = E(3nsigned :6ar S) 'HF"LM'"F'SEG#
I&LE ""s4din = E(3nsigned :6ar S) 'HF"KE/F0'R,"F'SEG#
in4 prin4:6ar(in4 :6)
E
3nsigned :6arS Lga74r#
Lga74r = (3nsigned :6arS)'HF"LM'"F'SE#
SLga74r = (:6ar):6#
re43rn(:6)#
G
in4 fp34:(in4 :62 I&LE Sf)
E
Figure 2> uHi"ion Proect
"tructure
re43rn(prin4:6ar(:6))#
G
in4 ferror(I&LE Sf)
E
re43rn !#
G
in4 Iro;KeyFoard()
E
:6ar :6#
3nsigned :6arS KF74r#
KF74r = (3nsigned :6arS)'HF"KE/F0'R,"F'SE#
:6 = SKF74r#
prin4:6ar(:6)#
re43rn((in4):6)#
G
in4 fge4:(I&LE Sf)
E
re43rn(Iro;KeyFoard())#
G
Coid "44ywr:6(in4 :6)
E
fp34:(:62$""s4do34)#
G
Coid "sys"eJi4(Coid) E
w6ile(*)#
G
cm8dsasm.s :
S4a:B"Si@e ED1 !J!!!>!!!!
'RE' ST'CK2 (0&(&T2 RE',%R&TE2 'L&M(=>
S4a:B"<e; S7'CE S4a:B"Si@e
""ini4ial"sp
Heap"Si@e ED1 !J!!*!!!!!
'RE' HE'72 (0&(&T2 RE',%R&TE2 'L&M(=>
""6eap"base
Heap"<e; S7'CE Heap"Si@e
""6eap"li;i4
# Le:4or Table
7RESERLE8
TH1<F
'RE' RESET2 ,'T'2 RE',0(L/
E=70RT ""Le:4ors
""Le:4ors ,C, ""ini4ial"sp
,C, Rese4"Handler
,C, (<&"Handler
,C, HardIa3l4"Handler
,C, !
,C, !
,C, !
,C, !
,C, !
,C, !
,C, !
,C, SLC"Handler
,C, !
,C, !
,C, 7endSL"Handler
,C, SysTi:B"Handler
,C, Ti;er"Handler
,C, KF"Handler
,C, &np34"Handler
,C, 1'RT"Handler
,C, !
,C, !
,C, !
,C, !
,C, !
,C, !
,C, !
,C, !
,C, !
,C, !
,C, !
,C, !

'RE' WQ4eJ4W2 C0,E2 RE',0(L/
#Rese4 Handler
Rese4"Handler 7R0C
ML0F'L Rese4"Handler
E(TR/
L,R R*2 =!JE!!!E*!! #&n4err3p4 Se4 Enable Regis4er
L,R R!2 =!J!!!!!!-I
STR R!2 )R*+
&<70RT "";ain
L,R R!2 ="";ain
F= R! #Fran:6 4o "";ain
E(,7

(<&"Handler 7R0C
F Q
E(,7

HardIa3l4"HandlerU
7R0C
F Q
E(,7

SLC"Handler 7R0C
F Q
E(,7

7endSL"Handler 7R0C
F Q
E(,7
SysTi:B"Handler 7R0C
F Q
E(,7

Ti;er"Handler 7R0C
E=70RT Ti;er"Handler
71SH ER!2R*2LRG
707 ER!2R*27CG
E(,7
&np34"Handler 7R0C
E=70RT &np34"Handler
&<70RT &(71T"&SR
71SH ER!2LRG
FL &(71T"&SR
707ER!27CG
E(,7
1'RT"Handler 7R0C
E=70RT 1'RT"Handler
&<70RT 1'RT"&SR
71SH ER!2R*2R92LRG
FL 1'RT"&SR
L,R R*2 =!JH*!!!!!! #1'RT
L,R R92 =!JHK!!!!!! #LM'
L,R R!2 )R*+ #Me4 ,a4a fro; 1'RT
STR R!2 )R9+ #%ri4e 4o LM'
707 ER!2R*2R927CG
E(,7
KF"Handler 7R0C
E=70RT KF"Handler
71SH ER!2R*2R92RK2LRG
L,R R*2 =!JH5!!!!!! #KF
L,R R92 =!JH>!!!!!! #1'RT
L,R RK2 =!JHK!!!!!! #LM'
L,R R!2 )R*+ #Read fro; KF
STR R!2 )R9+ #%ri4e o34 on 1'RT
STR R!2 )RK+ #,isplay on LM'
707 ER!2R*2R92RK27CG
E(,7

'L&M( >
'RE' Tes42 C0,E

'L&M( >
# 1ser &ni4ial S4a:B $ Heap
&I .,EI.""<&CR0L&F

E=70RT ""ini4ial"sp
E=70RT ""6eap"base
E=70RT ""6eap"li;i4

ELSE

&<70RT ""3se"4wo"region";e;ory
E=70RT ""3ser"ini4ial"s4a:B6eap
""3ser"ini4ial"s4a:B6eap
L,R R!2 = Heap"<e;
L,R R*2 =(S4a:B"<e; Y S4a:B"Si@e)
L,R R92 = (Heap"<e; Y Heap"Si@e)
L,R RK2 = S4a:B"<e;
F= LR
'L&M(
E(,&I
E(,

0"Program.c :
//
// This ? fi#e cntains the :
// 4 =enu disp#a& functins ;
// 4 c#ing and heating a#g!ith=s ;
//
@inc#ude 9A/?M0BDSAh9
@inc#ude -stdiAhC
@inc#ude -!t_=iscAhC
@inc#ude -std$#AhC
@define i!_cde (int+((4(unsigned int4+AHD_EFGHT_DASIJ0"0K00+CC3+ //
i!_cde pins
@define ct!#_ut (4(unsigned int4+AHD_?TRL_DASI+ // utput cnt!#
// Ma!ia$#es
int i; // inde" cunte!
int $itte=p[3]; // t st!e the te=pe!atu!e f!= the 3B$it $us
f#at te=pe!atu!e; // te=pe!atu!e 0a#ue %ith deci=a# pa!t
$# n_ff=fa#se; // t )n% in %hich state is u! cnt!# p#atf!=
$# f!ced_e"it=fa#se;
// used t )n% %hat =enu psitin t disp#a& n sc!een
int inde"_=enu=0;
int inde"_ptins_=enu=0;
int setpint=0; // the desi!ed te=pe!atu!e
// th!esh#d 0a#ues
int th!esh#d_heat=2;
int th!esh#d_heat_t=p;
int th!esh#d_c#=2;
int th!esh#d_c#_t=p;
f#at th!esh#d_te=pe!atu!e;
// Ma!ia$#es used f! GED cnt!##e!
f#at pid_e!!!; // pid e!!! ( the diffe!ence $et%een the setpint and the
cu!!ent te=pe!atu!e +
f#at #ast_pid_e!!=0;
f#at integ!ati0e_0a#=0;
f#at de!i0ati0e_0a#=0;
f#at p!p!tina#_0a#=0;
f#at pid_0a#ue=0;
int dt=1;
int ct!#_0a#ue; // pid utput 0a#ue
// Kunctin p!tt&pes
0id EFGHT_ESR(0id+;
0id tu!n_n_functin(0id+;
0id tu!n_ff_functin(0id+;
0id set_=de(0id+;
0id heating_=de(0id+;
0id app#&_heating(0id+;
0id c#ing_=de(0id+;
0id app#&_c#ing(0id+;
0id pid_ut(0id+;
0id cnt!#_$#c)(0id+;
0id sh%_=enu(0id+;
0id ptins_=enu(0id+;
0id sh%_ptins_=enu(0id+;
0id ptin_=enu_=dified(int inc!ease+;
0id end(0id+;
0id de#a&(int cunt+;
0id c#ea!_sc!een(0id+;
0id sh%_te=pe!atu!e(0id+;
0id get_te=pe!atu!e(0id+;
0id HART_ESR(0id+;
// Main functin
int =ain(0id+ 8
%hi#e(1+;
<
0id HART_ESR(+ //
8
p!intf(9Nn K!= HART Nn 9+;
<
// functin ca##ed $& i! !e=te ERO
/4 Ef %e p!essed the n/ff $uttn (it has cde . + *
then it %i## tu!n n/ff the s&ste= * depending n situatin; 4/
0id EFGHT_ESR(+8
if((i!_cde+==.+8
n_ff=,n_ff;
if(n_ff==t!ue+
tu!n_n_functin(+;
e#se if(n_ff==fa#se+
tu!n_ff_functin(+;
end(+;
<
<
/4 This is the c#ea!_sc!een functinA Phen %e %i## p!int n the sc!een
cha!acte! 11 ( ca!!iage !etu!n +*
it %i## set the cu!s! t the !igina# psitin (0*0+ A Afte! that %e %i##
fi## the 0ga !a= =e=!& %ith e=pt& spaces
( t 0e!%!ite the e"isting cha!acte!s + * and p!int the N! cha!acte! again
f! cu!s! !epsitining ;
4/
0id c#ea!_sc!een(+8
p!intf(9:c9*11+;
f!(i=0;i-3;i;;+
p!intf(9
9+;
p!intf(9:c9*11+;
<
/4 a !udi=enta!& De#a& functin 4/
0id de#a&(int cunt+8
f!(i=0;i-cunt;i;;+;
<
/4 Kunctin used t c!!ect signa# t!ans=isin f u! !e=te cnt!#A 4/
0id end(+8
%hi#e((4(unsigned int4+AHD_EFGHT_DASIJ0"0K00+,=0+;
<
/4 Tu!n ff functinA Ku!the!=!e * it !esets settings t defau#tA 4/
0id tu!n_ff_functin(+8
p!intf(9NnTu!ning ffAAA 9+;
th!esh#d_c#=2;
th!esh#d_heat=2;
inde"_=enu=0;
inde"_ptins_=enu=0;
setpint=0;
de#a&(10000+;
c#ea!_sc!een(+;
<
/4 Tu!n n functinA Et disp#a& n the sc!een a =enu f!= %he!e %e can
chse ne f the ptins
it %i## d&na=ica##& disp#a& a ce!tain 9=enu9 acc!ding t se#ected ptin;
4/
0id tu!n_n_functin(+8
inde"_=enu=0;
inde"_ptins_=enu=0;
p!intf(9Nn Nn Pe#c=e,9+;
de#a&(10000+;
c#ea!_sc!een(+;
p!intf(9Nn Qptins:Nn C 1A Heating Mde Nn 2A ?#ing MdeNn
1A Qptins9+;
%hi#e(i!_cde,=5 JJ i!_cde,=.+8
%hi#e(i!_cde==0+; // %ait unti# %e !ecei0e a c==and
/4 acc!ding t %hat )e& %e p!ess ( d%n B 5* ! up B6 + it
%i## sh% the cu!!ent =enu
%ith an a!!% indicating the cu!!ent se#ectin
4/
if(i!_cde==5+8
c#ea!_sc!een(+;
inde"_=enu;;; // inde"_=enu is used t )n% the psitin
%e a!e in the =enu and t )n% h% t !ed!a% the =enu
if(inde"_=enuC2+
inde"_=enu=0;
sh%_=enu(+;
<
e#se if(i!_cde==6+8
c#ea!_sc!een(+;
inde"_=enuBB;
if(inde"_=enu-0+
inde"_=enu=2;
sh%_=enu(+;
<
<
if(i!_cde==5+8 // if %e p!essed the )a& $uttn %e %i## ente! in the
chsen ptin
p!intf(9Nn QR, 9+;
de#a&(10000+;
c#ea!_sc!een(+;
s%itch(inde"_=enu+8
case 0: heating_=de(+;
$!ea);
case 1: c#ing_=de(+;
$!ea);
case 2: ptins_=enu(+;
$!ea);
<
<
if(i!_cde==.+8
EFGHT_ESR(+;
<
<
/4 Sh% =enu functin A Disp#a&s the =enu 9i=age9 acc!ding t u! inde"
se#ectin 4/
0id sh%_=enu(+
8
s%itch(inde"_=enu+8
case 0:
p!intf(9Nn Qptins :Nn C 1A Heating Mde Nn 2A
?#ing Mde Nn 1A Qptins9+;
$!ea);
case 1:
p!intf(9Nn Qptins :Nn 1A Heating Mde Nn C 2A
?#ing MdeNn 1A Qptins9+;
$!ea);
case 2:
p!intf(9Nn Qptins :Nn 1A Heating Mde Nn 2A
?#ing MdeNn C 1A Qptins9+;
$!ea);
<
<
/4 Set =de functinA Et disp#a&s the cu!!ent te=pe!atu!e A Pe ha0e the
pssi$i#it&
t set a desi!ed te=pe!atu!e $& p!essing up ! d%n )e&sA Pe can
set a desi!ed
te=pe!atu!e $et%een 0 and 77A Ku!the!=!e* %e can a$!t an&ti=e
u! actin and
!etu!n t =ain =enu;
4/
0id set_=de(+8
p!intf(9?u!!ent te=pe!atu!e : 9+;
sh%_te=pe!atu!e(+;
p!intf(9:c?NnSet &u! te=pe!atu!e : 9*15+;
p!intf(9:d:c?9*setpint*15+;
%hi#e(i!_cde,=5 JJ i!_cde,=.+8
%hi#e(i!_cde==0+; // %ait unti# %e p!ess a )e&;
if(i!_cde==6+ // if %e p!essed up )e& ( inc!ease +
8
if(setpint-10+8 // if setpint is #%e! than ten it %i##
$ac)space 1 cha!acte!s and disp#a& the inc!eased setpint
p!intf(9N$N$N$9+;
setpint;=1;
end(+;
<
e#se if(setpint-77+8 // if setpint is #%e! than 77 it
%i## $ac)space 5 cha!acte!s and disp#a& the ne% 0a#ue
p!intf(9N$N$N$N$9+;
setpint;=1;
end(+;
<
<
e#se if(i!_cde==5+ // if %e p!essed d%n )e& ( dec!ease +
8
if(setpint-10 JJ setpintC0+8 // if setpint is #%e!
than 10 and $igge! than 0
// it %i## $ac)space 1 cha!acte!s and disp#a& the ne%
0a#ue
p!intf(9N$N$N$9+;
setpintB=1;
end(+;
<
e#se if (setpintC=10+8 // if setpint is $igge! than 10
it %i## $ac)space 5 cha!acte!s and disp#a& the ne% 0a#ue
p!intf(9N$N$N$N$9+;
setpintB=1;
end(+;
<
<
<
if(i!_cde==.+ // if %e p!essed the n ff $uttn* %e %i## !etu!n t
the =ain =enu
8
f!ced_e"it=t!ue;
p!intf(9Nn Qpe!atin a$!tedAAA9+;
ct!#_ut=0"00;
de#a&(10000+;
setpint=0;
c#ea!_sc!een(+;
!etu!n;
<
e#se // if %e p!essed the )a& $uttn
8
f!ced_e"it=fa#se;
p!intf(9 QR, 9+;
de#a&(10000+;
c#ea!_sc!een(+;
<
<
/4 ?#ing =de functinA 4/
0id c#ing_=de(+8
c#ea!_sc!een(+;
p!intf(9Nn ?#ing =de n, Nn9+;
de#a&(10000+;
set_=de(+;
if(f!ced_e"it==t!ue+
gt e"it;
app#&_c#ing(+;
gt e"it;
e"it: // !etu!ns t =ain =enu
tu!n_n_functin(+;
<
/4 App#& c#ing functinA Et cntains the c#ing cnt!# a#g!ith= 4/
0id app#&_c#ing(+8
th!esh#d_te=pe!atu!e=(f#at+setpint;th!esh#d_c#;
%hi#e(i!_cde,=.+8
acti0e_c#ing:
%hi#e(i!_cde,=.+8
p!intf(9Nn?u!!ent : 9+;
sh%_te=pe!atu!e(+;
p!intf(9:c?NnSetpint :9*15+;
p!intf(9 :d:c?9*setpint*15+;
if(((f#at+setpint-te=pe!atu!e+ JJ (i!_cde,=.++
8
pid_ut(+;
<
e#se
8
c#ea!_sc!een(+;
gt pause_c#ing;
<
f!(i=0;i-10000;i;;+
8
if(i!_cde==.+
8
ct!#_ut=0"00;
c#ea!_sc!een(+;
gt e"it_c#ing;
<
<
c#ea!_sc!een(+;
<
pause_c#ing:
ct!#_ut=0"00;
p!intf(9Sing t pauseAAA9+;
de#a&(50000+;
c#ea!_sc!een(+;
%hi#e(i!_cde,=.+8
i=0;
%hi#e(i-7777+8
i;;;
if(i!_cde==.+
gt e"it_c#ing;
<
get_te=pe!atu!e(+;
if(te=pe!atu!eC=th!esh#d_te=pe!atu!e+
8
de#a&(20000+;
gt acti0e_c#ing;
<
<
gt e"it_c#ing;
<
e"it_c#ing:
p!intf(9Nn Qpe!atin a$!ted AA 9+;
setpint=0;
de#a&(50000+;
ct!#_ut=0"00;
integ!ati0e_0a#=0;
p!p!tina#_0a#=0;
de!i0ati0e_0a#=0;
pid_0a#ue=0;
ct!#_0a#ue=0;
c#ea!_sc!een(+;
f!ced_e"it=t!ue;
!etu!n;
<
/4 Gid ut functin; ca#cu#ates the GED 0a#ue f! the GPM utput 4/
0id pid_ut(+8
#ast_pid_e!!=pid_e!!!;
pid_e!!!=te=pe!atu!eBsetpint;
p!p!tina#_0a#=104pid_e!!!;
integ!ati0e_0a#;=pid_e!!!;
de!i0ati0e_0a#=14(pid_e!!!B#ast_pid_e!!+/dt;
pid_0a#ue=p!p!tina#_0a#;(0A24integ!ati0e_0a#+;de!i0ati0e_0a#;
cnt!#_$#c)(+;
<
/4 En this functin %e p!cess the GED 0a#ue and %e send the fina# 0a#ue
t the
GPM 0e!i#g =du#e th!ugh a 6$it $us data4/
0id cnt!#_$#c)(+8
ct!#_0a#ue=(int+pid_0a#ue;
if(ct!#_0a#ueC=61A0+
ct!#_ut=0".K; // =a" speed
e#se if(ct!#_0a#ue-61A0+
ct!#_ut=ct!#_0a#ue;65;
<
/4 Heating =de functinA 4/
0id heating_=de(+8
c#ea!_sc!een(+;
p!intf(9Nn Heating =de n, Nn9+;
de#a&(10000+;
set_=de(+; // set te=pe!atu!e functin
if(f!ced_e"it==t!ue+ // Ef %e a$!ted $& p!essing the n/ff $uttn
gt e"it;
app#&_heating(+;
gt e"it;
e"it: //!etu!ns t =ain =enu
tu!n_n_functin(+;
<
/4 App#& heating functinA Et cntains the heating cnt!# a#g!ith= 4/
0id app#&_heating(+8
th!esh#d_te=pe!atu!e=(f#at+setpintBth!esh#d_heat;
%hi#e(i!_cde,=.+8
acti0e_heating:
%hi#e(i!_cde,=.+8
p!intf(9Nn?u!!ent : 9+;
sh%_te=pe!atu!e(+;
p!intf(9:c?NnSetpint :9*15+;
p!intf(9 :d:c?9*setpint*15+;
// if the te=pe!atu!e is #%e! than the setpint the
heating s&ste= is tu!ned n
if(((f#at+setpintCte=pe!atu!e+ JJ (i!_cde,=.++
8
ct!#_ut=0"30;
<
e#se // the!%ise it ente!s the pasi0e state
( pause_heating+
8
ct!#_ut=0"00;
c#ea!_sc!een(+;
gt pause_heating;
<
f!(i=0;i-.0000;i;;+8 // a s=a## de#a& ( if %e p!ess
the n/ff )e& %e %i## a$!t this =de +
if(i!_cde==.+
8
gt e"it_heating;
<
<
c#ea!_sc!een(+;
<
pause_heating:
p!intf(9Sing t pauseAAA9+;
de#a&(10000+;
c#ea!_sc!een(+;
%hi#e(i!_cde,=.+8
i=0;
%hi#e(i-7777+8 // de#a& ( if %e p!ess the
n/ff )e& %e %i## a$!t this =de +
i;;;
if(i!_cde==.+
gt e"it_heating;
<
get_te=pe!atu!e(+;
/4 if the cu!!ent te=pe!atu!e is #%e! ! eTua#
t the th!esh#d te=pe!atu!e it %i## ente! the
acti0e state (acti0e_heating+A K! e"a=p#e if
%e ha0e setpint=27 deg!ees * a th!esh#d 0a#ue
at 2 deg!ees * it =eans that if the cu!!ent
te=pe!atu!e is eTua# ! #%e! than 2. deg!ees
( 2. = 27 B2 + * then the heating s&ste= %i##
$e tu!ned n againA
4/
if(te=pe!atu!e-=th!esh#d_te=pe!atu!e+8
de#a&(20000+;
gt acti0e_heating;
<
<
gt e"it_heating;
<
e"it_heating: // a$!ts cu!!ent pe!atin
p!intf(9Nn Qpe!atin a$!ted AA 9+;
setpint=0;
ct!#_ut=0"00;
de#a&(10000+;
c#ea!_sc!een(+;
f!ced_e"it=t!ue;
!etu!n;
<
/4 Qptins =enu functinA He!e %e can change the th!esh#d 0a#ues f!
c#ing and heating =des 4/
0id ptins_=enu(+8
c#ea!_sc!een(+;
th!esh#d_heat_t=p=th!esh#d_heat; // %e %i## st!e the #ast 0a#ues
in s=e 9te=p!a!&9 0a!ia$#es
th!esh#d_c#_t=p=th!esh#d_c#;
p!intf(9Nn Qptins =enu: Nn C 1A Heating Mde Th!esh#d : 9+;
p!intf(9:d:c?9*th!esh#d_heat_t=p*15+;
p!intf(9Nn 2A ?#ing Mde Th!esh#d : 9+;
p!intf(9:d:c?9*th!esh#d_c#_t=p*15+;
%hi#e(i!_cde,=. JJ i!_cde,=5+8
%hi#e(i!_cde==0+; // %ait unti# %e p!ess a )e&
// the =enu disp#a& a#g!ith= ( si=i#a! t the =ain =enu +
if(i!_cde==5+8
c#ea!_sc!een(+;
inde"_ptins_=enu;;;
if(inde"_ptins_=enuC1+
inde"_ptins_=enu=0;
sh%_ptins_=enu(+;
<
e#se if(i!_cde==6+8
c#ea!_sc!een(+;
inde"_ptins_=enuBB;
if(inde"_ptins_=enu-0+
inde"_ptins_=enu=1;
sh%_ptins_=enu(+;
<
e#se if(i!_cde==3+8 // if %e p!ess #eft ! !ight )e& %e can
inc!e=ent ! dec!e=ent th!esh#d 0a#ue f! each =de
c#ea!_sc!een(+;
ptin_=enu_=dified(1+; // sh% =dified 0a#ues f!
heating =de th!esh#d 0a#ue
<
e#se if(i!_cde==7+8
c#ea!_sc!een(+;
ptin_=enu_=dified(2+; // sh% =dified 0a#ues f!
c#ing =de th!esh#d 0a#ue
<
<
if(i!_cde==.+
8
p!intf(9Nn Qpe!atin a$!tedAAA9+;
de#a&(10000+;
c#ea!_sc!een(+;
tu!n_n_functin(+;
<
if(i!_cde==5+
p!intf(9Nn QR, I"iting t =ain =enuAAA9+;
th!esh#d_c#=th!esh#d_c#_t=p; // getting ne% 0a#ues
th!esh#d_heat=th!esh#d_heat_t=p;
de#a&(10000+;
c#ea!_sc!een(+;
tu!n_n_functin(+;
<
/4 This functin disp#a&s the =enu acc!ding t cu!!ent se#ectin 4/
0id sh%_ptins_=enu(+8
s%itch(inde"_ptins_=enu+8
case 0:
p!intf(9Nn Qptins =enu: Nn C 1A Heating
Mde Th!esh#d : 9+;
p!intf(9Nn 2A ?#ing Mde Th!esh#d :
9+;
$!ea);
case 1:
p!intf(9Nn Qptins =enu: Nn 1A Heating
Mde Th!esh#d : 9+;
p!intf(9Nn C 2A ?#ing Mde Th!esh#d :
9+;
$!ea);
<
<
/4 This functin disp#a&s the =enu and the ne% th!esh#d 0a#ue acc!ding
t se#ected ptinA
The th!esh#d 0a#ue can 0a!& $et%een 1 and 7 deg!eesA
4/
0id ptin_=enu_=dified(int inc!ease+8
s%itch(inde"_ptins_=enu+
8
case 0 : 8
if(inc!ease==1+8
if(th!esh#d_heat_t=pC1+8
th!esh#d_heat_t=pB=1;
p!intf(9Nn Qptins
=enu: Nn C 1A Heating Mde Th!esh#d : 9+;
p!intf(9:d
:c?9*th!esh#d_heat_t=p*15+;
p!intf(9Nn 2A ?#ing
Mde Th!esh#d : 9+;
p!intf(9:d
:c?9*th!esh#d_c#_t=p*15+;
end(+;
<
e#se
8
th!esh#d_heat_t=p=1;
p!intf(9Nn Qptins
p!intf(9:d
p!intf(9Nn 2A ?#ing
Mde Th!esh#d : 9+;
p!intf(9:d
end(+;
<
<
e#se if(inc!ease==2+8
if(th!esh#d_heat_t=p-7+8
th!esh#d_heat_t=p;=1;
p!intf(9Nn Qptins
p!intf(9:d
p!intf(9Nn 2A ?#ing
Mde Th!esh#d : 9+;
p!intf(9:d
end(+;
<
e#se
8
th!esh#d_heat_t=p=7;
p!intf(9Nn Qptins
p!intf(9:d
p!intf(9Nn 2A ?#ing
Mde Th!esh#d : 9+;
p!intf(9:d
end(+;
<
<
$!ea);
<
case 1 : 8
if(inc!ease==1+8
if(th!esh#d_c#_t=pC1+8
th!esh#d_c#_t=pB=1;
p!intf(9Nn Qptins
=enu: Nn 1A Heating Mde Th!esh#d : 9+;
p!intf(9:d
p!intf(9Nn C 2A ?#ing
Mde Th!esh#d : 9+;
p!intf(9:d
end(+;
<
e#se
8
th!esh#d_c#_t=p=1;
p!intf(9Nn Qptins
p!intf(9:d
Mde Th!esh#d : 9+;
p!intf(9:d
end(+;
<
<
e#se if(inc!ease==2+8
if(th!esh#d_c#_t=p-7+8
th!esh#d_c#_t=p;=1;
p!intf(9Nn Qptins
p!intf(9:d
Mde Th!esh#d : 9+;
p!intf(9:d
end(+;
<
e#se
8
th!esh#d_c#_t=p=7;
p!intf(9Nn Qptins
p!intf(9:d
Mde Th!esh#d : 9+;
p!intf(9:d
end(+;
<
<
$!ea);
<
<
<
/4 Set te=pe!atu!e is a functin %hich gets the te=pe!atu!e f!= a 3 $it
data $us and cn0e!ts it int a f#at 0a!ia$#e 4/
0id get_te=pe!atu!e(+8
f!(i=0;i-3;i;;+
8
$itte=p[i]=(4(unsigned int4+AHD_EFGHT_DASIJ(1--i++CCi;
<
te=pe!atu!e=($itte=p[0]40A5+;($itte=p[1]41+;($itte=p[2]42+;
($itte=p[1]45+;($itte=p[5]43+;($itte=p[5]416+;($itte=p[6]412+;
($itte=p[.]465+;
<
/4 This functin is used t disp#a& the te=pe!atu!eA Hnf!tunate#& the
S? s&ste= cannt disp#a& n the sc!een a f#at !
du$#e 0a!ia$#e ( n#& intege! ! cha!acte! +A 4/
0id sh%_te=pe!atu!e(+8
get_te=pe!atu!e(+;
if($itte=p[0]==0+ // if the deci=a# $it is 0 * %e %i## disp#a& the
intege! pa!t f the te=pe!atu!e and 9A09 cha!acte!s
8
p!intf(9:dA09*(int+te=pe!atu!e+;
<
e#se // %e %i## disp#a& the intege! pa!t f the te=pe!atu!e and
9A59 cha!acte!s
8
p!intf(9:dA59*(int+te=pe!atu!e+;
<
<
Appendi. D: 3ist 1it+ Design Flo1 C+arts
Here is t#e list wit# t#e !lowc#art submitted along t#e pro3ect documentation 4!older !lowc#arts57
9ame Comments
legend03pg Color Legend !or !lowc#arts
applyLcooling03pg applyLcooling45 !unction !lowc#art
applyL#eating03pg applyL#eating45 !unction !lowc#art
clearLscreen03pg clearLscreen45 !unction !lowc#art
controlLbloc+03pg controlLbloc+45 !unction !lowc#art
coolingLmode03pg coolingLmode45 !unction !lowc#art
#eatingLmode03pg #eatingLmode45 !unction !lowc#art
optionLmenuLmodi!ied03pg optionsLmenuLmodi!ied45 !unction !lowc#art
optionsLmenu03ps optionsLmenu45 !unction !lowc#art
setLmode03pg setLmode45 !unction !lowc#art
s#owLmenu03pg s#owLmenu45 !unction !lowc#art
s#owLoptionsLmenu03pg s#owLoptionsLmenu45 !unction !lowc#art
turnLonL!unction03pg turnLonL!unction45 !unction !lowc#art
Appendi. >: FPGA Climatic board description

Design Contest Report - FPGA Climatic 2

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