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The Datasheet of CH365

PCI Interface Chip CH365


English Datasheet
Version:1D
http://wch.cn
1. Introduction
CH365 is a universal PCI bus interface chip. It supports I/O mapping, memory mapping, expansion
ROM and interrupts. CH365 transforms the high-speed 32-bit PCI bus into 8-bit active parallel ISA analogue.
It is very useful to make the low cost PC card based on PCI bus or update ISA bus to PCI bus. Comparing
with other popular buses, the speed of PCI bus is faster and the capability of real-time and control is better.
So CH365 is applied to the I/O control card, communication interface card, A/D&D/A card, electron disk
and expansion ROM, which are high speed and real-time. The following is its basal application plan.


























2. Feature
Realize the slave device interface based on the 32-bit PCI bus.
Transform PCI interface into active parallel interface: 8-bit data bus, 16-bit address bus, I/O read and
write, memory read and write.
Set device identifier (Vendor ID, Device ID, Class code and so on) if you want to.
Write and read I/O port or memory by byte, word and double word.
The speed in test can reach to 7MB per second in no burst transfer condition and the pulse width can
be chosen from 30 ns to 240 ns at the 30ns interval
Distribute I/O base address automatically, and support the 240 words I/O ports.
Support local hardware fixed addressing function, which can realize the I/O addressing at the
PCI_INTA
SYS_EX
(INT_REQ)
MEM_WR
(IOP_HIT)
MEM_RD
IOP_WR
IOP_RD
D[7-0]
A[15-0]
PCI_CBE[3-0]
PCI_AD[31-0]
PCI_RST
PCI_CLK
PCI_DEVSEL
PCI_TRDY
PCI_IRDY
PCI_FRAME
PCI_IDSEL
PCI_PAR










CH365
Interface
Chip












PCI
Bus












Local
8-bit
Bus


The Datasheet of CH365 !
appointed position by choosing I/O port freely.
Update the ISA I/O card to PCI bus directly without modifying the interrelated software of ISA card.
Support the direct mapping of the 32KB memory SRAM or expansion ROM (Boot ROM).
Support the 64KB or 128KB memory or expansion ROM without adding the external components.
Support the expansion ROM without bootable hard disk and Flash-memory updated on line.
Provide the expansion ROM application subprogram library BRM which is used to display user
interface and deal with data under BIOS.
Support low local interrupt request and shareable interrupt.
Provide simple 2-wire serial host interface which is commonly connected with the similar component
of 24C0X EEPROM.
Contain hardware counters from 4us to 1ms that is the delay reference in the software runtime.
Adapt the big pin interval PQFP-80 encapsulation that is compatible with CH365 pins.
Universal driver supports windows 98/2000/xp and provide the API through DLL.
CH365 chip itself and the card upgrade works without driver.
Own some patents. Its usage is easy and its cost is low.

3. Package


























Package shape width of Plastic Pitch of pin Instruction of package Ordering type
PQFP-80 20mm x 14mm 0.8mm 31.5mil Plastic Quad Flat Package of 80-pin CH365P


The Datasheet of CH365 "
4. Pins
4.1. Power bus
Pin No. Pin Name Pin Type Pins Description
20,61,80 VCC Power Positive power
1,21,60 GND Power Public ground

4.2. PCI bus signal
Pin No. Pin Name Pin Type Pin Description
64 PCI_RST IN System reset signal, active with low
65 PCI_CLK IN System clock signal, active with rising-edge
2-5
14-19
22-23
25-32
66-73
76-79
PCI_AD31#PCI_AD0
Tri-state
output and
input
Address/data time-multiplexed bus
6,13
24,74
PCI_CBE3#CI_CBE0 IN Command / Byte enable signals
12 PCI_PAR
Tri-state
bidirectional
Data Parity error signal
75 PCI_IDSEL IN
Initialization device select signal,
active with high
7 PCI_FRAME IN Cycle frame signal, active with low
8 PCI_IRDY IN Initiator ready signal, active with low
9 PCI_TRDY
Tri-state
output
Target ready signal, active with low
10 PCI_DEVSEL
Tri-state
output
Device select signal, active with low
11 PCI_INTA
Tri-state
output
INTA interrupt request line, active with low

4.3. Local signal
Pin No. Pin Name Pin Type Pin note
51-58 D7#D0
Tri-state
output and
in
8-bit bidirectional data bus pulled up by resistors
D7 is still the 2-wire serial interface signal SDA
33-39
42-50
A15#A0 OUT
16-bit address bus, A15~A10 can be controlled to
export address alone
40 IOP_RD OUT I/O port read enable, active with low
41 IOP_WR OUT I/O port write enable, active with low
62 MEM_RD OUT
Memory or expansion ROM read enable, active with
low
MEM_WR OUT
Memory or expansion ROM write enable, active
with low 63
Time-multiplexed
IOP_HIT IN
Local hardware fixed address request, active with
low, pull-down resistor is embedded
The Datasheet of CH365 $
SYS_EX IN
Output signal, it can be controlled alone,
It is also the 2-wire serial interface clock signal SCL 59
time-multiplexed
INT_REQ IN
Local interrupt request input signal ,active with low,
pull-up resistor is embedded
5. Set the work mode
For providing more functions without adding the pins, CH365 uses some time-multiplexed pins and you
can choose the function through setting the work mode. The detailed method is the following. The native
8-bit data lines D[7: 0] are pull-up or pull-down to set the signals high or low. CH365 sets the work mode
and parameters according to the default status after resetting. The pull-up or pull-down won!t affect the data
bus drive as the current isn!t higher than 1mA when the signal is drive as data bus. In addition, the work
mode and parameters of CH365 are set once time in the 1us of resetting. If the drive ability of peripheral
equipment is low or it is drive by the OC circuit, the pull-down is realized in the short reset time and shield
or transformed into pull-up in other time.
The following figures are the two circuits for the work mode set. Data lines D[7:0] are connected with
the 40k ohm pull-up resistors in CH365. Data line is low when it is connected with pull-down resistor.
Otherwise, it is high. The left figure shows the common usage. D4 and D1 are pull-down by the 6.1k ohm.
So the data bus value is 11101101b. Because the pull-up or pull-down resistor value is high, CH365 and
peripheral equipments won!t affect data bus driver. When the drive current of peripheral equipments is lower
than 1mA or it is the OC drive circuit, you can consult the right figure. In the figure, RST is the PCI reset
signal. The point A affected by C5 lasts several ms in low after resetting. CH365 completes the work mode
and parameters set after the above operations. In the right circuit data bus D[7:0] value is 1101110b.











The following table shows the value of the various work modes and parameters. For example, D1=1
enables vendor to set the PCI card ID. D3=0 enables the interrupts. D3 and D4 can!t be 0 at the same time
Data bus Note of data bus Set the value to 0 Set the value to 1
D0
Set the default value of A15 after
resetting system
A15 is 0 after
resetting
A15 is 1 after resetting
D1
Choose the PCI Vendor ID and
Device ID
ID is provide by the
external
Use the default ID
D3
Select the function of the
time-multiplexed pin 59
INT_REQ SYS_EX
D4
Select the function of the
time-multiplexed pin 63
IOP_HIT MEM_WR
others
Product manufacture can use them according to their demands. Data status can be red from
configuration space 41H. For example, D2, D5, D6 and D7 are pull-down optionally to
identify the card function for application program.

The Datasheet of CH365 %
6. Register
6.1. Basal protocol
6.1.1. Attribute abbreviation: R=only-read, W=read and write, S=only-read but set before use, "=
suspension points.
6.1.2. Data regulation: if the data ends with h it is hex, otherwise, it is binary.
6.1.3. Data wildcard character and attribute: r=reserved (forbidden to use), x=random, "= suspension
points.
6.2. Configuration space (0FFH-00H)
Class Address Register name Register attribute
Default value after
resetting
01H-00H Vendor ID SSSS 4348H
03H-02H Device ID SSSS 5049H
05H-04H
Command
register
RRRRRRRRRRRRRRWW 0000000000000000
07H-06H Status register RRRRRRRRRRRRRRRR 0000010000000000
08H Revision ID SS 10H
0BH-09H
Device class
Code
SSSSSS 100000H
0FH-0CH SSSSSSSS 00000000H
13H-10H I/O Base Address
RRRRRRRRRRRRRRRR
WWWWWWWWRRRRRRRR
0000000000000000
0000000000000001
17H-14H
Memory Base
Address
WWWWWWWWWWWWWWWW
WRRRRRRRRRRRRRRR
0000000000000000
000000000000x000
2FH-18H SSSS".SSSS 0000".0000H
33H-30H
ROM Base
Address
WWWWWWWWWWWWWWWW
WRRRRRRRRRRRRRRW
0000000000000000
0000000000000000
3BH-34H SSSSSSSSSSSSSSSS 0000000000000000H
Standard
PCI
device
configuration
Space
3FH-3CH
Interrupt Line
& Pin
RRRRRRRRRRRRRRRR
RRRRRRRRWWWWWWWW
0000000000000000
0000000x00000000
40H
Chip control
register
RRRRRWWW rrrrr00x
41H
8-bit bus Output
ports
RR xxH
42H
Chip Status
register
RRRRRRRR xxrxrxrx
43H Reserved &forbidden' &forbidden'
Control
registers
and
others
Others 4FH-44H is the 43H-40H bynames. 50H-FFH is reserved, and only red out 00H

6.3. I/O space 0FFH-00H (actual address is the offset address added the I/O base address)
Class
Offset
address
Register name and note Register attribute
Default value after
resetting
Ports 0EFH-00H Standard local I/O ports WW
Connected with I/O
devices
0F0H A7-A0 address set register WWWWWWWW xxxxxxxx
0F1H A15-A8 address set register WWWWWWWW 000000xx
Memory
ports
0F2H Reserved &forbidden' &forbidden'
The Datasheet of CH365 (
0F3H Memory data access register WW
Connected with
memory
0F4H Data access register WW xxH
0F5H Control and status register WRRRRRRW 00000000
0F6H Address set register WW 00H
2-wire
serial
interfaces
0F7H Device and command register WW 00H
0F8H Chip control register RRRRRWWW rrrrr00x
0FAH
Read /write speed control
register
WRRWRWWW 0rr0r111
0FCH Hardware cycle count register RR xxH
Control
registers
and
others Other
address
Reserved &forbidden' &forbidden'

6.4. Note of register bit
Register name bit Attribute Bit usage note Value=0 Value=1
Bit-0 W Set A15 pin input value Low High
bit-1 W Set SYS_EX pin output value Low High
Chip control register
&configuration space
offset address 40H'
&I/O space offset address
0F8H'
Bit-2 W
Set INTA interrupt active
status
No
interrupt
Interrupt
bit-0 S
Select current PCI device
signature
External
ID
Default
ID
Bit-2 S
Local hardware addressing
function
Forbidden Use
Bit-4 S Internal Boot-ROM function Forbidden Use
Bit-6 S SYS_EX output signal Forbidden Use
Chip status register
(configuration space offset
address 42H'
Bit-7 S Interrupt enable function Forbidden Use
Bit-0 W
2-wire serial interface work
status
Completed Working
2-wire serial interface
control and status register
&I/O space offset address
0F5H'
Bit-7 W Select SCL output signal A15 SYS_EX
Bit-2
Bit-1
Bit-0
W
W
W
bit2#bit0 set read/write pulse width)interval is 30nS
bie4 is 0)the speed is 30nS#240nS according to 000#
111
bit4 is 1)the speed is 0nS#210nS according to 000#
111
Bit-4 W Data and address building time 15nS 45nS
Read/write speed control
register
&I/O space offset address
0FAH'
Bit-7 W Memory space access register Forbidden Enable

7. Space mapping
7.1. Space mapping
PC contains three spaces: memory space, I/O space and Configuration space. Memory space is
composed of EMS memory, VGA memory, expansion ROM, device buffer and so on, which are utilized to
access the block data or transfer data. I/O space contains the device control registers and state registers
which are generally utilized to the device control, detection and transfer little data. Configuration registers
mainly provide the basal device information to the system and accept the control and detection of the global
status.
For avoiding address confliction, PCI bus requires the device address can be relocated. The relocated is
The Datasheet of CH365 *
realized by the device base address of configuration space. Generally, the device base address registers are
distributed different base address. The devices are mapped to different base address range. If it is necessary,
application program itself can modify the base address.
Memory space of CH365 is 32KB and offset address range is from 00H to FFH. All address space is
able to be utilized by peripheral devices. The actual address is the memory base address added the offset
address. I/O space is 256 bytes and the user only can use the 240 bytes from 00 to EFH excluding the
registers of CH365 itself. The actual address is I/O base address added the offset address.

7.2. Internal framework and signal


The above figure is the primary framework of CH365. CH365 produces internal data bus D[31:0],
The Datasheet of CH365 +
internal address bus A[31:0], read I/O port signal, write I/O port signal, read memory signal, write memory
signal and so on. The transferring direction is marked in the figure.
The right signals of framework figure are the external pins provided by CH365. Address bus A[15:0]
offers the relative offset address. Data bus D[7:0] is used to import data in the read transaction and export
data in the write transaction. IOP_RD is utilized to afford the I/O read enable pulse signal. IOP_WR is
utilized to afford the I/O write enable pulse signal. MEM_RD is utilized to afford the memory read enable
pulse signal. MEM_WR is utilized to afford the I/O write enable pulse signal. The above read/write enable
pulse signals are asserted by low. CH365 offers data bus, address bus, read /write enable signals, which are
similar with the ISA signals. This benefits the update from ISA to PCI. In addition, the read /write enable
signals of CH365 are controlled by the internal CS (chip select). For the read/write enable signals are only
valid in the base address mapping scope, the CS decoding circuit for peripheral devices is unnecessary.
In the I/O read /write transaction, A[7:0] exports I/O port offset address that offers the offset address
ranged from 00H to FFH to peripheral devices. The peripheral devices can decode A[7:0] farther to produce
the 2-level CS. In the I/O read /write transaction, CH365 keeps A[15:0] unaltered, but the internal registers
can be set to low or high in advance. If using local hardware addressing function, decode the A[9:0] of
CH365. Through CH365 requiring local addressing, it realizes the I/O port addressing ranged from 000H to
3FFH, which is compatible with ISA bus.
In the memory read/write transaction, A[14:0] exports the offset address which offers the valid offset
address ranged from 0000h to 7FFFH to peripheral devices. In the memory read/write transaction, CH365
keeps A15 unaltered, but permits the internal registers to set to low or high beforehand. It is used to expand
memory address bus or choose page. For expansion ROM is one kind of memory, the usage is same to
memory.

7.3. Data width
CH365 supports PC program to read/write the I/O port and memory in byte, word and double word in
the continuous multi-byte read transaction. CH365 adds 1 to offset address after completing the read
transaction every time. The pointer points the next byte offset address. When PC executes a four-byte
instruction, CH365 decompounds it to four 8-bit data read/write transactions. In the PC view, CH365 offers
the 8-bit, 16-bit and 32-bit data width. In fact, the work efficiency is higher and the whole data transaction
speed is faster when it is32-bit data width.
The left figure is the wave of assemble language #out dx,eax$. DX is the first word of random double
word I/O base address in the I/O base address range. For example, DX=IoBaseAddress+4; the right is the
wave of assemble language #out dx,al $ and C-language instruction #output(IoBaseAddress+1,value)$. I/O
read and memory read/write are similar with I/O write. If PC executes a 32-bit instruction, CH365 produces
four continuous 8-bit data operations automatically. So the data transferring efficiency is higher than 8-bit
instruction.












7.4. Example explanation
Design a PCI card based on CH365, which is similar with the print port. The I/O offset address 00H is
The Datasheet of CH365 ,
assumed as the data port and 02H is the control port. After being inserted into PC, the card is distributed a
I/O base address 9600H, the control port I/O address is 9502h. Distinguishing the port is realized through
decoding A[7:0]. If other ports are unnecessary, the decode circuit is simple due to using A[1:0] only.
If insert two same card into PC, the second card is distributed a I/O base address automatically. The I/O base
address may be different from the first. If the second card is C700H, then the control port of the second is
actually C702H. In this mean, the two PCI card get the different I/O port address to avoid the confliction of
I/O address.
The card designer and relative application program know the card I/O offset address but not the base
address. Before the application program carries through the I/O transaction, we shall learn the current I/O
port base address from the I/O base address register of configuration space. The actual address is the I/O
base address added the offset address. The last, the I/O transaction is executed according to the actual
address.
Memory operation is similar with I/O. The example is the high-speed data transaction of CH365
connected with 32KB double-port SRAM. If the memory base address of CH365 is distributed to
E30500000H. The PC program reading or writing the physical address scope from E3050000H to
E3057FFFFH is reading or writing the double-port SRAM. Note, the actual PC program reads or writes
dummy address not the physical address. If memory reads or writes in DOS, the memory base address is set
under the 1MB, such as 000D0000H or 000D8000H
The following is the read/write process.
-1 Write 5AH to control port, the C-language program is that #outport (0x9502,0x5AH)$.After that,
address bus A[7:0] of CH365 exports the offset address 02H but not the base address 9500 of control port.
Data bus D[7:0] of CH365 exports 5Ah, at the same time IOP_WR is changed to low. The read/write speed
control register sets pulse width in advance. The default is 240ns.
-2 Read data from data ports and status ports, and the C-language program is that #inport(0x9500)$.
The low byte is read from the data port and the high byte from status port. After the operation, A[7:0] exports
the data port offset address 00H.IOP_RD exports the second low, and peripheral device imports the status to
data bus[7;0].
-3 Memory read/write is similar with I/O read/write, but there are two differences between them. One
is that memory exports the A[14:0] 15-bit offset address while I/O A[7:0] 7-bit offset address. The other is
that MEM_RD exports the read control signal instead of that IOP_RD exports the write control signal, then
peripheral device distinguishes whether t is memory read/write operation or I/O read /write operation.

8. Parameter
8.1. Absolute maximum (If equal to or exceed the value, the chip will work not normally or be
damaged)

Name Parameter note Minimum Maximum Unit
TA The environment temperature -20 70
TS Storage temperature -55 125
VCC
Power voltage&VCC connected with power)GND
connected with ground'
-0.5 6.5 V
VIO Input/output pin voltage -0.5 VCC+0.5 V

8.2. Electric parameter (test condition.TA=25)VCC=5V)excluding PCI bus pin'
Name Note Min Typical Maximum Unit
VCC
Power voltage&please refer to the following
note '
3.3 5 5.5 V
ICC Power current when working 10 20 50 mA
The Datasheet of CH365 /
VIL Low input voltage -0.5 0.8 V
VIH High input voltage 2.0 VCC+0.5 V
VOL Low output voltage&4mA sucking current' 0.5 V
VOH
High output voltage &4mA exporting
current'
4.5 V
IIN importing current without pull-up resistor 10 uA
IUP importing current with pull-up resistor 50 uA
RUP Pull-up resistor value&not linear equivalent' 40 60 100 K&
Note.the actual sustainable voltage of CH365 is the power voltage added 0.5V)For example)when CH365
works at 3.3V power voltage)input voltage provided by peripheral equipments must not exceed 3.8V0When
power voltage of CH365 is lower than 4V)the main frequency of PCI bus must not higher than 33MHz)in
other word, CH365 can!t exceed the main frequency.

8.3. Timing parameter&test condition.TA=25)VCC=5V)FCLK=33.3MHz)please refer to figure'
Name Parameter note Minimum Typical Max Unit
FCLK
CLK input frequency&PCI bus main
frequency'
0 33.3 40 MHz
TEN
IOP_RD1IOP_WR1MEM_RD1MEM_WR
Read /write enable low pulse width
30
Select
30#240
240
Default
nS
TENS
IOP_RD1IOP_WR1MEM_RD1MEM_WR
Multi-byte continuous enable high interval
width
30
default
Select
30 or 60
60 nS
TAS Address A15#A0 output building time 12
Select
15 or 45
nS
TAH Address A15#A0 output keeping time 12 15 nS
TDS Data D7#D0 output building time 12
Select
15 or 45
nS
TDH Data D7#D0 output keeping time 12 15 nS
TIS Data D7#D0 input building time 15 nS
TIH Data D7#D0 input keeping time 0 nS
TINT INT_REQ interrupt request pulse width 80 100 nS
FSCL
SCL output frequency &2-wire serial
interface '
FCLK / 128 = 260 KHz
TI2C0 Start and end operation SDA low time 3.84 uS
TI2C1 Start and end operation SDA high time 3.84 uS
TI2CS SDA data output building time 1.92 uS
TI2CH SDA data output keeping time 1.92 uS

8.3.1. Read/Write enable pulse width TEN is set by the bit 2 to bit 0 of read/write speed control register. It
can be chosen between 30ns-240ns. The interval is 30us. The error is 10%.
8.3.2. In the multi-byte continuous read/write operation, the internal of read/write enable pulse width is set
by bit 4 of read/write speed control register. The interval is 30ns when the bit is 0. Otherwise, it is 60ns.
The error is 10%. In the single byte operation, the minimum is 150ns, but we often set it above 400ns.
If CH365 is connected with double-port SRAM or its peripheral circuit read/write speed is less than
25ns, the interval is advised as 60us.
8.3.3. Address output building time TAS and data output building time TDS are the time ahead that the
address and data output are asserted relative to read/write enable pulse falling-edge. TAS and TDS are
set by bit 4 of read/write speed control register. Set to 0 is 15nS, and set to 1 is 45nS. The error is 10%.
8.3.4. For read transaction)CH365 samplings 8-bit data bus D[7:0] at the read enable pulse rising-edge. So
The Datasheet of CH365
the peripherals should send the valid data to data bus before the read enable pulse rising-edge. Data
building time TIS is the ahead time that data D[7:0] validly sent by device relative to the read enable
pulse rising-edge.
8.3.5. Interrupt request pulse width TINT is to ensure the width of interrupt request low received by CH365)
If the time of INT_REQ at low is too short)CH365 may not accept the interrupt0
8.3.6. 2-wire serial interface timing.SDA is input/output bidirectional port)CH365 exports data at CLK
rising-edge, and samplings input data at SCL rising-edge. If the 2-wire serial interface is idle)SCL
keeps low)SDA tri-state output is forbidden, and keeps high by internal pull-up resistor.


9. Application
9.1. Connected with PCI bus
The figure in the next page is the standard circuit of CH365 connected with PCI bus. The capacitors
C1-C4 is used to eliminate the power coupling. C2-C4 all are 0.1uf and they are monolithic or radioceramic
capacitor. They are connected with three power lines. The number of them is no less than 3 as better. The
power lines can be chosen freely but the number is no les than 4.
For CH365 is the high frequency digital circuit, the impedance matching should be considered. The PCI
bus specification should be referred in the PCI card design. The length of PCI bus is advised no more than
35mm. The line should be arc or 45 degree. Signal line should be distributed on the component surface and
the most area on the rear of PCB should be connected with ground or covered with copper. The length of
clock line CLK should kept between 50mm and 65mm, and be not close with another signal line. We advise
The Datasheet of CH365 !
that the both sides of CLK and the rear of PCB should be grounded or covered with copper to avoid other
signal interference.


9.2. Connected with memory
MEM_RD and MEM_WR connect CH365 and memory U2(SRAM2256) . Before reading and writing the
memory, the computer ought to get the memory base address register of CH365 configuration space. Then
the base address added offset address gets U2 physical address in the PC memory. Finally read and write the
content of the memory U2 through the actual physical address or the dummy address.
The C-language WDM and DLL program based CH365 is followed;
.





























UCHAR mByte; // data cell)used to store the data red from the memory or written to memory
mPCH365_MEM_REG mMemBase; // memory base address)the actual data address is equal to the base
address added the offset address
CH365OpenDevice( TRUE, FALSE ); // open CH365 device)similar with the file operation that you use
after opening
CH365GetMemBaseAddr( &mMemBase ); // get CH365 memory address
CH365ReadMemByte( & mMemBase -> mCh365MemPort[0x1234], &mByte );
// the above operation gets a byte data from the memory address 1234H
CH365WriteMemByte( & mMemBase -> mCh365MemPort[0x2E0C], mByte + 0x76 );
//the operation adds the 76H to the last data and writes it to the memory address 2E0CH
The Datasheet of CH365 "
CH365CloseDevice( ); // all the operations are over ,ensure the Ch365 device closed then exit the program.
In DOS or the PC without device OS surroundings, the assembler is the following;
MOV AX,0B10DH ;write data into the PCI configuration space in double-word
MOV BX,CH365_PCI_BUS_DEV_ADDR ;the PCI address of CH365 card)the bus/device/function number
CH365 Chinese manual &2' !
MOV ECX,000D0001H ;map memory to D000H which exists in the PC space
MOV DI,0014H ;the offset address of memory register PC_BASE_ADDRESS
INT 1AH ;set memory base address for memory space
;the memory base address attributed automatically is above 1000H)for DOS can!t b located in it)we should
modify the base address
MOV AX,0D000H
MOV ES,AX ;set the address at D000H
MOV AL,ES:[1234H] ; get a byte data from the memory address 1234H
ADD AL,76H
MOV ES:[2E0CH],AL ;read the data
If transform the normal SRAM to double-port SRAM, CH365 can exchange data with MCU or DSP through
the double-port SRAM.IF you set the read and write enable pulse width 30ns and exchange the data by
double word, the test speed of data exchange is 7MB per second.












9.3. Connected with the Expansion ROM
MEM_RD connects the CH365 and ROM U3. CH365 supports the 32KB or 64KB EPROM and
FLASH-Memory. IF SYS_EX is A16 address bus, the size can be 128 KB. CH365 supports 32KB expansion
ROM (the size of 27C256) directly. If controlled by A15 through expansion Rom program, CH365 supports
the 64KB ROM. The pull-down resistor R1 set the work mode. In the figure D0 is connected with pull-down
resister .So A15 is low after resetting system and U3 is set to the low 32KB(offset address is from 0000H to
7FFFH). When read the high 32KB offset address from 8000H to 0FFFFH by setting bit 0 of the chip control
register to reset the A15. The usage of A16 is similar with A15. In addition, the content of PCI expansion
ROM is copied to the EMS memory by BIOS. So you should reset the expansion ROM base address to map
U3 to memory space. A15 pin of CH365 is not only used as the address bus but also the control of selecting
the multi-chip freely. For example, when Ch365 is connected with SRAM and ROM at the same time, the
chip select is switched by A15.
If the boot program and application program are written in, the expansion ROM of PC without hard disk
and OS is equal to an election disk. The boot program and application program can control the computer to
realize some functions. For example, PC without hard disk is utilized to control the peripheral device and the
task flow in industry.

9.4. Be connected the 2 line serial interface EEPROM
The signal line SCL of CH365 selects SYS_EX or A15.The default is A15 after resetting system.
SYS_EX is chosen while A15 is address bus. Otherwise, choose A15. SDA is data bus too. For avoiding the
The Datasheet of CH365 $
unnecessary mistake operation, SCL keeps low after resetting system by the work mode set.
The two line serial interface of Ch365 using 7-bit device address can be connected with multi-devices.
The bit7 to bit1 of the device and command register choose the slave device and the bit 0 is the command bit.
Bit 0 represents write operation when it is 0 and read operation when it is 1. For example, CH365 is
connected with two 24C02 chips. The operation steps reading from one ship and writing to the other chip are
the following:
Operation steps Read from12H Write data to 34H Note
Examine A2-A1-A0 pin of 24C02 A2-A1-A0=000 A2-A1-A0=010
actual device
address
Set address and command register Import 10100001 Import 10100100
Device address and
command
Set address register Import 12H Import 34H
Set operation
address
Data access register Null Import 56H Import 56H
Control and status register Set bit 0 to 1)keep others unalterable
Start interface
operation
Control and status register
Wait until bit change into 0 or wait
10mS
Wait until operation
is completed
Data access register Export 78H Null Export 78H
The C-language WDM and DLL program based Ch365 is following:
CHAR mByte;//data cell, store the data red from or write to 24C02
CH365ReadI2C(0x50,0x12,&mByte);// read one byte from 24C02 address 12H
CH365WriteI2C(0x52,0x34,0x56);// write 56H to 24C02 address 34H

















9.5. Application of I/O port
Read enable signal IOP_RD and Write enable signal IOP-WR control the decode operation of 74LS139.
74LS139 exports 2-line read control and 2_line write control after decoding the address. The peripheral
circuit gets two groups 8-bit buffer input and two groups 8-bit locking output. For example, when the I/O
address of CH365 is 5A00H, reading the 5A00H port is reading the first group buffer input and writing the
5A00H port is writing the second group locking output. If Ch365 isn!t connected with expansion ROM or
memory, the idle address bus A14 to A10 and A15 can be used directly as the output control bus. In the time
of resetting the system, A15 is low. After resetting system, A14 to A10 is low. A15 is default as high by
setting the work mode. But when D0 is pull-down, A15 is set to low in the resetting system time.
The Datasheet of CH365 %
The input and output signals of CH365 are compatible with TTL power and CMOS power. The drive
current of output pins is more than 5mA. It can drive the LED after connected with limited current resistor.
Ch365 uses address bus A7-A0 to decode. The offset address scope is from 0EFH-00H and the length is no
more than 240 bytes. In most cases, the peripheral circuit is connected without CS or forcible directly to
select the chip.
The C-language WDM and DLL program based Ch365 is following:
UCHAR mByte; // data cell)store the data red from the I/O port or written to the I/O port
mPCH365_IO_REG mIoBase; // the base address of I/O port)the actual data added the offset address
CH365GetIoBaseAddr( &mIoBase ); // get the base address of I/O port, this operation is option.
// if It is not the base address, the I/O operation only sets the offset address equal to base address 0.
// after calling the DLL of CH365 )DLL operates the I/O port by added automatically offset address added
base address
//memory operation is similar with it)if the memory operation only provide the offset address, DLL operates
the I/O port by added automatically offset address to base address
CH365 Chinese manual&2' CH365ReadIoByte( & mIoBase -> mCh365IoPort[0x00], &mByte );
// the above operation gets a byte from the I/O port 00H, the data is the first buffer input
CH365WriteIoByte( & mIoBase -> mCh365IoPort[0x01], 0x47 );
// the above operation gets a byte from the I/O port 01H, the data is the second locking output
CH365SetA15_A8( 0x24 ); // set A13 and A10 high , the others are low
In DOS or the PC without device OS surroundings, the assembler is the following
MOV AX, 0B109H ; read the PCI configuration space by double-word
MOV BX, CH365_PCI_BUS_DEV_ADDR ; the PCI address of CH365 card, bus, device and function
number
MOV DI, 0010H ; the offset address of memory register PC_BASE_ADDR0
INT 1AH ; read the base address of I/O port set by the PC initiation automatically
AND CX,0FFFEH ;get the base address of I/O port)the low bit is the indication bit
MOV BX, CX ; set the base address of the I/O port I
LEA DX,[BX].CH365_IO_PORT[0] ; the first group I/O buffer exports the address, the base address added
0
IN AL, DX ;read the input data of 74LS244 buffer
LEA DX,[BX].CH365_IO_PORT[1] ; the second group flip-latch exports the I/O address, the base address
is added by 1.
MOV AL,47H
OUT DX,AL ;write the data 47H to the flip-latch output register
LEA DX,[BX].CH365_MEM_ADDR_H ;A15-A8 address set the I/O port register of CH365
IN AL,DX ;read A15 to A8 to keep the status of the other pins
OR AL,20H ; only set A13 high power and keep the others
AND AL,0F7H ;only set the A11 and keep the others
OUT DX,AL ;write new A15 to A8 address to the address setting register
The transferring speed of I/O port and memory data is the same. The instruction of I/O space is less than
memory space in PC. The peripheral device maps control register and state register into the I/O space and
data block exchange buffer area to memory space.

9.6. Be connected with MCU
There are four methods to exchange the data in the bidirectional way between Ch365 and MCU or DSP.
First, one memory connects CH365 and MCU, then use the double-port SRAM to exchange the bidirectional
data in data block. Second, use the bidirectional data buffer interface chip CH421 as the 64 byte buffer
between CH365 and MCU to exchange the data in 64 byte data block. The third is using the 8255 to
exchange the data in one byte. The last is the low transferring speed in four bits or one bit data without
adding hardware cost. For example, the 4-bits data exchange interface cooperated the software, the I2C
The Datasheet of CH365 (
interface provided by CH365 itself and the SPI interface with software simulation.

9.6.1. The asynchronous data exchange with the handshake signal
If working at the wok mode 2, the I/O expansion chip 8255 provides the standard asynchronous data to
exchange with the handshake signal by byte. If the port A of 8255 is connected with CH365, MCU will
control the MCU. If it is connected with MCU, PC will control the 8255 through CH365. When the port A is
working at the work mode 2, 8255 provides input buffer area full or empty signal, output buffer area full or
empty signal, handshake signal and interrupt signal.
In the figure the port A of U21(82C55A) is linked with the MCU U22. The address bus A15 resets the
system. The PC program sets the port A in the work mode 2. The low springs the interrupts of MCU.
After PC writes data to MCU, the operation changes the 'IBF to low. U22 enters the interrupt program.
MCU reads the data from the interrupt program. The reading operation sends out -ACK and gets back 'OBF
high. PC writes data to MCU after sensing 'OBF once again.
After MCU writes data to PC, the operation changes the 'STB to high. If CH365 starts the interrupt
function, -STB exports low to make PC entering the interrupt program. If CH365 doesn!t start the interrupt
function, the PC checks the IBF status in inquest. The PC program inquires IBF status and reads the MCU
data. The read operation changes IBF to low. MCU inquires the IBF status and writes data to PC once again.
















9.6.2. The usage of bidirectional data buffer interface CH421
CH421 provides the fast connection between CH365 and MCU. The detail content is in the CH421 chip
manual.

9.7. Expansion of I/O port (the reference is the above figure got rid of U22)
CH365 is able to linked with most common I/O expansion circuit. In the figure U21 is used to I/O
expansion. The speed of former 8255 is above 300ns, while the latter is under 200ns. So U21 is chosen as
82C55A. 8255 is addressed between 00Hand 0EFH. The actual address is from 03H to 00H and the others is
byname address. 8255 expands the 8-bit data bus to three groups 8-bit data ports. For example, write the
control word 10010000b to the offset address 03H sets the port A as 8-bit input port, then the port B and C
are set to 8-bit output.
The C-language WDM and DLL program based CH365 is the following:
UCHAR mByte; // data cell)used to store the data red from the memory or written to memory
mPCH365_IO_REG mIoBase = NULL; // the base address of I/O port, DLL adds base address automatically
when it is 0
CH365ReadIoByte( & mIoBase -> mCh365IoCtrl, &mByte ); // read the chip control register
CH365WriteIoByte( & mIoBase -> mCh365IoCtrl, mByte | mBitAddr15Out ); // A15=1
The Datasheet of CH365 *
CH365WriteIoByte( & mIoBase -> mCh365IoCtrl, mByte & ~ mBitAddr15Out); // A15=0
// the above three operations control A15 to export the high pulse and reset U21.
CH365WriteIoByte( & mIoBase -> mCh365IoPort[0x03], 0x90 ); // 10010000B
// set the control word of 8255 ,PA is input and PB/PC is output
CH365ReadIoByte( & mIoBase -> mCh365IoPort[0x00], &mByte );
// read data from PA of 8255
CH365WriteIoByte( & mIoBase -> mCh365IoPort[0x01], 0x8E );
// export 8EH from PB of 8255

9.8. Other assistant functions
9.8.1. Hardware cycle count register
CH365 provides a one-byte hardware count cell. Its count input frequency is the 1 /128. For PCI Bus is
the standard 33.3MHz main frequency, the hardware cycle count register adds 1 every 3.84us. The time from
00H to FFH then from FFH to 00H is totally 983.04us. Through comparing the different value of the two
times, working out the actual delay replaces the PC software instruction cycle whose error is bigger.

9.8.2. 8-bit bus input port
CH365 provides a 8-bit bus status input port in the PCI device configuration space. When read the port,
the real/write enable control bus only reads the D[7:0]static state and doesn!t export the output signal. If the
data bus D6 is linked with the pull-down resistor, bit 6 is 0. Otherwise, bit 6 is 1. The function is to identify
the card by application program or read the external configuration information by Expansion ROM boot
program. For example, it represents one configuration mode that D6 and D7 are pulled-down and another
mode that only D6 is pulled-down. The application program and boot program can work it out according the
pull-down.

9.9. Hardware interrupts
CH365 supports the low valid interrupt. If the data line D3 is pull-down, the work mode enables the
interrupt function. SYS_EX pin is used as the local interrupt function INT_REQ.
If INT_REQ pin sense the low, CH365 sets the interrupt active state bit to 1. It requires interrupt of PCI
bus through PCI_INIT. At that time CH365 keeps the interrupt active status regardless of the INT_REQ
status until the CH365 interrupt program sets the interrupt active state bit to 0. But CH365 enters the
interrupt active state once again if INT_REQ still sense the low power after clearing the interrupt active state
bit. If PC software program set the interrupt active state bit to 1,CH365 can enter the interrupt status too.
CH365 requires the interrupt of PCI bus. So the software interrupt possesses of the same features of
hardware interrupt by the low of INT_REQ to test the interrupt function.
The detail note is referred in the CH365EVT data <<CH365 interrupt function specification>>. The
following is the standard interrupt process:
-1 The peripheral circuit exports the low valid power to INT_REQ. It leads to the interrupt active
state bit changed to 1. If the peripheral circuit provides the low pulse, the pulse width must be longer than
TINT.
-2 CH365 requires the interrupt of PC through INTA of PCI bus.
-3 PC enters the CH365 Interrupt program.
-4 If the interrupt program provided by peripheral circuit is not the pulse signal, the interrupt program
informs the peripheral circuit to clear the interrupt inquest. INT_REQ resumes to high.
-5 Interrupt program clears the interrupt active state bit in the chip control register of CH365.
PC_INTA of CH365 is in the high impedance status and withdraws the interrupt inquest.
-6 Interrupt program does the necessary operation. This step can be executed first after entering the
interrupt
-7 The interrupt management is over and PC exits the interrupt program.

The Datasheet of CH365 +
9.10. Hardware local addressing and ISA update (fit to update the ISA I/O card )
In most cases, the base address of PCI device is attributed by PC initialization. It ensures that the
special I/O address and multi-device I/O address are not conflict. This is different from the ISA I/O address,
which is flexile. PCI specification hasn!t provided a method defining the PCI card I/O address by the product
manufacture .It is not convenient in the special application. First, the I/O address attributed automatically by
the PCI card is different. Secondly, the card can!t work before initializing the computer and the I/O address
configuration. In addition, the I/O address is always attributed above 1000H and can!t be located between
3FFH and 000H. Finally, when ISA card is updated to PCI bus you should modify application program so as
to get the I/O port address before I/O operation.
CH365 provides a method called local hardware addressing that is of use to choose the PCI device I/O
address. The theory is that some PCI device I/O decode is realized by the 2-level peripheral circuit that is
simple and similar with the ISA I/O address decode. CH365 provides the PC I/O operation address
synchronization. When the peripheral circuit matches the decode address, CH365 requires the local hardware
addressing then does the PCI I/O operate in this address.
The debug card (post card) based on PCI bus is an example about the method. PC exports the I/O port
post code incessantly to the I/O address 0080H. For PC gets the I/O address after POST, the normal PC card
can!t get the post code. In addition, the normal PC can!t locate the I/O address to 0080H after attributing the
I/O address.
The following figure is a part of CH365 debug card. Resistor R7 is utilized to set the work mode. The
data line D4 is pull-down and the data bus value is 11101111b. CH365 sets the time-multiplexed pin
MEM_WR to local hardware addressing request signal IOP_HIT. The encoder U11 (use 74F138) can
compare it with the address A9-A1 when the code is same with the preset address 0080H and 0081H. U11
exports the valid IO_RD to read the data or the valid IOP_WR to write data. As long Debug Card receives
the I/O data, U12 locks the post code and display the data with LED by the character decode circuit U13 and
U14.













CH365 has limited the local hardware addressing scope between 03FFH and 0000H according the ISA
card I/O port address scope. When PC is working, CH365 exports the operation address synchronously. The
peripheral 2-level decode circuit decides whether the A9 to A0 address match with the preset circuit or not.
CH365 demands the delay of 2-level decode no past 20us.In another word, the time that the local
hardware addressing request after the external 2-level decode is no more 20us. The above figure shows this
function by 74AL688.In fact, the external decode circuit usually chooses the PLD 16V8(16ms) or encoder
74F138.
The left figure uses the 2-level decode circuit by TTL. Because of its low speed the decode time can
exceed 20us. The usage is only to explain its function and logic. We advise the user to use the right circuit
which uses the simple PLD as the 2-level decode circuit.
U18 decodes the A9 to A4 of CH365 and provides eight 16-bit I/O address area. If the primary ISA card
uses the 270H to 27Fh, then U18 connects Y7 pin and IOP_HIT of CH365 directly. When PC operates the
The Datasheet of CH365 ,
I/O port between 270 and 27FH, IOP_HIT is set to low by U18.CH365 exports the read/write signal by
IOP_RD and IOP_WR. The external circuit changes data with PC according to control signal. Of course, the
external circuit can decode A3-a0 alone.
We approve to use PLD U20 (GAL 16V8) for the 2-level decode circuit in the actual application. This
circuit is neat and convenient. In most cases, 16V8 can use the surplus source (output 1,input 11, output
15-19) to do other things after completing the 2-level decode. For example, the low bits combined IOP_RD
and IOP_WR can decode the I/O port and produce the CS signal CS1 to Cs 5.
In addition, CH365 can/t always respond the I/O operation in the hardware located address scope
between 240h and 2FFH., but also I/O address attributed by PC automatically in the memory .For example,
the i/o address the PC can attributed the I/O address scope from C000h to C0FFH .The operation address
240H is equal to the PC operation address C000H.Reading or writing the 247H is equal to the c007h.
Based on the hardware located address function, the produce manufacture can update the ISA card to
PCI bus, and use the primary I/O port address without modify the application.








9.11. Set the PCI device ID
PCI card utilizes ordinarily the CH365 default ID .If setting their one ID or special device ID is
necessary, the manufacture shall pull the data bus D1 down to set the work mode for CH365 after resetting
the system. Then CH365 is working in the external ID mode and provides peripheral circuit the device ID.
After setting the work mode CH365 utilizes the external ID.CH365 configures all the location in the
configuration space register whose attribute is s. CH365 maps them directly to the located memory starting
from 0040H. In the other word the configuration space from 3Fh to 00H is mapped to the memory
space .7FH to 40H. For example, the configuration space address 00his the located memory address 0040H.
Similarly, the 2CH is 6CH. IF the located memory address from 0043H to 0040H is 12345678h,then the
Vendor ID is 1234H and the device ID is 1234H.By the same taken, the located memory address from
006FH to 006CHshall set the PCI card subsystem ID. The expansion ROM and other read-only memory
comprise the memory providing the device ID. For the PCI card supports the expansion ROM, you can
configure the PCI device ID in the ROM address FROM 007FH-0000H without adding any peripheral
components. PCI card itself doesn!t need the Expansion ROM. If setting the PCI ID is necessary, there are
two methods. One is connecting the extra ROM providing the PCI device ID and the other is utilizing the
simple PLD (16V8 and so on) instead of Expansion ROM to provide the new PCI ID for CH365.
In the following figure the tri-state output is forbidden while the MEM_RD of U16 is high power.
Otherwise the data A7-A0 is output. For example, when the MEM-RD is low power the value 48H of A7-A0
outputs the PCI Revision ID and the value 49H outputs the PCI device Class Code.










The Datasheet of CH365 !/
9.12. Memory read /write through I/O port
Generally, CH365 local memory is mapped to the PC memory space. Reading and writing the local
memory is processed in the PC memory space. For supporting the large size expansion ROM or memory and
convenience of addressing operation under the DOS surrounding. CH365 provides the transition from
memory space to I/O space. This method is fit to the large size expansion ROM and memory whose data
access is in order. It supports directly 64K expansion ROM or memory. The steps of reading and writing
memory through I/O port are showed in the table.

Register
Register
operation
Read data program
&ASM'
Read data program &C/C++'
A15#A0
Address set
register
Read-in start
address
mov dx,PORT_ADDR
mov ax,START_ADDR
out dx,ax
outport (PORT_ADDR,
START_ADDR);
Memory
data access
register
Read/write data in
order
Address added 1
automatically
mov dx,PORT_DATA
mov di,BUFFER_ADDR
mov cx,LENGTH
rep insb
int i;
char buf[LENGTH];
for (i=0; i<LENGTH; ++i)
buf[i]=inportb(PORT_DATA);
The constant and parameter used in the program.
PORT_ADDR represents the I/O address of the A15-A0 address register.
PORT_DATA represents the I/O address of the data access register.
START_ADDR represents the start address of access data in the expansion ROM and memory.
LENTH represents the length of the access data or the number of the byte
BUFFER_START represents the buffer start address of storage data; buf represents the date buffer.