1

Intel 8086
MICROPROCESSOR

Intel 8086
MICROPROCESSOR

2
Featres
Featres
It is a 16-bit p.
8086 has a 20 bit address bus can access up to 2
20

memory locations (1 MB).
It can support up to 6! I"# ports.
It pro$ides 1% 16 -bit re&isters.
'ord si(e is 16 bits and double )ord si(e is bytes.
It has multiple*ed address and data bus +,0- +,1-
and +16 . +1/.
It re0uires sin&le phase cloc1 )ith 223 duty cycle to
pro$ide internal timin&.
3
8086 is desi&ned to operate in t)o modes% Minimum and
Ma*imum.

It can pre4etches up to 6 instruction bytes 4rom memory and

0ueues them in order to speed up instruction e*ecution.

It re0uires 5-6 po)er supply.

+ 0 pin dual in line pac1a&e.

+ddress ran&es 4rom 000007 to 888887

Memory is byte addressable - 9$ery byte has a separate

address.
4
Intel 8086 Internal Arc!itectre
Intel 8086 Internal Arc!itectre
5
Internal arc!itectre of 8086
Internal arc!itectre of 8086

8086 !as t"o #loc$s BI% an& E%.

T!e BI% !an&les all transactions of &ata an&

a&&resses on t!e #ses for E%.

T!e BI% 'erfor(s all #s o'erations sc! as

instrction fetc!in), rea&in) an& "ritin)
o'eran&s for (e(ory an& calclatin) t!e
a&&resses of t!e (e(ory o'eran&s. T!e
instrction #ytes are transferre& to t!e
instrction *ee.

E% e+ectes instrctions fro( t!e instrction

syste( #yte *ee.
6
Bot! nits o'erate async!ronosly to )i,e
t!e 8086 an o,erla''in) instrction fetc!
an& e+ection (ec!anis( "!ic! is calle&
as Pi'elinin). T!is reslts in efficient se of
t!e syste( #s an& syste( 'erfor(ance.
BI% contains Instrction *ee, Se)(ent
re)isters, Instrction 'ointer, A&&ress
a&&er.
E% contains Control circitry, Instrction
&eco&er, A-%, Pointer an& In&e+ re)ister,
Fla) re)ister.
7
E.EC%TION %NIT

/eco&es instrctions fetc!e& #y t!e BI%

0enerate control si)nals,

E+ectes instrctions.
T!e (ain 'arts are1

Control Circitry

Instrction &eco&er

A-%
8
AH AL
BH BL
CH CL
DH DL
SP
BP
SI
DI
8 bits
8 bits
16 bits
Acc(lator
Base
Cont
/ata
Stac$ Pointer
Base Pointer
Sorce In&e+
/estination In&e+
A.
B.
C.
/.
Pointer
In&e+
8 bits
8 bits
16 bits
Acc(lator
Base
Cont
/ata
Stac$ Pointer
Base Pointer
Sorce In&e+
/estination In&e+
E.EC%TION %NIT 2 0eneral Pr'ose Re)isters
E.EC%TION %NIT 2 0eneral Pr'ose Re)isters
9
E.EC%TION %NIT 2 0eneral Pr'ose Re)isters
E.EC%TION %NIT 2 0eneral Pr'ose Re)isters
Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal
arithmetic
AH Byte multiply, byte divide
BX Store address inormation
!X Strin" operation, loops
!L #ariable shit and rotate
$X Word multil!" #ord di$id%" i&dir%'t I()
*+s%d to ,old I() -ddr%ss duri&. I() i&stru'tio&s/ I0 t,% r%sult is mor% t,-&
161bits" t,% lo#%r ord%r 161bits -r% stor%d i& -''umul-tor -&d ,i.,%r ord%r
161bits -r% stor%d i& D2 r%.ist%r3
14
Pointer An& In&e+ Re)isters
Pointer An& In&e+ Re)isters

us%d to 5%% o00s%t -ddr%ss%s/

+s%d i& $-rious 0orms o0 m%mor! -ddr%ssi&./

I& t,% '-s% o0 SP -&d BP t,% d%0-ult r%0%r%&'% to 0orm - ,!si'-l

-ddr%ss is t,% St-'5 S%.m%&t *SS1#ill b% dis'uss%d u&d%r t,% BI+3

6,% i&d%7 r%.ist%rs *SI 8 DI3 -&d t,% B2 .%&%r-ll! d%0-ult to t,%
D-t- s%.m%&t r%.ist%r *DS3/
SP9 St-'5 oi&t%r
: +s%d #it, SS to -''%ss t,% st-'5 s%.m%&t
BP9 B-s% Poi&t%r
: Prim-ril! us%d to -''%ss d-t- o& t,% st-'5
: C-& b% us%d to -''%ss d-t- i& ot,%r s%.m%&ts
11

SI9 Sour'% I&d%7 r%.ist%r

: is r%;uir%d 0or som% stri&. o%r-tio&s
: W,%& stri&. o%r-tio&s -r% %r0orm%d" t,% SI r%.ist%r
oi&ts to m%mor! lo'-tio&s i& t,% d-t- s%.m%&t #,i', is
-ddr%ss%d b! t,% DS r%.ist%r/ 6,us" SI is -sso'i-t%d #it,
t,% DS i& stri&. o%r-tio&s/

DI9 D%sti&-tio& I&d%7 r%.ist%r

: is -lso r%;uir%d 0or som% stri&. o%r-tio&s/
: W,%& stri&. o%r-tio&s -r% %r0orm%d" t,% DI r%.ist%r
oi&ts to m%mor! lo'-tio&s i& t,% d-t- s%.m%&t #,i', is
-ddr%ss%d b! t,% <S r%.ist%r/ 6,us" DI is -sso'i-t%d #it,
t,% <S i& stri&. o%r-tio&s/

6,% SI -&d t,% DI r%.ist%rs m-! -lso b% us%d to -''%ss d-t-

stor%d i& -rr-!s
12
E.EC%TION %NIT 2 Fla) Re)ister
E.EC%TION %NIT 2 Fla) Re)ister

A 0l-. is - 0li 0lo #,i', i&di'-t%s som% 'o&ditio&s rodu'%d b!

t,% %7%'utio& o0 -& i&stru'tio& or 'o&trols '%rt-i& o%r-tio&s o0
t,% <+ /

I& 8486 6,% <+ 'o&t-i&s

- 16 bit 0l-. r%.ist%r
9 o0 t,% 16 -r% -'ti$% 0l-.s -&d r%m-i&i&. 7 -r% u&d%0i&%d/
6 0l-.s i&di'-t%s som% 'o&ditio&s1 st-tus 0l-.s
3 0l-.s :'o&trol =l-.s
U U U U OF DF IF TF SF ZF U AF U PF U CF
Carry
O,er flo" /irection
Interr't
Tra'
Si)n
3ero
A+iliary
Parity
% 4 %nse&
13
E.EC%TION %NIT 2 Fla) Re)ister
E.EC%TION %NIT 2 Fla) Re)ister
Fla) Pr'ose
C-rr! *C=3 Holds t,% '-rr! -0t%r -dditio& or t,% borro# -0t%r subtr-'tio&/
Also i&di'-t%s som% %rror 'o&ditio&s" -s di't-t%d b! som%
ro.r-ms -&d ro'%dur%s /
P-rit! *P=3 P=>4?odd -rit!" P=>1?%$%& -rit!/
Au7ili-r! *A=3 Holds t,% '-rr! *,-l0 : '-rr!3 -0t%r -dditio& or borro# -0t%r
subtr-'tio& b%t#%%& bit ositio&s 3 -&d 4 o0 t,% r%sult
*0or %7-ml%" i& BCD -dditio& or subtr-'tio&/3
@%ro *@=3 S,o#s t,% r%sult o0 t,% -rit,m%ti' or lo.i' o%r-tio&/
@>1? r%sult is A%ro/ @>4? 6,% r%sult is 4
Si.& *S=3 Holds t,% si.& o0 t,% r%sult -0t%r -& -rit,m%ti'(lo.i' i&stru'tio&
%7%'utio&/ S>1? &%.-ti$%" S>4
14
Fla) Pr'ose
6r- *6=3
A 'o&trol 0l-./
<&-bl%s t,% tr-i&. t,rou., -& o&1',i d%bu..i&.
0%-tur%/
I&t%rrut *I=3
A 'o&trol 0l-./
Co&trols t,% o%r-tio& o0 t,% IB6C *i&t%rrut r%;u%st3
I>4? IB6C i& dis-bl%d/ I>1? IB6C i& %&-bl%d/
Dir%'tio& *D=3
A 'o&trol 0l-./
It s%l%'ts %it,%r t,% i&'r%m%&t or d%'r%m%&t mod% 0or DI
-&d (or SI r%.ist%rs duri&. t,% stri&. i&stru'tio&s/
)$%r0lo# *)=3
)$%r0lo# o''urs #,%& si.&%d &umb%rs -r% -dd%d or
subtr-'t%d/ A& o$%r0lo# i&di'-t%s t,% r%sult ,-s %7'%%d%d
t,% '--'it! o0 t,% D-',i&%
15
E+ection nit 2 Fla) Re)ister
E+ection nit 2 Fla) Re)ister

Si7 o0 t,% 0l-.s -r% st-tus i&di'-tors r%0l%'ti&.

ro%rti%s o0 t,% l-st -rit,m%ti' or lo.i'-l i&stru'tio&/

=or %7-ml%" i0 r%.ist%r AL > 7=, -&d t,% i&stru'tio&

ADD AL"1 is %7%'ut%d t,%& t,% 0ollo#i&. ,-%&
A- 5 80!
CF 5 0? t,%r% is &o '-rr! out o0 bit 7
PF 5 0? 84, ,-s -& odd &umb%r o0 o&%s
AF 5 6? t,%r% is - '-rr! out o0 bit 3 i&to bit 4
3F 5 0? t,% r%sult is &ot A%ro
SF 5 6? bit s%$%& is o&%
OF 5 6? t,% si.& bit ,-s ',-&.%d
16
B%S INTERFACE %NIT 7BI%8
B%S INTERFACE %NIT 7BI%8
Co&t-i&s

64#yte Instrction 9ee 798

T!e Se)(ent Re)isters 7CS, /S, ES, SS8.

T!e Instrction Pointer 7IP8.

T!e A&&ress S((in) #loc$ 7:8

17
T;E 9%E%E 798
T;E 9%E%E 798

6,% BI+ us%s - m%',-&ism 5&o#& -s -&

instrction strea( *ee to iml%m%&t - pipeline
architecture.

6,is ;u%u% %rmits r%10%t', o0 u to 6 #ytes o0

i&stru'tio& 'od%/ W,%&%$%r t,% ;u%u% o0 t,% BI+ is
&ot 0ull" it ,-s room 0or -t l%-st t#o mor% b!t%s -&d
-t t,% s-m% tim% t,% <+ is &ot r%;u%sti&. it to r%-d
or #rit% o%r-&ds 0rom m%mor!" t,% BI+ is 0r%% to
loo5 -,%-d i& t,% ro.r-m b! r%10%t',i&. t,% &%7t
s%;u%&ti-l i&stru'tio&/
18

6,%s% r%10%t',i&. i&stru'tio&s -r% ,%ld i& its FIFO

*ee/ Wit, its 66 bit d-t- bus" t,% BI+ 0%t',%s t#o
i&stru'tio& b!t%s i& - si&.l% m%mor! '!'l%/

A0t%r - b!t% is lo-d%d -t t,% i&ut %&d o0 t,% ;u%u%"

it -utom-ti'-ll! s,i0ts u t,rou., t,% FIFO to t,%
%mt! lo'-tio& &%-r%st t,% outut/

6,% E% accesses t!e *ee fro( t!e ot't en&/

It r%-ds o&% i&stru'tio& b!t% -0t%r t,% ot,%r 0rom t,%
outut o0 t,% ;u%u%/

6,% i&t%r$-ls o0 &o bus -'ti$it!" #,i', m-! o''ur

b%t#%%& bus '!'l%s -r% 5&o#& -s Idle state.
24
Se)(ente& Me(ory
Se)(ente& Me(ory
Cod% s%.m%&t *64EB3
D-t- s%.m%&t *64EB3
<7tr- s%.m%&t *64EB3
St-'5 s%.m%&t *64EB3
6

M
B

6,% m%mor! i& -& 8486(88

b-s%d s!st%m is or.-&iA%d -s
s%.m%&t%d m%mor!/

6,% CP+ 8486 is -bl% to

-ddr%ss 1Db!t% o0 m%mor!/

6,% Coml%t% ,!si'-ll!

-$-il-bl% m%mor! m-! b%
di$id%d i&to - &umb%r o0 lo.i'-l
s%.m%&ts/
00000
FFFFF
P!ysical Me(ory
21
6,% siA% o0 %-', s%.m%&t is 64 EB
A s%.m%&t is -& -r%- t,-t b%.i&s -t -&! lo'-tio& #,i', is
di$isibl% b! 16/
A s%.m%&t m-! b% lo'-t%d -&! #,%r% i& t,% m%mor!
<-', o0 t,%s% s%.m%&ts '-& b% us%d 0or - s%'i0i' 0u&'tio&/
: Cod% s%.m%&t is us%d 0or stori&. t,% i&stru'tio&s/
: 6,% st-'5 s%.m%&t is us%d -s - st-'5 -&d it is us%d to stor% t,% r%tur&
-ddr%ss%s/
: 6,% d-t- -&d %7tr- s%.m%&ts -r% us%d 0or stori&. d-t- b!t%/
> In t!e asse(#ly lan)a)e 'ro)ra((in), (ore t!an
one &ata? co&e? stac$ se)(ents can #e &efine&. Bt
only one se)(ent of eac! ty'e can #e accesse& at any
ti(e.
22

6,% 4 s%.m%&ts -r% Cod%" D-t-" <7tr- -&d St-'5 s%.m%&ts/

A S%.m%&t is - 645b!t% blo'5 o0 m%mor!/

6,% 16 bit 'o&t%&ts o0 t,% s%.m%&t r%.ist%rs i& t,% BI+

-'tu-ll! oi&t to t,% st-rti&. lo'-tio& o0 - -rti'ul-r s%.m%&t/

S%.m%&ts m-! b% o$%rl-%d or &o&1o$%rl-%d

A&,anta)es of Se)(ente& (e(ory Sc!e(e

Allo#s t,% m%mor! '--'it! to b% 1Db -lt,ou., t,% -'tu-l -ddr%ss%s to

b% ,-&dl%d -r% o0 16 bit siA%/

Allo#s t,% l-'i&. o0 'od%" d-t- -&d st-'5 ortio&s o0 t,% s-m% ro.r-m
i& di00%r%&t -rts *s%.m%&ts3 o0 t,% m(!" 0or d-t- -&d 'od% rot%'tio&/
P%rmits - ro.r-m -&d(or its d-t- to b% ut i&to di00%r%&t -r%-s o0
m%mor! %-', tim% ro.r-m is %7%'ut%d" i/%/ ro$isio& 0or r%lo'-tio& m-!
b% do&% /
6,% s%.m%&t r%.ist%rs -r% us%d to -llo# t,% i&stru'tio&" d-t- or st-'5
ortio& o0 - ro.r-m to b% mor% t,-& 64Eb!t%s lo&./ 6,% -bo$% '-& b%
-',i%$%d b! usi&. mor% t,-& o&% 'od%" d-t- or st-'5 s%.m%&ts/
23
Se)(ent re)isters
Se)(ent re)isters

I& 8486(88 t,% ro'%ssors ,-$% 4 s%.m%&ts

r%.ist%rs

Cod% S%.m%&t r%.ist%r *CS3" D-t- S%.m%&t

r%.ist%r *DS3" <7tr- S%.m%&t r%.ist%r *<S3 -&d
St-'5 S%.m%&t *SS3 r%.ist%r/

All -r% 16 bit r%.ist%rs/

<-', o0 t,% S%.m%&t r%.ist%rs stor% t,% u%r 16

bit -ddr%ss o0 t,% st-rti&. -ddr%ss o0 t,%
'orr%so&di&. s%.m%&ts/
24
25
@ABA
AAEB
BAEB
6CBE
CSR
/SR
ESR
SSR
Se)(ent Re)isters
BI%
CO/E 76A$8
/ATA 76AD8
E.TRA 76AD8
STACD 76AD8
6

M
B
00000
@ABA0
AABCF
AAEB0
BAEAF
BAEB0
6AEAF
6CBE0
ECB/
F
Eac! se)(ent re)ister store t!e
''er 66 #it of t!e startin)
a&&ress of t!e se)(ents
MEMORF
26
Instrction 'ointer G s((in) #loc$
Instrction 'ointer G s((in) #loc$

T!e instrction 'ointer re)ister contains a 664#it offset

a&&ress of instrction t!at is to #e e+ecte& ne+t.

T!e IP al"ays references t!e Co&e se)(ent re)ister

7CS8.

T!e ,ale containe& in t!e instrction 'ointer is calle&

as an offset #ecase t!is ,ale (st #e a&&e& to t!e
#ase a&&ress of t!e co&e se)(ent, "!ic! is a,aila#le in
t!e CS re)ister to fin& t!e <04#it '!ysical a&&ress.

T!e ,ale of t!e instrction 'ointer is incre(ente& after

e+ectin) e,ery instrction.

To for( a <0#it a&&ress of t!e ne+t instrction, t!e 66 #it

a&&ress of t!e IP is a&&e& 7#y t!e a&&ress s((in)
#loc$8 to t!e a&&ress containe& in t!e CS , "!ic! !as
#een s!ifte& for #its to t!e left.
27
28

T!e follo"in) e+a('les s!o"s t!e CS1IP sc!e(e of

a&&ress for(ation1
Insertin) a !e+a&eci(al 0; 70000B8
"it! t!e CSR or s!iftin) t!e CSR
for #inary &i)its left
@ A B A 0 7 C S 8 H
8 A B A 7 I P 8
@ / 6 B A 7ne+t a&&ress8
@ABA
8ABA
CS IP
@ABA0
@/6AB
AABCF
Co&e se)(ent
8ABA 7offset8
29

E+a('le For A&&ress Calclation 7se)(ent1 offset8

I0 t,% d-t- s%.m%&t st-rts -t lo'-tio& 1444, -&d - d-t-

r%0%r%&'% 'o&t-i&s t,% -ddr%ss 29, #,%r% is t,% -'tu-l
d-t-F
Re*ire& A&&ress
Offset
Se)(ent A&&ress
0000 0000 0060 6006
0000
0006 0000 0000 0060 6006
0006 0000 0000 0000
34
Se)(ent an& A&&ress re)ister
co(#ination
Se)(ent an& A&&ress re)ister
co(#ination
CS1IP
SS1SP SS1BP
/S1B. /S1SI
/S1/I 7for ot!er t!an strin) o'erations8
ES1/I 7for strin) o'erations8
31
S((ary of Re)isters G Pi'eline of 8086 IP
S((ary of Re)isters G Pi'eline of 8086 IP
A; A-
B; B-
C; C-
/; /-
SP
BP
SI
/I
F-A0S
/
E
C
O
/
E
R
A-%
A.
B.
C.
/.
E% E%
Ti(in)
control
SP
BP
/efalt Assi)n(ent
BI% BI%
IP
CS /S ES SS
PIPE-INE
7or8
9%E%E
C
O
/
E
O
%
T
C
O
/
E
I
N
IP B.
/I
SI
/I
=%t', 8
stor% 'od%
b!t%s i&
PIP<LIB<
M. Krishna Kumar MM/M1/LU3/V1/2004 66
Internal Registers of 8086 (cont..)
The 8086 has four groups of the user accessible internal
registers. They are the instruction pointer, four data
registers, four pointer and index register, four segment
registers.
The 8086 has a total of fourteen 16-bit registers including a
16 bit register called the status register, with 9 of bits
implemented for status and control flags.
M. Krishna Kumar MM/M1/LU3/V1/2004 67
Most of the registers contain data/instruction offsets within
64 KB memory segment. There are four different 64 KB
segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4
segments are located the processor uses four segment
registers:
Code segment (CS) is a 16-bit register containing address
of 64 KB segment with processor instructions. The
processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register
cannot be changed directly. The CS register is
automatically updated during far jump, far call and far
return instructions.
Internal Registers of 8086 (cont..)
M. Krishna Kumar MM/M1/LU3/V1/2004 68
Stack segment (SS) is a 16-bit register containing address
of 64KB segment with program stack. By default, the
processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in
the stack segment. SS register can be changed directly
using POP instruction.
Data segment (DS) is a 16-bit register containing address
of 64KB segment with program data. By default, the
processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is
located in the data segment. DS register can be changed
directly using POP and LDS instructions.
Internal Registers of 8086 (cont..)
M. Krishna Kumar MM/M1/LU3/V1/2004 69
Extra segment (ES) is a 16-bit register containing address
of 64KB segment, usually with program data. By default,
the processor assumes that the DI register references the
ES segment in string manipulation instructions. ES register
can be changed directly using POP and LES instructions.
It is possible to change default segments used by general
and index registers by prefixing instructions with a CS, SS,
DS or ES prefix.
All general registers of the 8086 microprocessor can be
used for arithmetic and logic operations. The general
registers are:
Internal Registers of 8086 (cont..)
M. Krishna Kumar MM/M1/LU3/V1/2004 70
Accumulator register consists of two 8-bit registers AL
and AH, which can be combined together and used as a 16-
bit register AX. AL in this case contains the low-order byte
of the word, and AH contains the high-order byte.
Accumulator can be used for I/O operations and string
manipulation.
Base register consists of two 8-bit registers BL and BH,
which can be combined together and used as a 16-bit
register BX. BL in this case contains the low-order byte of
the word, and BH contains the high-order byte. BX register
usually contains a data pointer used for based, based
indexed or register indirect addressing.
Internal Registers of 8086 (cont..)
M. Krishna Kumar MM/M1/LU3/V1/2004 71
Count register consists of two 8-bit registers CL and CH,
which can be combined together and used as a 16-bit
register CX. When combined, CL register contains the
low-order byte of the word, and CH contains the high-
order byte. Count register can be used in Loop, shift/rotate
instructions and as a counter in string manipulation,.
Data register consists of two 8-bit registers DL and DH,
which can be combined together and used as a 16-bit
register DX. When combined, DL register contains the
low-order byte of the word, and DH contains the high-
order byte. Data register can be used as a port number in
I/O operations. In integer 32-bit multiply and divide
instruction the DX register contains high-order word of the
initial or resulting number.
Internal Registers of 8086 (cont..)
M. Krishna Kumar MM/M1/LU3/V1/2004 72
The following registers are both general and index
registers:
Stack Pointer (SP) is a 16-bit register pointing to program
stack.
Base Pointer (BP) is a 16-bit register pointing to data in
stack segment. BP register is usually used for based, based
indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for
indexed, based indexed and register indirect addressing, as
well as a source data address in string manipulation
instructions.
Internal Registers of 8086 (cont..)
M. Krishna Kumar MM/M1/LU3/V1/2004 73
Destination Index (DI) is a 16-bit register. DI is used for
indexed, based indexed and register indirect addressing, as
well as a destination data address in string manipulation
instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flags is a 16-bit register containing 9 one bit flags.
Overflow Flag (OF) - set if the result is too large positive
number, or is too small negative number to fit into
destination operand.
Internal Registers of 8086 (cont..)
M. Krishna Kumar MM/M1/LU3/V1/2004 74
Direction Flag (DF) - if set then string manipulation
instructions will auto-decrement index registers. If cleared
then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables
maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will
occur after the next instruction.
Sign Flag (SF) - set if the most significant bit of the result
is set.
Zero Flag (ZF) - set if the result is zero.
Internal Registers of 8086 (cont..)
M. Krishna Kumar MM/M1/LU3/V1/2004 75
Auxiliary carry Flag (AF) - set if there was a carry from
or borrow to bits 0-3 in the AL register.
Parity Flag (PF) - set if parity (the number of "1" bits) in
the low-order byte of the result is even.
Carry Flag (CF) - set if there was a carry from or borrow
to the most significant bit during last result calculation.
Internal Registers of 8086