World Applied Sciences Journal 23 (11): 1471-1480, 2013

ISSN 1818-4952
IDOSI Publications, 2013
DOI: 10.5829/idosi.wasj.2013.23.11.13163
Corresponding Author: Muhammad Saleem, Department of Electrical Engineering,
Sarhad University of Science and Information Technology, KPK, Peshawar, Pakistan.
1471
Analysis and Comparison of DC-DC Boost Converters with
High Voltage Conversion Ratio
Muhammad Saleem and Iltaf Hussain
1 2
Department of Electrical Engineering,
1
Sarhad University of Science and Information Technology, Peshawar, KPK, Pakistan
Department of Basic Sciences and Islamiat, University of Engineering and Technology
2
Peshawar (Mardan Campus), Khyber Pakhtunkhwa, Pakistan
Submitted: Jun 8, 2013; Accepted: Jul 17, 2013; Published: Jul 25, 2013
Abstract: In this paper different types of converters based on different types of switching cells have been
studied and designed. The analysis of each converter has been carried out. The main objective of analysis is
to find out the advantages and disadvantages of each converter and to find the converter suitable for the given
application. The analysis of these converter result in a new converter. The proposed converter posses high
voltage conversion ratio and reduced switch voltage stress. The principles of operation and the theoretical
analysis of each converter have bee presented in this paper. The different converters have been simulated and
their results are compared. In order to verify the theoretical results the proposed converter is simulated for
35 W prototype operating at 100 KHz.
Key words: DC-DC converter Duty ratio Voltage stress Switching cell
INTRODUCTION constant frequency control, this topology provides
Several applications require high step-up, non- times that of a conventional non-isolated boost converter.
isolated DC-to-DC converters. Some applications are However, the use of two switches and auxiliary
renewable energy systems, fuel cells and uninterruptible transformer results in increase in cost, size and circuit
power supply (UPS) systems [1]. The duty ratio for complexity.
conventional step up converter is high for high output Another converter with high output voltage has been
voltage. In general converters with high voltage proposed which uses a clamp mode coupled inductor
conversion ratios have some constraints namely high with an active switch [5]. The converter achieves high
switch voltage stress and efficiency. So the current boost efficiency due to the leakage energy recovered by the
converters with high voltage conversion ratios require passive clamp circuit. High input ripple current and high
research in term of efficiency and switch voltage stress. magnitude clamp capacitors current are the main
A new family of boost converters based on a disadvantages of this converter.
four terminal switching cell has been presented in [2]. A switch-capacitor circuit has been combined with
The converters provide high voltage conversion ratio the conventional boost converter to get high step-up
with low switch voltage stress. conversion ratio [6]. The switch capacitor circuit is made
A quadratic boost converter can provide high of two diodes, two capacitors and one controlled switch.
output voltage with a small duty ratio. However, high This converter has many advantages as compared to the
voltage switch stress and low efficiency are the main quadratic boost converter, namely low switch voltage
disadvantages of this converter [3]. stress and better efficiency.
A boost converter with a voltage doublers has been Another idea of the switch-capacitor circuit has been
proposed in [4]. It provides high voltage with small duty applied to conventional Cuk, zeta and single-ended
ratio. It operates as interleaved boost converter. Using primary inductance converter (SEPIC) converters [7].
voltage regulation. The voltage conversion ratio is four
1
L1 1 g Lo
Lo
V , 2
2 , /
LO L
o c
LO
o c co co Lo
di di
v L v L v v
dt dt
di dv
v L v v i C i v R
dt dt
= = = =
= = = =
1
L1 1 g Lo
1
=V - , ,
( )
, /
2
LO L
c o c
c L Lo
c co co Lo
di di
v L v v L v v
dt dt
dv i i dv
i C i C i v R
dt dt
= = =

= = = =
World Appl. Sci. J., 23 (11): 1471-1480, 2013
1472
Fig. 1: Type1 converter
High efficiency and low voltage stress are the main
advantages of these converters. The conversion ratios are
smaller than quadratic converter. By increasing the
number of capacitors, conversion ratio can be increased
with small penalty on conduction losses.
A switch capacitor technique has been used to (b)
achieve high voltage conversion ratio [8, 9]. A switch
capacitor circuit is inserted within a boost converter. Fig. 2: (a) Circuit for the first switching Interval and (b)
It achieves high voltage conversion ratio with low duty for second switching Interva
ratio. High efficiency is the main advantage of this
converter. The major drawback of this converter is high Principle of Operation: The converter operates by
switch voltage stress which increase the rating of switch. repeatedly switching between two circuits. The first
A new family of boost converter has been presented circuit is produced when the switch is on and the second
in [10]. The proposed topology provide very high voltage circuit is produced when the switch is off. In first
conversion ratio with low duty ratio. The major draw back switching interval, the switch is on and the two diodes are
of this converter is the pulsating output current. off due to negative capacitor voltage -V . Both series
A cascade of two dc-to-dc boost converters is capacitors are discharge into the load as given in
proposed [11]. In this method an intermediate dc voltage Fig. 2(a).
is established between the two stages. Schottky diodes In the second switching interval, the switch is off and
have been used instead of fast-recovery diodes, as they diodes start conduction. The two series capacitors
have a lower forward-voltage drop and no reverse equally charged as given in Fig. 2(b).
recovery. However, the cascade of two boost The circuit equations for the first switching interval
converters implies a low total efficiency, which is (0 t DTs) are as follows:
equal to the product of the efficiencies of each converter.
This militates against the simplicity of the circuit.
The complexity and higher cost resulting from using two
dc-dc converters limits is use.
Type 1 Converter: Type 1 dc-to-dc converter is shown in
Fig. 1. It is based on the use of a new four terminal PWM
switching cell. The switching cell is made of two diodes
D and D , two identical capacitors C, one inductor L and
1 2 o
one switch S. The converter is formed by replacing
intermediate capacitor, output inductor and output
diode of the conventional Cuk converter with the new
switching cell presented in [2]. This converter provides
high voltage conversion ratio, low switch voltage stress
and high efficiency due to low switch conduction
losses.
(a)
c
The circuit equations for the second switching
Interval (DTs t Ts) are as follows:
Converter Voltages and Currents: Using the principle of
inductor volt-second balance and capacitor charged
balance the following equations are obtained.
1
1
g
V D
V D
+
=

o
V
I
R
=
1
(1 )
(1 )
Lo
L
D I
I
D
+
=

2 i
L1

1
L1
2 i
g
V
L DTs =

i
L1

o
2
,
2L
g
Lo c o
Lo
o
V
di V V
i DTs
dt L

= =
i
Lo

(1 )
,
2 (1 )
g
c
dv I V D DTs
c o
v
dt C C D R
+
= =

1
q , ( ) (2 )
2 2
o o o
Ts
C V i C v = =
i
Lo

2
16
g
o o
V DTs
v
L C
=
World Appl. Sci. J., 23 (11): 1471-1480, 2013
1473
Fig. 3: Inductor current waveform
Fig. 4: Series capacitor where is the output inductor current ripple and L is
(1)
(2)
(3)
where V is the output dc voltage, V is the input dc
g
voltage, I is the average load current and I is the output
o Lo
inductor current.
Expressions of Inductances L and L : During the first
1 o
switching interval (0 t DTs), the current through
inductor L increases linearly while for the second
1
switching interval (DTs t Ts), the decreases linearly as
shown in Fig. 3.
= S lope x Duration of the first switching interval
(2.6)
Where L is the input inductor inductance, is the
1
input inductor current ripple and T is the Switching time
s
period,
For 0 t D Ts
(4)
Fig. 5: Output capacitor current and voltage
o
the output inductor inductance
Expressions of Capacitances C and C
o
(5)
where C is the Series capacitor capacitance and v is the
c
series capacitor voltage ripple
Output capacitor capacitance C : Small ripple
o
approximation is not applicable to those converters
having two-pole low pass filter. The reason is that this
approximation shows zero ripple in the output voltage for
these converters independent the value of output filter
capacitance C . Inductor current consist of a dc
o
component and ac ripple current. The dc component
entirely flows through the load resistance where ac ripple
current divides between load resistance R and output
filter capacitance C This ac ripple current leads to output
o.
voltage ripple v. The value of v is calculated by the
total charge stored on capacitor.
Putting the value of leads to
(6)
where v is the output voltage ripple
2 2
1
1
2
1
1 1 1
1 1 1
1
1
1
g D
on L
on on on LO
D
V V
D
V
DR D D R D
D D R D
R
DR DR DR R D
R R D R R
+

=
+ + +
+ +



+
+ + + +

World Appl. Sci. J., 23 (11): 1471-1480, 2013
1474
Fig. 6: Non-inverting zeta-derived converter
(a)
(b)
Fig. 7: (a) Circuit for the first switching Interval and (b)
for second switching Interval
The output voltage of a practical converter is less
than ideal converter due to voltage drop in switch on
resistance, diode voltage drop and inductor internal
resistance. When these sources of voltage drop are
considered then expression for output voltage is given
by
(7)
where V is the diode voltage drop, R is the
D on
switch on resistance, R is the input inductor internal
L1
resistance and R is the output inductor internal
Lo
resistance.
Fig. 8: Inverting zeta-derived converter
(a)
(b)
Fig. 9: (a) Circuit for the first switching Interval and (b)
for second switching Interval
Non-Inverting Zeta-Derived Converter: This converter is
formed by replacing intermediate capacitor, output
inductor and output diode of the conventional Zeta
converter with non-inverting switching cell presented in
[11]. This converter provides high voltage conversion
ratio, low switch voltage stress and high efficiency due to
low switch conduction losses. The efficiency of this
converter is small compare to that of Type 1 converter due
to additional diode D . The main disadvantage of this
3
converter is pulsating output current which increases the
output voltage ripple.
Principle of Operation: During first switching interval
switch is on and diode D is on while D and D are off.The
3 1 2
output load and output capacitor Co are charged by the
two series capacitors as shown in Fig. 7(a). During second
switching interval switch is turned off and the two diodes
D and D start conduction.The two series capacitors are
1 2
equally charged by the input inductor current as shown
in Fig. 7 (b).
L1 g 1
V , ,
2
g
c
c L g c
v V
dv
v i C i i v
dt

= = = =
1 1
L1 1
,
2
c L L
c c
dv di i
v L v i C
dt dt
= = = =
1
1
g
V D
V D
+
=

1
2
1
g
L
I
I
D
=
+
1
/
2
o
L
I
I
D
=
1
L1
2 i
g
V
L DTs =

(1 )
2
o
o
I D Ts
v
C

=
2
o s
c
I T
v
C
=
1 1
2 2
1
3
1
2(1 ) 4 4 1
1
1
(1 ) (1 ) (1 )
g D
on on L L
D
V V
D
V
D R R DR R D
D R
D R D R D R
+

=
+ +
+ + + +

1
L1 g
V , ,
2
g L
c
co o o c
i i
dv dv
v i C i i C
dt dt

= = = = =
1
L1 1
1
2
L
c
c
c L
di
v L v v
dt
dv
i C i
dt
= =
= =
2
1
o
g
V D
M
V D

= =

L1
I
1
o
I
D
=

LI
I
2
g
I
D
=

World Appl. Sci. J., 23 (11): 1471-1480, 2013

1475
The circuit equations for the first switching interval
(0 = t = DT ) as follows:
s
The circuit equations for the second switching
Interval (Dt t T ) are as follows:
s s
Converter Voltages and Currents: Using the principle of
inductor volt-second balance and capacitor charged
balance the following equations are obtained
(8)
(9)
where I = D = Average input current
g g
i
Now for relation between inductor current and output
current
(10)
Inductance and Capacitance: For input inductor
inductance L
1
(11)
Now for output capacitor capacitance Co
(12)
For series capacitor C calculation
(13)
Output voltage expression is given by
(14)
InvertingZeta-Derived Converter: his converter is formed
by replacing intermediate capacitor, output inductor and
output diode of conventional Zeta converter with
inverting switching cell presented in [11].
Principle of Operation: During first switching interval
D and D are switch on while D is switch off due to
1 2 3
negative voltage (V -V) across it. In this interval input
g
current charges both series capacitors C. Output
capacitor C is discharged into load to supply the output
o
current I
o.
The reduce form of the circuit is given in fig. 9(a).
During the second switching interval D and D are switch
1 2
off due to negative voltage (V -V) across these diodes,
g
while D is switch on. The two series capacitors C are
3
discharged to charge the load and output capacitor as
given in Fig. 9(b).
Equations for the first switching interval (0 t D T
s)
are:
Equations for the second switching interval (DT t T )
s s
are
Converter Voltages and Currents:
(15)
(16)
(17)
where I = D and I is the average input current
g g g
i
1
L1
2 i
g
V
L DTs =

2 R
o
VDTs
C
v
=

1
1 1
2 2
(1 )
2
2
3
1
(2 ) 2
2 1
1
(1 ) (1 )
L
c
g D
on on L L
I D Ts
C
v
D
V V
D
V
D R R DR R D
R D R
D R D R

=

+ + + +

1
L1 1 1
/
1
(1 )
, ,
2
2
L
g co co L o
c
L
di dv D
v L V i C i i
dt dt D
dv D
i C I
c dt DC

= = = =
= =
1 1
L1 1
- , ,
2
L L
g c co co o c
di dv i
v L V v i C i i
dt dt
= = = = =
World Appl. Sci. J., 23 (11): 1471-1480, 2013
1476
(a)
(b)
Fig. 10: (a) New switching cell (b) Proposed Conveter
Inductance and Capacitance: For input inductance L
1
(18)
For output capacitor L
1
(19)
For Series capacitor capacitance C
0
(20)
Proposed New Converter: This propose new converter is
based on the use of new switching cell as shown in fig.
This new switching cell is derived from the idea of two
different switching cells switching cells presented in [2]
and [10]. Replacement of intermediate capacitor, output
inductor and output diode of conventional Cuk converter
with the new switching cell leads proposed new
converter as given Fig. 10.
(a)
(b)
Fig. 11: (a) First switching interval (b) Second switching
interval
Principle of Operation: During first switching interval
when the switch is on, diodes D and D are reverse
1 2
biased due to the negative voltage of capacitor -V and
c
D is forward biased and the simplified circuit is shown in
3
Fig. 11(a) During this interval the voltage across series
capacitors are equal. Both series capacitors C charging
the load and output capacitor C . The energy is stored
o
by inductor in this interval.
During second switching interval when the switch is
off, diodes D , D are forward biased and output diode D
1 2 3
is reversed biased. In this interval the two capacitors C
are in parallel. In this interval the two capacitors C are
equally charged. The simplified circuit is shown in
Fig. 11(b)
For first switching interval (0 t DT )
s
For second switching interval (DT t T )
s s
2
M
1
g
V
V D
= =

s 1
/
2 1
M ,
2
o
L
I
I
D
= =
1
L1
2 i
g
V
L DTs =

2
o s
c
I T
C
v
=

0
(1 )
2
o
I D Ts
C
v

1
2 2
2
3
1
4 2 4
(1 )
(1 ) (1 )
2 2
1
(1 ) (1 )
D
on on L
on on D D
Vg
V
D
V
DR DR R
D R
D R D R
R R R R
D R D R R R

=
+ + +

+ + + +

World Appl. Sci. J., 23 (11): 1471-1480, 2013
1477
Converter Voltages and Currents:
(21)
(22)
Inductance and Capacitance:
(23)
(24)
(25)
When these sources of voltage drop are considered then
expression for output voltage is given by
(26)
Simulation Result and Comparison: Circuit simulation of
different converters were simulated to validate theoretical
results and to measure the performance of the proposed
converter in term of voltage conversion ratio, voltage
ripple, inductor current ripple and switch voltage stress.
The results of different converters were compared for the
real application HID (high-intensity-discharge) lamp use
in a car, whose specifications are:
V =12 V, V= 100 V, P =35 W.
g out
The average output voltage value of the type 1 Cuk
topology, non-inverting zeta- derived converter, inverting
zeta-derived converter and proposed converter are 100V
with duty ratios of 0.78, 0.78,0.87 and 0.76 respectively as
shown in Fig 12(a), 12 (b) and 12 (c) and12 (d). This shows
that voltage conversion ratio of proposed converter is
higher as compare to other three converters.
(a)
(b)
(c)
(d)
(a) (100V with 0.78 duty ratio)
(b) (100V with 0.78 duty ratio)
(c) (100V with 0.86 duty ratio)
(d) (100V with 0.76 duty ratio)
Fig. 12: (a) Output voltage waveforms of (a) type 1 Cuk
topology (b) non-inverting zeta-derived
converter (c) inverting zeta -derived converter
(d) proposed converter
The output voltage peak-to-peak ripple values of the type
1 Cuk topology, non-inverting zeta- derived converter,
inverting zeta-derived converter and proposed converter
are 0.18V, 1.34V, 3.08V and 1.41V as shown in figures
World Appl. Sci. J., 23 (11): 1471-1480, 2013
1478
(a) (a)
(b) (b)
(c) (c)
(d) (d)
(a) (0.18V peak-to-peak ripple) (a) [58V] (b) (59V) (c) (94V) (d) (52. 8 V)
(b) (1.34V peak-to-peak ripple)
(c) (3.08V peak-to-peak ripple) Fig. 14: Switch voltage stress waveforms of (a) type 1
(d) (1.41V peak-to-peak ripple) Cuk topology (b) non-inverting zeta-derived
Fig. 13: Output voltage ripple waveforms of (a) type 1 proposed converter
Cuk topology (b) non-inverting zeta-derived
converter (c) of inverting zeta-derived converter and 14 (c) and14 (d) respectively. So the voltage stress
(d) proposed converter across the switch for proposed converter is smaller
Fig 13(a), 13 (b) and 13 (c) and13 (d) respectively. So the For the same value of input inductor, the
type 1 Cuk topology provides better output dc voltage as peak-to-peak input inductor current ripple values of
compare to other three converters. the type type 1 Cuk topology, non-inverting zeta-
The switch voltage stress values of the type 1 Cuk derived converter, inverting zeta-derived converter and
topology, non-inverting zeta- derived converter, inverting proposed converter are 0.6A, 0.85A, 0.66A and 0.59A
zeta-derived converter and proposed converter are 58V, respectively as shown in figures 15(a), 15(b) 15(c)and
59V, 94V and 52.8V as shown in figures Fig 14(a), 14 (b) 15(d).
converter (c) inverting zeta-derived converter (d)
compare to other three converters.
( i )
L1 pp

( ) v
C PP

( i )
L1 pp

( ) v
C PP

v
pp

World Appl. Sci. J., 23 (11): 1471-1480, 2013

1479
Table 1:
Proposed Converter Type 1 Cuk topology Non-verting Zeta derived converter Inverting Zeta derived converter
I 3.22A 3.19A 3.61A 3.02A
L1
0.59A 0.6A 0.85A 0.66A
0.74V 0.4V 0.75V 0.74V
v 1.41V 0.18V 1.34V 3.08V
pp
D 0.76 0.78 0.78 0.86
V 52.8V 58V 59 94V
s
(a)
(b)
(c)
(d)
(a) (0.6A peak to peak ripple)
(b) (0.85A peak to peak ripple)
(c) (0.66A peak to peak ripple)
(d) (0.59A peak to peak ripple)
Fig. 15: Input inductor current ripple waveforms of (a)
type 1 Cuk topology (b) non-inverting
zeta-derived converter (c) inverting zeta-derived
converter (d) proposed converter
The values of dc input inductor current, peak-to-peak
input inductor current ripple , peak-to-peak series
capacitor voltage ripple , peak-to-peak output
voltage ripple duty ratio D and switch voltage stress
,
V , of previous high voltage converters as well as hybrid
s
switch converter in summarize form is tabulated in
Table 1.
CONCLUSION
The study and analysis of different converters have
been carried out successfully. The paper present the
derivation of a new switching cell from the previous cells.
The new switching cell combines the idea of two
switching cells presented in two different papers.
The insertion of new switching cell in conventional Cuk
converter has resulted in new converter converter.
The result of this new DC-to-DC converter is compared
with other converters. The proposed converter has better
advantages over conventional DC-to-DC converters with
respect to high efficiency, high voltage conversion ratio
and reduced switch voltage stress. The simulation results
show full agreement with theoretical.
ACKNOWLEDGMENTS
The first author expresses his deep gratitude to Prof.
Dr. Salim-Ur-Rehman, Vice Chancellor, Sarhad University
of Science a nd Information Technology, Peshawar,
KPK, Pakistan, for his support and providing research
facilities.
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