Noise Source in a MOSFET

MOSFET noise properties depends on the parameters and c MOSFET noise properties depends on the parameters , , and c
Typical values for 0.18-m NMOS devices:
= 0.5 (bias dependent, can be made close to unity by using small V
gs
)
= 3; = 2 = 6; (for long channel devices)
( and increases with shorter channel length; determined from measured data)
c = j0.55
4
0
2
=
d nd
g
g kT i

Drain Gate
} 1 { 4
0
= =
d
m
m
g
g
g kT

2
4
g ng
g kT i =
g
m
V
gs
C
gs
g
g
4kTg
g
4kTg
m
/
0
2 2
5
4
d
gs
g
C
kT

=
Drain Gate
R
g
4kTR
g
+
Source
g
m
V
gs
C
gs
4kTg
m
/
+ -
0
2
5
4
4
d
g ng
g
kT
R kT v

=
=
Prof. C. Patrick Yue Slide 1
Source
coupling capacitive to due correlated are
2 2
ng nd
i and i
MOSFET Two Port Noise Parameters
4 4
2
,
m
n
m
n in nd
g
R
g
kT kTR v

= => = =
2 2
2 2
) 1 ( 4 4 ) (
2 2
2 2
c g kT c g kT i i i
g g ngu ngc ng
+ = + =
0) B d 0 G (b/
) ( ) ( + + + = + =
c u c u c u n
jB G
B B j G G Y Y Y
0) Bu and 0 Gc (b/c = = + =
c u
jB G
c gs
ng
m gs c
jB c C j
i
i
c g C j Y = = + = )
5
1 (
2
2

5
2
1
2 2

g
) c (
gs
C

u
G

=
The uncorrelated part of the gate noise is purely real.
i e G = 0
c gs
nd
gs c
i 5
2

0
5
d
g
u
" imaginery. purely is e conductanc noise of part correlated The "
5
1 )

c ( C B
gs c
=
i.e. G
c
= 0
Prof. C. Patrick Yue Slide 2
term)." 2nd (the noise gate induced the and term) 1st (the
noise current drain relfected the : parts two has n correlatio The "
5
Noise Factor for CS-LNA with Lg and Ls (Under Conjugate
Power Match) Power Match)

+ + + =

5
) 4 1 (
5
2 1
2
1
1
2
2
2
0
Q c
Q
F
NF depends on

5 5 2Q
T
(See supplementary slides for derivation)
The bias operating of the device which determines
T
and g
m
The Q of the input series which determines device W and therefore C
gs
There is an optimal bias for minimum NF
Higher g
m
gives higher
T
, but drain noise current is also increased
There is an optimal Q of the input resonant circuit for minimum NF
Increasing the Q of the input resonant circuit reduces the contribution of the c eas g t e Q o t e put eso a t c cu t educes t e co t but o o t e
channel noise to the total output noise
But gate induced noise is increased with larger Q
Mathematically, we take the derivative of NF wrt Q to find the optimal Q
Prof. C. Patrick Yue Slide 3
y
Conjugate Power Match vs. Conjugate Noise Match
Conjugate power match (adopted in most practical design)
2 2
5 5
2 1

+ = c Q
opt
gs s g
C L L ) (
1
2
+ =
2 2

p
2
0

Q F
2
1
0

+
Conjugate noise match (derivation shown in Tom Lees book 2
nd
Ed., p. 369)
opt
T
Q F
5
1
0
min

+ =
The input circuit is not at resonant at the operating frequency
)]
5
1 ( )[ (
1
2

c C L L
gs s g
+ =
) c 1 (
5 C
G
Q
2
opt
opt

= =
5
2
0

g g
) (
5 C
Q
gs
opt

) 1 (
2
1
2
0
i
c F + =

Prof. C. Patrick Yue Slide 4

) 1 (
5
1
min
c F
T
+

Optimal Q and Min. NF for 0.18-m NMOS

Typical values for 0.18-m NMOS devices
= 0.5 (bias dependent, can be made close to unity by using small V
gs
)
= 3; = 2 = 6; ( and increases with shorter channel length)
j0 55
74 . 2
5 5
2 1
2 2
= + =

c Q
opt
gs s g
C L L ) (
1
2
+ =

c = j0.55

0

33 . 1
5
2
1
0
min
= + =
opt
T
Q F

Prof. C. Patrick Yue Slide 5

Noise Factor vs. Q
Increasing the correlation between drain and induced gate noise results
Prof. C. Patrick Yue Slide 6
in lower NF
min
Low Noise Amplifier Design
Design Issues
Noise Figure impacts receiver sensitivity
Impedance match want Zin = Zo (usually = 50 )
Power want low power dissipation
Gain high gain reduces impact of noise from components that follow the
LNA (such as the mixer)
Reverse isolation prevent signal leaking from output back to input, the
amplifier can become unstable
Linearity (IIP3) impacts receiver blocking performance
Sensitivity to process/temp variations need to make it manufacturable in
hi h
Prof. C. Patrick Yue Slide 7
high
Narrowband Common-Source LNA with Degeneration
Prof. C. Patrick Yue Slide 8
Input Impedance for CS-LNA with Inductive Degeneration
Prof. C. Patrick Yue Slide 9
Input Impedance for CS-LNA with Lg and Ls
Prof. C. Patrick Yue Slide 10
R
L d
Voltage Gain of CS-LNA with Lg and Ls
C j
1
R
Load
L d 1 i
Load m Load m1
0

in
gs 0
v
R g Q
R G R g
Z
C j
A
=
= =
s
m
s
s g 0
s
m
s gs 0
in
s
m
s gs 0
Load m1
Load m1 in
L
C
g
R
) L (L
) L
C
g
(R C
1
Q : that Note
) L
C
g
(R C
R g
R g Q
+
+
=
+
=
+
=
s T s gs 0
Load m1
gs gs
g
gs
g
) L (R C
R g
C C C
+
=
s T s
s 0
Load T
L R set matching, input power conjucgate For
R 2
R
= =
s T 0
Load T
R
L 2
R
=
Prof. C. Patrick Yue Slide 11
s 0
Load
L 2
R
=
Practical Considerations
Minimum length device in a given process does not guarantee the
best noise performance
Longer than minimum length device have a lower
T
but lower noise
factors ,
Achieving NF
min
requires balancing these two opposing effects
Accurate prediction of NF
min
value therefore requires experimental p
min
q p
data of ,
In practice, by using minimum length device and biasing the device
at low V
gs
(i.e. I
den
just below
T
and g
m
peaks) will almost guarantee
gs
(
den
j
T
g
m
p ) g
the best noise performance
Q of Ls and Lg needs to be reasonable high (510), so their noise
contribution is secondary to the CS device y
Prof. C. Patrick Yue Slide 12
Id vs. Vgs for 0.18-m NMOS
~ 600 A/m at Vgs = Vds = Vdd (1.8V)
Linear dependence on V
gs
implies that the device is in
velocity saturation velocity saturation
Prof. C. Patrick Yue Slide 13
gm vs. Vgs for 0.18-m NMOS
b i iti t V g
m
becomes insensitive to V
gs
implies that the device is in
velocity saturation
good for linearity since g is good for linearity since g
m
is
not input amplitude dependent
( ) ( )
( )
sat t gs
sat t gs sat t gs
ox n
m
C
LE V V
LE V V LE V V
L
W
C
g
2
2
2
2 2

+
+
=
Prof. C. Patrick Yue Slide 14
sat
ox n
m
WE
C
g
2

gm vs. Id/W for 0.18-m NMOS

C W C 2 2
Slope = 1
den
ox n
d
ox n
m
I
L
C
W I
L
W C
g
2 2
= =
V = 0 8 V gives 100 A/m V
gs
= 0.8 V gives 100 A/m
Use minimum L for most g
m
per current density
Avoid operating at higher current density (not power efficient)
Want to operate at an I
den
where d (g
m
) / d I
den
> 1
Prof. C. Patrick Yue Slide 15
Want to operate at an I
den
where d (g
m
) / d I
den
> 1
for 0.18-m CMOS process, typically I
den
< 100 A/m
Optimal Bias Current Density for fT
NF depends on f
T
and thus current density (I
d
/ W)
Prof. C. Patrick Yue Slide 16
How to Chose the Proper Bias Point?
Prof. C. Patrick Yue Slide 17
Minimum NF vs. Vgs for Different L
V
gs
value for the lowest NF
min
decreases with smaller L
In low V
gs
region, NF
min
decreases when V
gs
increases
NF
min
drops because the increasing rate of g
m
(first derivative of g
m
wrt V
gs
) NF
min
drops because the increasing rate of g
m
(first derivative of g
m
wrt V
gs
)
is faster than drain current noise
In high V
gs
region, NF
min
decreases when V
gs
decreases
Due to velocity saturation and mobility degradation, gm decreases
Prof. C. Patrick Yue Slide 18
But drain current noise continues to increase
Transconductance and Drain Current Noise vs. Vgs
Lowest NF happens at a V before g peaks instead of the the peak Lowest NF
min
happens at a V
gs
before g
m
peaks, instead of the the peak
gm, because the derivative of g
m
wrt V
gs
is equal to zero at peak g
m
For 0.18-m device, optimal V
gs
is usually less than 1V
Prof. C. Patrick Yue Slide 19
Common-Base Broadband LNA
= 1/ g
m

+ = + = 1 1 F

s m
R g
Prof. C. Patrick Yue Slide 20
Broadband Low-Noise Shunt-Series Amplifier
Prof. C. Patrick Yue Slide 21
Broadband Low-Noise Shunt-Series Amplifier
Prof. C. Patrick Yue Slide 22
Noise Reduction Decouple Q and Cgs
(P. Andreani in IEEE Trans. CAS II, Sept. 2001)
Introducing an additional capacitance, C
d
, in parallel to the intrinsic gate
capacitance of transistor M
1
facilitates the decoupling of Q from C
gs
which allows which allows for an adjustable reduction of Q for any given
value of C This is important since induced gate noise grows with the
Prof. C. Patrick Yue Slide 23
value of C
gs
. This is important since induced gate noise grows with the
square of C
gs
.
Noise Reduction Noise From Cascode Device
(H. Samavati in JSSC, May 2000)
Prof. C. Patrick Yue Slide 24
LNA with Built-in Image Reject Filter
(H. Samavati in JSSC, May 2000)
Prof. C. Patrick Yue Slide 25
LNA with Built-in Image Reject Filter
(H. Samavati in JSSC, May 2000)
Prof. C. Patrick Yue Slide 26
( y )
Substrate Thermal Noise in MOSFET
Need to minimize R
sub
and g
mb
N d t t f th f d t R d C
Prof. C. Patrick Yue Slide 27
Need to account for the corner frequency due to R
sub
and C
cb
1/f noise
Get worse with technology scaling
K ~ 1e-26 for NMOS and 1e-28 for PMOS
Not a significant contributor noise for LNA design
Important for low-IF downconversion mixer and VCO po ta t o o do co e s o e a d CO
Prof. C. Patrick Yue Slide 28
Narrowband LNA IIP3 Estimation
Prof. C. Patrick Yue Slide 29
Wideband LNAs
Prof. C. Patrick Yue Slide 30
Bevilacqua, ISSCC2004.
Measured LNA Performance
Prof. C. Patrick Yue Slide 31
LNA with Shunt Feedback
C W Kim JSSC 2005
Prof. C. Patrick Yue Slide 32
C.-W. Kim, JSSC 2005.
Measured LNA Performance
C W Kim JSSC 2005
Prof. C. Patrick Yue Slide 33
C.-W. Kim, JSSC 2005.