RFIC Group

Advanced VLSI Design Lab

IIT Kharagpur
Activity: Design of 1V low power RF Front-end Receiver ---- ZigBee Compliance
[Sponsored By National Semiconductor Corporation USA]

Team Members: Ashudeb Dutta, Debashis Mandal, Sourish Haldar, Prabir Saha,
Prof. T. K. Bhattacharyya

Contact: t_k_bhattacharyya@yahoo.com
Brief Summary:
Aim of this work is to realize a low-power & low-voltage, single-chip ZigBee compliant receiver
front-end operating in the GSM band (850MHz -950MHz) for sensor networks application. Low
voltage operation allows the reduction of battery sizes and power consumption as well as low power
operation increases battery longevity. Design of 1 Volt receiver modules on standard epi 0.18 m digital
CMOS process (with a standard supply of 1.8V ) is highly challenging owing to the voltage headroom
problem, large parasitic capacitance due to increased device sizes and degradation of SNR due to decrease of
signal amplitude, hence demanding a careful design or even topological changes.
Features:
MOSes with low V
t
have been used in LNA and VCO
to solve voltage headroom problem.

Cascode Inductive source degenerated LNA.

Push-pull architecture based secondary
transconductance amplifier, providing more Gm than
a usual differential structure for a given current,
introduced in between LNA and Mixer, effecting a
low-power realization.

Different biases for NMOS and PMOS in secondary
transconductance amplifier to adapt to 1 V supply.

LC VCO with complementary cross-coupled
transistors, reuses the current to provide higher
negative G
m
as compared to a single cross-coupled
transistor.

VCO is designed at 1.8 GHz (2f0) that gives higher Q
of inductor, which helps in low power realization.

Frequency division done by a master-slave D flip-
flop.
Fig: 1(a), VCO freq. tuning
Fig: 1(b), QVCO freq. tuning graph
Fig: 1 (c), QVCO freq. spectrum

VCO Id(mA) Over-all
gain (dB)
NF
(dB)
1dB comp.
pt (dBm)
Phase noise Swing
(mV)
KVCO
(MHz/V)
Tuning
range
(MHz)
KVDD
(MHz/V)
Specifications
11.36 37.35 6.297 -40 -95 dBc/Hz
@100KHz
-136 dBc /Hz
@3MHz
612 47.5 810 - 987 6
Targeted 10 35 6 IIP3
(-30dBm)
-90 dBc/Hz
@100KHz
-130 dBc/Hz
@3MHz
- 50 850 - 950 20
Cross-coupled pair Varactor
I nductor
Pad Switched
Capacitors
Bias Generation
Circuitry
D Di i e e p ph ho ot t o o o of f Q QV VC CO O
System
Stand alone LNA
L La ay yo ou ut t o of f s sy ys st t e em m


Mixer
Divider
Output
Buffers

Recent Publications:

P. Saha, A.Dutta and T. K. Bhattacharyya, Design of a 1 V Low Power 900 MHz QVCO, IEEE
International Conference on VLSI Design 2006 (VLSID06).
System Performance














































Activity: 2.4GHz Fully-Integrated CMOS Integer-N Frequency Synthesizer
Team Members: Debashis Mandal, Prof. T. K. Bhattacharyya

Contact: t_k_bhattacharyya@yahoo.com
Brief Summary:
The recent developments and advanced scaling in sub-micron CMOS technologies have made it
more feasible, more promising and more attractive to implement a single-chip CMOS wireless transceiver
for its potential in achieving the highest possible level of integration and the best performance in terms of
cost, size, weight and power consumption. A frequency synthesizer is one of the most critical building
blocks in any integrated wireless transceiver systems. The challenges in its design are increasing by the day
as the demand for low-cost, low-voltage, low-power, high-frequency wireless systems is at an all time high.
This work aims to design a low-power, single-chip, CMOS frequency synthesizer conforming to
ZigBee standard. ZigBee is an industry standard for short range, low bit rate, low cost, low power wireless
applications. Application area includes home automation and networking, interactive toys and games,
industrial and commercial networking etc. Global band of ZigBee operates in license free ISM band (2.4
2.4835 GHz). There are 16 channels with a spacing of 5 MHz.
Features:
Implemented on 0.18m Epi Digital CMOS
process. Epi process reduces Q-factor of
inductor. It leads to poor phase-noise
performance and more power consumption.

Loop-filter is on-chip. 3
rd
order passive loop-
filter has been used.

LC VCO with complementary cross-coupled
transistors reuses the current to provide higher
negative G
m
as compared to a single cross-
coupled transistor.
Die photo of the synthesizer
Block Diagram of the Frequency Synthesizer
Buffer I
Buffer II
PFD CP +
LF
VCO
Programmable
Frequency
Divider
Fout+
Control Word
Reference
Signal
Fout-
Fref
Ffbk
Bias
Generator
Full Chip
Current
Control











































Recent Publications:

Debashis Mandal, T. K. Bhattacharyya, 7.95mW 2.4GHz Fully-Integrated CMOS Integer-N
Frequency Synthesizer. Accepted in IEEE International Conference on VLSI Design 2007.
Phase-noise measurement of the synthesizer
Output Spectrum of the synthesizer
Measured performance summary
Supply 1.8 V
Process 0.18 m Epi Digital CMOS
Architecture Integer N
Power consumption 7.95 mW
Frequency range 2.4 2.48 GHz
No. of channels 16
Reference frequency 5 MHz
Channel spacing 5 MHz
Phase-noise -81.55 dBc/Hz @100kHz;
-108.55 dBc/Hz @1MHz
Spurs -40.84 dBc
PLL -3dB BW 30KHz (estimated from
phase noise plot)
Settling time < 25 s (switching from 1
st

to last channel)
Size 0.4875 mm
2

Division ratio 480 - 496
On-chip loop filter Yes
Switch Capacitor Array (SCA) has been used to
reduce the VCO gain (Kvco) and to get faster
switching time.

Low Kvco also reduces the influence of loop-
filter noise on VCO frequency. As a result, much
smaller on-chip loop filter capacitors have been
used to filter out the noise.

Frequency to supply voltage sensitivity (Kvdd)
is kept low.

To reduce the power consumption,
programmable divider block with the
combination of power inefficient Current Mode
Logic (CML) for high frequency dividers and
power efficient CMOS Digital Logic (DL) for
low frequency dividers has been implemented.





































Activity: Transmitter front-end for 1V low power radio
Team Members: Sourish Haldar, Debash Bhatta, Sanjay Arya, Prof. T. K. Bhattacharyya

Contact: t_k_bhattacharyya@yahoo.com
Brief Summary:
The single sideband low-power transmitter is continuation of transceiver design for wireless sensor
networks, complying IEEE 802.15.4 standard commonly known as ZigBee. The transmitter has Inphase-
Quadrature architecture mixer to generate single sideband signal and also incorporates a power amplifier
to deliver the requisite power needed for the said standard. No external PA is needed.
Features:
Other than AC blocking inductors
to supply, the transmitter is fully
on-chip.

Simple but robust design to
maintain the strict power budget
and ensure operation in adverse
operating condition.

The full transmitter has a
bandwidth of 100 MHz, from 865
to 950 MHz covering the full
ZigBee channels in the 868MHz
and 902-928MHz ZigBee band.

The mixer is an improvisation over
MOS ring mixer, delivering over
70 dB sideband suppression.
Power Amplifier
Improvised Passive Mixer













































Activity: Broadband Model for On-Chip Inductors with Substrate Eddy Current Effect
Team Members: Sushanta K. Mandal, Prof. Shamik Sural and Prof. Amit Patra

Contact: amit.patra@ieee.org
Brief Summary:
Silicon based RF integrated circuits are becoming more and more competitive in a wide band
frequency range. Essential components of these IC are on-chip spiral inductor. The quality of inductor
fabricated on lossy silicon substrate is quite low. A successful design and simulation of RF ICs depends
on accurate modeling and characterization of on-chip spiral inductors. The existing models suffer from
broadband accuracy and scalability. The proposed model consists of a substrate network and a high
resistive component to model the reduction in equivalent series resistance and substrate eddy current
effects at higher frequencies.
Recent Publications:

Sushanta K. Mandal et al, Broadband Scalable Model for Si-RF On-chip Spiral Inductors
with Substrate Eddy Current Effect. Accepted in International Journal of RF and Microwave
CAE.
Sushanta K. Mandal et al, "A Wide-band Lumped Element Compact CAD Model of Si-Based
Planar Spiral Inductor for RFIC Design", in Proceedings of 19th International Conference on
VLSI Design, January 3rd-7th, 2006, Hyderabad India, pp. 619-624.
Features:
Compact model of on-chip spiral inductors with
substrate eddy current effect.

Accurately captures broadband characteristics
up to 20 GHz.

Frequency independent and can be easily
integrated with any SPICE compatible RFIC
design flow.

An automated parameter extraction and
optimization procedure through equivalent circuit
analysis and particle swarm optimization.

Scalable model and can be easily adopted to fit a
new process simply by recalibrating the model.
1 2
Cp
Ls
Rs
Rp
Rsub Cox1
Cox2
Lsub
Csub
Csi1 Gsi1 Csi2 Gsi2
Msub







































Activity: Designing and Behavioral Modeling of On-Chip Inductor, On-Chip Transformer,
On-Chip Antenna, Connector Network, Vias, etc.

Team Members: Rajarshi Bhattacharya, Sharmistha Dey, Prof. T. K. Bhattacharyya.

Contact: t_k_bhattacharyya@yahoo.com
Brief Summary:
Inclusion of a poorly characterized integrated passive component in a design turns the whole process to an
extremely risky matter. A lot of research is going on to model on-chip passive components in terms of
equivalent circuits. However, the traditional equivalent circuit based approaches lead to geometry specific
models. This work aims to develop a general behavioral modeling algorithm which can be used for
modeling of any arbitrary shaped linear passive components. As an example, on-chip inductor modeling is
illustrated here.

Recent Publications:

Bhattacharya Rajarshi, Joshi Alok, Bhattacharya T. K., PSO-based evolutionary
optimization for black-box modeling of arbitrary shaped on-chip RF inductors. Topical
Meeting on Silicon Monolithic Integrated Circuits in RF Systems, San Francisco, CA, USA,
2006, pp-103-106.
Features:
Accurate wide band behavioral models are obtained
for frequency domain/time domain circuit simulation
in SPICE like simulators.

The same behavioral modeling algorithm can be used
to model any linear passive components of any
arbitrary shape.

Optimal model order and model parameters are
calculated.

Order optimization ensures more flexibility. Hence,
highly accurate and reduced order models are
obtained.

Particle Swarm Optimization technique is used to
ensure convergence to global optima.

Optimized models can be readily inserted into SPICE
like simulators.
Model Order &
Parameter
Estimation
Algorithm
Transfer Function
Z_ind(s) = P(S)/Q(S)
S-Parameter
Numerical
Techniques
or Measurement
Dimension
and Material
Property
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
10
5
10
15
20
25
30
35
40
45
50
Frequency
a
b
s
(Z
I-m
o
d
e
l)d
b
Absolute Value of ZI-model
Measured
Modeled
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
10
20
30
40
50
60
70
80
90
Frequency
P
h
a
s
e
(Z
I-m
o
d
e
l)
Phase of ZI-model


Measured
Modeled