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DE LAB VIVA QUESTIONS

Q.1 The NAND gate output will be low if the two inputs are
(A) 0,0 (B) 0,1
(C) 1,0 (D) 1,1
Ans: D
Q.2 What is the binary equivalent of the decimal number !" (A)
101110000 (B) 110110000 (C)
111010000 (D) 111100000
Ans: A
Q.3 The decimal equivalent of he# number 1A$ is
(A) !%& (B) !%&
(C) !&% (D) !%&
Ans: B
Q.4 (%')
"
= ( )
1!
(A) ( 1 D (B) D ( 1
(C) 1 ( D (D) 1 D (
Ans: D
)%'*
"
+ )1 D (*
1!
Q.5 The simplification of the ,oolean e#pression (A,()+ (A,() is
(A) 0 (B) 1
(C) A (D) ,(
Ans: B
The ,oolean e#pression is (ABC )+ (ABC ) is equivalent to 1
(ABC )- (ABC ) = A - B - C - A - B - C + A - B - ( - A - , - C
+ )A- A *),- B *)(- C * + 1.1.1 + 1
Q.6 The number of control lines for a " / to / 1 multiple#er is
(A) 0 (B)
(C) ' (D) $
Ans: B
Q.7 1ow many 2lip32lops are required for mod/1! counter4
(A) $ (B) !
(C) (D) '
Ans: D
Q.8 56789 contents can be erased by e#posing it to
(A) :ltraviolet rays; (B) <nfrared rays;
(C) ,urst of microwaves; (D) <ntense heat radiations;
Ans: A
Q. The he#adecimal number =A0> has the decimal value equivalent to
(A) "0 (B) 0$!
(C) 100 (D) 1!0
Ans: D
Q.1! The ?ray code for decimal number ! is equivalent to
(A) 1100 (B) 1001
(C) 0101 (D) 0110
Ans: C
Q.11 The ,oolean e#pression A., + A., +
A.,
is equivalent to
(A) A - , (B) A.,
(C) A + , (D) A;,

Ans: A
Q.12 The digital logic family which has minimum power dissipation is
(A) TT@ (B) 7T@
(C) DT@ (D) (98A
Ans: D
The digital logic family which has minimum power dissipation is (98A;
)(98A being an unipolar logic family, occupy a very small fraction of silicon
(hip area*
Q.13 The output of a logic gate is 1 when all its inputs are at logic 0; the gate is either
(A) a NAND or an 5.387 (B) an 87 or an 5.3N87
(C) an AND or an 5.387 (D) a N87 or an 5.3N87
Ans: D
Q.14 Data can be changed from special code to temporal code by using
(A) Ahift registers (B) counters
(C) (ombinational circuits (D) ABD converters;
Ans: A
Data can be changed from special code to temporal code by using Ahift 7egisters;
)A 7egister in which data gets shifted towards left or right when clocC
pulses are applied is Cnown as a Ahift 7egister;*
Q.15 A ring counter consisting of five 2lip32lops will have
(A) $ states (B) 10 states
(C) 0 states (D) <nfinite states;
Ans: A
Q.16 The speed of conversion is ma#imum in
(A) Auccessive3appro#imation ABD converter;
(B) 6arallel3comparative ABD converter;
(C) (ounter ramp ABD converter;
(D) Dual3slope ABD converter;
Ans: B
Q.17 The 0>s complement of the number 1101101 is
(A) 0101110 (B) 0111110
(C) 0110010 (D) 0010011
Ans: D
Q.18 The correction to be applied in decimal adder to the generated sum is
(A) 00101 (B) 00110
(C) 01101 (D) 01010
Ans: B
The correction to be applied in decimal adder to the generated sum is 00110;
When the four bit sum is more than & then the sum is invalid; <n such cases, add
-!)i;e;
0110* to the four bit sum to sCip the si# invalid states; <f a carry is generated when
adding !, add the carry to the ne#t four bit group ;
Q.1 When simplified with ,oolean Algebra )# - y*)# - D* simplifies to
(A) # (B) # - #)y - D*
(C) #)1 - yD* (D) # - yD
Ans: D
Q.2! The gates required to build a half adder are
(A) 5.387 gate and N87 gate (B) 5.387 gate and 87 gate
(C) 5.387 gate and AND gate (D) 2our NAND gates;
Ans: C
Q.21 The code where all successive numbers differ from their preceding number by single bit is
(A) ,inary code; (B) ,(D;
(C) 5#cess / ; (D) ?ray;
Ans: D
)?ray is an unweighted code; The most important characteristic of this code is
that only a single bit change occurs when going from one code number to ne#t;*
Q.22 3" is equal to signed binary number
(A) 10001000 (B) 00001000
(C) 10000000 (D) 11000000
Ans: A
3 " is equal to signed binary number 10001000
Q.23 De9organ>s first theorem shows the equivalence of
(A) 87 gate and 5#clusive 87
gate; (B) N87 gate and ,ubbled
AND gate; (C) N87 gate and
NAND gate;
(D) NAND gate and N8T gate
Ans: B
Q.24 The device which changes from serial data to parallel
data is (A) (8:NT57 (B)
9:@T<6@5.57 (C) D59:@T<6@5.57 (D)
2@<632@86
Ans: C
Q.25 A device which converts ,(D to Aeven Aegment is called
(A) 5ncoder (B) Decoder
(C) 9ultiple#er (D) Demultiple#er
Ans: B
Q.26 <n a EF 2lip32lop, toggle means
(A) Aet G + 1 and G + 0;
(B) Aet G + 0 and G + 1;
(C) (hange the output to the opposite state;
(D) No change in output;
Ans: C
Q.27 The following switching functions are to be implemented using a DecoderH
f
1
=
I
m(1, 0, ', ", 10, 1')
f 0 + I m)0, $, &,11*
f + I m)0, ', $, !, %*
The minimum configuration of the decoder should be
(A) 0 / to / ' line; (B) / to / " line;
(C) ' / to / 1! line; (D) $ / to / 0 line;
Ans: C
Q.28 The decimal equivalent of ,inary number 11010 is
(A) 0! (B) !; (C) 1!; (D) 0;
Ans: A
Q.2 1>s complement representation of decimal number of 31% by using " bit representation is
(A) 1110 1110 (B) 1101 1101
(C) 1100 1100 (D) 0001 0001
Ans: A
Q.3! The e#cess code of decimal number 0! is
(A) 0100 1001 (B) 01011001
(C) 1000 1001 (D) 01001101
Ans: B
Q.31 1ow many AND gates are required to realiDe J + (D-52-?
(A) ' (B) $
(C) (D) 0
Ans: D
Q.32 1ow many select lines will a 1! to 1 multiple#er will have
(A) ' (B)
(C) $ (D) 1
Ans: A
Q.33 1ow many flip flops are required to construct a decade counter
(A) 10 (B)
(C) ' (D) 0
Ans: C
Decade counter counts 10 states from 0 to & ) i;e; from 0000 to 1001 *
Thus four 2lip2lopKs are required;
Q.34 The he#adecimal number for (&$;$)
10
(A) ($2;")
1!
(C) (05;2)
1!
is
(B) (&A;,)
1!
(D) ($A;')
1!
Ans: A
Q.35 The octal equivalent of (0'%)
10
is
(A) (0$0)
"
(B) ($0)
"
(C) (!%)
"
(D) ('00)
"
Ans: C
Q.36 <n a positive logic system, logic state 1 corresponds to
(A) positive voltage (B) higher voltage level
(C) Dero voltage level (D) lower voltage level
Ans: B
Q.54 The commercially available "3input multiple#er integrated circuit in the TT@ family is
(A) %'&$; (B) %'1$;
(C) %'1$'; (D) %'1$1;
Ans: B
Q.56 The 9A< chip %'%' is
(A) Dual edge triggered EF flip3flop )TT@*;
(B) Dual edge triggered D flip3flop )(98A*;
(C) Dual edge triggered D flip3flop )TT@*;
(D) Dual edge triggered EF flip3flop )(98A*;
Ans: C
Q.5 When the set of input data to an even parity generator is 0111, the output will be
(A) 1 (B) 0
(C) :npredictable (D) Depends on the previous input
Ans: B
Q.6! The number 1'0 in octal is equivalent to
(A) (&!)
10;
(B) ("!)
10;
(C) (&0)
10;
(D) none of these;
Ans: A
Q.61 The N87 gate output will be low if the two inputs are
(A) 0,0 (B) 0,1
(C) 1,0 (D) 1,1
Ans: B" C" #$ D
Q.62 Which of the following is the fastest logic4
(A) 5(@ (B) TT@
(C) (98A (D) @A<
Ans: A
Q.63 1ow many flip3flops are required to construct mod 0 counter4
(A) $ (B) !
(C) ' (D) "
Ans: A
9od 3 0 counter -B3 needs $ 2lip32lop as 0 L 0
$
9od 3 N counter counts total K N K number of states;
To count KNK distinguished states we need minimum n 2lip2lopKs as MN + 0
n
N 2or
eg; 9od " counter requires 2lip32lopKs )" + 0

*
Q.64 1ow many address bits are required to represent a 0 F memory
(A) 10 bits; (B) 10 bits;
(C) 1' bits; (D) 1! bits;
Ans: D
0F + 0
$
# 0
10
+ 0
1$
,
Thus 1$ address bits are required, 8nly 1! bits can address it;
Q.65 The number of control lines for 1! to 1 multiple#er is
(A) 0; (B) ';
(C) ; (D) $;
Ans: B
Q.66 Which of following requires refreshing4
(A) A7A9; (B) D7A9;
(C) 789; (D) 56789;
Ans: B
Q.67 Ahifting a register content to left by one bit position is equivalent to
(A) division by two; (B) Addition by two;
(C) multiplication by two; (D) Aubtraction by two;
Ans:C
Q.68 2or EF flip flop with E+1, F+0, the output after clocC pulse will be
(A) 0; (B) 1;
(C) high impedance; (D) no change;
Ans: B
Q.6 (onvert decimal 1$ to octal; 5quivalent in octal will be
(A) (01)
"
; (B) (1)
"
;
(C) ('1)
"
; (D) none of these;
Ans: A
)1$*
10
+ )01*
"
Q.7! The decimal equivalent of (1100)
0
is
(A) 10 (B) 1!
(C) 1" (D) 00
Ans: A
)1100*
0
+ )10*
10
Q.71 The binary equivalent of (2A)
1!
is
(A) 1010 1111 (B) 1111 1010
(C) 10110011 (D) none of these
Ans: B
)2A*
1!
+ )11111010*
10
Q.72 The output of A7 flip flop when A+1, 7+0 is
(A) 1 (B) 0
(C) No change (D) 1igh impedance
Ans: A
Q.73 The number of flip flops contained in <( %'&0 is
(A) 0; (B) ;
(C) '; (D) 10;
Ans: A
Q.74 The number of control lines for 0 to 1 multiple#er is
(A) '; (B) $;
(C) 1!; (D) !;
Ans: B
Q.75 1ow many two3input AND and 87 gates are required to realiDe J+(D-52-?
(A) 0,0; (B) 0,;
(C) ,; (D) none of these;
Ans: A
Q.76 Which of following can not be accessed randomly4
(A) D7A9; (B) A7A9;
(C) 789; (D) 9agnetic tape;
Ans: D
Q.77 The e#cess3 code of decimal % is represented by
(A) 1100; (B) 1001;
(C) 1011; (D) 1010;
Ans: D
Q.78 When an input signal A+11001 is applied to a N8T gate serially, its output signal is
(A) 00111; (B) 00110;
(C) 10101; (D) 11001;
Ans: B
Q.7 The result of adding he#adecimal number A! to A is
(A) DD; (B) 50;
(C) 20; (D) 52;
Ans: B
Q.8! A universal logic gate is one, which can be used to generate any logic function; Which of
the following is a universal logic gate4
(A) 87 (B) AND
(C) .87 (D) NAND
Ans: D
Q.81 The logic 0 level of a (98A logic device is appro#imately
(A) 1;0 volts (B) 0;' volts
(C) $ volts (D) 0 volts
Ans: D
Q.82 Farnaugh map is used for the purpose of
(A) 7educing the electronic circuits used;
(B) To map the given ,oolean logic function;
(C) To minimiDe the terms in a ,oolean e#pression;
(D) To ma#imiDe the terms of a given a ,oolean e#pression;
Ans: C
Q.83 A full adder logic circuit will have
(A) Two inputs and one output;
(B) Three inputs and three outputs;
(C) Two inputs and two outputs;
(D) Three inputs and two outputs;
Ans: D
Q.85 The output of a EF flipflop with asynchronous preset and clear inputs is =1>; The output can be
changed to =0> with one of the following conditions;
(A) ,y applying E + 0, F + 0 and using a clocC;
(B) ,y applying E + 1, F + 0 and using the clocC;
(C) ,y applying E + 1, F + 1 and using the clocC;
(D) ,y applying a synchronous preset input;
Ans: C
Q.8 The 0>s complement of the number 1101110 is
(A) 0010001; (B) 0010001;
(C) 0010010; (D) None;
Ans: C
Q.! The decimal equivalent of ,inary number 10101 is
(A) 01 (B) 1
(C) 0! (D) 0"
Ans: A
Q.1 1ow many two input AND gates and two input 87 gates are required to realiDe
J + ,D-(5-A,
(A) 1, 1 (B) ', 0
(C) , 0 (D) 0,
Ans: A
Q.2 1ow many select lines will a 0H1 multiple#er will have
(A) $; (B) ";
(C) &; (D) 11;
Ans: A
Q.3 1ow many address bits are required to represent 'F memory
(A) $ bits; (B) 10 bits;
(C) " bits; (D) 10 bits;
Ans: B
2or representing 'F memory, 10 address bits are required as
'F + 0
0
# 0
10
+ 0
10
)1F + 100' + 0
10
*
Q.4 2or EF flipflop E + 0, F+1, the output after clocC pulse will be
(A) 1; (B) no change;
(C) 0; (D) high impedance;
Ans: C
Q.5 Which of following are Cnown as universal gates
(A) NAND O N87; (B) AND O 87;
(C) .87 O 87; (D) None;
Ans: A
D E ! DI % I T A L S ELE C T & O NICS
'A&T ( II
NU ) E & I CA L S
Q.1 (onvert the octal number %'01 to ,inary; (4)
Ans:
C#n*+$s,#n #- O./01 n234+$ 74!1 /# B,n0$5:
5ach octal digit represents binary digits; To convert an octal number to binary
number, each octal digit is replaced by its digit binary equivalent shown below;
% ' 0 1
111 100 000 001
Thus, )%'01*
"
+ )111100000001*
0
Q.2 2ind the he# sum of (&)
1!
+ (D5)
1!
;
Ans:
1e# Aum of )&*
1!
- )D5*
1!
(4)
(onvert 1e#adecimal numbers & and D5 to its binary equivalent shown belowH3
& P 10010011
D5 P 11011110
3333333333333333
101110001 P 1%1
33333333333333333
Thus )&*
1!
- )D5*
1!
+ )1%1*
1!
Q.3 6erform 0>s complement subtraction of (%)
10
(11)
10
; (4)
Ans:
0>s (omplements Aubtraction of )%*
10
/ )11*
10
2irst convert the decimal numbers % and 11 to its binary equivalents;
)%*
10
+ )0111*
0
)11*
10
+ )1011*
0
in '3bit system
Then find out the 0>s complement for 1011 i;e;,
1>s (omplement of 1011 is 0100
0>s (omplement of 1011 is 0101
Ao, )%*
10
/ )11*
10
+ 0111
0101
333333333
1100
333333333
01
D E ! DI % I T A L S ELE C T & O NICS
Aince there is no carry over flow occurring in the summation, the result is a negative
number, to find out its magnitude, 0>s (omplement of the result must be found;
0>s (omplement of 1100 is 0011
1
33333333
0100
33333333
1ere the answer is )3'*
10
)or* in 0>s complement it is 1100;
Q.4 What is the ?ray equivalent of (0$)
10
; (2)
Ans:
?ray equivalent of )0$*
10
The binary equivalent of Decimal number 0$ is )00100101*
0
1; The left most bit )9A,* in gray code is the same as the left most in binary
0; Add the left most bit to the adQacent bit
; Add the ne#t adQacent pair and so on;, Discard if we get a carry;
0 - 0 - 1 - 0 - 0 - 1 - 0 - 1
0 0 1 1 0 1 1 1 ?ray Number
Q.5 5valuate # + A., + ((A.D) using the convention A + True and , + 2alse; (4)
Ans:
5valuate # + A ;, - C (A;D)
+ A , - ( ) A - D *
)Aince
+ A ., - ( . A - (. D
A;D + A - D by using Demorgan>s @aw*
,y using the given convention, A + True + 1R , + 2alse + 0
+1.0 - (;1- (; D + 0 - 0 - (; D + (; D
Q.6 Aimplify the ,oolean e#pression 2 + (), - (*)A - , - (*; (6)
Ans:
Aimplify the ,oolean 5#pression 2 + ( ), -(* )A-,-(*
2 + ( ),-(* )A-,-(*
+ (, - (( M)A-,-(*N
+ (, - ( M)A-,-(*N )G (( + (*
+ (,A - (,, - (,( - (A - (, - ((
+ A,( - (, - (, - (A - (, - (( )G (,, +(, O (,( + (,*
+ A,( - (, - (A - ( )G (,-(,-(, + (,R (( + (*
+ A,( - ,( - ( )1-A*
+ A,( - ,( - ( )G 1-A + 1*
+ A,( - ( )1-,*
00
D E ! D I % IT A L S ELE C T & O N I CS
+ A,( - ( )G 1-, + 1*
+ ( )1-A,* + ( SG )1-A,*+1T
Q.7 Aimplify the following e#pression into sum of products using Farnaugh map
2)A, ,, (, D* =
I
)1,,',$,!,%,&,10,1*
(7)
Ans:
Aimplification of the following e#pression into sum of products using Farnaugh
9apH
2)A,,,(,D* + )1,,',$,!,%,&,10,1*
Farnaugh 9ap for the e#pression 2)A,,,(,D* + )1,,',$,!,%,&,10,1*
is shown in 2ig;')a*; The grouping of cells is also shown in the 2igure;
The equations for )1* is A ,R )0* is C DR )* is A DR )'* is , C
1ence, the Aimplified 5#pression for the above Farnaugh map is
2)A,,,(,D* + A ,- C D- A D-, C
+ A ), - D* - C ) , - D*
Q.8 Aimplify and draw the logic diagram for the given e#pression
2 = A,( + A,( + A,( + A,( + A,( ; (7)
Ans:
Aimplification of the logic e#pression
2 + ABC - AB ( - A , C - A BC - A B
( 2 + ABC - AB ( - A , C - A BC - A
B (
0
D E ! D I % IT A L S ELE C T & O N I CS
2 + A - B - C - ) A - B *( - A , C - A ) B - C * - A B
(
)G ABC + A - B - C and AB + A - B by using Demorgan>s @aw*
+ A - B - C - A ( - B ( - A , C - A B - A C - A B (
+ A - A (- B - B ( - C - A C - A , C -A B - A B (
+ A )1-(*- B )1 - (* - C )1 - A* - A , C - A B - A B (
+ A - B - C - A , C - A B - A B ( SG )1-(* + 1 and )1-A* + 1T
+ ) A - A B * - B )1 - A(* - C )1- A ,*
+ ) A - B *- B - C SG ) A - A B * + ) A - B *R )1-A(* + 1 and )1- A ,*
+1T 2 + ) A - B - C * )G B - B + B *
The logic diagram for the simplified e#pression 2 + ) A - B - C * is given in fig;$)a*
_
A
A
_
B
_ _ _
B F = A + B +
C
_
C
C
6,7.5(0) L#7,. 8,07$03 -#$ /9+ +:;$+ss,#n 6 = ( A + B + C )
Q. Determine the binary numbers represented by the following decimal numbers; (6)
)i* 0$;$ )ii* 10;!0$ )iiii* 0;!"%$
Ans:
(,) C#n*+$s,#n #- 8+.,301 n234+$ 25.5 ,n/# 4,n0$5 n234+$:
1ere integer part is 0$ and fractional part is 0;$; 2irst convert the integer part 0$ into its
equivalent binary number i;e;, divide 0$ by 0 till the quotient becomes 0 shown in table
0)a*
Guotient 7emainder
0$
0
10 1
10
0
! 0
!
0
0

0
1 1
1
0
0 1
T041+ 2(0)
0'
D E ! D I % IT A L S ELE C T & O N I CS
Ao, integer part )0$*
10
is equivalent to the binary number 11001; Ne#t convert
fractional part 0;$ into binary form i;e;, multiply the fractional part 0;$ by 0 till you get
remainder as 0
0;$
. 0
333333
1;0 7emainder
1 )Guotient*
The decimal fractional part 0;$ is equivalent to binary number 0;1; 1ence, the
decimal number 0$;$ is equal to the binary number 11001;1
(,,) C#n*+$s,#n #- 8+.,301 n234+$ 1!.625 ,n/# 4,n0$5 n234+$:
1ere integer part is 10 and fractional part is 0;!0$; 2irst convert the decimal number 10
into its equivalent binary number i;e;, divide 10 by 0 till the quotient becomes 0
shown in table 0)b*
Guotient 7emainder
10
0
$ 0
$
0
0 1
0
0
1 0
1
0
0 1
T041+ 2(4)
Ao, the integer part 10 is equal to binary number 1010; Ne#t convert the decimal
fractional part 0;!0$ into its binary form i;e;, multiply 0;!0$ by 0 till the
remainder becomes 0
0;!0$ 0;0$0 0;$0
. 0 . 0 . 0
3333333 33333333 3333333
1;0$0 0;$0 1;0 )7emainder*
1 0 1 )Guotient*
Ao, the decimal fractional part 0;!0$ is equal to binary number 0;101; 1ence the
decimal number 1!.625 is equal to binary number 1!1!.1!1;
(,,,)C#n*+$s,#n #- -$0./,#n01 n234+$ !.6875 ,n/# ,/s +<2,*01+n/ 4,n0$5 n234+$:
9ultiply the fractional number 0;!"%$ by 0 till the remainder becomes 0 i;e;,
0$
D E ! D I % IT A L S ELE C T & O N I CS
0;!"%$ 0;%$0 0;%$ 0;$
. 0 . 0 . 0 . 0
=========== ========= ======== ======
1;%$0 0;%$ 1;$ 1;0 )7emainder*
1 0 1 1 )Guotient*
Ao, the decimal fractional number !.6875 is equal to binary number !.1!11;
Q.1! 6erform the following subtractions using 0>s complement method; (8)
)i* 01000 / 01001 )ii* 01100 / 00011 )iii* 0011;1001 / 0001;1110
Ans:
(,) S24/$0./,#n #- !1!!!=!1!!1: 1>s complement of 01001 is 10110 and 0>s
complement is
10110- 1 +10111; 1ence
01000 + 01000
3 01001 + -10111 )0Ks complement*
3333333333333333333333333
11111 )Aummation*
3333333333333333333333333
Aince the 9A, of the sum is 1, which means the result is negative and it is in 0Ks
complement form; Ao, 0Ks complement of 1111 +00001+ )1*
10;
Therefore, the result is / 1;
(,,) S24/$0./,#n #- !11!!=!!!11: 1>s complement of 00011 is 11100 and 0>s complement
is 11100 - 1 + 11101; 1ence
01100 + 01100
/ 00011 + - 11101 )0Ks complement*
33333333333333333333333333333333333333333333333333
1 01001 + - &
<gnore
33333333333333333333333333333333333333333333333333
<f a final carry is generated discard the carry and the answer is given by the remaining bits
Which is positive i;e;, )1001*
0
+ )- &*
10
(,,,) S24/$0./,#n #- !!11.1!!1 ( !!!1.111!: 1>s complement of 0001;1110 is 1110;0001
and its 0>s complement is 1110;0010;
0011;1001 + 0011;1001
3 0001;1110 + - 1110;1011 )0>s complement*
3333333333333333333333333333333333333333333
1 0001;101< + - 1 ;!"!0$
<gnore
0!
D E ! D I % IT A L S ELE C T & O N I CS
<f a final carry is generated discard the carry and the answer is given by the
remaining bits which is positive i;e;, )0001;1011*
0
+ )- 1;!"!0$*
10
Q.11 Aimplify the e#pressions using ,oolean postulates ()
(,)
X Y + XYZ + X )Y + X
Y *
(,,) J + )A - ,*) A - (*), - (*
(,,,) .J - XZ - . Y U ).J - U*
Ans:
(,)
X Y + XYZ + X )Y + X Y *
+ X Y + XYZ + X )Y + X Y *
+ X )Y + YZ * + X )Y + X Y *
= X )Y + Z * + X )Y + X *
),ecause Y +
YZ
+ Y + Z and Y + X
Y
+ Y + X *
+ X Y + XZ + XY +
XX
+ X Y + XZ + XY +
X
),ecause ..+.*
+ X Y + XZ + X )1 + Y *
= X Y + XZ + X ),ecause )1-J+1*
= ) X + Y *) X + Z * +
X
(,ecause XY = X - Y *
= X X + X Z + Y X + Y Z +
X
= X + X Z + Y X + Y Z +
X
= X )1 + Z + Y * + Y Z + X
= X + Y Z + X
= ) X + X * + Y Z
),ecause X X + X *
= 1 + Y Z
),ecause
X + X
+ 1*
=1 = 0 ),ecause 1 + Y Z +1*
(,,) J + )A - ,*) A - (*), - (*
J + )A - ,*) A - (*), - (*
+ )A A - A( - , A - ,(* ), - (*
+ )A( - , A - ,(* ), - (* ),ecause A A + 0*
+ A,( - ,, A - ,,( - A(( - , A ( - ,((
+ A,( - , A - ,( - A( - , A ( - ,( ),ecause ,, + ,*
+ A,( - A( - , A - , A (
- ,( ),ecause ,( - ,( + ,(*
+A( ),-1* - , A - ,( ) A -1*
+ A( - , A - ,( ),ecause , - 1 + 1 and A - 1 + 1*
+ A( - , A - ,( )A - A * ),ecause A - A + 1*
+ A( - , A - ,(A - ,( A
+ A()1 - ,* - , A )1 - (*
0%
D E ! D I % IT A L S ELE C T & O N I CS
+ A( - , A S,ecause )1 - ,* + 1 and )1 - (* +1T
(,,,) .J - XZ - . Y U ).J - U*
= .J - XZ - . Y U ).J - U*
+ .J - XZ - ..J Y U - . Y U U
+ .J - XZ - . Y U ),ecause J Y + 0 O UU + U*
+ .J - X - Z - . Y U ),ecause XZ + X - Z *
+ X - .J - Z - . Y U
= X - . )J - Y U* - Z
= X - . )J -U* - Z ),ecause J - Y U + J -U*
= X - . J )U- Z * - .U - Z ),ecause U- Z +1*
= X - . J U - .J Z - .U - Z
= X - .U )1- J* - Z )1-.J*
+ X - .U - Z ),ecause 1- J + 1 O1-.J + 1*
+ X - .U* - Z
+) X - U* - Z ),ecause X - .U + X - U
+ X -) U - Z *
+ X -1 ),ecause U - Z + 1*
+1 ),ecause X -1 + 1*
Q.12 9inimiDe the logic function J(A" ," (" D) = I
m(0"1"0""$"%"""&"11"1') ; :se Farnaugh map;
Draw logic circuit for the simplified function; ()
Ans:
2ig; ')a* shows the Farnaugh map; Aince the e#pression has ' variables, the
map
has 1! cells; The digit 1 has been written in the cells having a term in the given
e#pression; The decimal number has been added as subscript to indicate the
binary number for the concerned cell; The term ABC D cannot be combined with
any other
cell; Ao this term will appear as such in the final e#pression; There are four
groupings of ' cells each; These correspond to the min terms )0, 1, 0, *, )0, 1, ", &*,
)1, ,$,%* and )1, , &, 11*; These are shown in the map; Aince all the terms )e#cept
1'* have been included in groups of ' cells, there is no need to form groups of two
cells;
0"
D E ! D I % IT A L S ELE C T & O N I CS
The simplified e#pression is Y )A,B,(,D) + ABC D - A B - B C - B D- A
D 2ig;' )b* shows the logic diagram for the simplified e#pression
Y )A,B, (, D) + ABC D - A B - B C - B D- A D
A
B C D
_
A B C
D
_ _
A B
_
A D
Y
_ _
B C
_
B D
6,7.4(4) L#7,. 8,07$03 -#$ >
Q.13 Aimplify the given e#pression to its Aum of 6roducts )A86* form; Draw the logic circuit
for the simplified A86 function J = (A + ,)(A + A,)( + A(, + ()+ A, +
A,(
(5)
Ans:
Aimplification of given e#pression
J + )A - ,* )A - AB * ( - A ), - C * - A , - A,(
in some of products )A86* formH3
0&
D E ! D I % IT A L S ELE C T & O N I CS
J + )A - ,* )A - AB * ( - A ), - C * - A , - A,(
+)A - ,* )A - AB * ( - A ), - C * - A , - A,(
+)A - ,* )A - A - B *( - A ), - C * - A , - A,(
+)A - ,* )1- B *( - A ), - C * - A , - A,( ),ecause A - A + 1*
+ )A - ,* )(- B (* - A , - A C - A , - A,(
+ )A - ,* )(- B (* - A , - A C - A , - A,(
+A( - A B ( - ,( - , B ( - A , - A C - A , - A,(
+ A( - A() B - ,* - ,( - 0 - A , - A C - A , ),ecause , B + 0*
+ A( - A(- ,(- A , - A C ),ecause B - , + 1*
+ A(- ,(- A , - A C ),ecause A( - A( + A(*
+ ( )A- ,* - A ), - C *
A
B
C
C
A + B
C (A + B)
Y
_
A
_ _
A(B + C )
B
_
B + C
_
C
6,7.4(.) S,3;1,-,+8 L#7,. C,$.2,/
Q.14 Design a " to 1 multiple#er by using the four variable function given by
2(A" ," (" D) = I
m(0"1""'"""&"1$) ; (1!)
Ans:
D + s, 7n #- 8 /# 1 ) 21 /,;1 + : +$: This is a four3variable function and therefore we need a
multiple#er with three selection lines and eight inputs; We choose to apply variables B,
(, and D to the selection lines; This is shown inTable ";1; The first half of the minterms
are associated with A' and the second half with A. ,y circling the minterms of the function
and applying the rules for finding values for the multiple#er inputs, the implementation
shown in Table;";0;
The given function can be implemented with a "3to31 multiple#er as shown in fig;")a*;
Three of the variables, ,, ( and D are applied to the selection lines in that order i;e;, , is
connected to s
0
, ( to s1 and D to s
0
; The inputs of the multiple#er are 0, 1, A and A>;
When ,(D + 000,001 O 111 output 2 + 1 since <
0
O <
"
+ 1 for ,(D)000*, <
1
+ 1and <
&
+1 respectively; Therefore, minterms m
0
+ A> ,> (> m
1
+ A> ,> (, m
"
+ A>, ,>, (> and
m
&
+ A> ,> ( produce a 1 output; When ,(D + 010, 101 and 110, output 2 + 0, since <
0
, <
$
and <
!
respectively are equal to
0;
0
D E ! D I % IT A L S ELE C T & O N I CS
),n/+$3 A B C D 6
0 0 0 0 0 1
1 0 0 0 1 1
0 0 0 1 0 0
0 0 1 1 1
' 0 1 0 0 1
$ 0 1 0 1 0
! 0 1 1 0 0
% 0 1 1 1 0
" 1 0 0 0 1
& 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
10 1 1 0 0 0
1 1 1 0 1 0
1' 1 1 1 0 0
1$ 1 1 1 1 1
T041+ .8.1 T$2/9 T041+ -#$ 8=1 )21/,;1+:+$
T041+ 8.2 I3;1+3+n/0/,#n T041+ -#$ 8 /# 1 )U?
1
D E ! D I % IT A L S ELE C T & O N I CS
1
I
0
I
1
0
I
2
I
3
8 X 1
Y

F
MUX
I
4
I
5
I
6
S
S S
A
I
7
2 1
0
B
C
D
6,7.8(0) L#7,. .,$.2,/ -#$ 8=/#=1 )21/,;1+:+$
Q.15 (onvert the decimal number "0;!% to its binary, he#adecimal and octal equivalents; (6)
Ans:
(,)C#n*+$s,#n #- D+.,301 n234+$ 82.67 /# ,/s B,n0$5 E<2,*01+n/
(onsidering the integer part "0 and finding its binary equivalent
0 "0
0 '1 7emainder 33333 0 )@A,*
0 00 7emainder 33333 1
0 10 7emainder 33333 0
0 $ 7emainder 3333330
0 0 7emainder 33333 1
0 1 7emainder 3333 0
0 7emainder 3333 1 )9A,*
The ,inary equivalent is )1010010*
0
0
D E ! D I % IT A L S ELE C T & O N I CS
Now taCing the fractional part i;e;, 0;!%
2raction 2raction . 0 7emainder
New
2raction
<nteger
0;!% 1;' 0;' 1
0;' 0;!" 0;!" 0
0;!" 1;! 0;! 1
0;! 0;%0 0;%0 0
0;%0 1;'' 0;'' 1
0;'' 0;"" 0;"" 0
0;"" 1;%! 0;%! 1
0;%! 1;$0 0;$0 1
<t is seen that, it is not possible to get a Dero as remainder even after " stages; The
process continued further on an appro#imation can be made and the process is terminated
here;
The binary equivalent is 0;10101011
Therefore, the binary equivalent of decimal number 82.67 ,s (1!1!!1!.1!1!1!11)
2
(,,)C#n*+$s,#n #- /9+ 4,n0$5 +<2,*01+n/ #- 8+.,301 n234+$ 82.67 ,n/# @+:08+.,301:
The binary equivalent of decimal number "0;!% is )1010010;10101011*
0
(onvert each '3bit binary into an equivalent he#adecimal number i;e;
0101 0010 ;1010 1011
$ 0 A ,
Therefore, the he#adecimal equivalent of decimal number 82.67 ,s (52.AB)
16
(,,,)C#n*+$s,#,n #- /9+ 4,n0$5 +<2,*01+n/ #- 8+.,301 n234+$ 82.67 ,n/# O./01 n234+$:
The binary equivalent of decimal number "0;!% is )1010010;10101011*
0
(onvert each 3bit binary into an equivalent octal number i;e;
001 010 010 ;101 010 110
1 0 0 ; $ 0 !
T9+$+-#$+" /9+ O./01 +<2,*01+n/ #- 8+.,301 n234+$ 82.67 ,s (122.526)
8
Q.16 Add 00 and )31$* using 0>s complement; (4)

0 1!
0 " 7emainder 33333 0 )@A,*
0 ' 7emainder 33333 0
0 0 7emainder 33333 0
0 1 7emainder 3333330
0 7emainder 33333 1)9A,*
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
A88,/,#n #- 2! 0n8 (=15) 2s,n7 2As C#3;1+3+n/:
0 00
0 10 7emainder 33333 0 )@A,*
0 $ 7emainder 33333 0
0 0 7emainder 33333 1
0 1 7emainder 3333330
0 7emainder 33333 1)9A,*
)00*
10
+ 1 0 1 0 0 )1!*
10
+ 1 0 0 0 0
)31!*
10
+ 0 1 1 1 1)1>s (omplement*
-1)0>s (omplement*
333333333333333333333
1 0 0 0 0
333333333333333333333
Therefore, 00 + 1 0 1 0 0
31! + 1 0 0 0 0
33333333333333333333333333333
1 0 0 1 0 0
)Neglect*
33333333333333333333333333333333
Aince the 9A, of the sum is 0, which means /9+ $+s21/ ,s ;#s,/,*+ ,.+ +4
Q.17 Add !'" and '"% in ,(D code; (4)
Ans:
A88,/,#n #- 648 0n8 487 ,n BCD C#8+:
! ' " + 0 1 1 0 0 1 0 0 1 0 0 0
' " % + 0 1 0 0 1 0 0 0 0 1 1 1
33333333333333333333333333333333333333333333333333
1 0 1 0 1 1 0 0 1 1 1 1
10 10 1$
33333333333333333333333333333333333333333333333333
<n the above problem all the three groups are invalid, because the four bit sum is more than
&; <n such cases, add -!)i;e; 0110* to the four bit sum to sCip the si# invalid states; <f a
carry is generated when adding !, add the carry to the ne#t four bit group i;e;
'
D E ! D I % IT A L S ELE C T & O N I CS
! ' " + 0 1 1 0 0 1 0 0 1 0 0 0
' " % + 0 1 0 0 1 0 0 0 0 1 1 1
33333333333333333333333333333333333333333333333333
1 0 1 0 1 1 0 0 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1 0
1 1 1 1 1 1 1 1
333333333333333333333333333333333333333333333333333333
0001 0 0 0 1 0 0 1 1 0 1 0 1
1 1 $
3333333333333333333333333333333333333333333333333333333
A88,/,#n #- 648 0n8 487 ,n BCD C#8+ ,s 1135.
Q.18 6rove the following ,oolean identities; (4)
)i* .J - JU - Y U + .J - U
)ii* A., + A., + A., = A +
,
Ans:
(,) '$#*+ /9+ B##1+0n I8+n/,/5 .J - JU - Y U + .J - U
L.@.S + .J - JU - Y U
+ .J)U- Z * - JU + Y U )
G
U - Z + 1*
= .JU - .J Z - JU + Y U
= JU)1-.* - .J Z - Y U
= JU - .J
Z
- Y U )G 1-. + 1*
+ U )J-
Y
* - .J Z
+ U - .J Z )G J- Y +1*
+ U - .J)G U - .J
Z
+ U - .J*
+ &.@.S (@+n.+ '$#*+8)
(,,) '$#*+ /9+ B##1+0n I8+n/,/5 A , - A , - A B + A - ,
&.@.S + A - ,
= A ), - B * - , )A - A * )
G
, - B + 1 O A - A + 1*
+ A ), - B * - , )A - A *
+ A , -
A B
- , A - , A
+ A , - A B
- , A ) A , - A , + A ,*
+ L.@.S (@+n.+ '$#*+8)
Q.1 2or
2 = A.,.( + ,.(.D + A.,.( , write the truth table; Aimplify using Farnaugh map
and
realiDe the function using NAND gates only; (1!)
Ans:
S,3;1,-,.0/,#n #- L#7,. 62n./,#n 2 + A , ( - , C D - A , (
$
D E ! D I % IT A L S ELE C T & O N I CS
(,)T9+ T$2/9 T041+ ,s 7,*+n ,n T041+ 4.1
<nputs
A , ( D
8utput
)2*
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
T041+ 4.1
(,,) T9+ B0$n0279 )0; ,s s9#Cn ,n -,7.4(0).
The simplified e#pression is 2 + ,( - ,D
(,,,) T9+ NAND=NAND &+01,D0/,#n ,s s9#Cn ,n -,7.4(4)
!
1 ' 0

0
D E ! D I % IT A L S ELE C T & O N I CS
B
BC
C
B
BD
D
_
_ _
F = BC . BD = BC + BD
6,7. 4(4) NAND=NAND &+01,D0/,#n
Q.2! Determine the analog output voltage of !3bit DA( )7307 ladder networC* with V
ref
as $V when
the digital input is 011100; (1!)
Ans:
2or !3bit 7307 DA( ladder networC, the output voltage is given by
V
R
(
n 1 n0 1 0
) V
0
=
n
0
a
n1
0 + a
n 0
0 + +a
1
0
+ a
0
0
?iven Data H V
7
+ $V, n + !, a
$
+0, a
'
+1,a

+1,a
0
+1,a
1
+0,a
0
+0
V
0
= $
(a 0
0
!
$
$
(
$
+ a 0
$
'
+ a 0
'

+ a 0

0
+ a 0
0
1
+ a 0
0
)
1 0
) V
0
=
!
0
0 0 + 1
0
+ 1
0
+ 1
0
+ 0
0
+ 0 0
V = $
0"
0
!'
+ 2.1875 V
Q.21 Aolve the following equations for . (6)
)i* 0.!
10
= .
0
)ii* !$;$$
10
+ .
1!
Ans:
(,) S#1*+ /9+ +<20/,#n 23.6
1!
= ?
2
-#$ ?
0;!
10
+ .
0
<n order to find ., convert the Decimal number 0;!
10
into its ,inary form;
2irst taCe the decimal integer part 0 to convert into its equivalent binary form
0 0
0 11 3333333 1
0 $ 333333331
0 0 333333331
0 1 333333330
0 333333331
1ence 0
10
+ 10111
0
Ne#t taCe the decimal fractional part 0;! to convert into its equivalent binary form;
%
D E ! D I % IT A L S ELE C T & O N I CS
2raction 2raction . 0 7emainder new
fraction
<nteger
0;! 1;0 0;0 1
0;0 0;' 0;' 0
0;' 0;" 0;" 0
0;" 1;! 0;! 1
0;! 1;0 0;0 1
0;0 0;' 0;' 0
0;' 0;" 0;" 0
<t is seen that it is not possible to get a Dero as remainder even after % stages; The
process can be continued further or an appro#imation can be made and the process
terminated here; The binary equivalent is 0;1001100;
1ence 23.6
1!
= 1!111.1!!11!!
2.
(,,) <n order to find ., convert the Decimal number !$;$$ into its equivalent 1e#adecimal
form; 2irst taCing the integer part !$ to convert into its equivalent 1e#adecimal form;
1! !$
1! ' 3333 1
0 3333 '
1ence !$
10
+ '1
1!
Ne#t taCe the decimal fractional part 0;! to convert into its equivalent binary form;
2raction 2raction . 1! 7emainder new
fraction
<nteger
0;$$ ";$! 0;$! "
0;$! ";&! 0;&! "
0;&! 1$;! 0;! 1$ )2*
0;! $;%! 0;%! $
0;%! 10;1! 0;1! 10)(*
0;1! 0;$! 0;$! 0
0;$! ";&! 0;&! "
<t is seen that it is not possible to get a Dero as remainder even after % stages; The
process can be continued further or an appro#imation can be made and the process
terminated here; The 1e#adecimal equivalent is 0;""2$(0";
1ence 65.535
1!
= 41.8865C28
16.
Q.22 6erform the following additions using 0>s complement (5)
)i* 300 to -0! )ii* -0$ to 31$
Ans:
"
D E ! D I % IT A L S ELE C T & O N I CS
(,) 2irst convert the two numbers 00 and 0! into its "3bit binary equivalent and find out the
0>s complement of 00, then add 300 to -0!;
00 + 0 0 0 1 0 1 0 0 )"3bit binary equivalent of 00*
00 + 1 1 1 0 1 0 1 1 )1>s complement*
-1
3333333333333333333333333333333
00 + 300 + 1 1 1 0 1 1 0 0 )0>s complement of 00*
-0! + 0 0 0 1 1 0 1 0 )"3bit binary equivalent of 0!*
33333333333333333333333333333
Addition of 300 to -0!
+ -! + 0 0 0 0 0 1 1 0
33333333333333333333333333333
1ence 300 to -0! + )!*
10
+ )0110*
0;
(,,) 2irst convert the two numbers 0$ and 1$ into its "3bit binary equivalent and find
out the 0>s complement of 1$, then add -0$ to 31$;
1$ + 0 0 0 0 1 1 1 1 )"3bit binary equivalent of 1$*
1$ + 1 1 1 1 0 0 0 0 )1>s complement*
-1
333333333333333333333333333333
1$ + 31$ + 1 1 1 1 0 0 0 1 )0>s complement of 1$*
-0$ + 0 0 0 1 1 0 0 1 )"3bit binary equivalent of 0$*
333333333333333333333333333333
Addition of 31$ to -0$
+ -10 + 0 0 0 0 1 0 1 0
3333333333333333333333333333333
1ence 31$ to -0$ + )10*
10
+ )1010*
0;
Q.23 )i* (onvert the decimal number '0 to 5#cess3 codeH (6)
)ii* (onvert the binary number 10110 to ?ray codeH
Ans:
(,) 5#cess is a digital code obtained by adding to each decimal digit and then
converting the result to four bit binary; <t is an unweighted code i;e;, no weights can
be assigned to any of the four digit positions;
' 0
- - -
33333333333333333333333333333
% !
0111 0110 0011 )5#cess3 (ode*
33333333333333333333333333333333
(,,) The rules for changing binary number 10110 into its equivalent ?ray code are, the
left most bit )9A,* in ?ray code i;e;, 1 is the same as the left most bit in binary
and
&
A , (
A;)B;C * ) A;B*;C
0 0 0 1 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 1
1 1 1 1 1
D E ! D I % IT A L S ELE C T & O N I CS
add the left most bit )1* to the adQacent bit )0* then add the ne#t adQacent pair and
discard the carry; (ontinue this process till completion;
- - - -
1 ! 1 1 !
1 1 1 ! 1
1ence ?ray equivalent of ,inary number 10110 is 11101;
Q.24 Verify that the following operations are commutative but not associative (6)
)i* NAND )ii* N87
Ans:
(,) (ommutative @aw is AB + BA ; To verify whether the NAND operation is
(ommutative or not, prepare truth table shown in Table No;;1
A ,
AB BA
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
T041+ N#.3.1
2rom the Table No;;1, we observe that the last two columns are identical, which means
AB + BA
Associative @aw is A;)B;C
*
= ) A;B*;C
To verify whether the NAND operation is Associative or not, prepare truth table shown in
Table No;;0
T041+ N#.3.2
2rom the Table No;;0, we observe that the last two columns are not identical, which means
A;)B;C * W ) A;B*;C
'0
D E ! D I % IT A L S ELE C T & O N I CS
(,,) (ommutative @aw is
A + B + B + A ; To verify whether the N87 operation is
(ommutative or not, prepare truth table shown in Table No;;
A ,
A + B B + A
0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 1
T041+ N#.3.3
2rom the Table No;;, we observe that the last two columns are identical, which means
A + B + B + A
Associative @aw is
A + )B + C * = ) A + B* + C
To verify whether the N87 operation is Associative or not, prepare truth table shown in
Table No;;'
A , (
A + )B + C * ) A + B* + C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 1
1 1 1 0 0
T041+ N#.3.4
2rom the Table No;;', we observe that the last two columns are not identical, which means
A;+ )B + C * W ) A + B* + C
Q.25 6rove the following equations using the ,oolean algebraic theoremsH (5)
)i* A - A ;, - A ; B + A - , )ii* A ,( - A B ( - A, C - A,( + A, - ,( - A(
Ans:
(,) ?iven equation is A - A ;, - A; B + A - ,
L.@.S; + A - A ;, - A; B
+ )A - A; B * - A ;,
= A )1- B * - A ;,
= A - A ;, )G 1- B +1*
= )A - A * )A - ,*
= )A - ,* )G A - A + 1*
+ &.@.S
@+n.+ '$#*+8
'1
D E ! D I % IT A L S ELE C T & O N I CS
(,,) ?iven equation is A ,( - A B ( - A, C - A,( + A, - ,( - A(
L.@.S = A ,( - A B ( - A, C - A,(
+ A ,( - A B ( - A, C - A,(
= A ,( - A B ( - A, )( - C *
= A ,( - A B ( - A, )G ( - C + 1*
= A ,( - A ), - B (*
+ A ,( - A ), - (* )G , - B ( + , - (*
+ A ,( - A , - A(
+ ( )A - A ,* - A , - A(
+ ( )A - ,* - A , - A( )G A - A , + A - ,*
+ A( - ,( - A, - A(
+ A, - ,( - A( )G A( - A( + A(*
+ &.@.S
@+n.+ '$#*+8
Q.26 A staircase light is controlled by two switches one at the top of the stairs and another at the
bottom of stairs (5)
)i* 9aCe a truth table for this system;
)ii* Write the logic equation is A86 form;
)iii* 7ealiDe the circuit using AND387 gates;
Ans:
A staircase light is controlled by two switches A
1
and A
0
, one at the top of the stairs and
another at the bottom of the stairs; The circuit diagram of the system is shown in fig;')a*;
1 0
0
1
S
S
1
SU PPLY
L
BU LB
2
ON = 1
OFF = 0
6,7.4(0) C,$.2,/ 8,07$03
(,) The truth table for the system is given in truth table ';1
A
1
A
0
@
0 0 0
0 1 1
1 0 1
1 1 0
T041+ 4.1
(,,) The logic equation for the system is given by @ + S
1
A
0
- A
1
S
0
'0
D E ! D I % IT A L S ELE C T & O N I CS
(,,,) 7ealiDation of the circuit using AND387 gates is shown in fig ')b*
_
S . S
S
1
2
1
S
2
L
_
S . S
1
2
6,7.4(4) L#7,. D,07$03 -#$ /9+ s5s/+3
Q.27 9inimiDe the following logic function using F3maps and realiDe using NAND and N87 gates;
2(A" ," (" D) =
I
m(1""$"""&"11"1$) +
d(0"1)
()
Ans:
9inimiDation of the logic function 2)A, ,, (, D* + I m)1,,$,",&,11;1$* - d)0,1* using F3
maps and 7ealiDation using NAND and N87 ?ates
(,) B0$n0279 )0; -#$ /9+ 1#7,. -2n./,#n ,s 7,*+n ,n /041+ 4.1
The minimiDed logic e#pression in A86 form is 2 + A B C - C D - B D - AD
The minimiDed logic e#pression in 68A form is 2 + )A - B - C * ) C -D* ) B -D* )A-D*
(,,) &+01,D0/,#n #- /9+ +:;$+ss,#n 2s,n7 NAND 70/+s:
The minimiDed logic e#pression in A86 form is 2 + A B C - C D - B D - AD and
the logic diagram for the simplified e#pression is given in fig;')c*
'
D E ! D I % IT A L S ELE C T & O N I CS
A B
C D
_
A + B + C
_
C + D
F
_
B + D
_ _
A + D
6,7.4(.) L#7,. D,07$03
(,,,) &+01,D0/,#n #- /9+ +:;$+ss,#n 2s,n7 NO& 70/+s:
The minimiDed logic e#pression in 68A form is 2 + )A - B - C * ) C -D* ) B -D*
)A-D*
and the logic diagram for the simplified e#pression is given in fig;')d*
A B C D
_
_ _
A + B + C
_
C + D
_
F
_
B + D
A + D
6,7.4(8) L#7,. D,07$03
Q.28 Design a ' to 1 9ultiple#er by using the three variable function given by
2(A" ," () = I
m(1""$"!)
Ans:
D+s,7n #- 4 /# 1 )21/,;1+:+$ 45 2s,n7 /9+ /9$++ *0$,041+ -2n./,#n 7,*+n 45
6(A"B"C) = I 3(1"3"5"6)
(7)
The function 6(A"B"C) = I 3(1"3"5"6) can be implemented with a '3to31 multiple#er as
shown in 2ig;%)a*; Two of the variables, , and ( are applied to the selection lines in
that order, i;e;, B is connected to A
1
and ( to S
0
. The inputs of the multiple#er are 0, <, A,
and A'. When BC + 00, output F + 0 since I
0
+ 0; Therefore, both minterms m
0
+ A' B' (K
and
m4 + A B' (K produce a 0 output, since the output is 0 when BC + 00 regardless of the value
of A.
When BC + 01, output F + 1, since I
1
+ 1; Therefore, both minterms m
1
+AK B'C
and
''
D E ! D I % IT A L S ELE C T & O N I CS
m
5
+ AB'C produce a 1 output, since the output is 1; when BC + 01 regardless of the
value of A.
When BC + 10, input I
2
is selected; Aince A is connected to this input, the output will
be equal to 1 only for minterm m
6
+ ABC', but not for minterm m
2
+ A' BC', because when
A' + <, then A + 0, and since I
2
+ 0, we have F + 0;
2inally, when BC + 11, input I
3
is selected; Aince A' is connected to this input, the output
will be equal to 1 only for minterm m
3
+ A' BC, but not for m
7
+ ABC. This is given in the
Truth Table shown in Table No %;1
9interm A , ( 2
0 0 0 0 0
1 0 0 1 1
0 0 1 0 0
0 1 1 1
' 1 0 0 0
$ 1 0 1 1
! 1 1 0 1
% 1 1 1 0
T041+ 7.1 T$2/9 T041+
6,7.7(0) I3;1+3+n/0/,#n T041+
'$
D E ! D I % IT A L S ELE C T & O N I CS
0
I
0
1 I
1
4 1
MUX
Y F
A
I
2
A! I
3
S
1
S
0
B
C
6,7.7(4) L#7,. D,07$03 #- 4?1 )21/,;1+:+$
Q.2 2ind the conversion time of a Auccessive Appro#imation ABD converter which uses a 0 91D
clocC and a $3bit binary ladder containing "V reference; What is the (onversion 7ate4
Ans:
%,*+n 80/0:
2requency of the clocC )2* + 0 91U
Number of bits )n* + $
(4)
)i* (onversion Time )T* +
n
+
cloc!a"#
$
0 X 10
!
+ 0;$
sec
)ii* (onversion 7ate +
1
+
$
1
0;$ X 10
!
+ '00,000 conversionsBsec
Q.3! A !3bit 7307 ladder DBA converter has a reference voltage of !;$V; <t meets standard linearity;
2ind
)i* The 7esolution in 6ercent;
)ii* The output voltage for the word 011100; (4)
Ans:
?iven Data Number of ,its )n* + !
7eference Voltage )V
7
* + !;$ V
2or 7307 @adder DBA (onverter,
)i*The 7esolution in 6ercent is given by
1
=
0
n
1
1
=
0
!
1
1
= 1;$& X
!
)ii*The 8utput Voltage )V
8
* of !3bit 7307 @adder DBA (onverter for the word 011100 is
given by
V
R
[
n 1 n 0 1 0
] V
%
=
n
0
a
n1
;0 + a
n 0
;0 + +a
1
0
+ a
0
0
'!
%
D E ! D I % IT A L S ELE C T & O N I CS
V =
!;$
[
0;0
!1
+ 1X 0
$1
+ 1X 0
'1
+ 1X 0
1
+ 0 X 0
01
+ 0 X 0
0
]
%
0
!
V =
!;$
[0
'
+ 0

+ 0
0
]
0
!
V
%
= 0;"' V;
Q.31 (onvert 0000 in 1e#adecimal number; (4)
Ans:
0000
1! 1" 1'
1! " 10 +"A5
0 "
Q.32 Aubtract /0% from !" using 0>s complements; (6)
Ans:
!"3)30%*+!"3)30%*using 0>s complement
0>s complement representation of !"+01000100)!'-'*
0>s complement representation of 3 )30%* + 00011011 +- 0%
11100101 +30% in 0>s complement
Now add !" and 0%
!" 0 1 0 0 0 1 0 0
3)30%* - 0 0 0 1 1 0 1 1
&$ 0 1 0 1 1 1 1 1 1
Which is equal to -&$
Q.33 Divide (101110)
0
by (101)
0
; (4)
Ans:
1 0 1 1 0 1 1 1 0 1 0 0 1
1 0 1
0 0 0 1 1 0
1 0 1
0 0 1
Guotient 31001
7emainder 3001
Q.34 6rove the following identities using ,oolean algebraH
)i* (A + ,)(A + A,)( + A(, + ()+ A, + A,( = ((A + ,) + A(, + ();
)ii*
A(A ,) ,(A ,) = A , ;
'%
D E ! D I % IT A L S ELE C T & O N I CS
)iii*
A, + A + A, = 0 ; ()
Ans:
(,) )A-,*)A-A>,>*(-A>),-(>*-A>,-A,(
+()A-,*-A>),-(>*
L@S )A-,*)A-A>-,>*(-A>,-A>(>-A>,-A,(
+ )A-,*)1-,>*(-A>,- A>(>-A,( as )A-A>+1*
+ )A-,*;1;(-A>,- A>(>-A,(
+ A,-A(-A>,- A>(>-A,(
+ A,(-A,-A,(-A(-A>,-A>(>
A,)(-1*-A(),-1* -A>,- A>(>
+ A,-A(-A>,- A>(>
+ ()A-,* - A>),-(>* + &@S
@+n.+ '$#*+8
(,,)
A) A;B*;B) A;B* = A B
@et us taCe
Ao we have
X = A) A;B*
Y = B) A;B*
X ;Y = A
B
3333333
Also
X = A) A;B*
+ A) A + B*
,y using De9organ>s @aw )A,*>+A>-,>
. + )A)A>-,>**>+)AA>-A,>*>+)A,>*>+)A>-,* 3333331
Now J + ),)A,*>*>+M,)A>-,>*N>+ MA>,-,,>N>+)A>,*>+)A-,>* 3333330
Now (ombining . O J from 1 O 0 above, we have @;1;A in as H
))A-,>*)A>-,**>
+MAA>-,,-A>,>-A,N>
+)A,-A>,>*>
+A .87 , + &@S
@+n.+ '$#*+8
(,,,) ))A,*>-A>-A,*>+0
@1A
) AB + A + AB*
+ )1 + A* since AB + AB = 1
+ 1 since 1 + A = 1
+ 0 = &@S @+n.+ '$#*+8
Q.35 A combinational circuit has inputs A, ,, ( and output 2; 2 is true for following input
combinations
A is 2alse, , is True
A is 2alse, ( is True
A, ,, ( are 2alse
A, ,, ( are True
'"
D E ! D I % IT A L S ELE C T & O N I CS
)i* Write the Truth table for 2; :se the convention True+1 and 2alse + 0;
)ii* Write the simplified e#pression for 2 in A86 form;
)iii* Write the simplified e#pression for 2 in 68A form;
)iv* Draw logic circuit using minimum number of 03input NAND gates; (7)
Ans:
(,) )0E,n7 /9+ /$2/9 /041+
A , ( 2
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
A is false b is true 2or both value of c 2 is true;
(,,) S,3;1,-,+8 +:;$+ss,#n -#$ 6 .0n 4+ -#2n8 45 B=30;
<n A86 2orm
2 + A>-,(
(,,,) S,3;1,-,+8 +:;$+ss,#n -#$ 6 ,n 'OS -#$3
<; <n 68A 2orm 9<N<9<U5 U578A
2>+A,>-A(>
<<; 2+A>-,( taCing complement twice
2>+) A>-,(*>+)A;),(*>*
2Y+2+)A;),(*>*>
(,*) L#7,. .,$.2,/ 45 2s,n7 3,n,323 n234+$ #- 2=,n;2/ NAND 70/+s
Q.36 9inimise the logic function
2 (A, ,, (, D) = Z 9 (1, 0, , ", &, 10, 11,1') d (%, 1$)
:se Farnaugh map; Draw the logic circuit for the simplified function using N87 gates
only; (7)
'&
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
2+[9)1,0,,",&,10,11,1'*;d)%, 1$*
2>+,>D-,>(-A(-A,>
,y (omplementing 2
2+),>D-,>(-A(-A,>*>
+ M),>D*>),>(*>)A(*>)A,>*>N>
+ ),-D>*),-(>*)A>-(>*)A>-,*
TaCing complement twice and without opening the bracCet
2+M),-D>*-),-(>*>)=A>-(>*-)A>-,*N>
The logic circuit for the simplified function using N87 gates
Q.37 The capacity of 0F 1! 6789 is to be e#panded to 1! F 1!; 2ind the number of 6789
chips required and the number of address lines in the e#panded memory; (4)
Ans:
7equired capacity +1!C # 1!
Available chip )6789* +0C # 1!
The no of chip +1!C # 1! + "
0C # 1!
<n the chip total word capacity + 0 # 0
10
$0
D E ! D I % IT A L S ELE C T & O N I CS
Thus the address line required for the single chip + 11
<n the e#panded memory the word capacity 1!C + 0
1'
Now the address lines required are 1'; Among then 11 will be common and will be
connected to #" decoder;
Q.38 6erform following subtraction
)i* 11001310110 using 1>s complement
)ii* 11011311001 using 0>s complement (8)
Ans:
), * 11001 3 10110
1K s (ompliment of 10110 + 01001
1 1 0 0 1
- 0 1 0 0 1
333333333333333333
1 0 0 0 1 0
Add 1 and ignore carry;
Ans is 00011 + ;
(,,) 11011 / 11001 + A / ,
0Ks complement of , + 00111
1 1 0 1 1
- 0 0 1 1 1
1 0 0 0 1 0
<gnore carry to get answer as 00010 + 0;
Q.3 7educe the following equation using C3map
J = A,( + A(D + A, + A,(D +
A,(
(8)
Ans:
Y & ABC ' AC D ' AB ' ABC
Y & ABC D ' ABCD ' ABC D ' ABC D ' ABCD ' ABCD
' ABC D ' ABC D ' ABC D ' ABC D '
ABCD
Q.4! Write the e#pression for ,oolean function
$1
"
D E ! D I % IT A L S ELE C T & O N I CS
2 )A, ,, (* + Im )1,',$,!,%* in standard 68A form; (8)
Ans:
( (A,B,C )& \) (1,',$,!,%) in standard 68A form
2 + m
1
- m
'
- m
$
- m
!
- m
%
2 + \m)1,',$,!,%*
+ [ 9)0,0,*
+ 9
0
9
0
9

+ )A-,-(*)A- , -(*)A- , - ( *
Q.41 Design a 0H1 multiple#er using two 1!H1 multiple#ers and a 0H1 multiple#er; (8)
Ans:
To design a 0 . 1 9:. using
I0
I15
I16
I31
"3
"2 "1
0
16 X1
MUX
"2
"1
"3
"0
16X1
MUX
2X1
#
MUX
S$%$&' %()$ M
Two 1! . 1 9:. O one 0 . 1
There are total 0 input lines and one 8B6 line; The 0 . 1 9:. will transmit
one of the two <B6 to output depending upon its select line 9; 2or 9 + 0 upper 9:.
) <
0 /
<
1$ *
will be selected and 9 + 1 lower 9:. ) <
1! /
<
1
* will be selected;
Q.42 <mplement the following function using a line to " line decoder;
A )A,,,(* + I m)1,0,',%*
( )A,,,(* + I m ) ,$,!,%* (8)
Ans:
A )A,,,(* + m )1,0,',%*
( )A,,,(* + m ),$,!,%*
These are full adderKs output as sum )A* and carry ) ( *; We Cnow that to " line decoder
generates all the minterms from 0 to %; <n the decoder shown in the figure, Do correspond
to minterm m
o
, and so on; Ao by 87ing appropriate outputs of the decoder we can
implement these functions;
$0
D E ! D I % IT A L S ELE C T & O N I CS
Q.43 6erform the following operations using the 0>s complement methodH
)i* 0 / '" )ii* / '" / 0 (4)
Ans:
(,) 0 3 '"
add them
0 0 1 0 1 1 1
* )3 '"* - 0 1 0 0 0 0
%1 1 0 0 1 1 1
(,,) / '" 3 0 + 3 '" - )30*
3'" + 1 1 0 1 0 0 0 0
30 + 1 1 1 0 1 0 0 1
1 1 0 1 1 1 0 0 1 + 3%1
(arry is discarded
Q.44 6rove the following ,oolean identities using the laws of ,oolean algebraH
)i* (A + ,)(A + () = A + ,(
)ii* A,( + A,( + A,( = A(, +
()
(4)
Ans:
)i* )A-,*)A-(*+A-,(
L@S AA-A(-A,-,(+A-A(-A,-,(
87 A))(-1*-A),-1**-,(
87 A-A-,(
87 A-,( + &@S
@+n.+ '$#*+8
)ii* A,(-A,>(-A,(>+A), - (*
L@S A(),-,>*-A,)(-(>*
87 A(-A,
87 A),-(*+ &@S
@+n.+ '$#*+8
$
D E ! D I % IT A L S ELE C T & O N I CS
Q.45 The Farnaugh map for a A86 function is given below in 2ig;1; Determine the simplified
A86 ,oolean e#pression; (5)
Ans:
Q.46
A certain memory has a capacity of 'F "
)i* 1ow many data input and data output lines does it have4
)ii* 1ow many address lines does it have4
)iii* What is its capacity in bytes4 (5)
Ans:
(,) available capacity +'F#"
+ 0
10
#0
10
# "
+ 0
10
#"
As in the 'F#" ,the second number represents the number of bits in each word so the
number of data input lines will be ")also the data output lines* ;
(,,) <t has total 'F )0
10
* address line which are required to address 0
10
locations;
(,,,) <ts capacity in bytes is 'F bytes.
Q.47 A $3bit DA( produces an output voltage of 0;0V for a digital input of 00001; 2ind the
value of the output voltage for an input of 11111; What is the resolution of this DA(4 (6)
Ans:
2or the Digital output of 00001
8utput voltage is +0;0 volt +7esolution
The output+;0#1+1$;$volts
7esolution+)0;0volt*B)1$;$v*#100+1;0&0
$'
D E ! D I % IT A L S ELE C T & O N I CS
Q.48 An "3bit successive appro#imation AD( has a resolution of 00mV; What will be its digital
output for an analog input of 0;1%V4 (4)
Ans:
7esolution +00mv
Analog input +0;1%v
5quivalent value+)0;1%*B)0;1%*+10";$
5quivalent ,inary value+1101100;1
Q.4 A microprocessor uses 7A9 chips of 100' 1 capacity;
(,) 1ow many chips will be required and how many address lines will be connected to
provide capacity of 100' bytes;
(,,) 1ow many chips will be required to obtain a memory of capacity of 1! F bytes; (5)
Ans:
) i * Available chips + 100' # 1 capacity
7equired capacity + 100' # " capacity
*o. o( C+,-.=
100' ."
= "
100'.1
Number of address lines are required + 10 )i;e; 100' + 0
10
*
As the word capacity is same ) 100' * so same address lines will be connected to all chips;
) ii *
*o.%( C+,-. R#/0,!#1 =
1! .1 00' ."
= 10"
100'.1
Q.5! 2ind the ,oolean e#pression for logic circuit shown in 2ig;1 below and reduce it using
,oolean algebra; (6)
Ans:
J + )A,*> - )A> - ,*>
= A> - ,> - A,> :sing Demorgan>s Theorem;
= A> - ,>)1-A*
= A> - ,> Aince 1-A+1
Q.51 <mplement the following function using '3to31 multiple#er;
J(A, ,, () =
I
(0,,$,!) (8)
$$
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
J)A,,,(*+I)0,,$,!*
@et us taCe ,,( as the select bits and A as input; To decide the input we write;
J + A>,(>-A>,(-A,>(-A,(>
+ 0 if ,+0, (+0
+ A if ,+0, (+1
+ 1 if ,+1, (+0
+ A> if ,+1, (+1
The corresponding implementation is shown in the figure; Thus
0
A '#1 J
1 9:.
A>
, (
Q.52 Design a mod310 Aynchronous up counter; (8)
Ans:
D+s,7n 0 3#8 12 s5n.9$#n#2s .#2n/+$ 2s,n7 D=-1,;-1#;s.
I s /0/+ /0 41 +
6resent state Ne#t state 7equired D <nputs
A , ( D A , ( D D
A
D
,
D
(
D
D
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 1 0 0 1 1
0 0 1 1 0 1 0 0 0 1 0 0
0 1 0 0 0 1 0 1 0 1 0 1
0 1 0 1 0 1 1 0 0 1 1 0
0 1 1 0 0 1 1 1 0 1 1 1
0 1 1 1 1 0 0 0 1 0 0 0
1 0 0 0 1 0 0 1 1 0 0 1
1 0 0 1 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 1 1
1 0 1 1 0 1 0 0 0 1 0 0
$!
D E ! D I % IT A L S ELE C T & O N I CS
2irst draw the state table having present state, ne#t state and required flip3flop input to give
the transition; D flip flop gives the output same as the ne#t state itself; Then solve by using F
maps to find out D
A
D
,
D
(
D
D
for all states;
:nused states are 1100,1101,1110,1111 they can be treated as don>t care conditions from the
table; Draw Farnaugh3maps for D
A
, D
,
, D
(
and D
D
as follows and obtain
,oolean e#pressions for them;
$%
D E ! D I % IT A L S ELE C T & O N I CS
$"
D E ! D I % IT A L S ELE C T & O N I CS
L#7,. 8,07$03 -#$ 3#8=12 S5n.9$#n#2s 2;=.#2n/+$
Q.53 2ind how many bits of AD( are required to get an resolution of 0;$ mV if the ma#imum
full scale voltage is 10 V; (8)
Ans:
7esolution+;$mv
2ull scale output+-10v
Xresolution +)$mv*B10#100+0;0$X
No of bits +@og
0
)0#1000* + 00
Q.54 (onvert the decimal number '$!%" to its he#adecimal equivalent number; (4)
Ans:
)'$!%"*
10
+),0!5*
1!
$&
1! '$!%"
1! 0"$'
1! 1%"
1'
!
1! 11 0
0 11
D E ! D I % IT A L S ELE C T & O N I CS
5
!
0
,
)'$!%"*
10
+),0!5*
1!
Q.55 Write the truth table of N87 gate; (4)
Ans:
A , 2
0 0 1
0 1 0
1 0 0
1 1 0
Q.56 Design a ,(D to e#cess code converter using minimum number of NAND gates; 1intH
use C map techniques; (8)
Ans:
2irst we maCe the truth table
,(D no
A , ( D
5.(5AA3 N8
W . J U
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Then by using F maps we can have simplified functions for w, #, y, D as shown belowH
!0
D E ! D I % IT A L S ELE C T & O N I CS
!1
D E ! D I % IT A L S ELE C T & O N I CS
NAND 70/+ ,3;1+3+n/0/,#n -#$ s,3;1,-,+8 -2n./,#n
!0
D E ! D I % IT A L S ELE C T & O N I CS
W + ,D - AD - A,> - ,(
,y complementing twice we get
W + )),D - AD - A,> - ,(*>*>
+ )),D*> ; )AD*> ; )A,>*> ; ),(*>*>
. + ,(>D - ,>D - ,>(
,y complementing twice we get
. + ,(>D - ,>D - ,>(
+ )),(>D*> ; ),>D*> ; ),>(*>*>
J + (>D> - (D
+ ))(>D>*> - )(D*>*>
U + D>
L#7,. 8,07$03 -#$ BCD /# +:.+ss 3 .#8+ .#n*+$/+$ 45 2s,n7 3,n,323 n234+$ #-
NAND 70/+s
Q.57 With the help of a suitable diagram, e#plain how do you convert a EF flipflop to T type
flipflop; (4)
!
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
?iven flip flop is EF flip flop and it is required to convert EF into T; 2irst we draw the
characteristic table of T flip flop and then relate the transition with e#citation table of EF flip
flop;
Now we solve F maps for E and F by considering T and G)t* as input;
L#7,. 8,07$03 .#n*+$/ 0 FB -1,;-1#; /# T /5;+ -1,;-1#;.
Q.58 A number of 0$! # " bit memory chips are available; To design a memory organiDation of
0 F # " memory; <dentify the requirements of 0$! # " memory chips and e#plain the
details; (8)
Ans:
(hips available+0$!#"
7equired capacity+00'"#"
Number of chips+)00'"#"*B)0$!#"*+"+)0$!+0
"
*
Address lines required for 00'"#"chip+11)00'"+0
11
*
Thus the siDe of the decoder+#"
!'
" 1%%
1
" 00
6
" 0
2
0
D E ! D I % IT A L S ELE C T & O N I CS
Q.5 (onvert (1%%;0$)
10
to octal; (8)
Ans:
)1%%;0$*
10
+ ) *
"
2irst we taCe integer part
Thus )1%%*
10
+ )0!1*
"
Now as 0;0$ # " + 0;00
and 0;00 # " + 0
Thus )0;0$*
10
+ )0;0*
"
Therefore, Thus )1%%;0$*
10
+ )0!1;0*
"
Q.6! 6erform the following subtraction using 1>s complement
)i* 11001 / 10110 )ii* 11011 3 11001 (8)
Ans:
)i* 11001 / 10110 + . / J
. + 11001
1>s complement of J + 01001
Aum + 1 00010
5nd around carry + 1
Ao .3J + 00011
)ii* 11011 / 11001 + . / J
. + 11011
1>s complement of J + 00110
Aum + 1 00001
5nd around carry + 1
Ao .3J + 00010
Q.61 6rove the following identities
)i* A , ( + A , ( + A, ( + A , ( = (
)ii* A , + A , ( + A , + A , ( = , +
A (
(8)
Ans:
(,) L@S + A>,>(> - A>,(> - A,>(> - A,(>
+ A>(> ),> - ,* - A(> ),> - ,*
+ A>(> - A(> Mas ,>-, + 1N
+ (> )A> - A*
+ (> Mas A>-A +1N
!$
D E ! D I % IT A L S ELE C T & O N I CS
+ &@S.
@+n.+ '$#*+8
(,,) L@S + A, - A,( - A>, - A,>( + , - A(
+ , )A - A>* - A( ), - ,>*
+ , - A( Mas , - ,> + A - A> + 1N
+ , - A(
+ &@S.
@+n.+ '$#*+8
Q.62 2ind the boolean e#pression for the logic circuit shown below; (8)
Ans:
8utput of ?ate31 )NAND* + )A,*>
8utput of ?ate30 )N87* + )A>-,*>
8utput of ?ate3 )N87* + M)A,*> - )A>-,*>N>
Now applying De39organs law, ).-J*> + .>J>
and ).J*> + ).>-J>*
M)A,*> - )A>-,*>N> + M)A,*>N> M)A>-,*>N>
+ )A,* )A>-,*
+ AA>, - A,,
+ A,,
+ A,;
Q.63 7educe the following equation using C3map
J = , ( D + A , ( D + A , ( D + A , ( D + A ,
( D
(8)
Ans:
9ultiplying the first term by )A-A>*
J + A>,(>D> - A,(>D> - A>,(>D - A,(>D - A>,(D - A,(D
+
I
)',10,$,%,1$,1*
+ ,(> - ,D
!!
D E ! D I % IT A L S ELE C T & O N I CS
Q.64 <mplement the following function using " to 1 multiple#er
J(A, ,, (, D) =
I
(0,1,0,$,&,11,1,1
$)
(8)
Ans:
We will taCe three variables ,,( O D at selection lines and A as input; Now there are
eight inputs and they can be 0,1,A or A> depending on the ,oolean function;
<
0
<
1
<
0
<

<
'
<
$
<
!
<
%
A> 0 1 0 ' $ ! %
" & 10 11 10 1 1' 1$ A
A> 1 A> A 0 1 0 A
Now, the realiDation isH
!%
" # 1
9:.
D E ! D I % IT A L S ELE C T & O N I CS
<
0
+ A>
<
1
+ 1
<
0
+ A>
<

+ A
>
<
'
+ 0
<
$
+ 1
<
!
+ 0
<
%
+ A
B C D
S+1+./ L,n+s
Q.65 )i* 1ow many
bytes;
10" " 7A9 chips are required to provide a memory capacity of 00'"
)ii* 1ow many lines of address bus must be used to access 00'" bytes of memory; 1ow
many lines of these will be common to each chip4
)iii* 1ow many bits must be decoded for chip select4 What is the siDe of decoder4
(8)
Ans:
(,) Available 7A9 chips + 10" # "
7equired memory capacity + 00'" # "
Number of chips required + )00'" # "* B )10" # "*
+ 1!;
(,,) (hips available are of 10" # " in siDe; <t means that total 10" )0
%
* locations are there
and each location can store " bits; Thus the total number of address lines required to access
10" locations is %; As seven address lines can address 0
%
locations; These seven lines are
common to all chips;
Now to access 00'" locations, we require 11 address lines, as 00'" + 0
11
(,,,) These higher order lines will be applied to decoder input; The number of inputs to the
decoder will be 11 3 % + '; The siDe of the decoder will be '#1!; These 1! decoder outputs
will be connected to the chip select input of individual chips;
A
10
A
&
A
"
A
%
' # 1!
Decoder
D
0
To chip select input of chip31
D
1$
To chip select input of chip31!
A
!
]
A
0
To all chips
!"
D E ! D I % IT A L S ELE C T & O N I CS
Q.66 1ow many bits are required at the input of a ladder DBA converter, if it is required to give a
resolution of $mV and if the full scale output is -$V; 2ind the Xage resolution;
(8)
Ans:
2irst we find out the ratio of 2ull scale output to 7esolution + $V B $ mV + 1000;
Now number of bits + log
0
1000 + 10;
6ercentage 7esolution + $ mV B $ V ^ 100 + 0;1X
Q.67 A !3bit Dual Alope ABD converter uses a reference of /!V and a 1 91D
clocC; <t uses a fi#ed count of '0 )101000*; 2ind 9a#imum (onversion Time; (4)
Ans
The time T
1
given by
T
1
+ 0
N
T
(
where N + no; of ,its, T
c
+ time period of clocC pulse
?iven N + !, T
(
+ 1B 191D + 1 _ s;
Therefore T
1
+ 0
!
. 10
3!
s + !' _
s;
Q.68 A 03digit ,(D DBA converter is a weighted resistor type with
5
7
= 1 Volt, with 7 = 19 ,
7
f
= 10F ; 2ind resolution in 6ercent and Volts; (5)
Ans
7esolution + 1B0
0
+ 0;0$ volts;
As the resolution is determined by number of input bits of DBA converterR 2or e#ample two
bit converter has 0
0
)'* possible output levels, therefore its resolution is 1 part in '
<n percent it will be ` . 100 + 0$X
<n volts, it will be 0;0$ volts;
!&
D E ! D I % IT A L S ELE C T & O N I CS
'A&T ( III
D E SC& I ' TI V E S
Q.1 Distinguish between min terms and ma# terms; (6)
Ans: Distinguish between 9interms and 9a#termsH
)i* 5ach individual term in standard Aum 8f 6roducts form is called as minterm whereas
each individual term in standard 6roduct 8f Aums form is called ma#term;
)ii* The unbarred letter represent 1>s and the barred letter represent 0>s in min terms,
whereas the unbarred letter represent 0>s and the barred represent 1>s in ma#terms;
)iii* <f a system has variables A, ,, ( then the minterms would be in the form A,(,
whereas the ma#term would be in the form A-,-(;
)iv* The minterm designation for three variable e#pression be
J+Im )1, , $, %*
Where the capital I represents the product and m stands for minterms;
Decimal number 1 corresponds to binary number 001 or A B (
Decimal number corresponds to binary number 011 or A ,(
Decimal number $ corresponds to binary number 101 or A B (
Decimal number % corresponds to binary number 111 or A,(;
Whereas the 9a#term designation for three variable e#pression be
J+[9 )0, 1, , '*
Where the capital [ represents the product and 9 stands for ma#terms;
Decimal 0 means binary 000 and term is A-,-(
Decimal 1 means binary 001 and term is A-,- C
Decimal means binary 011 and term is A- B -
C Decimal ' means binary 100 and term is A
-,-(
Q.2 What are universal gates; (onstruct a logic circuit using NAND gates only for the
e#pression # + A ; ), - (*; (7)
Ans:
Un,*+$s01 %0/+s: NAND and N87 ?ates are Cnown as :niversal gates; The AND, 87,
N8T gates can be realiDed using any of these two gates; The entire logic system can be
implemented by using any of these two gates; These gates are easier to realiDe and
consume less power than other gates;
(onstruction of a logic circuit for the e#pression . + A ), - (* using NAND gates is
Ahown in fig;' )b*
%0
D E ! D I % IT A L S ELE C T & O N I CS
_
B
_
A
AC
C
_
_ _
(AB) (AC ) = AB + AC
6,7.4(4) L#7,. D,07$03 -#$ /9+ +:;$+ss,#n ? = A (B + C)
Q.3 9ention the various <( logic families; (7)
Ans:
V0$,#2s IC L#7,. 603,1,+s: Digital <(>s are fabricated by employing either the ,ipolar
or the :nipolar Technologies and are referred to as ,ipolar @ogic 2amily or :nipolar
@ogic 2amily
I B,;#10$ L#7,. 603,1,+s:
There are two types of operations in ,ipolar @ogic 2amilies
1; Aaturated @ogic 2amilies
0; Non3saturated @ogic 2amilies
1. S0/2$0/+8 L#7,. 603,1,+s: <n Aaturated @ogic, the transistors in the <( are
driven to saturation;
)i* 7esistor3Transistor @ogic )7T@*;
)ii* Direct3(oupled Transistor @ogic )D(T@*
)iii* <ntegrated3<nQection @ogic )<a@*
)iv* Diode 3Transistor @ogic )DT@*
)v* 1igh3Threshold @ogic )1T@*
)vi*Transistor3Transistor @ogic )TT@*
2. N#n=s0/2$0/+8 L#7,.: <n Non3saturated @ogic, the transistors are not driven into
saturation;
)i* AchottCy TT@
)ii* 5mitter (oupled @ogic )5(@*
II Un,;#10$ L#7,. 603,1,+s:
98A devices are :nipolar devices and only 98A25Ts are employed in 98A logic
circuits; The 98A logic families are
)i* 698A
)ii* N98A, and
)iii* (98A
while in 698A only p3channel 98A25Ts are used and in N98A only n3channel
98A25Ts are used, in complementary 98A )(98A*, both 6 and N channel
98A25Ts are employed and are fabricated on the same silicon chip;
Q.4 What is a half3adder4 5#plain a half3adder with the help of truth3table and logic diagram; (1!)
Ans:
@01- A88+$: A logic circuit for the addition of two one3bit numbers is referred to as an
half3adder; The addition process is illustrated in truth table shown in Table !;1; 1ere A
and , are the two inputs and A )A:9* and ( )(A77J* are two outputs;
%1
D E ! D I % IT A L S ELE C T & O N I CS
A , A (
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
T041+ 6.1 T$2/9 T041+ -#$ @01- A88+$
2rom the truth table, we obtain the logical e#pressions for A and ( outputs as
A + A ,-A B
( + A,
The logic diagram for an 1alf3adder using gates is shown in fig;!)a*
A
S
B
C
6,7.6(0) L#7,. D,07$03 -#$ 0n @01-=088+$
Q.5 :sing a suitable logic diagram e#plain the worCing of a 13to31! de multiple#er;(7)
Ans:
G#$E,n7 #- 0 1=/#=16 D+321/,;1+:+$: A demultiple#er taCes in data from one line and
directs it to any of its N outputs depending on the status of the selected inputs; <f the
number of output lines is N )1!*, the number of select lines m is given by 0
m
+ N;i;e;, 0
'
+
1!; Ao, the number of select lines required for a 13to31! demultiple#er is '; Table %;1
shows the Truth Table of 13to31! Demultiple#er; The input can be sent to any of the 1!
outputs, D
0
to D
1$
; <f D(,A + 0000, the input goes to D
0
; <f D(,A + 0001, the input
goes to D
1
and so on;
2ig;%)a* shows the logic diagram of a 13to31! demultiple#er, consists of " N8T gates, 1!
NAND gates, one data input line)?*, ' select lines )A,,,(,D* and 1! output lines )D
0
, D
1
, D
0
333333D
1!
*; The " N8T gates prevent e#cessive loading of the driving source; 8ne data input
line ? is implemented with a N87 gate used as negative AND gate; A low level in each input
2
1
and
2
0
is required to maCe the output ? high; The output ? of enable is one of the inputs
to all the 1! NAND gates; ? must be high for the gates to be enabled; <f the enable gate is not
activated then all si#teen de multiple#er outputs will be high irrespective of the state of the
select lines A,,,(,D;
%0
D E ! D I % IT A L S ELE C T & O N I CS
Demulti-
plexer
Input
Selection
Lines
D C B A
Logic
Function
Demultiplexer Outputs
D
0
D
1
D
2
D
3
D
4
D

D
!
D
"
D
#
D
$
D
10
D
11
D
12
D
13
D
14
D
1
0 0 0 0 0
D C B A
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 1
D C B A
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 0 0 1 0
D C B A
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
3 0 0 1 1
D C B A
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
4 0 1 0 0
D C B A
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
5 0 1 0 1
D C B A
1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
6 0 1 1 0
D C B A
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
7 0 1 1 1
D C B A
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
8 1 0 0 0
D C B A
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+ 1 0 0 1
D C B A
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
10 1 0 1 0
D C B A
1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
11 1 0 1 1
D C B A
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
12 1 1 0 0
D C B A
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
13 1 1 0 1
D C B A
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
14 1 1 1 0
D C B A
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
15 1 1 1 1 D C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
T041+ 7.1 T$2/9 T041+ #- 1=/#=16 D+321/,;1+:+$
%
D E ! D I % IT A L S ELE C T & O N I CS
,
_
A _
_
B
C
_
D
A
B
_
1
,
_ _ _ _
D ( A B C D )
0
_ _ _
D ( A B C D )
1
_ _ _
D ( A B C D )
2
D-' - I) ./
'
_
,
2
_ _
D ( A B C D )
3
C
_ _ _
A
D ( A B C D )
A
4
_
A
_ _
D ( A B C D )
5
S
0
B
L
B
0
C
_
1
B
L
I
N
C
D
0
C
S
_
C
_ _
D ( A B C
D )
6
_
D ( A B C
D )
7
_ _ _
D ( A B C
D )
8
_ _
D ( A B C D
)
+
D
_ _
D
D ( A B C D )
_ 10
D
_
_
D ( A B C D )
C
11
_ _
D ( A B C D )
12
_
_
B
D ( A B C D )
13
_
A
_
D ( A B C D )
14
A D ( A B C D )
B
C
15
D
6,7.7(0) L#7,. D,07$03 #- 1=/#=16 D+ 321/,;1+:+$
%'
D E ! D I % IT A L S ELE C T & O N I CS
Q.6 ; With relevant logic diagram and truth table e#plain the worCing of a two input 5.387 gate;
(7)
Ans:
TC#=In;2/ E?=O& %0/+: An 5#clusive387 )5.387* gate recogniDes words which have
an odd number of ones; 2ig;%)b* shows the logic diagram of an 5.387 gate and 2ig;%)c*
shows the symbol of an 5.387 ?ate; The upper AND gate gives an output A , and the
lower AND gate gives an output A B ;
_
_
A
A
A B
_
_
A B
B
B
_ _
Y = A B + A
B
6,7.7(4) L#7,. D,07$03 #- E?=O& %0/+
A
B
Y
6,7.7(.) S534#1 #- E?=O& %0/+
Therefore, the output equation becomes J + A , - A B + A 5.387 , + A ,
<f both A and , are low, the output is low; <f either A or , )not both* are high )and the
other is low*, the output is high; <f both A and , are high, output is low; Thus the output
is 1 when A and , are different; Table %;0 shows the Truth Table for 5.387 gate;
A B
> ( A B + A B )
0 0 0
0 1 1
1 0 1
1 1 0
T041+ 7.2 T$2/9 T041+ #- E?=O& %0/+
Q.7 With the help of clocCed EF flip flops and waveforms, e#plain the worCing of a three bit
binary ripple counter; Write truth table for clocC transitions; (14)
Ans:
3=B,/ B,n0$5 &,;;1+ C#2n/+$: <n 7ipple (ounters, all the 2lip32lops are not clocCed
simultaneously and the flip3flops do not change state e#actly at the same time; A 3bit
%$
D E ! D I % IT A L S ELE C T & O N I CS
,inary (ounter has ma#imum of 0

states i;e;, " states, which requires 2lip32lops;
The word ,inary (ounter means a counter which counts and produces binary
outputs
000,001,01033111;<t goes through a binary sequence of " different states )i;e, from 0 to
%*; 2ig;")a* shows the logic circuit of a 3bit ,inary 7ipple (ounter consisting of
5dge Triggered EF flip3flops; As indicated by small circles at the (@F input of flip3
flops, the triggering occurs when (@F input gets a negative edge; G
0
is the @east
Aignificant ,it )@A,* and G
0
is the 9ost Aignificant ,it )9A,*; The flip3flops are
connected in series; The G
0
output is connected to (@F terminal of second flip3flop;
The G
1
output is connected to (@F terminal of third flip3flop; <t is Cnown as a 7ipple
(ounter because the carry moves through the flip3flops liCe a ripple on water;
G#$E,n7: <nitially, (@7 is made @ow and all flip3flops 7eset giving an output G + 000;
When (@7 becomes 1igh, the counter is ready to start; As @A, receives its clocC pulse,
its output changes from 0 to 1 and the total output G + 001; When second clocC pulse
arrives, G
0
resets and carries )i;e;, G
0
goes from 1 to 0 and, second flip flop will
receive (@F input*; Now the output is G + 010; The third (@F pulse changes G
0
to 1
giving a total output G + 011; The fourth (@F pulse causes G
0
to reset and carry and G
1
also resets and carries giving a total output G + 100 and the process goes on; The action
is shown is Table ";1;The number of output states of a counter are Cnown as 9odulus
)or 9od*; A 7ipple (ounter with flip3flops can count from 0 to % and is therefore,
Cnown as 9od3" counter;
(ounter Atate G
0
G
1
G
0
0 0 0 0
1 0 0 1
0 0 1 0
0 1 1
' 1 0 0
$ 1 0 1
! 1 1 0
% 1 1 1
T041+.8.1 C#2n/,n7 S+<2+n.+ #- 0 3=4,/ B,n0$5 &,;;1+ C#2n/+$
%!
%
D E ! D I % IT A L S ELE C T & O N I CS
&I '& % %
0
1
2
(
%
( %
0
0
1
1
(
2
%
2
CLOC)
FF FF
FF
*+LS,S
0
)
0 Cr
1
)
1 Cr
2
)
2 Cr
CL,A-
6,7.8(0) L#7,. D,07$03 #- 3=B,/ B,n0$5 &,;;1+ C#2n/+$
7ipple counters are simple to fabricate but have the problem that the carry has to propagate
through a number of flip flops; The delay times of all the flip flops are added; Therefore,
they are very slow for some applications; Another problem is that unwanted pulses occur at
the output of gates;
1
CL OC2
1 2 3 4 5 6 7 8 + 10
P ULS0S
0
1
%
0
0
1
%
1
0
1
%
2
0
1 (3 $
6,7.8(4) T,3,n7 D,07$03 #- 3=4,/ B,n0$5 &,;;1+ C#2n/+$
The timing diagram is shown in F,3.456). FF
0
is @A, flip flop and FF
2
is the 9A, flip
flop; Aince FF0 receives each clocC pulse, G
0
toggles once per negative clocC edge as
shown in 2ig; "56).The remaining flip flops toggle less often because they receive
negative clocC edge from preceding flip flops; When G
0
goes from 1 to 0, FF
1
receives
a negative edge and toggles; Aimilarly, when G
1
changes from 1 to 0, FF
2
receives a
negative edge and toggles; 2inally when G
0
changes from 1 to 0, FF
3
receives a
negative edge and toggles; Thus whenever a flip flop resets to 0, the ne#t higher flip flop
toggles;
This counter is Cnown as ripple counter because the "th clocC pulse is applied, the trailing
edge of "th pulse causes a transition in each flip flop; G
0
goes from 1igh to @ow, this
causes G
1
go from 1igh to @ow which causes G
0
to go from 1igh to @ow which causes
G

%%
0
D E ! D I % IT A L S ELE C T & O N I CS
to go from 1igh to @ow; Thus the effect ripples through the counter; <t is the delay caused
by this ripple which result in a limitation on the ma#imum frequency of the input signal;
Q.8 :sing D32lip flops and waveforms e#plain the worCing of a '3bit A<A8 shift register; (14)
Ans:
S+$,01 In = S+$,01 O2/ S9,-/ &+7,s/+$: 2ig;&)a* shows a ' bit serial in 3 serial out shift
register consisting of four D flip flops FF
0
, FF
1
, FF
2
and FF
3
. As shown it is a
positive edge triggered device; The worCing of this register for the data 1010 is
given in the following steps;
DA.A
D
%
D
%
D % D %
I/
0
0
1
1
2
2
3
3
FF FF
FF FF
3
0 1
2
0
%
3
CLOC)
6,7.(0) L#7,. D,07$03 #- 4=4,/ S+$,01 In ( S+$,01 O2/ S9,-/ &+7,s/+$
C L2
1
2
3
4
D A1A
1
0 1
%
0
%
1
%
2
%
3
6,7.(4) O2/;2/ G0*+-#$3s #- 4=4,/ S+$,01=,n S+$,01=#2/ &+7,s/+$
1; ,it 0 is entered into data input line; D
0
+ 0, first clocC pulse is applied, FF
0
is reset
and stores 0;
0; Ne#t bit 1 is entered; G
0
+ 0, since 7
0
is connected to D
1
, D
1
becomes 0;
; Aecond clocC pulse is applied, the 1 on the input line is shifted into FF
0
because FF
0
sets; The 0 which was stored in FF
0
is shifted into FF
1
.
'; Ne#t bit 0 is entered and third clocC pulse applied; 0 is entered into FF
0
, 1 stored in FF
0
is shifted to FF
1
and 0 stored in FF1 is shifted to FF
2.
$; @ast bit 1 is entered and 'th clocC pulse applied; 1 is entered into FF
0
, 0 stored in FF
0
is shifted to FF
1
, 1 stored in FF
1
is shifted to FF
2
and 0 stored in FF2 is shifted to FF
3
.
%"
1
o
D E ! D I % IT A L S ELE C T & O N I CS
This completes the serial entry of ' bit data into the register; Now the @A, 0 is on the
output G

;
!; (locC pulse $ is applied; @A, 0 is shifted out; The ne#t bit 1 appears on G

output;
%; (locC pulse ! is applied; The 1 on G

is shifted out and 0 appears on G

output;
"; (locC pulse % is applied; 0 on G

is shifted out; Now 1 appears on G

output;
&; (locC pulse " is applied; 1 on G

is shifted out;
10; When the bits are being shifted out )on (@F pulse $ to "* more data bits can be
entered in;
Q. With the help of 7307 binary ladder, e#plain the worCing of a '3bit DBA converter (14)
Ans:
&=2& L088+$ n+/C#$E 3+/9#8: <n a 7307 ladder networC method of digital to analog
conversion, irrespective of number of bits of the DA( only two convenient values of
resistors are needed in the ratio of 1H0 as depicted in fig 10)a*; An 7307 @adder
NetworC based on constant reference current; <n the circuit of fig 10)a* points ? are
actual ground and points ?K are virtual ground; Therefore the potential at all the 2
.
and
28
.
is Dero; ,etween ground )actual or virtual* and node A there are two resistors each
of value 07 in parallel; Therefore this resultant resistance between ground and node A is
7 and the current through each of the 07 resistance connected to node A must be same;
@et us say this current is <; Then the current flowing from A to , through the resistor 7
is 0<; Then the total resistance from ground to node , through the node A becomes 07;
Also the resistance directly connected between ground and , is also 07; Ao between the
node , and ground there are two equal resistances in parallel each of value 07;
Therefore, the resultant resistance is 7 and the current approaching to node , from both
sides must be equal; Aince current approaching from the side of node A is 0<, therefore
the current approaching to the node , from the resistor 07 under it must also be 0<;
1ence the total current approaching the node ( from the side of node , is '<; 8n the
basis of the same logic the current approaching to node D from the side of node ( must
be "< and the current approaching it form the 07 resistor under node D should also be
"<;
D
I = 16 I
4$ #
5 C
5
B
8 I
4 I
5
A
2 I
I
I
25
8 I
4$ #
25
4 I
25
2 I
25
I
25
* 6
D
3
,
, !
D
D D
2
0
,
, ,
5
#
, ! , ! , !
I
7/ '
-
6(4 '/-% ,4 7/)8 L()$ , !
1
,
+
6,7.1!(0) &=2& L088+$ N+/C#$E DHA C#n*+$/+$
%&
D E ! D I % IT A L S ELE C T & O N I CS
Whenever any of the bit or bits of the digital input word D

D
0
D
1
D
0
is high,
the corresponding transistor switch is 8N ,.#. connected to virtual ground and the current of
that vertical branch of the ladder comes from the output, otherwise the current of the
vertical branch comes directly from the actual ground without any effect on the output;
1ence the output current )lout* gives the analog current value corresponding to the digital
input word; This analog current gets converted to the analog voltage V
o
;
An &=2& 4=B,/ L088+$ N+/C#$E DAC 40s+8 #n $+-+$+n.+ *#1/07+: An 7307 '3bit @adder
NetworC DBA (onverter is shown in fig; 10)b*
LO9
D
: I,:
D D
6
4$ #
D
0
1 2
3
5
#
25
25 25 25
25 5
5 5 5
-
A
B C D
1
+
o
6,7.1!(4) &=2& 4=4,/ L088+$ N+/C#$E DHA C#n*+$/+$
' $ ## - :
S/+; 1: <f the digital value to be converted to analog value is 0001 ,.#.D
0
is on the high side
connected to V
ref
while D
1
, D
0
, and D

are connected to ground; Then the circuit redrawn as
shown in2ig;10)c*;
5
#
6
4$ #
X
1
25
A
5
25
X X X
2 3
4
B
5
C
5
D
5
-
1
+
o
25
25
25
X ! X ! X ! X !
1 2 3 4
6,7.1!(.) &=2& L088+$ N+/C#$E DHA C#n*+$/+$ C9+n D
!
,s .#nn+./+8 /# V
$+-
0n8
D
1
"D
2
"D
3
0$+ .#nn+./+8 /# 7$#2n8
Applying Thevenin>s theorem at .
1
,.
1
> , the circuit of fig;10)c* becomes the equivalent
circuit shown in fig;10)d*
"0
1
D E ! D I % IT A L S ELE C T & O N I CS
5
#
X
2
X
1
5
B
5
C
5
D
5
-
1
o
5
+
+
6 ; 2
* 4$ #
25 25 25
X !
1
X !
2
6,7.1!(8) &=2& L088+$ N+/C#$E DHA C#n*+$/+$ C9+n T9+*+n,nAs T9+#$+3 0;;1,+8
0/ ?
1
0n8 ?
1
A
Again Applying Thevenin>s Theorem at .
0
,.
0
>, then the circuit of fig;10)d* becomes the
equivalent circuit shown in fig;10)e*;
5
#
X
2
5
5
X
3
C
5
D
5
-
1
+
o
+
6 ; 4
*
4$ #
25 25
X !
2
X !
3
6,7.1!(+) &=2& L088+$ N+/C#$E DHA C#n*+$/+$ C9+n T9+*+n,nAs T9+#$+3 0;;1,+8 0/
?
2
0n8 ?
2
A
Again Applying Thevenin>s Theorem at .

,.

> the circuit of fig;10)e* becomes the


equivalent circuit shown in fig;10)f*H
5
#
X
4
X
3
5
D
5
-
+
o
5
+
25
6 ; 8
*
4$ #
X !
3
X !
4
6,7.1!(-) &=2& L088+$ N+/C#$E DHA C#n*+$/+$ C9+n T9+*+n,nAs T9+#$+3 0;;1,+8 0/
?
3
0n8 ?
3
A
"1
o
D E ! D I % IT A L S ELE C T & O N I CS
8nce Again applying Thevenin>s theorem at section .
'
, .
'
> the circuit of fig;10)f* finally
becomes the equivalent circuit shown in fig;10)g*.
5
#
5
#
5
-
25
1 6 ; 16 -
+
4$#
1
5
+
o
+
6 ; 16
*
4$#
6,7.1!(7) &=2& L088+$ N+/C#$E DHA C#n*+$/+$ C9+n T9+*+n,nAs T9+#$+3 0;;1,+8
0/ ?
4
0n8 ?
4
A
S/+; 2: <f D
1
is high )connected to V
ref
* and D
0
, D
0
, D

are all low )connected to ground*,
then the circuit becomesH
5
#
X X X
6
4$ #
1 2 3
25
B
5
C
5 D 5
-
1
+
o
25
25 25
X !
X !
X !
1
2
3
6,7.1!(9) &=2& L088+$ N+/C#$E DHA C#n*+$/+$ C9+n D
1
,s .#nn+./+8 /# V
$+-
0n8
D
!
"D
2
"D
3
0$+ .#nn+./+8 /# 7$#2n8
Applying Thevenin>s Theorem, three times and reducing the circuit each time at sections
.
1
, .
0
, .

we finally get the circuit as shown in fig;10)i*;
5
#
25
6 ; 8 -
4$ #
1
+
o
6,7.1!(,) E<2,*01+n/ C,$.2,/ C9+n D
1
,s .#nn+./+8 /# V
$+-
D
!
"D
2
"D
3
0$+ .#nn+./+8
/# 7$#2n8
"0
D E ! D I % IT A L S ELE C T & O N I CS
S/+; 3: 7epeating the same e#ercise of D
0
1igh and other bits @ow, we get the
finally reduced (ircuit as shown in fig;10)Q*;
5
#
25
6 ; 4 -
4$ #
1
+
o
6,7.1!(I) E<2,*01+n/ C,$.2,/ C9+n D
2
,s .#nn+./+8 /# V
$+-
D
!
"D
1
"D
3
0$+ .#nn+./+8
/# 7$#2n8
S/+; 4H 7epeating the same for D

1igh and other bits @ow, we can reduce the circuit
shown in fig;10)C*;
5
#
25
6 ; 2 -
4$ #
1
+
o
6,7.1!(E) E<2,*01+n/ C,$.2,/ C9+n D
3
,s .#nn+./+8 /# V
$+-
D
!
"D
1
"D
2
0$+ .#nn+./+8
/# 7$#2n8
S/+; 5: (ompiling the reduced circuits of the above four steps by applying Auperposition
Theorem, then the networC of fig 10)g*,10)i*,10)Q*,10)C* becomes the equivalent circuit
shown in fig;10)m*;
6 ; 16
4$ #
6 ; 8
4$ #
6 ; 4
4$ #
6 ; 2
4$ #
25 5
#
D
0 25
D
- 1
25
1
D
+
o
2
25
D
3
6,7.1!(3) E<2,*01+n/ .,$.2,/ 45 0;;15,n7 S2;+$;#s,/,#n T9+#$+3 -#$ /9+ .,$.2,/s #-
-,7.1!(7)"1!(,)"1!(I)"1!(E)
"
(
0 '
D E ! D I % IT A L S ELE C T & O N I CS
1ence the derived equivalent circuit of the 7307 ladder networC proves that the bits of the
input digital word D

, D
0
, D
1
, D
0
receive the applied voltages as per their binary weights
and we get the corresponding analog value at V
o
; Therefore,
V
!#(
D D D D

V = ;R

+
0
+
1
+
0

%
V
!#(
0R

0 '

D D
" 1!

V = ;R
n 1
+
n 0
+ ;;;;; +
0
%
0R
(

0
'
0
n

<f 7
f
is also selected equal to 07, then

D D D

V = V ;
n 1
+
n 0
+ ;;;;; +
0

% !#(

0
n

V
8
is independent of the numerical values of 7; Thus any convenient value of 7 O 07 can
be taCen for the design of the DBA converter; The ma#imum output analog voltage is
nearly equal to V
ref
; The actual values of 7307 resistors influence only the ma#imum
current handled by the op3amp; Voltage resolution of n3bit ladder networC DA( is V
ref
B0
n
Q.1! With relevant diagram e#plain the worCing of master3slave EF flip flop; ()
Ans:
)0s/+$=S10*+ J-K 6LI'=6LO': A master3slave 9:; 2@<632@86 is a cascade of two
S:
R 2@<632@86A; 8ne of them is Cnown as 9aster and the other one is slave; 2ig;11)a*
shows the logic circuit; The master is positively clocCed; Due to the presence of
inverter, the slave is negatively clocCed; This means that when clocC is high, the master
is active and the slave is inactive;
When the clocC is low, the master is inactive and the slave is active; 2ig;11)b* shows the
symbol; This is a level clocCed 2lip32lop; When clocC is high, any changes in E and F
inputs can affect A and 7 outputs; Therefore, E and F are Cept constant during positive
half of clocC; When clocC is low, the master is inactive and E and F inputs can be allowed
to be changed; The different conditions are Aet, 7eset, and Toggle; The race condition is
avoided because of feedbacC from slave to master and the slave being inactive during
positive half of clocC;
(,) SET S/0/+H Assume that G is low )and 7 is high*; 2or high E, low F and high
(@F, the 9aster goes to A5T state giving 1igh A and @ow 7; Aince Alave is
inactive, G and 7 do not change; When (@F becomes @ow, the Alave becomes to
Aet state giving 1igh G )and low 7 *;
(,,) &ESET S/0/+H At the end of Aet Atate G is 1igh )and 7 low*; Now if E is low, F is
high and (@F is high, the 9aster 7esets giving @ow A and 1igh 7; G and 7 do
not change because Alave is inactive; When (@F becomes @ow, the Alave becomes
active and resets giving @ow G )and 1igh 7 *;
"'
M * S
< * 2
F F
D E ! D I % IT A L S ELE C T & O N I CS
(,,,) T#771+ S/0/+: <f both E and F are 1igh, the Alave copies the 9aster; When (@F is
1igh, the 9aster toggles once; Then the Alave toggles once when (@F is low; <f the
9aster toggles into Aet state, the slave copies the 9aster and toggles into Aet state; <f the
9aster toggles into 7eset state, the slave again copies the 9aster and toggles into 7eset
state; Aince the second 2@<632@86 simply follows the first one, it is referred to as the
.la<# and the first one as the ma."#!. 1ence, this configuration is referred to as ma."#!:
.la<#5):S) F=I>:2@86;
Truth Table of EF 9aster Alave 2lip32lop in Table 11;1 shows that a @ow 67 and @ow
(@7 can cause race condition; Therefore, 67 and (@7 are Cept 1igh when inactive; To
clear, we maCe (@7 @ow and to preset we maCe 67 @ow; <n both cases we change them
to 1igh when the system is to be run;
@ow E and @ow F produce inactive state irrespective of clocC input; <f F goes 1igh, the
ne#t clocC pulse resets the 2lip32lop; <f E goes 1igh by itself, the ne#t clocC pulse sets the
2lip32lop; When both E and F are 1igh, each clocC pulse produces one toggle;
P5
S
<
%
C L2
2
2AS.,-
SLA1,
0
%
-
C L5
_
CL2
6,7.11(0) L#7,. D,07$03 #- )0s/+$=S10*+ F=B 6LI'=6LO'
P4
< =
C L2
_
2
=
C 4
6,7.11(4) L#7,. S534#1 #- )0s/+$=S10*+ F=B 6LI'=6LO'
"$
D E ! D I % IT A L S ELE C T & O N I CS
In;2/s O2/;2/
67 (@7 (@F E F G
0 0 . . . 7ace (ondition
0 1 . . . 1
1 0 . . . 0
1 1 . 0 0 No change
1 1 0 1 0
1 1 1 0 1
1 1 1 1 Toggle
T041+ 11.1 T$2/9 T041+ #- FB )0s/+$=S10*+ 61,;=61#;
Q.11 (ompare the memory devices 7A9 and 789; (5)
Ans:
(omparison of Aemi3conductor 9emories 789 and 7A9
T9+ 08*0n/07+s #- &O) 0$+:
1; <t is cheaper than 7A9;
0; <t is non3volatile; Therefore, the contents are not lost when power is switched off;
;<t is available in larger siDes than 7A9; K
'; <tKs contents are always Cnown and can be easily tested;
$; <t does not require refreshing;
!; There is no chance of any accidental change in its contents;
T9+ 08*0n/07+s #- &A) 0$+H
1; <t can be updated and replaced;
0; <t can serve as temporary data storage;
; <t does not require lead time )as in 789* or programming time )as in 6789*;
'; <t does not require any programming equipment
Q.12 Atate and prove Demorgan>s laws; (5)
Ans:
D+ )#$70nJs T9+#$+3s:
(,) S/0/+3+n/ #- 6,$s/ T9+#$+3: A + B = A
.
B
'$##-: The two sides of the equation
in fig; )a* O )b*
A + B =
AB
is represented by logic diagrams shown
"!
B
D E ! D I % IT A L S ELE C T & O N I CS
_
A
A
A
A + B
B
_
_
B
A + B
B
_ _
A . B
6,7.3(0) L#7,. 8,07$03 -#$
A + B 6,7.3(4) L#7,. 8,07$03 -#$ AB
The equality of the logic diagrams of fig; )a* O )b* is proved by the truth table shown in
table 0)c*
In;2/s In/+$3+8,0/+ V012+s O2/;2/s
A , A - ,
A B A + B A B
0 0 0 1 1 1 1
0 1 1 1 0 0 0
1 0 1 0 1 0 0
1 1 1 0 0 0 0
T041+ 2(.)
(,,) S/0/+3+n/ #- s+.#n8 /9+#$+3:
AB = A + B
'$##-: The two sides of the equation
shown in fig;)c* O )d*;
AB = A + B is represented by the logic diagrams
_
A
A
A
A . B
B
_
A . B
B
_ _
A + B
6,7.3(.) L#7,. 8,07$03 -#$ AB 6,7.3(8) L#7,. 8,07$03 -#$
A + B
The equality of the logic diagrams of fig;)c* O )d* is proved by the truth table shown in
table 0)d*
In;2/s In/+$3+8,0/+ V012+s O2/;2/s
A , A ;,
A B A;B A - B
0 0 0 1 1 1 1
0 1 0 1 0 1 1
1 0 0 0 1 1 1
1 1 1 0 0 0 0
T041+ 2(8)
Q.13 Discuss in detail, the worCing of 2ull Adder logic circuit and e#tend your discussion to
e#plain a binary adder, which can be used to add two binary numbers; (14)
"%
A
n
,
n
1 1
1 1
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
6211=A88+$: A half3adder has only two inputs and there is no provision to add a carry
from the lower order bits when multibit addition is performed; 2or this purpose, a third
input terminal is added and this circuit is used to add A
n
, ,
n
, and (
n31
, where A
n
and ,
n
are the nth order bits of the numbers, A and , respectively and (
n31
is the carry
generated from the addition of )n31*th order bits; This circuit is referred to as full3
adder and its truth table is given in Table $;1
<nputs 8utputs
A
n
,
n
(
n31
A
n
(
n
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
T041+ 5.1 T$2/9 T041+ #- 0 6211=A88+$
The F3maps for the outputs A
n
and (
n
are given in 2ig;$)a* and 2ig;$)b* respectively
and the minimiDed e#pressions are given by
A
n
+
A
n
,
n
C
n
1
- A
n
B
n
(
n31
- A
n
B
n
C
n 1
- A
n
,
n
(
n31
(
n
+ A
n
,
n
- ,
n
(
n31
- A
n
(
n31
A
n
B
n A
n
,
n
A
n
,
n
A
n
,
n
(
n31
(
n31
6,7.5(0) B=30; -#$ S
n
6,7.5(4) B=30; -#$ C
n
""
D E ! D I % IT A L S ELE C T & O N I CS
The logic diagrams for the An and (n are shown in fig;$)c* O fig;$)d*;
A
)
B
) C
)*1
S
n
6,7.5(.) NAND=NAND &+01,D0/,#n #- S
n
A
)
B
)
C
C
n
)*1
A
)
C
)*1
6,7.5(8) NAND=NAND &+01,D0/,#n #- C
n
B,n0$5 A88+$: The full adder forms the sum of two bits and a previous carry; Two binary
numbers of n bits each can be added by means of ,inary Adder; <f A + 1011 and , + 0011,
whose sum is A + 1110; When pair of bits is added through a full3adder, the circuit produces a
carry to be used with the pair of bits one significant position higher; This is shown in Table $;0
The bits are added with full3adders, starting from the @east Aignificant 6osition )subscript 1*,
to form the sum bit and carry bit; The input carry (1 in the @east Aignificant position must be
0; The value of (
i-1
in a given significant position is the output carry of the full3adder; This
value is transferred into the input carry of the full3adder that adds the bits one higher
significant position to the left; The sum bits are thus generated starting form the rightmost
position and are available as soon as the corresponding previous carry bit is generated
Aubscript i ' 0 1 2ull3Adder
<nput (arry 0 1 1 0 (
i
U
Augend 1 0 1 1 A
i
.
Addend 0 0 1 1 ,
i
J
Aum 1 1 1 0 A
i
A
8utput (arry 0 0 1 1 (
i-1
(
T041+ 5.2 T$2/9 T041+ -#$ B,n0$5 A88+$
"&
C
1
S
D E ! D I % IT A L S ELE C T & O N I CS
A ,inary 6arallel Adder is a digital function that produces the arithmetic sum of two binary
numbers in parallel; <t consists of full3adders connected in cascade, with the output carry from
one full3adder connected to the input carry of the ne#t full3adder; 2ig;$)e* shows a '3bit ,inary
6arallel Adder; The augend bits of A and the addend bits of the , are designated by subscript
numbers from right to left, with subscript 1 denoting the low3order bit; The carries are
connected in a chain through the full3adders; The input carry to the adder is (
1
and the output
carry is (
$
; The A outputs generate the required sum bits;
B
4
A
4
B
3
A
3
B
2
A
2
B
1
A
1
C
C
FU LL 4
5
AD D05
FU LL
AD D05
C
3
FU LL
AD D05
2
FU LL
C
AD D05
S
4
S
3
S
2
1
6,7.5(+) 4=4,/ B,n0$5 '0$011+1 A88+$ 2s,n7 6211=A88+$s
Q.14 What is a decoder4 Draw the logic circuit of a line to " line decoder and e#plain its
worCing; (7)
Ans:
D+.#8+$: A Decoder is a combinational logic circuit that converts ,inary words into
alphanumeric characters; Thus the inputs to a decoder are the bits 1, 0 and their
combinations; The output is the corresponding decimal number; <t converts binary
information from n input lines to a ma#imum of 0
n
unique output lines; <f the n:6,"
decoded information has unused or donKt3care combinations, the decoder output will
have less than 0
n
outputs;
G#$E,n7H The logic circuit of a line to " line decoder is shown in fig;! )a*; The three
inputs )#, y, D* are decoded into eight outputs )from D
0
to D
%
*, each output representing
one of the minterms of the 3input variables; The three inverters provide the complement
of the inputs, and each one of the eight AND gates generate one of the minterms; A
particular application of this decoder is a binary3to3octal conversion; The input variables
may represent a binary number, and the outputs will then represent the eight digits in the
octal number system; 1owever, a 3to3" line decoder can be used for decoding any 3bit
code to provide eight outputs, one for each element of the code;
The operation of the decoder may be verified from its input3output relationships shown in
Table !;1;The table shows that the output variables are mutually e#clusive because only
one output can be equal to 1 at any one time; (onsider the case when .+0, J+0 and U+0,
the output line D
0
).>, J>, U>* is equal to 1 represents the minterm equivalent of the binary
number presently available in the input lines;
&0
D E ! D I % IT A L S ELE C T & O N I CS
In;2/s
? > K
O2/;2/s
D
!
D
1
D
2
D
3
D
4
D
5
D
6
D
7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
T041+ 6.1 T$2/9 T041+ #- 3=/#=8 1,n+ D+.#8+$
D 3 45 Y5 65
0
D 3 45 Y5 6
1
D 3 45 Y 65
2
> D 3 45 Y 6
3
D 3 4 Y5 65
Y
4
X
D 3 4 Y5 6

D 3 4 Y 65
!
D 3 4 Y 6
"
6,7. 6(0) L#7,. C,$.2,/ #- 3=/#=8 1,n+ D+.#8+$
Q.15 What is an encoder4 Draw the logic circuit of Decimal to ,(D encoder and e#plain its
worCing; (7)
&1
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
En.#8+$H An 5ncoder is a combinational logic circuit which converts Alphanumeric
characters into ,inary codes; <t has 0n )or less* input lines and n output lines; An
5ncoder may be Decimal to ,inary, 1e#adecimal to ,inary, 8ctal to ,(D
etc;
D+.,301 /# BCD En.#8+$: This encoder has 10 inputs )for decimal numbers 0 to p*
and ' outputs for the ,(D number; Thus it is a 10 line to ' line encoder; Table !)a*
lists the decimal digits and the equivalent ,(D numbers; 2rom the table, we can find
the relationship between decimal digit and ,(D bit; 9A, of ,(D bit is J

; 2or
decimal digits " or &, Y
3
+ 1; Thus we can write 87 e#pression for Y
3
bit as
Y
3
+ " - &
Aimilarly , ,it Y
2
is 1 for decimal digits ',$,! and %; Thus we can write
87
e#pression
Y
2
+ ' - $ - ! - %
Y
1
+ 0 - - ! - %
Y
o
+ 1 - - $ - % - &
The logic circuit for the e#pressions )J0, J1, J0, J* is shown in fig; !)b*; When a 1igh
appears on any of input lines the corresponding 87 gates give the ,(D output; 2or #.3.,
if decimal input is ", 1igh appears only on output )and @8W on Y
0
, Y
1
, Y
2
), thus giving
the ,(D code for decimal " as 1000; Aimilarly, if decimal input is %, then 1igh appears
on outputs Y
0
, Y
1
, Y
2
)and @8W on Y3), thus giving ,(D output as 0111;
D+.,301
D,7,/
BCD C#8+
>
3
>
2
>
1
>
!
0 0 0 0 0
1 0 0 0 1
0 0 0 1 0
0 0 1 1
' 0 1 0 0
$ 0 1 0 1
! 0 1 1 0
% 0 1 1 1
" 1 0 0 0
& 1 0 0 1
&0
D E ! D I % IT A L S ELE C T & O N I CS
1
Y 7 LSB 8
0
2
3
Y
1
4
5
6
Y
2
7
8
+
Y 7 2 SB 8
3
6,7.6(4) L#7,. 8,07$03 -#$ D+.,301 /# BCD En.#8+$
Q.16 What is a flip3flop4 What is the difference between a latch and a flip3flop4 @ist out the
application of flip3flop; (4)
Ans:
61,;=61#;: A flip3flop is a basic memory element used to store one bit of information; ,oth
2lip3flops and latches are bistable logic circuits and can reside in any of the two stable
states due to a feedbacC arrangement; The main difference between them is in the method
used for changing the state;
A;;1,.0/,#ns #- 61#;=61#;s:
)1* ,ounce elimination switch
)0* 6arallel Data Atorage in 7egisters
)* Transfer of Data from one bit to another;
)'* (ounters
)$* 2requency Division
Q.17 Draw the circuit diagram of a 9aster3slave E3F flip3flop using NAND gates; What is race
around condition4 1ow is it eliminated in a 9aster3slave E3F flip3flop; (1!)
Ans:
L#7,. D,07$03 #- )0s/+$=S10*+ F=B 61,;=61#; 2s,n7 NAND %0/+s: 2ig;%)a* shows
the logic diagram of 9aster3Alave E3F 2lip32lop using NAND gates;
&
M
D E ! D I % IT A L S ELE C T & O N I CS
P5
,
3M
,
1M
= S
M S
<
,
3S ,
1S
%
C L2
2
2AS.,-
SLA1,
0
%
,
4M
C L5
_ -
S ,
,
2S
,
2M
= 4S
_
CL2
6,7.7(0) L#7,. D,07$03 #- )0s/+$=S10*+ F=B 6LI'=6LO'
T9 + &0 .+ =0 $ # 2n 8 C# n8, /, # n : The difficulty of both inputs 1 )A + R + <* being not allowed
in an S:R 2lip32lop is eliminated in a 9:; Fl,-:Flo- by using the feedbacC connection from
outputs to the inputs of the gates; <n 73A 2lip32lop, the inputs do not change during the clocC
pulse 5C; + 1*, which is not true in E3F 2lip32lop because of the feedbacC connections;
(onsider that the inputs are 9 + ; + 1 and 7 + 0 and a pulse as shown in 2ig; %)b* is applied
at the clocC input; After a time interval bt equal to the propagation delay through two
NAND gates in series, the output will change to 7 + 1;
Now we have 9 + ; + 1 and 7 + 1 and after another time interval of bt the output will
change bacC to 7 + 8; 1ence, for the duration "
-
of the clocC pulse, the output will oscillate
bacC and forth between 0 and 1; At the end of the clocC pulse, the value of 7 is uncertain;
This situation is referred to as the race3around condition.The race3around condition can be
avoided if "
-
L bt L $. 1owever, it may be difficult to satisfy this inequality because of very
small propagation delays in <(s; A more practical method of overcoming this difficulty is
the use of the master3slave 5):S) configuration;
1 5AIL IN, (N0,A1 I
60) 0D,0
L0ADI N, (POSI1 I
60) 0D,0
'
P
0 1
6,7.7 (4) 0 C1#.E '21s+
A master3slave E3F 2lip32lop is a cascade of two A37 2lip32lops with feedbacC from the
outputs of the second to the inputs to the first as illustrated in 2ig;%)a*; 6ositive clocC pulses
are applied to the first 2lip32lop and the clocC pulses are inverted before these are applied
to the second 2lip32lop; When (F+1, the first 2lip32lop is enabled and the outputs G
9
and
7
)
respond to their inputs E and F according the Table %;1; At this time, the second 2lip3
2lop is inhibited because its clocC is @8W ) C; + 0*; When (F goes @8W ) C; + 1*,
the first 2lip32lop is inhibited and the second 2lip32lop is enabled, because now its clocC
is
1<?1 ) C; + 1*; Therefore, the outputs G and 7 2ollow the outputs G
9
and 7
)
respective )second and third rows of Table %;1*; Aince the second 2lip32lop simply follows
the first one, it is referred to as the Alave and the first one as the 9aster; 1ence, this
&'
D E ! D I % IT A L S ELE C T & O N I CS
configuration is referred to as 9aster3Alave 2lip32lop; <n this circuit, the inputs to the gates
?
9
and ?
'9
do not change during the clocC pulse, therefore the 7ace3around condition
does not e#ist; The state of the 9aster3Alave 2lip32lop changes at the negative transition
)trailing end*;
In;2/s O2/;2/
67 (@7 (@F E F G
0 0 . . . 7ace (ondition
0 1 . . . 1
1 0 . . . 0
1 1 . 0 0 No change
1 1 0 1 0
1 1 1 0 1
1 1 1 1 Toggle
T041+ 7.1 T$2/9 T041+ #- FB )0s/+$=S10*+ 61,;=61#;
Q.18 What is a demultiple#er4 Discuss the differences between a demultiple#er and a decoder; (4)
Ans:
D+321/,;1+:+$: <t is a logic circuit that accepts one data input and distributes it over
several outputs; A demultiple#er has one data input, m select lines, and n output lines,
whereas a decoder does not have the data input but the select lines are used as input lines;
Q.1 What is a shift register4 (an a shift register be used as a counter4 <f yes, e#plain how4 (4)
Ans:
S9,-/ &+7,s/+$: A register in which data gets shifted towards left or right when clocC pulses
are applied is Cnown as a Ahift 7egister; A shift register can be used as a counter; <f the
output of a shift register is fed bacC to serial input, then the shift register can be used as a
7ing (ounter;
Q.2! What are synchronous counters4 Design a 9od3$ synchronous counter using E3F 2lip32lops;
(1!)
Ans:
&$
D E ! D I % IT A L S ELE C T & O N I CS
S5n.9$#n#2s C#2n/+$s: The term synchronous means that all flip3flops are clocCed
simultaneously; The clocC pulses drive the clocC input of all the flip3flops together so
that there is no propagation delay;
)#8=5 C#2n/+$ S5n.9$#n#2s C#2n/+$: The 9od3$ Aynchronous (ounter have five
counter states; The counter design table for this counter lists the three flip3flop and
their states )0 to $ states*, as shown in table &)a*, the si# inputs required for the three
flip3flops; The flip3flop inputs required to step up the counter from the present to the
ne#t state have been worCed out with the help of the e#citation table shown in the
table;
In;2/
;21s+
C#2n/
C#2n/+$ S/0/+s
A , (
61,;=61#; In;2/s
E
A
F
A
E
,
F
,
E
(
F
(
0 0 0 0 1 . 0 . 0 .
1 1 0 0 . 1 1 . 0 .
0 0 1 0 1 . . 0 0 .
1 1 0 . 1 . 1 1 .
' 0 0 1 0 . 0 . . 1
$)0* 0 0 0
T041+ (0) .#2n/+$ D+s,7n T041+ -#$ )#8=5 C#2n/+$
A -1,;=-1#;: The initial state is 0; <t changes to 1 after the clocC pulse; Therefore E
A
should be 1 and ;
A
may be 0 or 1 )that is . *;
B -1,;=-1#;: The initial state is 0 and it remains unchanged after the clocC pulse;
Therefore 9
B
should be 0 and ;
B
may be 0 or 1 )that is .*
C -1,;=-1#;: The state remains unchanged; Therefore 9c should be 0 and ;
C
should be
.;The flip3flop input values are entered in Farnaugh maps shown in Table &)b* M)i*
)ii* )iii* )iv* )v* and )vi*N and a boolean e#pression is found for the inputs to the three
flip3flops and then each e#pression is simplified; A. all the counter states have not
been utiliDed, .>s )donKt* are entered to denote un3utiliDed states; The simplified
e#pressions for each input shown under each map; 2inally, these minimal e#pressions
for the flip3flop inputs are used to draw a logic diagram for the counter, which is
shown in fig;& )b*;
&!
D E ! D I % IT A L S ELE C T & O N I CS
(,) )0; -#$ F
A
(,,) )0; -#$ B
A
F
A
= C B
A
= 1
(,,,) )0; -#$ F
B
(,*) )0; -#$ B
B
F
B
= A B
B
= A
(*) )0; -#$ F
C
(*,) )0; -#$ B
C
F
C
= AB B
C
= 1
T041+ (4) B0$n0279 )0;s -#$ )OD=5 S5n.9$#n#2s C#2n/+$
A B
C
(
A
A (
B B
(
C
C
CLOC)
FF FF
FF
*+LS,S A
0
1 )
A A
B
0
)
B B
C
0
1
)
C
C
6,7. (4) L#7,. D,07$03 #- )OD=5 S5n.9$#n#2s C#2n/+$
&%
+-
D E ! D I % IT A L S ELE C T & O N I CS
Q.21 With the help of a neat diagram, e#plain the worCing of a successive appro#imation ABD
converter; (14)
Ans:
S2..+ss,*+ A;;$#:,30/,#n ADC:
This is the most widely used ABD converter; As the name suggests, the digital output tends
towards analog input through successive appro#imations; <n Auccessive Appro#imation
AD(, the comparison with the input analog voltage is done in descending order starting
from ma#imum voltage; 2ig;10 )a* shows the blocC diagram of AA ABD converter; The
main components are 8p3amp (omparator, (ontrol @ogic, AA register and DBA converter;
<t uses Digital to Analog converter as a feedbacC element; The control logic is the most
important part of Auccessive Appro#imation (onverter, as this decides the ne#t step to be
taCen; The ring counter provides timing waveform to control the operation of the converter;
The Digital to Analog (onverter unit, n bit register and ring counter are all reset by the first
pulse from the ring counter; The ring counter containing a single one sets the 9A, of the
Digital to Analog (onverter to 1 and the other to 0
5()?
C7/)'$4
C %7& @
-----------------
-
C7)'47%
% 7?(&
6
7 ---------
6
()
6
#
) * A('
4$?("'$
4
----------
-
0
-
*************
1
S ; :
A)-%7?
( )./'
D ; A
&7)B$4'$
4
-
) * 2
-
) * 1
6,7.1! (0) B1#.E D,07$03 #- S2..+ss,*+ A;;$#:,30/,#n AHD C#n*+$/+$
The basic operating principle of Auccessive Appro#imation (onverter is that the voltage
ouput of DA( corresponding to 9A, is compared by the comparator with the input voltage
and if the voltage is less, the bit 1 is retained; <f the voltage is more, it is reset to 0 and
counter moves to ne#t position; Aimilar decisions are made at each bit position until the
nearest value is reached;
&"
D E ! D I % IT A L S ELE C T & O N I CS
Assume that the 9A, of a unipolar ! bit converter produces 10 V output and we have to
measure an analog output voltage of ";0 V; 5ach bit divides the voltage by 0 so that the
voltages for the ! bits from 9A, downwards is
,its $ ' 0 1 0
Voltage 10 $ 0;$ 1;0$ 0;!0$ 0;10$
9A, @A,
The operation of AA ABD converter is shown in Table No;10)a*; @et the analog input be
";0 V; The AA register is first set to Dero; Then 10 is placed in 9A,; This is fed to DBA
converter whose output goes to comparator; Aince the analog input )";0 V* is greater than
DBA output )i;e;,10 V*, the 9A, is set to one; Then 1 is placed in bit ne#t to 9A, )i;e;, 1 is
placed in second position*; Now the output of DBA is $ V; Aince analog input is less than $
V, it is reset to 0; Ne#t 0 is placed in third position; Now the DBA output is )$-0;$+%;$V*
which is less than analog input; Therefore, this 0 bit is retained and 0 is placed in the ne#t
bit )i;e;, fourth position*; Now the DBA output is )%;$-1;0$+";%$*, which is more than
analog input; Therefore, the 1 bit is placed in fifth position; Now the DBA output is
)";%$-0;!0$+";10$* which is less than analog input, it is reset to 0; Now 0 is placed in @A,
producing a DBA output of )";10$-0;10$+";'%$* which is more than analog input;
Therefore, @A, is set to one;
The various steps and voltages are tabulated in Table No;10 )a*;
S/+; &+7,s/+$ DAC O2/;2/ C#3;0$0/#$ 8+.,s,#n
C.$./ 8.2V.
Atart
0

'
$
!
100000
010000
011000
011100
011010
011011
10
$
$-0;$+%;$
%;$-1;0$+";%$
%;$-0;!0$+";10$
";10$-0;10$+";'%$
1igh
@ow
@ow
1igh
@ow
1igh
T041+ 1!(0)
The DBA converter waveform is shown in fig;10 )b*
&&
D E ! D I % IT A L S ELE C T & O N I CS
10
+
8
7
6
5
0 1 1
4
0 1 0
3
2
1
0
6+0/2$+s:
6,7.1! (4) O2/;2/ G0*+-#$3 #- DHA C#n*+$/+$
)i* <t is one of the most widely used AD(
)ii* <ts conversion time is very ne#t only to 2lash or 6arallel
AD(
)iii* AA(s have fi#ed value of conversion time that is not dependent on the value of analog
input voltage;
)iv* Data can be taCen out either in serial or in parallel;
)v* During the period of comparison the input analog voltage should be held constant and
so the input to comparator is through a Aample 1old circuit;
Q.22 Difference between static and dynamic 7A9; Draw the circuits of one cell of each and e#plain
its worCing; (1!)
Ans:
D,--+$+n/,0/,#n 4+/C++n S/0/,. &A) 0n8 D5n03,. &A):
Atatic 7A9s store ones and Deros using conventional 2@<632@86s; whereas, the memory
cells of dynamic 7A9s are basically charge storage capacitors with driver transistors;The
presence or absence of charge in a capacitor is interpreted as @ogic1 or 0;
Atatic 7A9s do not require refreshing because there is no problem of charge leaCing3off in
2@<632@86s whereas Dynamic 7A9s require periodic charge refreshing to maintain data
storage because the charge stored on capacitors leaC3off with time;
Atatic 7A9s are slower but easier to drive than dynamic memories, which generally require
clocC signals in addition to e#tra power supplies whereas dynamic circuits usually require
e#ternally generated clocC voltages,
A8*0n/07+s #- S/0/,. &A)s #*+$ D5n03,. &A)s:
)i*1igher speed of operation )faster*i;e, lower access /time;
)ii*Does not require refreshing;
A8*0n/07+s #- S/0/,. &A)s #*+$ D5n03,. &A)s:
)i*1igher number of bits storage on a given silicon chip area; i;e, 1igher pacCaging
density;
)ii*@ower power consumption;
100
D E ! D I % IT A L S ELE C T & O N I CS
S/0/,. &A) C+11: A 7A9 memory cell consisting of two cross3coupled 98A inverters is
shown in 2ig;11 )a*; <t is addressed by setting A
.
and A
J
to 1; When A
.
+ 1, the cell is
connects to the data and 1a"a line; When A
J
+ 1, T
%
and T
"
are 8N;
To write into the cell, set W + 1, T
&
becomes 8N; <f data input is 1, the voltage at node D
will correspond to level 1 maCing T

8N and level at D will be 0; 8n the other hand, if the
data input is at logic 0, then T

will be 822 and D would be at 1; To read the state of the
2@<632@86, we set 7 + 1;This connects the data output to D ; Thus, the complement of the
data level written into the cell is read at 1a"a output;
A
X 6
DD
17 7'C$4 &$%%"
D('C "-3$ A
X
17 7'C$4 &$%%"
D('C "-3$ A
1
Y 2
6
,,
1
4
17 7'C$4 &$%%"
D('C "-3$ A
Y
D -'- %()$ 1 1
_
D -'- %()$
5
D D
6
1
1
1
3
94 ('$ ( 9)
5 $-8 ( 5)
1
7
D -'-
I)./'
1
+

1
8
1
10
A
Y
D -'-
O/'./'
6,7.11(0) L#7,. D,07$03 #- 0 S/0/,. )OS &A) C+11
D5n03,. &A) C+11: A dynamic cell uses four transistors in place of the si# used in a static
cell; This reduces the silicon chip area and results in saving of power; The circuit of a '3
transistor dynamic 98A 7A9 cell is shown in 2ig;11 )b*;The state of the cell is stored on
the stray capacitances (
1
and (
0
, whose presence is essential; The cell is addressed by
maCing A
.
+ A
J
+1; <n one state of the cell, the voltage across (
1
is large and T
1
is
8N; (orrespondingly, (
0
has Dero voltage and T
0
is 822; <n the other state, the voltages
on (
1
and (
0
and the conducting states of T
1
and T
0
are reversed; 2or writing into the cell,
we set W + 1 and for reading from the cell we set 7 + 1;<t is necessary to refresh
the cell periodically, otherwise the charge stored on the capacitors leaC off; The refreshing
operation is accomplished by allowing brief access from the supply voltage V
DD
to the
cell; This is done by maCing A
.
+ 1 and the refresh terminal voltage corresponding to 1
level; This maCes T

, T
'
, T
&
, and T
10
8N; Auppose initially T
1
is 8N, T
0
is 822; The
voltage across (
1
is large and across (
0
it is Dero volt; During the refresh interval, V
DD
is
applied through T
10
and T
'
to (
1
, since T
0
is 822; Therefore, current from V
DD
will flow
through (
1
, allowing (
1
to replenish any charge lost due to leaCage; Aince T1 is 8N, hence
(
0
will not charge as rapidly as (
1
; Aimilarly V
DD
is applied to (
0
, which is in parallel to
T
1
when T
1
is 822 and T
0
is 8N;
101
9
2
D E ! D I % IT A L S ELE C T & O N I CS
17 7'C$4 &$%%"
5 $#4 $"
C
17 7'C$4 &$%%"
6
DD
1 1
+ 10
A
X
17 7'C$4 &$%%"
D -'- %()$
1
1
D -'- %()$
3
4
1
1
1
2
C
1
C
5
1
5
D -'-
1
6
D -'-
1 1
I)./'
7
A
Y
8
I)./'
6,7.11(4) L#7,. D,07$03 #- D5n03,. )OS &A) C+11
Q.23 Distinguish between 789, 6789, 56789, 556789; (4)
Ans:
&O): 7ead 8nly 9emory is a 6ermanent 9emory; <n 6ermanent 789, the data is
permanently stored and cannot be changed; <t can only be read from the memory; There
cannot be a write operation because the specified data is programmed into the device by
the manufacturer or the user; 789 is a Non3volatile memory; Aome e#amples of 789 are
conversion tables, pre3programmed instructions etc;
'&O): 6rogrammable 7ead 8nly 9emory allows user to store the data; An instrument
6789 programmer is used to store the required data; The process used is opening the
linCs at bit locations using high current )this process is called burning in*; 8nce this
process has been done, the data is permanently stored and no change is possible;
E'&O): 56789 means 5rasable 6789; <t can be reprogrammed by first erasing the
e#isting program; 56789 uses N398A25T array with isolated gate structure; The
isolated transistor gate has no electrical connection and can store an electrical charge
indefinitely; The data bits in this memory array are represented by presence or absence of
charge; 5rasure is achieved by removing the gate charge; 56789 can be :V 56789 or
556789;
UV E'&O) means :ltra Violet 5rasable 6789; 5rasure is achieved by using ultra
violet light; The light passes through a window in the <( pacCage to the chip where there
are stored charges; Thus the stored contents are erased;
EE'&O): 556789 means 5lectrically 5rasable 6789; <n this memory device,
the erasure and programming is done by electrical pulses;
Q.24 What is a universal gate4 ?ive e#amples; 7ealiDe the basic gates with any one universal gate;
(8)
100
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
Un,*+$s01 %0/+sH NAND and N87 are Cnown as :niversal gates The AND, 87, N8T
gates can be realiDed using any of these two gates; The entire logic system can be
implemented by using any of these two gates; These gates are easier to realiDe and
consume less power than other gates;
&+01,D0/,#ns #- NOT" AND 0n8 O& 70/+s 2s,n7 NAND 70/+s
NOT %ATEH 2ig; )a* shows the realiDation of <nverter )N8T* gate using NAND gate;
,oth the inputs to the NAND gates are tied together so that the gate worCs as an inverter
)N8T* gate;
_
A
A
6,7. 3(0) &+01,D0/,#n #- In*+$/+$ (NOT) 70/+ 2s,n7 NAND 70/+
AND %ATE: 2ig; )b* shows the realiDation of AND gate using two NAND gates; <t has
combination of two NAND gates gives AND operation; The first NAND gate has two
i nputs A and ,; The two inputs to the second NAND gate are tied together and the
output
AB
of the first gate is fed to this common terminal; The output is A, thus giving
AND operation;
A
AB
B
;
AB = AB
6,7. 3(4) &+01,D0/,#n #- AND 70/+ 2s,n7 NAND 70/+s
O& %ATEH 2ig; )c* shows the realiDation of 87 gate using NAND gates; The two inputs
from each of the first two NAND gates are tied together and fed by A and , as shown in the
figure; The outputs are A and B ; They are fed to as inputs to third NAND gate; The final
output is A 87 , thus giving 87 operation;
_
A
A
_
_ _
_
A B = A +
B B
6,7. 3(.) &+01,D0/,#n #- O& 70/+ 2s,n7 NAND 70/+s
Q.25 ?ive the circuit of a TT@ NAND gate and e#plain its operation in brief; (6)
Ans:
O;+$0/,#n #- TTL NAND %0/+: 2ig;)d* shows a TT@ NAND gate with a totem pole
output; The totem pole output means that transistor T
'
sits atop T

so as to give low
output impedance; The low output impedance implies a short time constant 7( so that the
10
D E ! D I % IT A L S ELE C T & O N I CS
output can change quicCly from one state to another; T
1
is a multiple emitter transistor;
This transistor can be thought of as a combination of many transistors with a common base
and collector; 9ultiple emitter transistors with about !0 emitters have been developed; <n
the figure, T
1
has emitters so that there can be three inputs A, ,, (; The transistor T
0
acts as a phase splitter because the emitter voltage is out of phase with the collector
voltage; The transistors T

and T
'
from the totem pole output, The capacitance (@
represents the stray capacitance etc; The diode D is added to ensure that T
'
is cut off
when output is low; The voltage drop of diode D Ceeps the base3emitter Qunction of T
'
reverse biased so that only T

conducts when output is low; The operation can be
e#plained briefly by three conditions as given belowH
C#n8,/,#n 1: At least one input is low )i;e;, 0*; Transistor T
1
saturates; Therefore, the base
voltage of T
0
is almost Dero; T
0
is cut off and forces T

to cut off; T
'
acts liCe an
emitter follower and couples a high voltage to load; 8utput is high )i;e; J+1*;
C#n8,/,#n 2: All inputs are high; The emitter base Qunctions of T
1
are reverse biased; The
collector base Qunction of T
1
is forward biased; Thus, T
1
is in reverse active mode; The
collector current of T1 flows in reverse direction; Aince this current is flowing into the base
of T
0
, the transistors T
0
and T

saturate and output J is low;
C#n8,/,#n 3: The circuit is operating under << when one of the input becomes low; The
corresponding emitter base Qunction of T
1
starts conducting and its base voltage drops to a
low value; Therefore, T
1
is in forward active mode; The high collector current of T
1
removes the stored charge in T
0
and T

and therefore, T
0
and T

go to cutoff and T
1
saturates and output J returns to high;
6 = + 56
&&
10 0 OC3 "
4 2 OC3 "
1. 4 2 OC 3"
1
4
1 1
2
D(7 8$
A
C
Y
.
.
1
3
.
.
C
1 2OC3 "
L
.
.
.
.
;
6,7.3(8) L#7,. D,07$03 #- TTL NAND %0/+ C,/9 T#/+3 '#1+ O2/;2/
Q.26 With the help of a truth table e#plain the worCing of a half subtractor; Draw the logic diagram
using gates; (8)
10'
:AL F
SUB1 5AC1 O5
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
@01- S24/$0./#$: A logic circuit for the subtraction of , )subtrahend* from A )minuend*
where A and , are 13bit numbers is referred to as a 1alf3Aubtractor. The truth table for half
subtractor is given in Table No;$;1; 1ere A and , are the two inputs and D
i
)difference* and
,
o
)borrow* are the two outputs; <f , is larger than A )e;g;, A+0 and ,+1*, a borrow is
necessary,
In;2/s
A B
O2/;2/s
D
,
(D,--+$+n.+) B
#
(B#$$#C)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
T041+ 5.1
2rom the Truth Table, the logical e#pressions for D
i
and ,
o
are obtained as
D
i
+ A , - A B
,
8
+ A ,
A
D
B
(
A
D
(
B
B
B
7
7
6,7.5(0) L#7,. D,07$03 #- @01- S24/$0./#$ 6,7.5(4) B1#.E D,07$03 #- @01- S24/$0./#$
<n Table $;1, input variable B is subtracted from A to give output D
i
)difference*; <f , is
larger than A 5#.3., A + 0 and B + 1*, a borrow is necessary; <n the Truth Table, inputs
are A and B, 8utputs are D
,
)difference* an1 B
%
56o!!o?). 1ence, the
,oolean e#pressions for the half subtractor from the Truth Table can be written as
D
i
+ A , 333333333
)1* ,
8
+ A ,
33333333)0*
,y combining ,oolean 5#pressions )1* O )0*, we get the logic circuit for 1alf Aubtractor
shown in fig;$)a* and its blocC diagram is shown in fig;$)b*;
Q.27 Draw the logic diagram of a full subtractor using half subtractors and e#plain its worCing with
the help of a truth table; (6)
Ans:
10$
D E ! D I % IT A L S ELE C T & O N I CS
6211 S24/$0./#$: A 2ull Aubtractor has to taCe care of repeated borrow from the ne#t
higher bit; At any stage alongwith the two bits )one of which is to be subtracted from the
other* is another input ,
in
, i;e;, borrow bit from the D
i
and borrow ,
o
; Table shows the truth
table;
B
() D
FULL
(
INPU1S
A
B
SUB 1 5AC1
O5
OU1PU1S
B
7
6,7.5(.) B1#.E D,07$03 #- 6211 S24/$0./#$
B D
()
: ALF
(
D
(
SU B15AC 1O5
B
7
A
: ALF
B
7
SU B15AC 1O5 B
7
B
6,7.5(8) B1#.E D,07$03 #- 6211 S24/$0./#$ 0s C#34,n0/,#n #- /C# @01-
S24/$0./#$s 0n8 O& %0/+
B
()
&ALF
S+B.-AC.O-
&ALF S+B.-AC.O-
D
(
D
(
D
A
(
B
7
B
O- 'A.,
B
7
B
7
6,7.5(+) L#7,. D,07$03 #- 6211 S24/$0./#$
2ig;$)c* shows a blocC diagram for a full subtractor; <t can be constructed from two 1alf
Aubtractors and an 87 gate as shown in 2ig;$)d*; The logic diagram is shown in 2ig;$)e*;
This logic diagram is as per the truth table of Table $;1;
10!
BC D
1O
S060N S0,M 0N 1
D 0COD05
D E ! D I % IT A L S ELE C T & O N I CS
In;2/s O2/;2/s
A B B
,n
D
,
B
O
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
T041+ 5.1 T$2/9 T041+ -#$ 6211 S24/$0./#$
Q.28 Design a ,(D to seven segment decoder that accepts a decimal digit in ,(A and generates the
appropriate output for segments in display indicator;(14)
Ans:
BCD=TO=7=S+73+n/ D+.#8+$: A digital display that consists of seven @5D segments is
commonly used to display decimal numerals in digital systems; 9ost familiar e#amples are
electronic calculators and watches where one %3segment display device is used for
displaying one numeral 0 through &; 2or using this display device, the data has to be
converted from some binary code to the code required for the display; :sually the binary
code used is Natural ,(D; 2ig;!)a* shows the display device; 2ig;!)b* shows the segments
which must be illuminated for each of the numerals and 2ig;!)c* gives the display system;
-
# A
$
?
&
8
6,7.6(0) 6,7.6(4)
B
D
A -
-
A
B &
I
N
C
$
U
D
?
1
S
# A
$
?
&
8
6,7.6(.)
10%
D E ! D I % IT A L S ELE C T & O N I CS
Table !;1 gives the truth table of ,(D3to3%3segment Decoder; 1ere A,(D is the Natural ,(D
code for numerals 0 through &; The F3maps for each of the outputs a through g are given in
2ig;!)d*, !)f*,!)h*,!)Q*,!)l*,!)n*,!)p*; The entries in the F3map corresponding to si# binary
combinations not used in the truth table are . /don>t care;
D+.,301 D,7,/
D,s;105+8
In;2/s O2/;2/s
A B C D 0 4 . 8 + - 7
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
0 0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
' 0 1 0 0 0 1 1 0 0 1 1
$ 0 1 0 1 1 0 1 1 0 1 1
! 0 1 1 0 0 0 1 1 1 1 1
% 0 1 1 1 1 1 1 0 0 0 0
" 1 0 0 0 1 1 1 1 1 1 1
& 1 0 0 1 1 1 1 0 0 1 1
T041+ 6.1 T$2/9 T041+ #- BCD=/#=7 S+73+n/ D+.#8+$
(,) B=30; 0n8 L#7,. D,07$03 -#$ D,7,/01 O2/;2/ L0A:
10"
D E ! D I % IT A L S ELE C T & O N I CS
The simplified e#pressions for the 2ig;!)d* is given by a + B D - ,D - (D - A and the
logic diagram is given in 2ig;!)e*
_
B
_
D
B
9
D
C
D
_
A
6,7.6(+) L#7,. D,07$03 -#$ O2/;2/ L0A
(,,) B=30; 0n8 L#7,. D,07$03 -#$ D,7,/01 O2/;2/ L4A:
The simplified e#pressions for the 2ig;!)f* is given by b + B - C D - (D and the logic
diagram is given in 2ig;!)g*
_
C
_
D
:
C
D
B
6,7.6(7) L#7,. D,07$03 -#$ O2/;2/ L4A
(,,,) B=30; 0n8 L#7,. D,07$03 -#$ D,7,/01 O2/;2/ L.A:
10&
D E ! D I % IT A L S ELE C T & O N I CS
The simplified e#pressions for the 2ig;!)h* is given by c + B - C - D and the logic diagram is
given in 2ig;!)i*
_
B
C c
_
D
6,7.6(,) L#7,. D,07$03 -#$ O2/;2/ L . A
(,*) B=30; 0n8 L#7,. D,07$03 -#$ D,7,/01 O2/;2/L8A:
110
D E ! D I % IT A L S ELE C T & O N I CS
The simplified e#pressions for the 2ig;!)Q* is given by
d + B D - ( D - B ( -, C D and the logic diagram is given in 2ig;!)C*
_
B
_
D
C
_
D
_
;
B
C
B
_
C
D
6,7.6(E) L#7,. D,07$03 -#$ O2/;2/ L 8 A
(*) B=30; 0n8 L#7,. D,07$03 -#$ D,7,/01 O2/;2/ L+A:
The simplified e#pressions for the 2ig;!)l* is given by e + B D - ( D and the logic
diagram is given in 2ig;!)m*
_
B
_
D
e
C
_
D
6,7.6(3) L#7,. D,07$03 -#$ O2/;2/ L+A
111
D E ! D I % IT A L S ELE C T & O N I CS
(*,) B=30; 0n8 L#7,. D,07$03 -#$ D,7,/01 O2/;2/ L-A:
The simplified e#pressions for the 2ig;!)n* is given by f + A - C D - , C -, D and the
logic diagram is given in 2ig;!)o*
_
C
_
D
B
_
C
<
B
_
D
_
A
6,7.6(#) L#7,. D,07$03 -#$ O2/;2/ L -A
110
D E ! D I % IT A L S ELE C T & O N I CS
(*,,)B=30; 0n8 L#7,. D,07$03 -#$ D,7,/01 O2/;2/ L7A:
The simplified e#pressions for the 2ig;!)p* is given by g + A - , C - B (- ( D and the
logic diagram is given in fig;!)q*;
B
_
C
_
B
C g
C
_
D
_
A
6,7.6(<) L#7,. D,07$03 -#$ O2/;2/ L 7 A
Q.2 5#plain the worCing of a demultiple#er with the help of an e#ample; (6)
Ans:
1:4 D+321/,;1+:+$: 2ig;%)a* shows the logic circuit of a 1H' demultiple#er; <t has two
N8T gates, ' AND gates, one data input line, 0 select lines )A
0
,A
1
* and four output lines
5D
0
, D
1
,D
2
,D
3
). The data input line feeds all the AND gates; 1owever, the two select lines
enable only one gate at one time; <f A
1
A
0
+ 00 then the data goes to D
0
; if A
1
A
0
+ 01, then the
data goes toD
1
. <f A
1
A
0
+ 10, then the data goes to D
0
and if A
1
A
0
+ 1, then the data goes to
D
3
.
11
In;2/
D
n
O2/;2/
Q
n+1
0 0
1 1
U
D E ! D I % IT A L S ELE C T & O N I CS
DA1 A INP U1
D
0
O
S D
0
1
1
P
U
S
1
D
1
2
S
D
3
6,7.7(0) L#7,. C,$.2,/ #- 1:4 D+321/,;1+:+$
Q.3! ?ive the truth table of A37 and D3flipflops; (onvert the given A37 flipflop to a D3flipflop; (8)
Ans:
The Truth Table of A37 2lip32lop is shown in 2ig;%)b* and truth table of D 2lip32lop is
shown in 2ig;%)c*
In;2/s O2/;2/
S
n
&
n
Q
n+1
0 0 Gn
1 0 1
0 1 0
1 1 4
6,7.7(4) T$2/9 T041+ -#$ S=& 61,;=61#; 6,7.7(.) T$2/9 T041+ -#$ D=61,;=61#;
<f we use only the middle two rows of the truth table of the A37 2lip32lop shown in 2ig;%)b*
then we obtain a D3type 2lip32lop as shown in 2ig;%)d* and %)e*; <t has only one input
referred to as D3input or Data <nput; <ts truth table is given in 2ig;%)c* from which it is clear
that the output G
n-1
at the end of the clocC pulse equals the input D
n
before the clocC pulse;
This is equivalent to saying that the input data appears at the output at the end of the clocC
pulse; Thus, the transfer of data from the input to the output is delayed and hence the name
Delay )D* 2lip32lop; The D3type 2lip32lop is either used as a Delay Device or as a @atch to
store 13bit of binary information;
11'
D E ! D I % IT A L S ELE C T & O N I CS
P4
P4
S
D
CL2
5
=
S*5
FL IP*FLOP
_
=
D
CL2
=
D
FL IP
*FLOP
_
=
C4
C4
6,7.7 (8) S=& 61,;=61#; .#n*+$/+8 ,n/# 0 D=61,;=61#; 6,7.7 (+) L#7,. S534#1 #- D 61,;=61#;
Q.31 Define a register; (onstruct a shift register from A37 flip3flops; 5#plain its worCing;(8)
Ans:
&+7,s/+$: A register consists of a group of flip3flops and gates that effect their
transition; The flip flops hold the binary information and the gates control when and
how new information is transformed into the register;
S=& 61,;=61#; S9,-/ &+7,s/+$: Ahift registers can be built by using A7 flip3flops;2ig;&)a*
shows the '3bit shift register, which uses 7A flip3flops; <t uses 2our A7 2lip32lops in
cascade and the inputs to the last three flip3flops in the chain receive complementary
inputs, that is if A + 0, R & 1 and if A + 1, R & 0; The first flip3flop has complementary A
and R inputs and, therefore, it behaves liCe a D3type flip3flop; ,ecause of the <nverter in
the clocC line, data will be transferred to flip3flop outputs on the positive going edge of the
clocC pulse;
There are two inputs A and B. Any one of the inputs can be used; Aince a 1 input at A or B
will be a 1 input at A of the first flip3flop, as a result of double complementation, a positive
going clocC pulse will produce an output of 1 at G of the first flip3flop; Normally both A
and , inputs of the NAND gate are connected together when data is being fed and the
NAND is not required to serve as a gate;
S,-IAL A
I/*+. B S %
S--
S
%
S--
S
%
S--
S
%
S--
S,-IAL
O+.*+.S
FLI *-FLO*
0
-
%
FLI *-
FLO*
0
-
%
FLI *-FLO*
0
-
%
FLI *-FLO*
0
- %
CLOC)
6,7.(0)L#7,. D,07$03 #- S=& 61,;=61#; S9,-/ &+7,s/+$
Q.32 5#plain how a shift register can be used as a ring counter giving the wave forms at the output
of the flipflops; (6)
11$
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
S9,-/ &+7,s/+$ 0s 0 &,n7 C#2n/+$: A 7ing (ounter is a (ircular Ahift 7egister with only
one flip3flop being set at any particular timeR all other are cleared; The single bit is shifted
from one flip3flop to the other to produce the sequence of timing signals; 2ig;&)b* shows a
'3bit shift register connected as a ring counter; The initial value of the register is 1000,
which produces the variable T
0
; The single bit is shifted right with every clocC pulse and
circulates bacC from T

to T
0
; 5ach flip3flop is in the 1 state once every four clocC pulses
and produces one of the four timing signals shown in 2ig;&)c*; 5ach output becomes 1
after the negative3edge transition of a clocC pulse and remains 1 during the ne#t clocC
pulse;
S: IF1 5 I,: 1
5 0,IS105
1
1 1 1
0
1 2 3
6,7.(4) 4=4,/ s9,-/ $+7,s/+$ .#nn+./+8 0s 0 $,n7 .#2n/+$.
C LOC2 PU LS0
1
0
1
1
1
2
1
3
6,7.(.) G0*+-#$3s 0/ /9+ #2/;2/ #- 61,;=61#;s
Q.33 Differentiate between linear addressing and matri# addressing modes with e#amples; Which of
them is the best method4 (4)
Ans:
L,n+0$ A88$+ss,n7: Addressing is the process of selecting one of the cells in a memory to
be written into or to be read from; <n order to facilitate selection, memories are generally
arranged by placing cells in @inear form or 9atri# form;
L,n+0$ A88$+ss,n7 )#8+: A single column that has n rows and 1 column )such as the
1!.1 array of cells* shown in fig;11)a* is frequently called @inear Addressing; Aelection of
a cell simply means selection of the corresponding row and the column is used;
11!
16
X
1
=
=
=
=
=
=
D E ! D I % IT A L S ELE C T & O N I CS
1 COLU M
N
1
1
2
3
16
5 O9S
16
6,7.11 (0) L,n+0$ A88$+ss,n7 )#8+
)0/$,: A88$+ss,n7 )#8+: The arrangement that requires the fewest address lines is a
square array of n rows and n columns for a total memory capacity of n # n + n
0
cells; This
arrangement of n rows and n columns is frequently referred to as 9atri# Addressing which
is shown in fig;11)b*;
4 COLU M N
S
1 2 3 4
1
5 O9S
3
4
4 4
6,7.11(4) )0/$,: A88$+ss,n7 )#8+
B+s/ )+/9#8: 9atri# Addressing is the best method, because this configuration only
requires " address lines )i;e;,' rows and ' columns*, whereas @inear Addressing method
requires a total of 1% address lines )i;e;, 1 column and 1! rows*;The square configuration is
so widely used in industry;
Q.34 Write short note on the followingH Eohnson counter; (4)
Ans:
F#9ns#n C#2n/+$: Eohnson (ounter is an synchronous counter, where all flip3flops are
clocCed simultaneously and the clocC pulses drive the clocC input of all the flip3flops
together so that there is no propagation delay; 2ig;11)e* shows the circuit of Eohnson
counter; <n this case the D input of FF
0
is driven by 7 output of FF
3
, ,.#., the
complement of the output of the last flip flop is fed to the D of FF
0
. This feedbacC
arrangement produces the sequence of states shown in Table 11;0; The ' bit sequence
11%
D E ! D I % IT A L S ELE C T & O N I CS
has a total of " states ) n bit sequence will have 2n states*; Thus an n bit Eohnson counter
will have a modulus of 2n.
The G output of each stage feeds the D input of ne#t stage; ,ut the 7 output of the last
stage feeds the D input of first stage; The counter fills up with 1>s from left to right and
then fills up 0s again as shown in Table 11;0; 2ig; 115() shows the waveshapesBtiming
diagram of ' bit Eohnson counter;
% % % %
0 1
2 3
D % D
%
D % D %
0
0
1
1
2
2
3
3
FF FF
FF FF
3
0 1
2
0
%
3
CLOC)
6,7.11(+) L#7,. D,07$03 #- F#9ns#n .#2n/+$
(locC 6ulse G
0
G
1
G
0
G

0 0 0 0 0
1 1 0 0 0
0 1 1 0 0
1 1 1 0
' 1 1 1 1
$ 0 1 1 1
! 0 0 1 1
% 0 0 0 1
T041+ 11.2 S+<2+n.+ #- s/0/+s #- 4 4,/ F#9ns#n C#2n/+$
C L2
1 2 3 4 5 6 7 8
=
0
=
1
=
2
=
3
6,7.11(-) T,3,n7 D,07$03 #- 4=4,/ F#9ns#n C#2n/+$
11"
D E ! D I % IT A L S ELE C T & O N I CS
Q.35 The voltage waveforms shown in 2ig;1 are applied at the inputs of 03input AND and 87 gates;
Determine the output waveforms; (3)
Ans:
The 8utput waveforms for AND and 87 gates are shown in fig;)a*
1
A
0
0 1 2 3
4
5
1
B
0
'(3$ (3")
'(3$ (3")
1
A/ D OF A > B
i=e=? A 4 B
0
1
O- OF A > B
i=e=? A @ B
0
6,7.3(0) O2/;2/ G0*+-#$3s
Q.36 What are the advantages of (98A logic and e#plain (98A <nverter with the help of a neat
circuit diagram; (7)
Ans:
A8*0n/07+s #- C)OS L#7,.H
)i* The power dissipation is minimum of all the logic families
)ii* @A< O V@A< are possible
C)OS In*+$/+$:
The basic (98A logic circuit is an inverter shown in 2ig;$)a*; 2or this circuit the logic
levels are 0 V )logic 0* and V
CC
)logic 1*; When V
,
+ Vcc, T
1
turns 8N and $
2
turns
822; Therefore V
%
c 0 V and since the transistors are connected in series, the current I
D
is very small; 8n the other hand, when V
,
+ 0 V, T
1
turns 822 and $
2
turns 8N giving
an output voltage V
%
c Vcc and I
D
is again very small; <n either logic state, T
1
or $
2
is
822 and the quiescent power dissipation which is the product of the 822 leaCage current
and V
cc
is very low; 9ore comple# functions can be realiDed by combinations of inverters;
11&
D E ! D I % IT A L S ELE C T & O N I CS
+ 6
CC
S
2
1 (.*
&C-))$%)
2
D I
2 D
6 , D
6
( 7
D
1
1 ()*
&C-))$%)
1
S
1
6,7.5(0) L#7,. D,07$03 #- C)OS In*+$/+$
Q.37 What is Tri3state logic and e#plain Tri3state logic inverter with the help of a circuit diagram;
?ive its Truth Table; (7)
Ans:
T$,=s/0/+ L#7,.H
<n normal logic circuits, there are two states of the output, @8W and 1<?1; <f the output is
not in the @8W state, it is definitely in the other state )1<?1*; Aimilarly, if the output is
not in the 1<?1 state, it is definitely in the @8W state; <n comple# digital systems liCe
microcomputers and microprocessors, a number of gate outputs may be required to be
connected to a common line which is referred to as a bus which in turn may be required to
drive a number of gate inputs;
When a number of gate outputs are connected to the bus, Totem pole TT@ outputs leads to
heating of the <(s which may get damaged and 8pen3collector TT@ outputs causes the
problems of loading and speed of operation; To overcome these difficulties, in addition to
low impedance outputs 0 O 1, there is a third state Cnown as the 1igh3impedance state;
Auch logic circuits in which the output can have three states is called tri3state logic;
<n the Tri3state @ogic, in addition to low impedance outputs 0 O 1, there is a third state
Cnown as the 1igh3impedance state; When the gate is disabled, it is in the third state;
T$,=s/0/+ L#7,. In*+$/+$H
The functional diagram of Tri3state @ogic <nverter is shown in fig;$)b* and its logic diagram
is shown in fig; $)c*; When the control input is @8W, the drive is removed from T

O T
'
;
1ence both T

O T
'
are cut3off and the output is in the third state; When the control input
is 1<?1, the output J is @ogic 1 or 0 depending on the data input; Truth table of Tri3state
@ogic <nverter is given in Table No;$;1
D A1A IN PU1
C ON 15OL
D A1A OU 1PU 1
6,7.5(4) 62n./,#n01 D,07$03 #- T$,=s/0/+ L#7,. In*+$/+$
100
4
D E ! D I % IT A L S ELE C T & O N I CS
+ 6
C C
C 7)'47%
1
5
1
1
1 1
2
D -'- ()./'
Y
D 9t 9 out put
1
3
6,7.5(.) L#7,. D,07$03 #- T$,=s/0/+ L#7,. In*+$/+$
Data <nput (ontrol Data 8utput
0 0 1igh 3 U
1 0 1igh 3 U
0 1 1
1 1 0
T041+ 5.1 T$2/9 T041+ #- T$,=s/0/+ L#7,. In*+$/+$
Q.38 What is a digital comparator; 5#plain the worCing of a 03bit digital comparator with the help of
Truth Table; (6)
Ans:
D,7,/01 C#3;0$0/#$: The comparison of two numbers is an operation that determines if
one number is greater than, less than, or equal to the other number; A Digital comparator is
a combinational circuit that compares two numbers, A and ,, and determines their relative
magnitudes; The outcome of the comparison is specified by three binary variables that
indicate whether A d ,, A + ,, or A L ,;
(omparators can be designed for comparing multibit numbers; 2igure !)e* shows the blocC
diagram of an n:6," comparator; <t receives two n:6," numbers A and B as inputs and the
outputs are A d B, A + B, and A L B. Depending upon the relative magnitude of the two
numbers, one of the outputs will be 1<?1; Table !;0 gives the truth table of a 03bit
comparator;
(I) I- /9+ 307n,/28+ #- /9+ ,n;2/s A 0n8 B 0$+ +<201 (,.+." A = B):(onsider two numbers,
A and , as inputs with two digits each i;e;, A1, A0 and ,1, ,0; The two numbers are equal
if all pairs of significant digits are equal i;e;, if A
1
+ 0, A
0
+ 0, ,
1
+ 0, ,
0
+ 0, then A
1
+
,
1
and A
0
+ ,
0
; 2or e#ample if A
1
+ 0, A
0
+ 0, ,
1
+ 0, ,
0
+ 0, then pairs of significant
digits i;e;, A
1
+ ,
1
+ 0 and A
0
+ ,
0
+0; 8utput for this combination becomes 1 for A + ,
and 0 for A L , and A d ,; This is given in the Truth Table;
101
<nputs 8utputs
A
1
A
0
,
1
,
0
A d , A + , A L ,
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
D E ! D I % IT A L S ELE C T & O N I CS
(II) I- /9+ 307n,/28+ #- /9+ ,n;2/ A ,s 7$+0/+$ /90n #$ 1+ss /90n B (,.+." A M B #$ A N
B):To determine if A is greater than or less than ,, we inspect the relative magnitude of
pairs of significant digits starting from the most significant position; <f the two digits are
equal, we compare the ne#t lower significant pair of digits; This comparison continues
until a pair of unequal digits is reached;
(,)I- /9+ ,n;2/ A ,s 7$+0/+$ /90n B (,.+." A M B): <f the corresponding digit of A is 1 and
that of , is 0, we conclude that A d ,; 2or e#ample if A
1
+ 0, A
0
+ 1, ,
1
+ 0, ,
0
+ 0,
then pairs of significant digits are A
1
+ ,
1
+0, and A
0
)i;e;, digit 1* d ,
0
)i;e;, digit 0*
;
This is shown in the Truth Table;
(,,) I- /9+ ,n;2/ A ,s 1+ss /90n B (,.+." A N B):<f the corresponding digit of A is 0 and that
of , is 1, we conclude that A L ,; 2or e#ample if A
1
+ 0, A
0
+ 0, ,
1
+ 0, ,
0
+ 1, then
pairs of significant digits are A
1
+ ,
1
+0, and A
0
) i;e;, digit 0* L ,
0
)i;e;, digit 1*
;
This is
shown in the Truth Table;
T041+ 6.2 T$2/9 T041+ #- 0 2=B,/ C#3;0$0/#$
100
D E ! D I % IT A L S ELE C T & O N I CS
Q.3 What is a Ahift 7egister4 What are its various types4 @ist out some applications of Ahift
7egister; (6)
Ans:
S9,-/ &+7,s/+$: A register in which data gets shifted towards left or right when clocC
pulses are applied is Cnown as a Ahift 7egister;
T5;+s #- S9,-/ &+7,s/+$s:
)i* Aerial3<n Aerial38ut )A<A8* Ahift 7egister
)ii* Aerial3<n 6arallel 8ut )A<68* Ahift 7egister
)iii* 6arallel3<n Aerial 8ut )6<A8* Ahift 7egister
)iv* 6arallel3<n 6arallel 8ut )6<68* Ahift 7egister
A;;1,.0/,#ns #- S9,-/ &+7,s/+$s:
)i* Aerial to 6arallel (onverter
)ii* 6arallel to Aerial (onverter
)iii*Delay line
)iv*7ing (ounter
)v* Twisted3ring (ounter
)vi*Aequence ?enerator
Q.4! Design a 98D3! synchronous counter using E3F 2lip32lops; (8)
Ans:
D+s,7n #- )#8=6 C#2n/+$: The 9od3! synchronous counter, have si# counter states )i;e;,
from 0 to !*; The counter design table for this counter lists the three flip3flop and their
states as 0 to ! and the si# inputs for the three flip3flops; The flip3flop inputs required to
step up the counter from the present to the ne#t state is worCed out with the help of the
e#citation table; The desired counter states and "+# 9 F inputs required for counter flip3
flops are given in the counter design table shown in Table No;";1
In;2/ ;21s+
.#2n/
C#2n/+$ S/0/+s 61,;=61#; In;2/s
A , ( E
A
F
A
E
,
F
,
E
(
F
(
0 0 0 0 1 . 0 . 0 .
1 1 0 0 . 1 1 . 0 .
0 0 1 0 1 . . 0 0 .
1 1 0 . 1 . 1 1 .
' 0 0 1 1 . 0 . . 0
$ 1 0 1 . 1 0 . . 1
!)0* 0 0 0
T041+ 8.1 .#2n/+$ D+s,7n T041+ -#$ )#8=6 C#2n/+$
10
D E ! D I % IT A L S ELE C T & O N I CS
61,;=61#; A:
The initial state is 0; <t changes to 1 after the clocC pulse; Therefore, E
A
should be 1 and ;
A
may be 0 or 1 )that is . *; <n the ne#t state 1 changes to 0 after the clocC pulse; Therefore,
E
A
may be 0 or 1 )i;e;, . *and F
A
should be 1;
61,;=61#; B:
The initial state is 0 and it remains unchanged after the clocC pulse; Therefore, E
,
should
be 0 and ;
B
may be 0 or 1 )that is .*; <n the ne#t state 0 changes to 1 after the clocC pulse;
Therefore, E
,
should be 1 and F
,
may be 0 or 1 )i;e;, .*;
61,;=61#; C:
The initial state is 0 and it remains unchanged after the clocC pulse; Therefore 9
C
should be
0 and ;
C
may be 0 or 1 )i;e;, .*; <n the ne#t state, it remains unchanged after the clocC
pulse ; Therefore, E
(
should be 0 and F
(
may be 0 or 1 )i;e;, .*;The EF inputs required
for
this have been determined with the help of the e#citation table, )Table ";1*; The flip3flop
input values are entered in Farnaugh maps shown in 2ig; "b M)i*, )ii*, )iii*, )iv*, )v* and
)vi*N and a ,oolean e#pression is found for the inputs to the three flip3flops and then each
e#pression is simplified; A. all the counter states have not been utiliDed, .s )donKt* are
entered to denote un3utiliDed states; The simplified e#pressions for each input have been
shown under each map; 2inally, these minimal e#pressions for the flip3flop inputs are used
to draw a logic diagram for the counter shown in fig;")c*;
A. before, the EF inputs required for this have been determined with the help of the
e#citation table, )Table ";1*; These input values are entered in Farnaugh maps 2ig; ")b*Mi to
viN and a ,oolean e#pression is found for the inputs to the three flip3flops and then each
e#pression is simplified; .s have been entered in those counter states which have not been
utiliDed; The simplified e#pressions for each input have been shown under each map and
finally a logic diagram based on these e#pressions is drawn and is shown in fig;")c*;
)0; -#$ F
A
)0; -#$ B
A
F
A
= 1 B
A
= 1
6,7.(,) 6,7.(,,)
)0; -#$ F
B
)0; -#$ B
B
F
B
= A C B
B
= A
6,7.(,,,) 6,7.(,*)
10'
B
D E ! D I % IT A L S ELE C T & O N I CS
)0; -#$ F
C
)0; -#$ B
C
F
C
= AB B
C
= A
6,7.(*) 6,7.(*,)
6,7.8(4) B0$n0279 )0;s -#$ F
A
"B
A
"F
B
"B
B
"F
C
"B
C
A
C
B
1
( A
A
(
(
C
B
C
CLOC)
*+LS,S
FF
A
0
1
)
A A
FF
B
0
)
B B
FF
C
0
)
C C
6,7.8(.) L#7,. D,07$03 -#$ )OD=6 S5n.9$#n#2s C#2n/+$
Q.41 What is 7894 <s the 789 a volatile memory4 5#plain; (3)
Ans:
&O)H 7ead 8nly 9emory is a 6ermanent or Aemi3permanent 9emory; <n 6ermanent
789, the data is permanently stored and cannot be changed; <t can only be read from the
memory; There cannot be a write operation because the specified data is programmed into
the device by the manufacturer or the user; <n Aemi3permanent 789 also there is no write
operation, but the data can be altered, to a limited e#tent, by special methods;
No; 789 is a Non3Volatile memory; 6rogramming of 789 involves maCing of the
required interconnections at the time of fabrication and therefore, its contents are
unaffected, even when the power is 822; Thus it is a Non3Volatile 9emory;
Q.42 Draw the logic diagram of 1!3bit 789 Array and e#plain its principle of operation; (8)
Ans:
16=4,/ &O) A$$05: A read3only memory is an array of selectively open and closed
unidirectional contacts; ;A 1!3bit 789 array is shown in 2ig; &)b*; To select any one of the
1! bits, a '3bit address )A

, A
0
, A
1,
A
0
) is required; The lower order two bits )A1, A
0
) are
decoded by the decoder D
=
which selects one of the four rows, whereas the higher order
10$
D E ! D I % IT A L S ELE C T & O N I CS
two bits )A

, A
2
) are decoded by the decoder D
@
which activates one of the four column
sense amplifiers;
0 1 2 3
C OLUM N
5 O9
D D
00 01
D
02
0
D
03
A
0
1 7# 4
D0COD05
D
L
A
1
D
10
D
11 D
12
1
D
13
2
D
20
D
21
D
22
D
23
4* BI1
AD D5 0SS
5O9
D 5I605 S
D IOD0
M A15
IX
D
30
D
31
D
32
3
D
33
A
2
1 7# 4
D0COD05
D
C OLUM
N 0N
ABL0
C OLUM N S0N
S0 AM
PLIFI05S
:
A
3
C :IP S0L0C
1 (C S)
D A1A OU 1PU 1
6,7.(4) L#7,. D,07$03 #- 16=4,/ &O) 0$$05
The diode matri# is formed by connecting one diode along with a switch between each
row and column; 2or e#ample the diode D
01
is connected between row 0 and column
1;The output is enabled by applying logic 1 at the chip select 5CS) input; 6rogramming a
789 means to selectively open and close the switches in series with the diodes; 2or
e#ample, if the switch of diode D
01
is in closed position and if the address input is 0110,
the row 0 is activated connecting it to the column 1; Also the sense amplifier of column
1 is enabled which gives logic 1 output if the chip is selected 5CS + 1*; This shows that a
logic1 is stored at the address 0110; 8n the other hand if the switch of diode D
01
is open,
logic 0 is stored at the address 0110;
Q.43 5#plain briefly, why dynamic 7A9s require refreshing4 (3)
Ans:
,ecause of the charge>s natural tendency to distribute itself into a lower energy3state
configuration )i;e;, the charge stored on capacitors leaC3off with time*, dynamic 7A9s
require periodic charge refreshing to maintain data storage;
10!
R
+
B
D E ! D I % IT A L S ELE C T & O N I CS
Q.44 Draw the schematic circuit of an Analog to Digital converter using Voltage3to 2requency
conversion and e#plain its principle of operation; Draw its relevant Waveforms; (1!)
Ans:
An01#7 /# D,7,/01 C#n*+$/+$ Us,n7 V#1/07+=/#=6$+<2+n.5 C#n*+$s,#nHAn analog
voltage can be converted into digital form by producing pulses whose frequency is
proportional to the analog voltage; These pulses are counted by a counter for a fi#ed
duration and the reading of the counter will be proportional to the frequency of the pulses
and hence to the analog voltage;
A voltage3to3frequency converter is shown in 2ig; 10)a*. The analog voltage V
a
is applied
to an integrator whose output is applied at the inverting input terminal of a comparator;
The non3inverting input terminal of the comparator is connected to a reference voltage /
V
7
;
<nitially, the switch A is open and the voltage <
o
decreases linearly with time )v
o
+ V
a
tB *
which is shown in 2ig; 10)b*; When the decreasing <
o
reaches 3V
R
at " +$, the
comparator
output V
C
goes 1<?1; This is used to close the switch A through a monostable
multivibrator; When the switch A is closed, the capacitor ( discharges, thereby returning
the integrator output <
o
to 0; Aince the pulse width of the waveform V
C
is very small,
therefore, a monostable multivibrator is used to Ceep the switch A closed for a sufficient
time to discharge the capacitor completely; The rate at which the capacitor discharges
depends upon the resistance of the switch;
@et the pulse width of the monostable multivibrator be $
1
. Therefore, the switch A remains
closed for $
1
after which it opens and <
o
starts decreasing again;
<f the integration time $ AA $
1
, the frequency of the waveforms <
o
and V
C
is given
by
( =
1
$ + $
1

1
=
1 V
a
$ V
R
Thus we obtain an output waveform whose frequency is proportional to the analog input
voltage; An ABD converter using the voltage3to3frequency 5VBF) converter is shown in 2ig;
10)c*; The output of the VBF converter is applied at the clocC 5C;) input of a counter
through an AND gate; The AND gate is enabled for a fi#ed time interval T
1
; The reading of
the counter at t + T
1
is given by
n = ($ =
1 V
a
$ which is proportional to V 1
V
1
a;
S
M 7)7"
'-A%$
M /%'(B(A4-'74
C
5
6 -
-
-
7
6
+
C
* 6
5
6,7.1!(0) L#7,. 8,07$03 #- V#1/07+=/#=6$+<2+n.5 C#n*+$/+$
10%
1
-
D E ! D I % IT A L S ELE C T & O N I CS
B
7
8
1
0
'
* 6
5
6
C
1
0
1
'
6,7.1!(4) G0*+-#$3s #- V#1/07+=/#=6$+<2+n.5 C#n*+$/+$
6
B
N*1
6 ; F
C
6
C 7)B$4'$4
C L2
B()-4E
C7/)'$
4
.
B
N*2
.
.
N *A(' A()-4
E 7/'./'
B
1
B
0
6
0N
1
1
6,7.1!(.) S.9+30/,. .,$.2,/ #- AHD .#n*+$/+$ 2s,n7 0 VH6 .#n*+$/+$
Q.45 With the help of 7307 binary networC, e#plain the worCing of a 3bit DBA converter and derive
an e#pression for the output voltage; (1!)
Ans:
&=2& 1088+$ DHA .#n*+$/+$: An R:2R ladder DBA converter is shown in 2ig;11)a*; <t uses
resistors of only two values 7 and 2R. The inputs to the resistor networC are applied
through digitally controlled switches; A switch is in 0 or 1 position corresponding to the
digital input for that bit position being 0 or 1 respectively; Now, we consider a 3bit R:2R
ladder DBA networC shown in 2ig;11)b*;<n this circuit we have assumed that the digital
input as 001;
10"
D E ! D I % IT A L S ELE C T & O N I CS
5
F
5 5 5
25
-
1
7
25 25
25 25 25 25
+
LSB
0 1 0 1 0 1
0 1 0
M SB
1
6 6 6 6 6
5 5 5
5 5
6,7.11(0) L#7,. D,07$03 #- &=2& L088+$ DHA C#n*+$/+$
X Y >
5 5
25
25 25
25 25
X ! Y ! > !
LSB M SB
6
5
6,7.11(4) 3 4,/ &=2& L088+$ DHA N+/C#$E
The circuit is simplified using TheveninKs theorem; Applying TheveninKs theorem at XX', we
obtain the circuit of 2ig; <1)c*; Aimilarly, applying TheveninKs theorem at YY' and ZZ', we
obtain the circuits of 2ig;11)d* and 11)e* respectively; 1ere, @A, is assumed as 1 and the
equivalent voltage obtained is V
R
B 2
3
.
5 X 5
Y
5
> 25
6 ; 2
5
25
25
X !
Y !
> !
6,7.11(.) E<2,*01+n/ .,$.2,/ 0-/+$ 0;;15,n7 T9+*+n,nAs T9+#$+3 0/ ??A
10&
D E ! D I % IT A L S ELE C T & O N I CS
5 Y 5
>
25
2 25
6 ; 2
5
Y !
> !
6,7.11(8) E<2,*01+n/ .,$.2,/ 0-/+$ 0;;15,n7 T9+*+n,nAs T9+#$+3 0/ >>A
5
>
25
3
6 ; 2
5
> !
6,7.11(+) E<2,*01+n/ .,$.2,/ 0-/+$ 0;;15,n7 T9+*+n,nAs T9+#$+3 0/ KKA
Aimilarly for the digital input of 010 and 100 the equivalent voltages are V
7
B0
0
and V
7
B0
1
respectively; The value of the equivalent resistance is 7 in each case; Therefore, we obtain
an equivalent circuit of 3bit 7307 @adder DBA (onverter which is given in 2ig;11) f *;
The output analog voltage V
8
is given by

R
F
V
R
R
F
V
R
R
F
V
R

V
%
= ;

6
0
+ ;
0
6
1
+ ;
1
6
0

R 0 R 0 R 0

V =

F
;
R

['6
+
06
+ 16 ]
%

R

0

0 1 0
1ence the above equation shows that the analog output voltage is proportional to the
digital input;
5
F
3
6 ; 2
5
2
6 ; 2
5
6 ; 2
5
LSB 35
-
35
1
+
o
35
M SB
6,7.11(-) E<2,*01+n/ .,$.2,/ #- 3=4,/ &=2& L088+$ DHA C#n*+$/+$
10
D E ! D I % IT A L S ELE C T & O N I CS
Q.46 What is meant by Wired3AND connection of digital <(s4 What are its advantages and
disadvantages4 Draw a circuit of TT@ gates with Wired3AND connection and e#plain its
operation; (1!)
Ans:
G,$+8 AND 8,7,/01 IC: <f input 2 and 2> at two DT@ NAND gates connected, the output can
be considered as AND operations between the logic output; ,ecause when both the output
corresponds to cut3off stages of the transistors, the output will be unaffected and logic 1;when
any of the outputs corresponds to the saturation condition appro# 0;0 volt, the output from
common point will become 0;0 volt; <f A and , both input are DT@ NAND gate and the (,D,
are input for another ,NAND the output J on Qoining 2 and 2> at common terminal as
followsH J+)A;,*>;)(;D*>+)A;,-(;D*>
G,$+8 ( AND C#nn+./,#n
<n digital <(es NAND and N87 gates are most often used; 2or this reason NAND and N87
logic implementation are the most important from the practical point of view, some NAND O
N87 gates are realiDed using wire connections between the oBpes of two gates to provide a
specific logic function; This type of logic is called as wired logic;
G,$+8 ( AND ,n #;+n .#11+./#$ TTL 70/+s
A8*0n/07+s 0n8 8,s08*0n/07+s
<n this <( additional logic is performed without additional hardware;
There is an effective reduction in the fan out of the gate;
<n the wired3 AND connection speed of operation increases;
6ower dissipation in low output state in 6)8* increases because of reduction in
effective collector resistor;
(urrent dissipation in logic 0 state will increases when two TT@ gates with passive
pull ups are ANDed by wired logic;
The TT@ fates with missing pull up circuit at the collector are also called open
collector gates; These are more suitable for the wired connections;
11
D E ! D I % IT A L S ELE C T & O N I CS
Q.47 What is the necessity of <nterfacing in digital <(s and what are the points to be Cept in view,
while interfacing between TT@ gate and (98A gate4 (4)
Ans:
To achieve the optimum performance in digital system, device from more than one logic
families can be used ,which taCes advantages of the superior characteristics of each logic
families; 2or e#ample, (98A logic <(s can be used in those parts of the system where low
power dissipation is required, and TT@ can be used where high speed of operation is
required; When (98A derives TT@, the following conditions are required to be satisfied;
V
O@(C)OS)
f V
I@(TTL)
V
OL(C)OS)
g V
IL(TTL)
=I
O@(C)OS)
f NI
I@(TTL)
=I
O@(C)OS)
f =NI
IL(TTL)
6,72$+ 1: TTL=/#=C)OS ,n/+$-0.,n7 2s,n7 ;211=2; $+7,s/+$.
6,72$+ 2: C)OS=/#=TTL ,n/+$-0.,n7 2s,n7 0 C)OS 42--+$ IC
Q.48 Draw the logic diagram of '3bit odd parity checCer using 5.3N87 gates and e#plain its
operation with the help of Truth table; (7)
Ans:
4 4,/ #88 ;0$,/5 .9+.E+$ 2s,n7 ?NO& .,$.2,/:=The concept of parity checCer ,Wherein the
additional bit is Cnown as parity; <t can be either even or odd; The following circuit will give
the ' bit parity checCer circuit;
10
D E ! D I % IT A L S ELE C T & O N I CS
1#7,. 8,07$03 #- 4=4,/ #88 ;0$,/5 .9+.E+$ 2s,n7 E?=NO& 70/+s
6arity checCer networCs are logic circuits with e#clusive / 87 functions; 5# 87 operation of
parity bit is a scheme for detecting errors during transmission of binary information; <t is an
e#tra bit transmitted and then checCed at the receiving end for errors;
<n ' bit odd parity checCer, the three bits .,J,U constitute the message and e6e is the parity
bit; 2or odd parity bit e6e is generated, so as to maCe the total number of 1es odd )including
6*; The three bit message and the parity bit are transmitted to their destinationR they are
applied to a parity checCer circuit; An error occurs during transmission if the parity of the
four bits received is even, since binary information transmitted was originally odd; The
output h(Y of the parity checCer should be h1Ywhen an error occurs i;e; when the number of
1>s in the four input is even;
T$2/9 T041+
2 o u r b it s rece i v e d 6 a r i t y e rr o r c h e c C
# y D 6 (
0 0 0 0 3333333333333 1
0 0 0 1 3333333333333 0
0 0 1 0 3333333333333 0
0 0 1 1 3333333333333 1
0 1 0 0 3333333333333 0
0 1 0 1 3333333333333 1
0 1 1 0 3333333333333 1
0 1 1 1 3333333333333 0
1 0 0 0 3333333333333 0
1 0 0 1 3333333333333 1
1 0 1 0 3333333333333 1
1 0 1 1 3333333333333 0
1 1 0 0 3333333333333 1
1 1 0 1 3333333333333 0
1 1 1 0 3333333333333 0
1 1 1 1 3333333333333 1
1
D E ! D I % IT A L S ELE C T & O N I CS
Q.4 What is a Decoder4 (ompare a decoder and a demultiple#er with suitable blocC diagrams;
(4)
Ans:
D+.#8+$H3 <t decodes the information; The decoders have n inputs % at the end ma#imum
0
n
outputs because n bit no can decode ma# 0
n
information , Now 1 enable input =5 > is
connected to the decoder; <f it is high then only the circuit will be enabled and it will
worC as a decoder; <f =5> is low then the circuit will be disabled;
D+321/,;1+:+$ has the same circuit as decoder but here e is taCen as the single input
line, the output lines are same as decoder )i;e ma# 0
n
*; The information at 5 will be
transmitted to one of the output line and the output line will be selected by bit
combination of n select lines;
B1#.E 8,07$03s #- 0 8+.#8+$ 0n8 0 8+321/,;1+:+$
Q.5! Draw the logic diagram of '3bit Twisted 7ing counter and e#plain its operation with the
help of timing diagram; (6)
Ans:
TC,s/+8 $,n7 .#2n/+$ (4 BIT) We Cnow that shift registers can operate in ' different
modes that is A<A8, A<68, 6<A8 and 6<68;
2ollowing is the ' ,<T register which can operate in any of the mode; <f G
0
is
applied to the serial input , the resulting circuit is called twisted ring or Eohnson
(ounter; <f the clocC pulse are applied after clearing the 2lip 2lops, square wave
form is obtained at the G output;
1'
D E ! D I % IT A L S ELE C T & O N I CS
T9+ 1#7,. 8,07$03 #- 4=4,/ TC,s/+8 &,n7 .#2n/+$
2or decoding the count, two input AND ?ates are required Decoding logic for ' stage twisted
ring counter are
1$
D E ! D I % IT A L S ELE C T & O N I CS
Q.51 5#plain the following characteristics for digital <(>s; (8)
)i* 6ropagation delay )ii* 6ower dissipation
Ans:
' $ # ; 070/ , #n D + 1 05H3 The speed of operation of a digital <( is specified in terms of
propagation delay time; The delay time is measured between the $0X voltage levels of
input O output wave forms; There are two delay times;
a* t
phl
+ When the 8B6 goes from 1<?1 state to @8W state;
b* t
plh
+ When the 8B6 goes from @ow state to 1<?1 state;
The propagation delay time of the logic gate is taCen as the average of these two
delay times;
' # C + $ D ,ss,; 0/ , # n H3 This is amount of power dissipated in an <(; <t is determined by the
current <
((
, that it draws from the V
cc
supply and is given by V
((
. <
((
; This is specified
in milliwatts; <
cc
is the average value of <
cc
)o* and <
cc
)1*
Q.52 1ow will you form an " bit adder using 0 four bit adder <(>s %'"4 (8)
Ans:
<( %'" is a ' bit adder <(; <t has two four bit data inputs and output carry, ' bit data
output carry; These two <(Ks should be connected in ca s ca d e, the first <( will add lower
order bits and it generate sum and carry; This carry should be the input of second <(, The
inputs of second <( will be the higher order bits of number A O ,
Q.53 Distinguish between combinational logic circuits and sequential logic circuits; 1ow are the
design requirements of combinational circuits specified4 (7)
Ans:
C#34,n0/,#n01 1#7,. .,$.2,/s:=
)i* 8utputs only depends upon present state of the input;
)ii* No memory element present or no feedbacC connection;
S+<2+n/,01 1#7,. .,$.2,/:=
)i* 8utput not only depends on the present state of the input but also depend on the
previous state of the output;
)ii* 9emory element is present or a feedbacC connection is there;
1!
D E ! D I % IT A L S ELE C T & O N I CS
D+s,7n &+<2,$+3+n/s #- C#34,n0/,#n01 L#7,.H3
)i* 2rom the specifications of circuit, we determine the no of inputs O outputs;
)ii* Derive the truth table which contains all possible combination of the inputs and
corresponding outputs;
)iii* 9inimiDe the output function using F39ap;
)iv* Draw the logic diagram;
D+s,7n &+<2,$+3+n/s #- S+<2+n/,01 .,$.2,/:
)i* The circuit specifications translated into a state diagram;
)ii* The state diagram is then converted into state table;
)iii* 2rom state table, information for obtaining logic circuit diagram is obtained;
Q.54 What are the characteristics of digital <(s used to compute their performance4 (11)
Ans:
C 9 0 $ 0 . /+ $ ,s /, . s #- D , 7 , /01 In /+ 7 $ 0/ + 8 C , $ . 2, /s
1; S;++8 #- #;+$0/,#n: The Apeed of a digital circuit is specified in terms of the
propagation delay time; The input and output delay times can be shown asH
1%
D E ! D I % IT A L S ELE C T & O N I CS
The delay times are measured between the $0 percent voltage levels of input and
output wave forms; There are two delay times t
phl
, when the 8B6 goes from the high
state to low state and t
phl
, when 8B6 goes from low state to high state;
0 '#C+$ D,ss,;0/,#n: This is the amount of power dissipated in an <(; <t is
determined by the current, <
((
that it draws from the V
cc
supply and is given by
V
cc
. <
cc
; <
cc
is the av value of <
((
M8N and <
cc
M1N; <t is specified in
mW;
6,72$+ #- 3+$,/: 2or digital <(, it is defined as the product of speed and power;
<t is specified in 6ico Qoules Mas ns # mw+ pQN; A low value of speed power product
is desirable;
' 60n O2/: This is the no of similar gates which can be driven by a gate; 1igh fan
out is advantageous, as it reduces the need for additional drivers to drive more gates;
$ N#,s+ I332n,/5: Atray electric and magnetic fields induce unwanted voltages
Cnown as noise, on the connecting wires between logic circuits; This may cause the
voltage at the <B6 to a logic circuit to drop below V
ih
or fuse above V
il
and may
produce undesired operation; The circuites ability to tolerate noise signals is referred
to as the noise immunity;
!; O;+$0/,n7 T+3;+$0/2$+: The temperature range in which an <( functions
properly must be Cnown; The accepted temperature range for consimer <(e s are 0
to %0 degree ( and for industrial applications M3$$i ( to -10$i ( for military
applicationsN;
Q.55 What is a digital multiple#er4 <llustrate its functional diagram; Write the scheme of a '3
input multiple#er using basic gates )ANDB87BN8T* and e#plain its operation; (8)
Ans:
)21/,;1+:+$: )U? or data selector is a logic circuit selects binary information from one
of many input and directs it to a single output line; Aelection of the particular input line is
controlled by a set of selection lines; Normally there are 0
n
input lines and
correspondingly n selection lines;
There are ' inputs <
1
<
0
<
0
<

and two selection line A
0
and A
1
; Depending upon the
bit combination of A
0
and A
1
one of the input is transferred to the output; ,asically there
is a decoder circuit with one input for each bit of information and one 87 gate
connected to
D E ! D I % IT A L S ELE C T & O N I CS
the output; <f A
o
, A
i
+ 00 ,then first AND gate will have the two inputs as one output will
depend on <
0;
At the same time outputs of all other AND gates are Uero;
The multiple#er is a combinational circuit which is one of the most widely used standard
circuit in digital design; <t has N select lines 0
N
inputs and a single output;
)21/,;1+:+$:=
Y = S
1
S
0
I
0
+ S
1
S
0
I
1
+ S
1
S
0
I
0
+ S
1
S
0
I

T$2/9 /041+ #- 4:1 )2:


Aelect inputs 8utput
A
1
A
0
J
0 0 <
0
0 1 <
1
1 0 <
0
1 1 <

C,$.2,/ D,07$03 #- 4 ? 1 )U? 2s,n7 40s,. 70/+


Q.56 What is meant by a priority encoder4 Name the %'00 series TT@ chip which is a priority encoder;
Write its truth table; <llustrate how it can be used as a decimal3to3,(D encoder; (8)
1&
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
'$,#$,/5 +n.#8+$= An encoder is a combinational circuit that performs the inverse operation
of a decoder; <f a device output code has fewer bits than the input code has, the device is
usually called an encoder; e;g; 0
n
3to3n, priority encoders; The simplest encoder is a 0
n
3to3n
binary encoder, where it has only one of 0
n
inputs + 1 and the output is the n3bit binary
number corresponding to the active input;
8ne of the most commonly used input device for a digital system is a set of 10 switches,
one for each numeral between 0 O &; These switches generate 1 or 0 logic levels in
response to turning them off or on; When a particular number is to be fed to the digital
circuit in ,(D code, the switch corresponding to that number is pressed; Available <( in %'
series is %'1'% which is a priority encoder; This <( has active low inputs and outputs; The
meaning of the word priority can be understood from the truth table; 2or e#ample if 0 O $
are low, the output will be corresponding to $ which has a higher priority than 0 i;e; the
highest numbered <B6 has priority over lower numbered input>s;
T$2/9 /041+ #- 74147
A./,*+ 1#C 8+.,301 ,n;2/Os A./,*+ 1#C BCD
#2/;2/s
1 0 ' $ ! % " & D ( , A
1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 0
. 0 1 1 1 1 1 1 1 1 1 0 1
. . 0 1 1 1 1 1 1 1 1 0 0
. . . 0 1 1 1 1 1 1 0 1 1
. . . . 0 1 1 1 1 1 0 1 0
. . . . 1 0 1 1 1 1 0 0 1
. . . . 1 1 0 1 1 1 0 0 0
. . . . . . . 0 1 0 1 1 1
. . . . . . . . 0 0 1 1 0
1'0
D E ! D I % IT A L S ELE C T & O N I CS
Q.57 What is a flip3flop4 Write the truth table for a clocCed E3F flip3flop that is triggered by the
positive3going edge of the clocC signal; 5#plain the operation of this flip3flop for the
following conditions;
<nitially all inputs are Dero and assume the =G> output to be 1; (1!)
Ans:
2lip /flop is single bit memory cell; <t stores single bit information in its true and
compliment form; This is the fundamental blocC of any sequential circuit;
T$2/9 /041+ -#$ .1#.E+8 F B 61,;= -1#;
clocC E F G)t-1*
0 . . G)t*
0 1
0 0 G)t*
3do3 1 0 1
3do3 0 1 0
3do3 1 0 Ge)t*
1'1
D E ! D I % IT A L S ELE C T & O N I CS
1'0
D E ! D I % IT A L S ELE C T & O N I CS
Q.58 1ow is it possible to maCe a modulo 0
n
counter using N3flipflops4 Name the two types of
such counters; (4)
Ans:
9odule 0
n
counter counts total 0
n
distinguishable states we Cnow that n3bit can represent
0
n
unique combinations for eg; 9od3" counter will count total " states and as "+)0

* each
state will have combination of bits;
Two types of such counters areH
9od " counter
9od 1! counter
Q.5 <n applications where the required memory capacity cannot be satisfied by a single available
memory <( chip, what should the designer do to meet this requirement4 (1!)
Ans:
<f the single memory chip can not be specified the required memory capacity then the designer
should do the followings;
)1* 2ind out the no of single chip required to full fill the total capacity by
No of chip + 7equired capacity
Available capacity
)0* There are two type of e#pression
)i* <ncreasing memory location or words
)ii* <ncreasing word siDe, i;e; no of bits in each word;
)* <n case )i* the number will be of same as the address lines of available chip; The difference of
the address lines of the capacity % availability will give the siDe of the decoder and the
output of the decoder will decode among the chips;
<n case )ii* address line data lines will be common to all chips because all chips at the same
location collectively maCe a single word;
Q.6! 5#plain the operation of "H1 multiple#er; (8)
Ans:
There are " <nputs O 1 8utput and three select lines A0, A1, A0; Any one of the inputs will be
selected O transmitted to the output depending upon the combination of the select lines, for
e;g; <f A
0
A
1
A
0
+ 001 then information present on <1 line will be transmitted to the output;
Q.61 What is race around condition4 1ow it can be avoided4 (8)
1'
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
&0.+ A$#2n8 C#n8,/,#n:=
En Fn G)n-1* output
0
1
0
1
0
0
1
1
G)n*
1
0
G)n*>
<n EF flip3flop, When E+C+1 then output will be the complement of the previous state; Auppose
the output G
n
is 0 and clocC pulse is high; After the time interval bt equal to the propagation
delay through two NAND gates the output will change to the G
n-1
+1 )if E+F+1*; Now we
have+F+1 and G+1 and after another bt interval the output, G will change to 0 from 1; 1ence
after every bt duration of the output will flip between 0 and 1; At the end of the clocC pulse the
value of G is uncertain because the value of bt is not Cnown e#actly; This situation is Cnown as
race around condition ;
The race around condition can be avoided if
1 Duration of clocC pulse being high is small as compare to the delay of the gates;
This is difficult because of very small propagation delay in <(>s;
0 A master slave EF flipflop is used; <n this 0 A7 flip3flops are there; The feedbacC from the
output of the second to the input of the first flip3flop; 6ositive clocC pulses are applied to the
first clocC pulse and clocC pulse are inverted at the second flip3flop when clC+1 first flip3flop is
enabled and second is disabled clC>+0;
Q.62 Draw the circuit diagram of Asynchronous decade counter and e#plain its worCing; (8)
Ans:
T# 8+s,7n 0 8+.08+ 0s5n.9$#n#2s .#2n/+$ first we draw the circuit for 98D 1!
asynchronous counter which counts from 0 to 1$ using four flip3flop )EF or T flipflop*; <t
should count from 0 to & and then come to 0; The first state to be sCipped is 1010 )10*here G

and G
1
are 1 and G
0
and G
0
are 0 if we taCe G

and G
1
and applied these to a NAND gate
then the output of the NAND gate will be low only where G

and G
1
are high; This signal
can be used to asynchronously clear all flipflops to maCe the counting state 0000; <n this
way 98D
1! counter will be restricted to count 10 state that is from 0 to &;
Q.63 5#plain the following for an AD(
)i* <nput stage; )ii* 7esolution;
)iii* Accuracy; )iv* GuantiDation error; (8)
Ans:
(,) In;2/ S/07+= <n A3D (onverter at the input stage, analog voltage can have any value in a
range but the digital output can have only 0
N
discrete values for an n bit A3D converter;
(,,) &+s#12/,#n= This is the smallest possible change in input voltage as the fraction of
percentage of the full scale output range;
(,,,)A..2$0.5=The accuracy of DBA converter is the difference between actual output voltage
and the e#pected output voltage in DBA converter;
(,*)Q20n/,D0/,#n +$$#$= An analog voltage is in the range of 0 to 1V and for bit output, the
siDe of each interval is A+1B";5ach interval is assigned a bit binary value ;We observe that the
1''
D E ! D I % IT A L S ELE C T & O N I CS
whole range of voltage in an interval is represented by only one digital value ;This error is
referred to an quantiDation error which is because of process of quantiDation;
Q.64 ?ive the details of e#cess code and gray code using four binary digits; (ompare the two codes;
(8)
Ans:
,inary no 5#cess ?ray code
0 0 0 0 0 0 1 1 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 1
0 0 1 0 0 1 0 1 0 0 1 1
0 0 1 1 0 1 1 0 0 0 1 0
0 1 0 0 0 1 1 1 0 1 1 0
0 1 0 1 1 0 0 0 0 1 1 1
0 1 1 0 1 0 0 1 0 1 0 1
0 1 1 1 1 0 1 0 0 1 0 0
1 0 0 0 1 0 1 1 1 1 0 0
1 0 0 1 1 1 0 0 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
E:.+ss 3 C#8+
1; <t is another from of ,(D code; 5ach decimal digit is coded in ' bit binary code;
0;The code for each decimal digit is obtained by adding decimal to the
natural ,(D code of the digit;
;The code is obtained by adding to the decimal no
';Aelf complementing code3useful in subtraction;
%$05 C#8+
1; Very useful code; Also called reflected code;
0; 5ach gray code differs from the preceding and succeeding codes by a single bit;
; :sed in shaft encoders;
Q.65 Distinguish between enhancement mode and depletion mode metal o#ide semiconductor field
effect transistors giving their characteristics; (6)
1'$
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
5 9ode 98A25T Depletion 9ode 98A25T
01; No channel e#ists between rain and
source at V
?A
+ 0
01; (hannel e#ists at V
?A
+ 0 Min
fabrication n type impurity is diffused
between two n- regions
00; Threshold voltage is positive for
n98A Device;
00; Threshold voltage is negative for
n98A Device;
0; No current flows for negative V
?A
Mn98AN
0; (urrent flows even for negative V
?A
Q.66 The clocC and the input waveforms shown below are applied to the D input of a positive edge
triggered D flipflop; ACetch the output waveforms; (6)
Ans:
As it is D 2lip 2lop at the positive edge ,output will be same as the input;
1'!
D E ! D I % IT A L S ELE C T & O N I CS
Q.67 What are the specificationsB characteristics used by the manufacturers to describe a digital to
analog converter; 5#plain each one briefly; (8)
Ans:
T9+ .90$0./+$,s/,.s #- DHA .#n*+$/+$ 0$+
(,)&+s#12/,#n:= This is the smaller possible change in output voltage as a function of percentage of
full scale output voltage;
(,,) L,n+0$,/5:=<n a DBA converter equal increments in the numerical significance of the digital
circuit the input3output relationship is not linear;
(,,,)T9+ 0..2$0.5 of DBA converter is a measure of the difference between the actual output
voltage and the e#pected output voltage;
(,*) S+//1,n7 /,3+:=when the digital input to a DBA (onverter changes the analog output voltage
does not change absolutely; ,ecause of the presence of switches, active devices, stray capacitances
and inductances associated with passive circuit components; The transient appears in the output
voltages and oscillations may also occur the time required for the analog output to settle within -3
j @A, of the final value after a change in the digital input is Cnown as settling time;
Q.68 Describe (98A inverter and state advantages of (98A; (8)
Ans:
(98A inverters )(omplementary 98A25T <nverters* are some of the most widely used and
adaptable 98A25T inverters used in chip design; They operate with very little power loss and
at relatively high speed; 2urthermore, the (98A inverter has good logic buffer
characteristics, in that, its noise margins in both low and high states are large;A (98A
inverter contains a 698A and a N98A transistor connected at the drain and gate terminals, a
supply voltage V
DD
at the 698A source terminal, and a ground connected at the N98A
source terminal, were V
<N
is connected to the gate terminals and V
8:T
is connected to the drain
terminals;)Aee diagram*;
<t is important to notice that the (98A does not contain any resistors, which maCes it more
power efficient that a regular resistor398A25T inverter; As the voltage at the input of the
(98A device varies between 0 and $ volts, the state of the N98A and 698A varies
accordingly; <f we model each transistor as a simple switch activated by V
<N
, the inverter>s
operations can be seen very easilyH
1'%
D E ! D I % IT A L S ELE C T & O N I CS
2ollowing are the advantages of (98AH
,oth n3channel O p3channel devices are fabricated on the same substrate;
@ow power dissipation, so more efficiency;
?ood noise immunity;
1igh pacCing density;
Q.6 What is parallel adder4 Draw and e#plain blocC diagram for ' bit parallel adder; (8)
Ans:
,y using full adder circuit, any two bits can be added with third input as carry; <f numbers of bits
are more than one, then full adder circuits are cascaded; Addend O Augend bits are applied
simultaneously at inputs to the full adders; (arry generated in the lower significant stage is
transferred to the ne#t higher stage so that it can be added there;
A

,

A
0
,
0
A
1
,
1
A
0
,
0
2ull
(
'
Adder
(

2ull
Adder
2ull
(
0
Adder
(
1
2ull
Adder
(
0
A

A
0
A
1
A
0
Q.7! What is parity generator and checCer4 Describe five bit even parity checCer; (8)
Ans:
When a digital signal is transmitted, it may not be received correctly by the receiver; At the
receiving end it may or may not be possible to detect the error; To overcome this problem, an
e#tra bit is attached to the n3bit code word to maCe the number of bits )n-1* in such a way so as
to maCe the number of ones in the resulting )n-1* bit code even or odd; Then it will be an error
detecting code; Ao for detection of error this e#tra bit is Cnown as parity bit; 6arity term is used to
specify the number of ones in a word as odd or even; A logic circuit that checCs the parity of a
binary word is called as parity checCer; Aimilarly a logic circuit that generates an additional bit to
maCe the digital word of desired parity )even or odd* is Cnown as parity generator;
6,*+ 4,/ +*+n ;0$,/5 .9+.E+$:
5.387 gates are used for checCing the parity as they produce output 1, when the input has
an
odd number of 1>s; Therefore an even parity input to an 5.387 gate produces a low output;
1'"
D E ! D I % IT A L S ELE C T & O N I CS
T$2/9 /041+
G ? > K ' C
0 0 0 0 0 1
0 0 0 0 1 1
0 0 0 1 0 1
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 0 1 1 1 1
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 1 0 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 1 1
0 1 1 1 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 1 0 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 1 1
1 0 1 1 0 1
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 0 1 1
1 1 0 1 0 1
1 1 0 1 1 0
1 1 1 0 0 1
1 1 1 0 1 0
1 1 1 1 0 0
1 1 1 1 1 1
Q.71 Describe the operation of parallel in parallel out )6<68* shift register; (8)
1'&
D E ! D I % IT A L S ELE C T & O N I CS
Ans:
'0$011+1 In '0$011+1 O2/
<

G

<
0
G
0
<
1
G
1
<
0
G
0
D

D
0
G
0
D
1
G
1
D
0
G
0
(
6
(lear <nputs
As the name suggests, in parallel in parallel out )6<68*, inputs are given in parallel, and
outputs are also taCen in parallel fashion; 2or synchroniDation same clocC pulse is connected to
all flip3 flops; Thus any state change will taCe place simultaneously; (lear inputs are also
connected to all flip3flops; Ao that the register can be cleared if required;
Q.72 Describe the operation of voltage to frequency AD(; (8)
Ans:
A voltage3to3frequency converter )V2(* is an oscillator whose frequency is linearly
proportional to a control voltage; The V2(Bcounter AD( is monotonic and free of missing
codes, integrates noise, and can consume very little power;
The current3steering multivibrator V2( is actually a current to3frequency converter rather
than a V2(, but, as shown in 2igure below, practical circuits invariably contain a voltage to3
current converter at the input; The principle of operation is evidentH the current discharges
the capacitor until a threshold is reached, and when the capacitor terminals are reversed, the
half cycle repeats itself; The waveform across the capacitor is a linear triangular wave,
but the waveform on either terminal with respect to ground is the more comple# waveform
shown;
1$0
D E ! D I % IT A L S ELE C T & O N I CS
A

A
0
A
1
A
0
d
!
d
$
d
'
d

d
0
d
1
d
0
k #
3 3 3 3 3 3 3 3 3 3 3 333 3
0 0 0 3 3 3 3 3 3 3 0 k 0
0 0 0 3 3 3 3 3 3 3 1 k 1
0 0 1 3 3 3 3 3 3 0 3 k 0
0 0 1 3 3 3 3 3 3 1 3 k 1
0 1 0 3 3 3 3 3 0 3 3 k 0
0 1 0 3 3 3 3 3 1 3 3 k 1
0 1 1 3 3 3 3 0 3 3 3 k 0
0 1 1 3 3 3 3 1 3 3 3 k 1
1 0 0 3 3 3 0 3 3 3 3 k 0
1 0 0 3 3 3 1 3 3 3 3 k 1
1 0 1 3 3 0 3 3 3 3 3 k 0
1 0 1 3 3 1 3 3 3 3 3 k 1
1 1 0 3 0 3 3 3 3 3 3 k 0
1 1 0 3 1 3 3 3 3 3 3 k 1
G;% Draw and e#plain the function of dual slope analogue to digital converter; Derive the
equations used; (8)
Ans.
Dual slope A to D converterH <t has ' maQor blocCs;
1; An integrator
0; A (omparator
; A binary counter
'; A switch driver
The conversion process at T+0 with switch A1 in position 0; This connects the analogue
voltage Va to the input of the integrator; The output of the integrator will be
This results in high V
c
; This enables the AND ?ate and the clocC pulse reaches the cC input of
the counter, which was initially clear; The counter counts from 00ll00 to 11l;;11 when
1$1
D E ! D I % IT A L S ELE C T & O N I CS
0
n
31 clocC pulses are applied; At the ne#t clocC pulse 0
n
the counter is cleared and G becomes
1; This controls the state of A
1
which now moves to position 1 at T
1,
thereby connecting 3V
7
to
the input of the integrator; The output of the integrator now starts to move in the positive
direction; The counter continues to count until V
0
is less than 0; As soon as V
0
goes positive at
T
0
, V
(
goes @8W disabling the AND ?ate;
1$0
D E ! DI % I T A L S ELE C T & O NICS
Wave form of dual slope ABD convertor
The time T1 is given by
T
1
+ 0
N
T
(
where T1 is time period of clocC pulse;
When the switch A1 is in position 1, the output voltage of the integrator is given by
V
0
+ 0 at t + T
0
Therefore, T
0
/ T
1
+
@et the count recorded in the counter be n at T
0
therefore T
0
/ T
1
+ n T
(
+
which gives n +
G;%' What is a 9ultiple#er Tree4 Why is it needed4 Draw the blocC diagram of a 0H1
9ultiple#er Tree and e#plain how input is directed to the output in this system;(1!)
Ans
)21/,;1+:+$ T$++: The largest available 9:. <( is 1! to 1; To meet the larger input
needs there should be a provision to e#pand it; This can be achieved with the help of
Atrobe <nputs and so 9:. trees are designed;
8ne of the possible method is shown for 0 to 1 9:., by using two 1! to 1 9:. and
87 ?ate;
1$
D E ! DI % I T A L S ELE C T & O NICS
There are two 1! to 1 9:. 9
1
and 9
0
having data inputs 0l;;1$ and 1!l;;1
respectively; The selection lines are A

A
0
A
1
A
0
, which are able to select one input
among 1! inputs; Now the strobe pin is used as fifth selection line that is if it is 0 than
one input among the upper 9:. is selected and if A + 1, than one among the data input
of lower 9:. is selected; The output of both the 9:. are 8 7ed;
G; %$ With the help of a neat diagram, e#plain the worCing of a weighted3resistor DBA converter;
()
Ans
G+,79/+8 &+7,s/+$ DHA C#n*+$/+$:
N ,it digital input is applied to a register networC through electronic switch; This
electronic switch produces current < at 9A, )corresponding to @ogic 1*, <B0 at the ne#t
lower significant position; The total current produced will be proportional to digital
input; This current can be converted to corresponding voltage by using an op3ampere;
This circuit is referred to as weighted register converter since the resistance values are
weighted in accordance with the binary weights;
The current <
i
is given by
<
i
+ <
N31
- <
N30
- ll;;- <
0
where <
N31 +
V
N31
B 7, <
N30 +
V
N30
B 07, <
N3 +
V
N3
B' 7
also V
N
+ V)1* if bn + 1, V)8* if bn + 0
2or straight binary inputs V)0* + 0 and V)1* + 3 V
7
and the output voltage is given
by
G; %! ,riefly e#plain the followingH
)i* ,inary number system;
1$'
D E ! DI % I T A L S ELE C T & O NICS
)ii* Aigned binary numbers (7)
Ans
(,) B,n0$5 N234+$ S5s/+3
The number of system with base or 7adi# two is Cnown as the ,inary Number Aystem;
To represent the number, 0 O 1 are used; These are Cnown as bits; <t is a positional
system that is every place carries specific weight; As the base is two, the coefficients can
taCe only two value i;e; 0 O 1;
)N*
b
+ d
n31
d
n30
llllll;d
0 ^
d
31
d
30
llllllll;;d
3m
b + 0 )7adi#*
integer portion 7adi# 6oint 2raction
d
n31
+ 9ost significant bit
d
3m
+ @east significant bit
O ;0 g )d
i
or d
3f
* g b
31
(,,) S,7n+8 B,n0$5 N234+$s: <n decimal number system positive numbers are denoted
by )-* sign and negative numbers are denoted by /ve sign Digital circuits understand only
the language of 0es and 1es; Thus normally an additional bit is used for sign and it is
placed at the most significant position;
1; A e8e is used for -ve nos; and 1 is for /ve numbers; 2or e#ample an eight bit
signed number 00000100 represents -' and 10000100 represents )3'*; This
representation is Cnown as sign magnitude number; There are three different
ways by which signed numbers are presented;
0; On+As .#3;1,3+n/ $+;$+s+n/0/,#n: <n this system the -ve numbers are
represented by their ,inary equivalent with a 0 placed at most significant
position to represent the /ve numbers compliment is taCen and than a e1e is
placed as 9A, to represent the /ve sign; 2or e#ample - % + )0111*
0
3 % + )1000*
0
; TC#As C#3;1,3+n/ ;$+s+n/0/,#nH <f 1 is added number is Cnown as <es
compliment of the binary No; 2or e#ample 0es compliment representation of
0101 is 1011; Aince 0101 represents )-$*
10
therefore 1011 represents )3$*
10
in
two>s compliment representation;
G;%% What is chattering as applied to mechanical switches used in digital systems and why do
they occur4 What is its effect on the functioning of a sequential circuit4 (6)
Ans
C90//+$,n7:
9echanical switches are employed in digital systems as input devices by which digital
information )0 or 1* is entered into the system; When the arm of the switch is thrown
from one position to another, it chatters or bounces several times before finally coming
to the root in the position of contact; This is Cnown as bouncing or chattering; This
bounce is result of the spring loaded impact of the switch through contact and the pole
1$$
D E ! DI % I T A L S ELE C T & O NICS
contacts; <n a sequential circuit, if a 1 is to be entered through a switch then the switch is
thrown to the corresponding position, as soon as it is thrown to this position, the output
is 1 but the output oscillates between 0 O 1 for some times due to maCe and breaC
)bouncing* of the switch at the point of contact before coming to rest; This changes the
output of the sequential circuit and creates difficulties in the operation of the system;
This problem is eliminated by using bounce / free elimination switches
Q.78 Design a ' H 1 multiple#er with strobe input using NAND gates; (5)
Ans
D+s,7n #- 4 : 1 321/,;1+:+$ C,/9 s/$#4+ ,n;2/ 2s,n7 NAND 70/+s.
Q.7 5#plain the operation of octal to binary encoder; (8)
Ans
8ctal to binary encoder consists of eight inputs, one for each of eight digits and three
outputs that generate the corresponding binary number; 2or e#ampleH low order output bit U
is if the input octal digit is odd;
1$!
D E ! DI % I T A L S ELE C T & O NICS
1ere D
8
input is not connected to any 8 7 gateR the binary output must be all Deroes in
this case and all 0>s output is also obtained, when all inputs are Deroes; This discrepancy
can be resolved by providing one more output to indicate the fact that all inputs are not
Deroes;
T$2/9 /041+
In;2/s O2/;2/s
D
!
D
1
D
2
D
3
D
4
D
5
D
6
D
7
: 5 D
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
L#7,. 8,07$03 #- #./01 /# 4,n0$5 +n.#8+$
1$%

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