EE282 Lab 3

Clock generation, counting, and seven-segment display

3.1 Objectives
Learn to use 555 timer to generate clock signal to be used in a digital circuit.
Learn to use decade counter to count up to 99 and repeat.
Learn to use BCD-to-seven-segment decoder.

3.2 Components needed
One 555 timer.
One 74F193 (74LS193) up/down binary counter
one 74LS48 common cathode seven-segment decoder
one command cathode seven-segment display
one 3.0K and one 75K resistor
4.7 F capacitor
wires

3.3 Theory
A 555 timer can be used to generate low frequency signals to be used in many applications. For
this purpose, we need to configure the 555 timer to operate in the astable mode. The frequency of
the square wave is determined by two resistors and one capacitor.

A common-cathode seven-segment display can be driven by a 7448 common-cathode seven-
segment display decoder. By applying the BCD value (four bits) to the data input, the
corresponding seven-segment pattern will be generated.

A up/down decade counter can count from 0 to 9 and repeat or count from 9 down to 0 and then
repeat.

3.4 Lab procedure
1. Construct the 555 timer circuit to generate a digital waveform with 2 Hz frequency. The
circuit is shown in Figure 3.1. By choosing R1, R2, and C2 properly, any frequency can
be generated.
2. Construct a BCD counter in the count up mode. The pin assignment of the 74LS193 is
shown in Figure 3.2. For this experiment, connect the following:
- MR: tied to ground
- connect the CP
U
pin

to 555 pin 3 output
- tie the CP
D
pin to high to select count up
- connect Q3..Q0 to seven-segment decoder inputs
- use a resistor (1K) to pull PL pin to high
3. Connect the seven-segment decoder 74LS48 to the seven-segment display and the
counter output properly. The pin assignment of the 74LS48 is shown in Figure 3.3. Since
you only use one seven-segment display, all blanking signals need not be connected. The
light test (LT) input should be tied to high.

V
CC
(5V)
8
4
3
0.01 F
1 5
7
6
2
R
1
R
2
C
555
Timer
Figure 3.1 555 timer circuit in astable mode
f =
1.44
(R
1
+ 2R
2
)C
V
OUT


1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 3.2 74LS190 decade counter pin assignment
VCC
P0
P1
P2
P3
MR
TC
U
PL
GND
Q3
Q2
CP
D
Q0
Q1
74LS193
CP
U
: count up clock
CP
D
: count down clock
MR: Asynchronous
PL: parallel load (active low)
Pn: parallel data input
Qn: flip-flop outputs
TC
D
: terminal count down output
TC
U
: terminal count up output
CP
U
TC
D



B
C
D
A
GND
LT
BI/RBO
RBI
VCC
f
g
a
b
c
d
e
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
74LS48
Figure 3.3 74LS48 seven-segment decoder


4. Connect Q3..Q0 of 74LS193 to DCBA inputs of the 74LS48.
5. Connect the corresponding signals (a, b, c, d, e, f, g) of 74LS48 to those of the seven-
segment display.

The TC
U
signal is normally high. When a circuit has reached the maximum count state of 15, the
next high-to-low transition of the count up clock will cause TC
U
to go low. TC
U
will stay low
until CP
U
goes high again, thus effectively repeating the count up clock, but delayed by two gate
delays. This signal is used to cascade multiple 74LS193s.

3.5 Further investigation.

1. Choose a set of R1, R2, and C2 for the 555 timer to generate waveforms with 200 Hz and
1 KHz frequency.
Set 1. R1 = R2 = C2 =
Set 2. R1 = R2 = C2 =

The 74LS193 binary counter can be cascaded to become two-digit decimal counter. Draw the
circuit in the following space. Connect the circuit and use the LEDs on the Lab kit to display the
counter value. Set the clock frequency to about 1 Hz.