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Published by ER/J Y 1164 BU TV Consumer Care Printed in the Netherlands Subject to modification EN 3122 785 19130

2011-Apr-29

Copyright 2011 Koninklijke Philips Electronics N.V.


All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.
Colour Television Chassis
L11M1.1L
LA
19130_000_110421.eps
110421
Contents Page
1. Revision List 2
2. Technical Specifications and Connections 2
3. Precautions, Notes, and Abbreviation List 4
4. Mechanical Instructions 8
5. Service Modes, Error Codes, and Fault Finding 12
6. Alignments 18
7. Circuit Descriptions 20
8. IC Data Sheets 26
9. Block Diagrams
Wiring Diagram 32" (Thriller) 35
Wiring Diagram 40" (Thriller) 36
Block Diagram Video 37
Block Diagram Audio 38
Block Diagram Control & Clock Signals 39
Block Diagram I2C 40
Supply Lines Overview 41
10. Circuit Diagrams and PWB Layouts
B01 393912365052 42
B02 393912365052 43
B03 393912365052 45
B04 393912365052 46
B05 393912365052 50
B06 393912365052 52
B07 393912365052 56
313912365052 SSB Layout 57
T01 393912365071 59
313912365071 TCON Layout 65
11. Styling Sheets
Styling Sheet Thriller 32" 66
Styling Sheet Thriller 40" 67
Revision List EN 2 L11M1.1L LA 1.
2011-Apr-29
1. Revision List
Manual xxxx xxx xxxx.0
First release.
2. Technical Specifications and Connections
Index of this chapter:
2.1 Technical Specifications
2.2 Directions for Use
2.3 Connections
Notes:
Figures can deviate due to the different set executions.
Specifications are indicative (subject to change).
2.1 Technical Specifications
For on-line product support please use the links in Table 2-1.
Here is product information available, as well as getting started,
user manuals, frequently asked questions and software &
drivers.
Table 2-1 Described Model numbers
2.2 Directions for Use
You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com
2.3 Connections
Figure 2-1 Connection overview
Note: The following connector colour abbreviations are used
(according to DIN/IEC 757): Bk=Black, Bu=Blue, Gn=Green,
Gy=Grey, Rd=Red, Wh=White, Ye=Yellow.
2.3.1 Side Connections
1 - USB2.0
Figure 2-2 USB (type A)
CTN Styling Published in:
32PFL3606D/78 Thriller 3122 785 19130
40PFL3606D/78
S R O T C E N N O C E D I S S R O T C E N N O C R A E R
DIGITAL
AUDIO OUT
AUDIO IN
DVI/VGA
SERV.U
R L Pr Pb Y
CVI 1
BOTTOM REAR CONNECTORS
VGA HDMI 1
(ARC)
R L Pr Pb Y
CVI 2 ANTENNA
19130_001_110421.eps
110421
1
3
2
4 5 6 7
8 9 10 11
1 2 3 4
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090121
Technical Specifications and Connections EN 3 L11M1.1L LA 2.
2011-Apr-29
1 - +5V k
2 - Data (-) jk
3 - Data (+) jk
4 - Ground Gnd H
2 - AV IN: Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS 1 V
PP
/ 75 ohm jq
Wh - Audio L 0.5 V
RMS
/ 10 kohm jq
Rd - Audio R 0.5 V
RMS
/ 10 kohm jq
3 - HDMI: Digital Video, Digital Audio - In
Figure 2-3 HDMI (type A) connector
1 - D2+ Data channel j
2 - Shield Gnd H
3 - D2- Data channel j
4 - D1+ Data channel j
5 - Shield Gnd H
6 - D1- Data channel j
7 - D0+ Data channel j
8 - Shield Gnd H
9 - D0- Data channel j
10 - CLK+ Data channel j
11 - Shield Gnd H
12 - CLK- Data channel j
13 - Easylink Control channel/CEC jk
14 - n.c.
15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk
17 - Ground Gnd H
18 - +5V j
19 - HPD Hot Plug Detect j
20 - Ground Gnd H
2.3.2 Rear Connections
4 - CVI-1: Cinch: Video YPbPr - In, Audio - In
Wh - Audio - L 0.5 V
RMS
/ 10 k jq
Rd - Audio - R 0.5 V
RMS
/ 10 k jq
Rd - Video Pr 0.7 V
PP
/ 75 jq
Bu - Video Pb 0.7 V
PP
/ 75 jq
Gn - Video Y 1 V
PP
/ 75 jq
5 - Cinch: Digital Audio - Out
Bk - Coaxial 0.4 - 0.6V
PP
/ 75 ohm kq
6 - Service Connector (UART)
1 - Ground Gnd H
2 - UART_TX Transmit k
3 - UART_RX Receive j
7 - Mini Jack: Audio - In DVI/VGA
Bk - Audio 0.5 V
RMS
/ 10 k jo
2.3.3 Bottom Connections
8 - CVI-2: Cinch: Video YPbPr - In, Audio - In
Wh - Audio - L 0.5 V
RMS
/ 10 k jq
Rd - Audio - R 0.5 V
RMS
/ 10 k jq
Rd - Video Pr 0.7 V
PP
/ 75 jq
Bu - Video Pb 0.7 V
PP
/ 75 jq
Gn - Video Y 1 V
PP
/ 75 jq
9 - HDMI1: Digital Video, Digital Audio - In
Figure 2-4 HDMI (type A) connector
1 - D2+ Data channel j
2 - Shield Gnd H
3 - D2- Data channel j
4 - D1+ Data channel j
5 - Shield Gnd H
6 - D1- Data channel j
7 - D0+ Data channel j
8 - Shield Gnd H
9 - D0- Data channel j
10 - CLK+ Data channel j
11 - Shield Gnd H
12 - CLK- Data channel j
13 - Easylink Control channel/CEC jk
14 - ARC Audio Return Channel j
15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk
17 - Ground Gnd H
18 - +5V j
19 - HPD Hot Plug Detect j
20 - Ground Gnd H
10 - Aerial - In
- - F-type Coax, 75 D
11 - VGA: Video RGB - In
Figure 2-5 VGA Connector
1 - Video Red 0.7 V
PP
/ 75 j
2 - Video Green 0.7 V
PP
/ 75 j
3 - Video Blue 0.7 V
PP
/ 75 j
4 - n.c.
5 - Ground Gnd H
6 - Ground Red Gnd H
7 - Ground Green Gnd H
8 - Ground Blue Gnd H
9 - +5V
DC
+5 V j
10 - Ground Sync Gnd H
11 - n.c.
12 - DDC_SDA DDC data j
13 - H-sync 0 - 5 V j
14 - V-sync 0 - 5 V j
15 - DDC_SCL DDC clock j
10000_017_090121.eps
090428
19 1
18 2
10000_017_090121.eps
090428
19 1
18 2
1
6
10
11
5
15
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090127
Precautions, Notes, and Abbreviation List EN 4 L11M1.1L LA 3.
2011-Apr-29
3. Precautions, Notes, and Abbreviation List
Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List
3.1 Safety Instructions
Safety regulations require the following during a repair:
Connect the set to the Mains/AC Power via an isolation
transformer (>800 VA).
Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:
Route the wire trees correctly and fix them with the
mounted cable clamps.
Check the insulation of the Mains/AC Power lead for
external damage.
Check the strain relief of the Mains/AC Power cord for
proper function.
Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the on position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
4. Switch off the set, and remove the wire between the
two pins of the Mains/AC Power plug.
Check the cabinet for defects, to prevent touching of any
inner parts by the customer.
3.2 Warnings
All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
Be careful during measurements in the high voltage
section.
Never replace modules or other components while the unit
is switched on.
When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.
3.3 Notes
3.3.1 General
Measure the voltages and waveforms with regard to the
chassis (=tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).
Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
3.3.2 Schematic Notes
All resistor values are in ohms, and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k).
Resistor values with no multiplier may be indicated with
either an E or an R (e.g. 220E or 220R indicates 220 ).
All capacitor values are given in micro-farads ( = 10
-6
),
nano-farads (n= 10
-9
), or pico-farads (p= 10
-12
).
Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
An asterisk (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
The correct component values are listed on the Philips
Spare Parts Web Portal.
3.3.3 Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.
3.3.4 BGA (Ball Grid Array) ICs
Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
Magazine, then go to Repair downloads. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.
3.3.5 Lead-free Soldering
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
To reach a solder-tip temperature of at least 400C.
To stabilize the adjusted temperature at the solder-tip.
To exchange solder-tips for different applications.
Adjust your solder tool so that a temperature of around
360C - 380C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~4 sec.
Avoid temperatures above 400C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch off unused equipment or
reduce heat.
Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.
3.3.6 Alternative BOM identification
It should be noted that on the European Service website,
Alternative BOM is referred to as Design variant.
Precautions, Notes, and Abbreviation List EN 5 L11M1.1L LA 3.
2011-Apr-29
The third digit in the serial number (example:
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
result in sets which have the same CTN (Commercial Type
Number; e.g. 28PW9515/12) but which have a different B.O.M.
number.
By looking at the third digit of the serial number, one can
identify which B.O.M. is used for the TV set he is working with.
If the third digit of the serial number contains the number 1
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is
a 2 (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z
can be used, so in total: 9 plus 26=35 different B.O.M.s can be
indicated by the third digit of the serial number.
Identification: The bottom line of a type plate gives a 14-digit
serial number. Digits 1 and 2 refer to the production centre (e.g.
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M.
code, digit 4 refers to the Service version change code, digits 5
and 6 refer to the production year, and digits 7 and 8 refer to
production week (in example below it is 2010 week 10 / 2010
week 17). The 6 last digits contain the serial number.
Figure 3-1 Serial number (example)
3.3.7 Board Level Repair (BLR) or Component Level Repair
(CLR)
If a board is defective, consult your repair procedure to decide
if the board has to be exchanged or if it should be repaired on
component level.
If your repair procedure says the board should be exchanged
completely, do not solder on the defective board. Otherwise, it
cannot be returned to the O.E.M. supplier for back charging!
3.3.8 Practical Service Precautions
It makes sense to avoid exposure to electrical shock.
While some sources are expected to have a possible
dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.
Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
It is easy to do, and is a good service precaution.
3.4 Abbreviation List
0/6/12 SCART switch control signal on A/V
board. 0 =loop through (AUX to TV),
6 =play 16 : 9 format, 12 =play 4 : 3
format
AARA Automatic Aspect Ratio Adaptation:
algorithm that adapts aspect ratio to
remove horizontal black bars; keeps
the original aspect ratio
ACI Automatic Channel Installation:
algorithm that installs TV channels
directly from a cable network by
means of a predefined TXT page
ADC Analogue to Digital Converter
AFC Automatic Frequency Control: control
signal used to tune to the correct
frequency
AGC Automatic Gain Control: algorithm that
controls the video input of the feature
box
AM Amplitude Modulation
AP Asia Pacific
AR Aspect Ratio: 4 by 3 or 16 by 9
ASF Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
bars without discarding video
information
ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA
ATV See Auto TV
Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
AV External Audio Video
AVC Audio Video Controller
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz
BDS Business Display Solutions (iTV)
BLR Board-Level Repair
BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries
B-TXT Blue TeleteXT
C Centre channel (audio)
CEC Consumer Electronics Control bus:
remote control bus on HDMI
connections
CL Constant Level: audio output to
connect with an external amplifier
CLR Component Level Repair
ComPair Computer aided rePair
CP Connected Planet / Copy Protection
CSM Customer Service Mode
CTI Color Transient Improvement:
manipulates steepness of chroma
transients
CVBS Composite Video Blanking and
Synchronization
DAC Digital to Analogue Converter
DBE Dynamic Bass Enhancement: extra
low frequency amplification
DCM Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
DDC See E-DDC
10000_053_110228.eps
110228
Precautions, Notes, and Abbreviation List EN 6 L11M1.1L LA 3.
2011-Apr-29
D/K Monochrome TV system. Sound
carrier distance is 6.5 MHz
DFI Dynamic Frame Insertion
DFU Directions For Use: owner's manual
DMR Digital Media Reader: card reader
DMSD Digital Multi Standard Decoding
DNM Digital Natural Motion
DNR Digital Noise Reduction: noise
reduction feature of the set
DRAM Dynamic RAM
DRM Digital Rights Management
DSP Digital Signal Processing
DST Dealer Service Tool: special remote
control designed for service
technicians
DTCP Digital Transmission Content
Protection; A protocol for protecting
digital audio/video content that is
traversing a high speed serial bus,
such as IEEE-1394
DVB-C Digital Video Broadcast - Cable
DVB-T Digital Video Broadcast - Terrestrial
DVD Digital Versatile Disc
DVI(-d) Digital Visual Interface (d=digital only)
E-DDC Enhanced Display Data Channel
(VESA standard for communication
channel and display). Using E-DDC,
the video source can read the EDID
information form the display.
EDID Extended Display Identification Data
(VESA standard)
EEPROM Electrically Erasable and
Programmable Read Only Memory
EMI Electro Magnetic Interference
EPG Electronic Program Guide
EPLD Erasable Programmable Logic Device
EU Europe
EXT EXTernal (source), entering the set by
SCART or by cinches (jacks)
FDS Full Dual Screen (same as FDW)
FDW Full Dual Window (same as FDS)
FLASH FLASH memory
FM Field Memory or Frequency
Modulation
FPGA Field-Programmable Gate Array
FTV Flat TeleVision
Gb/s Giga bits per second
G-TXT Green TeleteXT
H H_sync to the module
HD High Definition
HDD Hard Disk Drive
HDCP High-bandwidth Digital Content
Protection: A key encoded into the
HDMI/DVI signal that prevents video
data piracy. If a source is HDCP coded
and connected via HDMI/DVI without
the proper HDCP decoding, the
picture is put into a snow vision mode
or changed to a low resolution. For
normal content distribution the source
and the display device must be
enabled for HDCP software key
decoding.
HDMI High Definition Multimedia Interface
HP HeadPhone
I Monochrome TV system. Sound
carrier distance is 6.0 MHz
I
2
C Inter IC bus
I
2
D Inter IC Data bus
I
2
S Inter IC Sound bus
IF Intermediate Frequency
IR Infra Red
IRQ Interrupt Request
ITU-656 The ITU Radio communication Sector
(ITU-R) is a standards body
subcommittee of the International
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.
SDI), is a digitized video format used
for broadcast grade video.
Uncompressed digital component or
digital composite signals can be used.
The SDI signal is self-synchronizing,
uses 8 bit or 10 bit data words, and has
a maximum data rate of 270 Mbit/s,
with a minimum bandwidth of 135
MHz.
iTV Institutional TeleVision; TV sets for
hotels, hospitals etc.
LS Last Status; The settings last chosen
by the customer and read and stored
in RAM or in the NVM. They are called
at start-up of the set to configure it
according to the customer's
preferences
LATAM Latin America
LCD Liquid Crystal Display
LED Light Emitting Diode
L/L' Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band
I, L is all bands except for Band I
LPL LG.Philips LCD (supplier)
LS Loudspeaker
LVDS Low Voltage Differential Signalling
Mbps Mega bits per second
M/N Monochrome TV system. Sound
carrier distance is 4.5 MHz
MHEG Part of a set of international standards
related to the presentation of
multimedia information, standardised
by the Multimedia and Hypermedia
Experts Group. It is commonly used as
a language to describe interactive
television services
MIPS Microprocessor without Interlocked
Pipeline-Stages; A RISC-based
microprocessor
MOP Matrix Output Processor
MOSFET Metal Oxide Silicon Field Effect
Transistor, switching device
MPEG Motion Pictures Experts Group
MPIF Multi Platform InterFace
MUTE MUTE Line
MTV Mainstream TV: TV-mode with
Consumer TV features enabled (iTV)
NC Not Connected
NICAM Near Instantaneous Compounded
Audio Multiplexing. This is a digital
sound system, mainly used in Europe.
NTC Negative Temperature Coefficient,
non-linear resistor
NTSC National Television Standard
Committee. Color system mainly used
in North America and J apan. Color
carrier NTSC M/N=3.579545 MHz,
NTSC 4.43=4.433619 MHz (this is a
VCR norm, it is not transmitted off-air)
NVM Non-Volatile Memory: IC containing
TV related data such as alignments
O/C Open Circuit
OSD On Screen Display
OAD Over the Air Download. Method of
software upgrade via RF transmission.
Upgrade software is broadcasted in
TS with TV channels.
OTC On screen display Teletext and
Control; also called Artistic (SAA5800)
P50 Project 50: communication protocol
between TV and peripherals
Precautions, Notes, and Abbreviation List EN 7 L11M1.1L LA 3.
2011-Apr-29
PAL Phase Alternating Line. Color system
mainly used in West Europe (colour
carrier =4.433619 MHz) and South
America (colour carrier
PAL M=3.575612 MHz and
PAL N =3.582056 MHz)
PCB Printed Circuit Board (same as PWB)
PCM Pulse Code Modulation
PDP Plasma Display Panel
PFC Power Factor Corrector (or Pre-
conditioner)
PIP Picture In Picture
PLL Phase Locked Loop. Used for e.g.
FST tuning systems. The customer
can give directly the desired frequency
POD Point Of Deployment: a removable
CAM module, implementing the CA
system for a host (e.g. a TV-set)
POR Power On Reset, signal to reset the uP
PSDL Power Supply for Direct view LED
backlight with 2D-dimming
PSL Power Supply with integrated LED
drivers
PSLS Power Supply with integrated LED
drivers with added Scanning
functionality
PTC Positive Temperature Coefficient,
non-linear resistor
PWB Printed Wiring Board (same as PCB)
PWM Pulse Width Modulation
QRC Quasi Resonant Converter
QTNR Quality Temporal Noise Reduction
QVCP Quality Video Composition Processor
RAM Random Access Memory
RGB Red, Green, and Blue. The primary
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced.
RC Remote Control
RC5 / RC6 Signal protocol from the remote
control receiver
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorcepteurs et
Tlviseurs
SCL Serial Clock I
2
C
SCL-F CLock Signal on Fast I
2
C bus
SD Standard Definition
SDA Serial Data I
2
C
SDA-F DAta Signal on Fast I
2
C bus
SDI Serial Digital Interface, see ITU-656
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mmoire.
Colour system mainly used in France
and East Europe. Colour
carriers =4.406250 MHz and
4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY
SVGA 800 600 (4:3)
SVHS Super Video Home System
SW Software
SWAN Spatial temporal Weighted Averaging
Noise reduction
SXGA 1280 1024
TFT Thin Film Transistor
THD Total Harmonic Distortion
TMDS Transmission Minimized Differential
Signalling
TS Transport Stream
TXT TeleteXT
TXT-DW Dual Window with TeleteXT
UI User Interface
uP Microprocessor
UXGA 1600 1200 (4:3)
V V-sync to the module
VESA Video Electronics Standards
Association
VGA 640 480 (4:3)
VL Variable Level out: processed audio
output toward external amplifier
VSB Vestigial Side Band; modulation
method
WYSIWYR What You See Is What You Record:
record selection that follows main
picture and sound
WXGA 1280 768 (15:9)
XTAL Quartz crystal
XGA 1024 768 (4:3)
Y Luminance signal
Y/C Luminance (Y) and Chrominance (C)
signal
YPbPr Component video. Luminance and
scaled color difference signals (B-Y
and R-Y)
YUV Component video
Mechanical Instructions EN 8 L11M1.1L LA 4.
2011-Apr-29
4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing
4.2 Service Positions
4.3 Assy/Panel Removal
4.4 Set Re-assembly
Notes:
Figures below can deviate slightly from the actual situation,
due to the different set executions.
4.1 Cable Dressing
Figure 4-1 Cable dressing 32"
19130_002_110421.eps
110421
Mechanical Instructions EN 9 L11M1.1L LA 4.
2011-Apr-29
Figure 4-2 Cable dressing 40"
19130_003_110426.eps
110426
11 mm saddle 1
150 mm tape 3
70 mm tape 4
Foam 2
Mechanical Instructions EN 10 L11M1.1L LA 4.
2011-Apr-29
4.2 Service Positions
For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Ensure that ESD safe measures are taken.
4.3 Assy/Panel Removal
Instructions below apply to the 40PFL3606D/78, but will be
similar for other models.
4.3.1 Rear Cover
Figure 4-3 Rear cover removal (40" )
Warning: Disconnect the mains power cord before removing
the rear cover.
See Figure 4-3.
1. Remove fixation screws [2] and [3] that secure the rear
cover. It is not necessary to remove the stand first [1].
2. Lift the rear cover from the TV. Make sure that wires and
flat foils are not damaged while lifting the rear cover from
the set.
3
2
1
19130_004_110426.eps
110426
3
3
2 2
3 2
2
3
3
3
3
2
1
1
2
3 2
3 2
1
1
3
Mechanical Instructions EN 11 L11M1.1L LA 4.
2011-Apr-29
4.3.2 LCD Panel
Refer to Figure 4-4 for details.
1. Remove the Stand [A].
2. Remove the Speakers/Subwoofer [B].
3. Remove the PSU [C], SSB [D] and TCON (E).
4. Remove the IR/LED board [F].
5. Remove the Local Control board [G].
6. Remove the clamps [1].
7. Remove all metal subframes [2] that do not belong to the
LCD display.
Figure 4-4 LCD Panel removal (based on 40" model)
4.4 Set Re-assembly
To re-assemble the whole set, execute all processes in reverse
order.
Notes:
While re-assembling, make sure that all cables are placed
and connected in their original position. See Figure 4-5
Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.
Figure 4-5 Flat Foil Cable (FFC) precautions
19130_006_110426.eps
110426
1 A
1 B
1 C
12 12
12
12
D
E
F
1 1
1 1 1 1
G
Proper FFC insertion: Silver line is not
visible when connector lock is closed
Improper FFC insertion: Silver line is
visible when connector lock is closed
Panel
Thinner blue FFC supporting
tapebelong to Panel side
Thicker blue FFC supporting
tapebelong to SSB side
TCON
19130_007_110426.eps
110426
Service Modes, Error Codes, and Fault Finding EN 12 L11M1.1L LA 5.
2011-Apr-29
5. Service Modes, Error Codes, and Fault Finding
Index of this chapter:
5.1 Test Points
5.2 Service Modes
5.3 Service Tools
5.4 Error Codes
5.5 The Blinking LED Procedure
5.6 Fault Finding and Repair Tips
5.7 Software Upgrading
5.1 Test Points
In the chassis schematics and layout overviews, the test points
are mentioned. In the schematics and layouts, test points are
indicated with Fxxx or Ixxx.
As most signals are digital, it will be difficult to measure
waveforms with a standard oscilloscope. Several key ICs are
capable of generating test patterns, which can be controlled via
ComPair. In this way it is possible to determine which part is
defective.
Perform measurements under the following conditions:
Service Default Mode.
Video: Colour bar signal.
Audio: 3 kHz left, 1 kHz right.
5.2 Service Modes
The Service Mode feature is split into four parts:
Service Default Mode (SDM).
Service Alignment Mode (SAM).
Customer Service Mode (CSM).
Computer Aided Repair Mode (ComPair).
SDM and SAM offer features, which can be used by the Service
engineer to repair/align a TV set. Some features are:
A pre-defined situation to ensure measurements can be
made under uniform conditions (SDM).
Activates the blinking LED procedure for error identification
when no picture is available (SDM).
The possibility to overrule software protections when SDM
is entered via the Service pins.
Make alignments (e.g. White Tone), (de)select options,
enter options codes, reset the error buffer (SAM).
Display information (SDM or SAM indication in upper
right corner of screen, error buffer, software version,
operating hours, options and option codes, sub menus).
The CSM is a Service Mode that can be enabled by the
consumer. The CSM displays diagnosis information, which the
customer can forward to the dealer or call centre. In CSM
mode, CSM, is displayed in the top right corner of the screen.
The information provided in CSM and the purpose of CSM is to:
Increase the home repair hit rate.
Decrease the number of nuisance calls.
Solved customers' problem without home visit.
ComPair Mode is used for communication between a computer
and a TV on I2C /UART level and can be used by a Service
engineer to quickly diagnose the TV set by reading out error
codes, read and write in NVMs, communicate with ICs and the
uP (PWM, registers, etc.), and by making use of a fault finding
database. It will also be possible to up and download the
software of the TV set via I2C with help of ComPair. To do this,
ComPair has to be connected to the TV set via the ComPair
connector, which will be accessible through the rear of the set
(without removing the rear cover).
5.2.1 General
Next items are applicable to all Service Modes or are general.
Life Timer
During the life time cycle of the TV set, a timer is kept (called
Op. Hour). It counts the normal operation hours (not the
Stand-by hours). The actual value of the timer is displayed in
SDM and SAM in a decimal value. Every two soft-resets
increase the hour by +1. Stand-by hours are not counted.
Software Identification, Version, and Cluster
The software ID, version, and cluster will be shown in the main
menu display of SDM, SAM, and CSM.
The screen will show: AAAAAAB-XX.YY, where:
AAAAAA is the chassis name: L11M11.
B is the region indication: E=Europe, A=AP/China, U=
NAFTA, L=LATAM.
XX is the main version number: this is updated with a major
change of specification (incompatible with the previous
software version). Numbering will go from 01 - 99 and AA -
ZZ.
If the main version number changes, the new version
number is written in the NVM.
If the main version number changes, the default
settings are loaded.
YY is the sub version number: this is updated with a minor
change (backwards compatible with the previous versions)
Numbering will go from 00 - 99.
If the sub version number changes, the new version
number is written in the NVM.
If the NVM is fresh, the software identification, version,
and cluster will be written to NVM.
Display Option Code Selection
When after an SSB or display exchange, the display option
code is not set properly, it will result in a TV with no display.
Therefore, it is required to set this display option code after
such a repair.
To do so, press the following key sequence on a standard RC
transmitter: 062598 directly followed by MENU/HOME and
xxx, where xxx is a 3 digit decimal value of the panel type,
see sticker on the side/bottom of the cabinet. When the value
is accepted and stored in NVM, the set will switch to Stand-by,
to indicate that the process has been completed.
Figure 5-1 Location of Display Option Code sticker
During this algorithm, the NVM-content must be filtered,
because several items in the NVM are TV-related and not SSB-
related (e.g. Model and Prod. S/N). Therefore, Model and
Prod. S/N data is changed into See Type Plate.
In case a call centre or consumer reads See Type Plate in
CSM mode, he needs to look to the side/bottom sticker to
identify the set, for further actions.
10000_038_090121.eps
090819
PHI LI PS
MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001
040
39mm
2
7
m
m
(CTN Sticker)
Display Option
Code
Service Modes, Error Codes, and Fault Finding EN 13 L11M1.1L LA 5.
2011-Apr-29
5.2.2 Service Default Mode (SDM)
Purpose
Set the TV in SDM mode in order to be able to create a pre-
defined setting for measurements to be made. In this platform,
a simplified SDM is introduced (without protection override and
without tuning to a predefined frequency).
Specifications
Set linear video and audio settings to 50%, but volume to
25%. Stored user settings are not affected.
Set Smart Picture to Game.
Set Smart Sound to Standard.
Tune channel to:
- for analogue SDM: channel 3 (61.25 MHz)
- for digital SDM: channel 26 (545.143 MHz).
For digital SDM: set PID default from the stream.
All service-unfriendly modes (if present) are disabled, since
they interfere with diagnosing/repairing a set. These
service unfriendly modes are:
(Sleep) timer.
Blue mute/Wall paper.
Auto switch off (when there is no ident signal).
Hotel or hospital mode.
Child lock or parental lock (manual or via V-chip).
Skipping, blanking of Not favourite, Skipped or
Locked presets/channels.
Automatic storing of Personal Preset or Last Status
settings.
Automatic user menu time-out (menu switches back/
OFF automatically.
Auto Volume levelling (AVL).
How to Activate
To activate analogue SDM, use one of the following methods:
Press the following key sequence on the RC transmitter:
062596 directly followed by the MENU button.
Short one of the Service pads on the TV board during cold
start (see Figure 5-2). Then press the mains button
(remove the short after start-up).
Caution: When doing this, the service-technician must
know exactly what he is doing, as it could damage the
television set.
To activate digital SDM:
Press the following sequence on the RC transmitter:
062593 directly followed by the MENU button.
Figure 5-2 Service pads (SSB component side)
On Screen Menu
After activating SDM, the following items are displayed, with
SDM in the upper right corner of the screen to indicate that the
television is in Service Default Mode.
Menu items and explanation:
xxxxx: Operating hours (in decimal).
AAAAAAB-XX.YY: See paragraph Software
Identification, Version, and Cluster for the SW name
definition.
ERR: Shows all errors detected since the last time the
buffer was erased in format <xxx><xxx><xxx><xxx>
<xxx>(five errors possible).
OP: Used to read-out the option bytes. Ten codes (in two
rows) are possible.
How to Navigate
As this mode is read only, there is not much to navigate. To
switch to other modes, use one of the following methods:
Command MENU from the user remote will enter the
normal user menu (brightness, contrast, color, etc...) with
SDM OSD remaining, and pressing MENU key again will
return to the last status of SDM again.
To prevent the OSD from interfering with measurements in
SDM, command OSD or i+ (STATUS or INFO for
NAFTA and LATAM) from the user remote will toggle the
OSD on/off with SDM OSD remaining always on.
Press the following key sequence on the remote control
transmitter: 062596 directly followed by the INFO[i+]/OK
button to switch to SAM (do not allow the display to time out
between entries while keying the sequence).
How to Exit
Switch the set to Stand-by by
pressing the standby button on the remote control
transmitter or on the television set, or
via a standard RC-transmitter by keying the 00 sequence.
If you switch the television set off by removing the mains (i.e.,
unplugging the television), the television set will remain in SDM
when mains is re-applied, and the error buffer is not cleared.
The error buffer will only be cleared when the clear command
is used in the SAM menu.
Note:
If the TV is switched off by a power interrupt while in SDM,
the TV will show up in the last status of SDM menu as soon
as the power is supplied again. The error buffer will not be
cleared.
In case the set is accidentally in Factory mode (with an F
displayed on the screen), pressing and holding VOL-
button for 5 seconds and then followed by pressing and
holding the CH- button for another 5 seconds should exit
the Factory mode.
5.2.3 Service Alignment Mode (SAM)
Purpose
To change option settings.
To display / clear the error code buffer.
To perform alignments.
Specifications
Operation hours counter (maximum five digits displayed).
Software version, error codes, and option settings display.
Error buffer clearing.
Option settings.
Software alignments (White Tone).
NVM Editor.
Set screen mode to full screen (all content is visible).
Set Smart Picture to Game.
How to Activate
To activate SAM, use one of the following methods:
Press the following key sequence on the remote control
transmitter: 062596 directly followed by the INFO[i+] /OK
button. Do not allow the display to time out between entries
while keying the sequence.
Or via ComPair.
After entering SAM, the following items are displayed, with
SAM in the upper right corner of the screen to indicate that the
television is in Service Alignment Mode.
19130_008_110426.eps
110426
SDM
Service Modes, Error Codes, and Fault Finding EN 14 L11M1.1L LA 5.
2011-Apr-29
Menu items and explanation:
1. System Information.
Op Hour: This represents the life timer. The timer
counts normal operation hours, but does not count
Stand-by hours.
MAIN SW ID: See paragraph Software Identification,
Version, and Cluster for the SW name definition.
ERR: Shows all errors detected since the last time the
buffer was erased. Five errors possible.
OP1/OP2: Used to read-out the option bytes. See
paragraph 6.6 Option Settings in the Alignments
section for a detailed description. Ten codes are
possible.
2. Tuner.
AGC Adjustment: See paragraph 6.3.1 for
instructions.
Store: To store the data.
3. Clear. Erases the contents of the error buffer. Select this
menu item and press the MENU RIGHT key on the remote
control. The content of the error buffer is cleared.
4. Options. To set the option bits. See paragraph 6.6 Option
Settings in the Alignments chapter for a detailed
description.
5. RGB Align. To align the White Tone. See White Tone
Alignment: for a detailed description.
6. NVM Editor. To change the NVM data in the television set.
See also paragraph 5.6 Fault Finding and Repair Tips.
7. Upload to USB.
8. Download from USB.
9. Initialise NVM. To initialize a (corrupted) NVM. Be careful,
this will erase all settings!
10. Auto ADC. Refer to chapter 6. Alignments for detailed
information.
11. EDID Write Enable. Enables EDID writing (not applicable
to Berlinale sets).
12. Service Data. Virtual Key board for character input entry.
How to Navigate
In the SAM menu, select menu items with the UP/DOWN
keys on the remote control transmitter. The selected item
will be indicated. When not all menu items fit on the screen,
use the UP/DOWN keys to display the next / previous
menu items.
With the LEFT/RIGHT keys, it is possible to:
Activate the selected menu item.
Change the value of the selected menu item.
Activate the selected sub menu.
When you press the MENU button twice while in top level
SAM, the set will switch to the normal user menu (with the
SAM mode still active in the background). To return to the
SAM menu press the MENU button.
The INFO[i+]/OK key from the user remote will toggle the
OSD on/off with SAM OSD remaining always on.
Press the following key sequence on the remote control
transmitter: 062596 directly followed by the MENU button
to switch to SDM (do not allow the display to time out
between entries while keying the sequence).
How to Store SAM Settings
To store the settings changed in SAM mode (except the
OPTIONS and RGB ALIGN settings), leave the top level SAM
menu by using the POWER button on the remote control
transmitter or the television set. The mentioned exceptions
must be stored separately via the STORE button.
How to Exit
Switch the set to STANDBY by pressing the mains button on
the remote control transmitter or the television set, or by
keying-in the 00 sequence on a standard RC-transmitter.
Note:
When the TV is switched off by a power interrupt while in
SAM, the TV will show up in normal operation mode as
soon as the power is supplied again. The error buffer will
not be cleared.
In case the set is in Factory mode by accident (with F
displayed on screen), pressing and holding VOL- button
for 5 seconds and then followed by pressing and holding
the CH- button for another 5 seconds should exit the
Factory mode.
5.2.4 Customer Service Mode (CSM)
Purpose
The Customer Service Mode shows error codes and
information on the TVs operation settings. A call centre can
instruct the customer (by telephone) to enter CSM in order to
identify the status of the set. This helps them to diagnose
problems and failures in the TV before making a service call.
The CSM is a read-only mode; therefore, modifications are not
possible in this mode.
Specifications
Ignore Service unfriendly modes.
Set volume to 25%.
Set Smart Picture to Game.
Set Smart Sound to Standard.
Line number for every line (to make CSM language
independent).
Set the screen mode to full screen (all contents on screen
is visible).
After leaving the Customer Service Mode, the original
settings are restored.
Possibility to use CH+ or CH- for channel surfing, or
enter the specific channel number on the RC.
How to Activate
To activate CSM, press the following key sequence on a
standard remote control transmitter: 123654 (do not allow the
display to time out between entries while keying the sequence).
After entering the Customer Service Mode, the following items
are displayed:
Menu Explanation CSM1
1. Set Type. Type number, e.g. 32PFL3605/78. (*)
2. Production code. Product serial no., e.g.
BZ1A1008123456 (*). BZ=Production centre, 1=BOM
code, A=Service version change code, 10=Production
year, 08=Production week, 123456=Serial number.
3. Installation date. Indicates the date of the first initialization
of the TV. This date is acquired via time extraction.
4. a - Option Code 1. Option code information (group 1).
b - Option Code 2. Option code information (group 2).
5. SSB. Indication of the SSB factory ID (=12nc). (*)
6. Display. Indication of the display ID (=12 nc). (*)
7. PSU. Indication of the PSU factory ID (=12nc).
(*) If an NVM IC is replaced or initialized, these items must be
re-written to it. ComPair will foresee in a possibility to do this.
Also the NVM editor in the SAM menu can be used.
Menu Explanation CSM2
1. Current Main SW. Shows the main software version.
2. Standby SW. Shows the Stand-by software version.
3. Panel Code. Shows the current display code.
4. Bootloader ID. Shows the Bootloader software ID.
5. NVM Version. The NVM software version no.
6. Flash ID. Shows the flash ID.
Menu Explanation CSM3
1. Signal Quality. Shows the signal quality (No Tuned/Poor/
Average/Good).
2. Child lock. This is a combined item for locks. If any lock
(Preset lock, child lock, lock after, or Parental lock) is
active, this item indicates active.
Service Modes, Error Codes, and Fault Finding EN 15 L11M1.1L LA 5.
2011-Apr-29
3. HDCP Keys. Indicates if the HDMI keys (or HDCP keys)
are valid or not. Not applicable to Berlinale series.
4. not used
5. not used
6. not used
7. not used.
Create a CSM dump on an USB stick
There will be CSM dump to a plugged in USB-stick upon
entering CSM-mode. An extended CSM dumpwill be created
when the OK button on RC is pressed in CSM while a USB
stick is plugged in. A direct CSM flash dump will be created
when the buttons red +2679 on the remote control are
pressed in CSM while a USB stick is plugged in.
How to Exit
To exit CSM, use one of the following methods:
Press the MENU/HOME button on the remote control
transmitter.
Press the POWER button on the remote control
transmitter.
Press the POWER button on the television set.
5.3 Service Tools
5.3.1 ComPair
Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps you to quickly get an understanding on how
to repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. You do not
have to know anything about I2C or UART commands
yourself, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the uP
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The (new) ComPair II interface box is connected to the PC via
an USB cable. For the TV chassis, the ComPair interface box
and the TV communicate via a bi-directional cable via the
service connector(s).
How to Connect
This is described in the ComPair chassis fault finding database.
Figure 5-3 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs will be
blown!
How to Order
ComPair II order codes:
ComPair II interface: 3122 785 91020.
ComPair UART interface cable: 3138 188 75051.
Program software can be downloaded from the Philips
Service web portal.
Note: For this chassis, Pgammar and T-con NVM
programming (VCOM alignment) are added to ComPair.
Additional cables for VCOM Alignment
ComPair/I
2
C interface cable: 3122 785 90004.
ComPair/VGA adapter cable: 9965 100 09269.
5.4 Error Codes
5.4.1 Introduction
Error codes are required to indicate failures in the TV set. In
principle a unique error code is available for every:
Activated (SW) protection.
Failing I
2
C device.
General I
2
C error.
The last five errors, stored in the NVM, are shown in the
Service menus. This is called the error buffer.
The error code buffer contains all errors detected since the last
time the buffer was erased. The buffer is written from left to
right. When an error occurs that is not yet in the error code
buffer, it is displayed at the left side and all other errors shift one
position to the right.
An error will be added to the buffer if this error differs from any
error in the buffer. The last found error is displayed on the left.
An error with a designated error code never leads to a
deadlock situation. It must always be diagnosable (e.g. error
buffer via OSD or blinking LED or via ComPair).
In case a failure identified by an error code automatically
results in other error codes (cause and effect), only the error
code of the MAIN failure is displayed.
10000_036_090121.eps
091118
TO
UART SERVICE
CONNECTOR
TO
UART SERVICE
CONNECTOR
TO
I2C SERVICE
CONNECTOR
TO TV
PC
HDMI
I
2
C only
Optional power
5V DC
ComPair II Developed by Philips Brugge
RC out
RC in
Optional
Switch
Power Mode Link/
Activity
I
2
C
ComPair II
Multi
function
RS232 /UART
Service Modes, Error Codes, and Fault Finding EN 16 L11M1.1L LA 5.
2011-Apr-29
5.4.2 How to Read the Error Buffer
You can read the error buffer in three ways:
On screen via the SAM/SDM/CSM (if you have a picture).
Example:
ERROR: 0 0 0 0 0 : No errors detected
ERROR: 6 0 0 0 0 : Error code 6 is the last and only
detected error
ERROR: 9 6 0 0 0 : Error code 6 was detected first and
error code 9 is the last detected (newest) error
Via the blinking LED procedure (when you have no
picture). See paragraph 5.5 The Blinking LED Procedure.
Via ComPair.
5.4.3 Error codes
The layer 1 error codes are pointing to the defective board.
They are triggered by LED blinking when CSM is activated. In
the LC10 platform, only two boards are present: the SSB and
the PSU/IPB, meaning only the following layer 1 errors are
defined:
2: SSB
3: IPB/PSU
4: Display
Table 5-1 Error code table
5.4.4 How to Clear the Error Buffer
The error code buffer is cleared in the following cases:
By using the CLEAR command in the SAM menu:
By using the following key sequence on the remote control
transmitter: 062599 directly followed by the OK button.
If the contents of the error buffer have not changed for 50
hours, the error buffer resets automatically.
Note: If you exit SAM by disconnecting the mains from the
television set, the error buffer is not reset.
5.5 The Blinking LED Procedure
5.5.1 Introduction
The software is capable of identifying different kinds of errors.
Because it is possible that more than one error can occur over
time, an error buffer is available, which is capable of storing the
last five errors that occurred. This is useful if the OSD is not
working properly.
Errors can also be displayed by the blinking LED procedure.
The method is to repeatedly let the front LED pulse with as
many pulses as the error code number, followed by a period of
1.5 seconds in which the LED is off. Then this sequence is
repeated.
Example (1): error code 4 will result in four times the sequence
LED on for 0.25 seconds / LED off for 0.25 seconds. After
this sequence, the LED will be off for 1.5 seconds. Any RC
command terminates the sequence. Error code LED blinking is
in red color.
Example (2): the content of the error buffer is 12 9 6 0 0
After entering SDM, the following occurs:
1 long blink of 5 seconds to start the sequence,
12 short blinks followed by a pause of 1.5 seconds,
9 short blinks followed by a pause of 1.5 seconds,
6 short blinks followed by a pause of 1.5 seconds,
1 long blink of 1.5 seconds to finish the sequence,
The sequence starts again with 12 short blinks.
5.5.2 Displaying the Entire Error Buffer
Additionally, the entire error buffer is displayed when Service
Mode SDM is entered.
5.6 Fault Finding and Repair Tips
Notes:
It is assumed that the components are mounted correctly
with correct values and no bad solder joints.
Before any fault finding actions, check if the correct
options are set.
5.6.1 NVM Editor
In some cases, it can be convenient if one directly can change
the NVM contents. This can be done with the NVM Editor in
SAM mode. With this option, single bytes can be changed.
Caution:
Do not change these, without understanding the
function of each setting, because incorrect NVM
settings may seriously hamper the correct functioning
of the TV set!
Always write down the existing NVM settings, before
changing the settings. This will enable you to return to the
original settings, if the new settings turn out to be incorrect.
5.6.2 Load Default NVM Values
It is possible to download default values automatically into the
NVM in case a blank NVM is placed or when the NVM first 20
address contents are FF. After the default values are
downloaded, it is possible to start-up and to start aligning the
TV set. To initiate a forced default download the following
action has to be performed:
1. Switch off the TV set with the mains cord disconnected
from the wall outlet (it does not matter if this is from Stand-
by or Off situation).
2. Short-circuit the SDM pads on the SSB (keep short
circuited, see Figure 5-2).
3. Press P+ or CH+ on the local keyboard (and keep it
pressed).
4. Reconnect the mains supply to the wall outlet.
5. Release the P+ or CH+ when the set is started up and
has entered SDM.
When the downloading has completed successfully, the set will
perform a restart. After this, put the set to Stand-by and remove
the short-circuit on the SDM pads.
Alternative method:
It is also possible to upload the default values to the NVM with
ComPair in case the SW is changed, the NVM is replaced with
a new (empty) one, or when the NVM content is corrupted.
After replacing an EEPROM (or with a defective/no EEPROM),
default settings should be used to enable the set to start-up and
allow the Service Default Mode and Service Alignment Mode to
be accessed.
Layer-1
error code
Defective
board
Layer-2
error code Defective device
2 SSB 11 Speaker DC protection active on SSB
3 IPB/PSU 16 +12 missing/low, PSU defective
3 IPB/PSU 17 POK line defective
2 SSB 35 EEPROM I2C error on SSB, M24C16
2 SSB 34 Tuner I2C error on SSB
2 SSB 23 HDMI Mux IC I2C error on SSB - Berninale
models with Mux only
2 SSB 27 Channel decoder on SSB
4 Display
(Inverter)
18 LCD Panel inverter error. INV_STATUS
(for 32sets only)
Service Modes, Error Codes, and Fault Finding EN 17 L11M1.1L LA 5.
2011-Apr-29
5.6.3 No Picture
When you have no picture, first make sure you have entered
the correct display code.
See Display Option Code Selection for the instructions.
5.6.4 Unstable Picture via HDMI input
Check (via ComPair) if HDMI EDID data is properly
programmed.
5.6.5 No Picture via HDMI input
Check if HDCP key is valid. This can be done in CSM.
5.6.6 HDMI CEC Not Functioning
Go to Home/Menu ->Setup ->Installation ->Preference and
set the Easylink option to on. Also check if the connected
device is CEC enabled.
5.6.7 TV Will Not Start-up from Stand-by.
Possible Stand-by Controller failure. Reflash the SW.
5.7 Software Upgrading
5.7.1 Introduction
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
stand alone set. A description on how to upgrade the main
software can be found in the DFU or on the Philips website.
5.7.2 Main Software Upgrade
Automatic Software Upgrade
In normal conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the autorun.upg (FUS part
in the one-zip file). This can also be done by the consumers
themselves, but they will have to get their software from the
commercial Philips website or via the Software Update
Assistant in the user menu (see DFU). The autorun.upg file
must be placed in the root of your USB stick.
How to upgrade:
1. Copy the autorun.upg file to the root of an USB stick.
2. Insert the USB stick in the side I/O while the set is on.
The TV will prompt an upgrade message. Press Update
to continue, after which the upgrading process will start. As
soon as the programming is finished, the set must be
restarted.
In the Setup menu you can check if the latest software is
running.
5.7.3 How to Copy NVM Data to/from USB
Write NVM Data to USB
1. Insert the USB stick into the USB slot while in SAM mode.
2. Execute the command "NVM Copy" >"NVM Copy to USB",
to copy the NVM data to the USB stick. The NVM filename
on the USB stick will be named
"L11M11L_NVM_T2U.BIN" (this takes a couple of
seconds).
Write NVM Data to TV
1. First, ensure (via a PC) that the filename on the USB stick
has the correct format: "L11M11L_NVM_U2T.BIN".
2. Insert the USB stick into the USB slot while in SAM mode.
3. Execute the command "NVM Copy" >"NVM Copy from
USB" to copy the USB data to NVM (this takes about a
minute to complete).
To write an NVM mask to the TV, ensure that the mask has the
correct format: "L11M11L_NVM_U2T.MAK" (0x00 to write
protect, 0xFF to overwrite).
Important: The file must be located in the " /Repair" directory
of the USB stick.
5.7.4 How to Copy EDID Data to/from USB
Write EDID Data to USB
1. Insert the USB stick into the USB slot while in SAM mode.
2. Execute the command "NVM Copy" >"EDID Copy to
USB", to copy the EDID data to the USB stick. The
filename on the USB stick will be named
"L11M11L_EDID_T2U.BIN" (this takes a couple of
seconds).
Write EDID Data to TV
1. First, ensure (via a PC) that the filename on the USB stick
has the correct format: "L11M11L_EDID_U2T.BIN".
2. Insert the USB stick into the USB slot while in SAM mode.
3. Execute the command "NVM Copy" >"EDID Copy from
USB" to copy the USB data to EDID (this takes about a
minute to complete).
Important: The file must be located in the " /Repair" directory
of the USB stick.
5.7.5 How to Copy the Channel List to/from USB
Write Channel List Data to USB
1. Insert the USB stick into the USB slot while in SAM mode.
2. Execute the command "Channel list Copy to USB", to copy
the channel list data to the USB stick. The filename on the
USB stick will be named "L11M11L_CHTB_T2U.BIN" (this
takes a couple of seconds).
Write Channel List Data to TV
1. First, ensure (via a PC) that the filename on the USB stick
has the correct format: "L11M11L_CHTB_U2T.BIN".
2. Insert the USB stick into the USB slot while in SAM mode.
3. Execute the command "Chanel list Copy from USB" to
copy the USB data to the TV (this takes about a minute to
complete).
Important: The file must be located in the " /Repair" directory
of the USB stick.
Alignments EN 18 L11M1.1L LA 6.
2011-Apr-29
6. Alignments
Index of this chapter:
6.1 General Alignment Conditions
6.2 Hardware Alignments
6.3 Software Alignments
6.4 ADC gain adjustment
6.6 Option Settings
Note: Figures below can deviate slightly from the actual
situation, due to the different set executions.
General: The Service Default Mode (SDM) and Service
Alignment Mode (SAM) are described in chapter 5. Menu
navigation is done with the CURSOR UP, DOWN, LEFT or
RIGHT keys of the remote control transmitter.
6.1 General Alignment Conditions
Perform all electrical adjustments under the following
conditions:
Power supply voltage (depends on region):
AP-NTSC: 120 V
AC
or 230 V
AC
/ 50 Hz ( 10%).
AP-PAL-multi: 120 - 230 V
AC
/ 50 Hz ( 10%).
EU: 230 V
AC
/ 50 Hz ( 10%).
LATAM-NTSC: 120 - 230 V
AC
/ 50 Hz ( 10%).
US: 120 V
AC
/ 60 Hz ( 10%).
Connect the set to the mains via an isolation transformer
with low internal resistance.
Allow the set to warm up for approximately 15 minutes.
Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to
AUDIO_GND).
Caution: It is not allowed to use heatsinks as ground.
Test probe: Ri >10 Mohm, Ci <20 pF.
Use an isolated trimmer/screwdriver to perform
alignments.
6.2 Hardware Alignments
There are no hardware alignments foreseen for this chassis,
but below find an overview of the most important DC voltages
on the SSB. These can be used for checking proper functioning
of the DC/DC converters.
6.3 Software Alignments
With the software alignments of the Service Alignment Mode
(SAM) the Tuner and RGB settings can be aligned.
6.3.1 Tuner Adjustment (RF AGC Take Over Point)
Purpose: To keep the tuner output signal constant as the input
signal amplitude varies.
No alignment is necessary, as the AGC alignment is done
automatically.
6.3.2 RGB Alignment
Before alignment, set the picture as follows:
White Tone Alignment:
Activate SAM.
Select RGB Align. and choose a color temperature.
Use a 100% white screen as input signal and set the
following values:
Red BL Offset and Green BL Offset to 7 (if
present).
All White point values initial to 127.
In case you have a color analyzer:
Measure with a calibrated (phosphor- independent) color
analyzer (e.g. Minolta CA-210) in the centre of the screen.
Consequently, the measurement needs to be done in a
dark environment.
Adjust the correct x,y coordinates (while holding one of the
White point registers R, G or B on max. value) by means of
decreasing the value of one or two other white points to the
correct x,y coordinates (see Table 6-1 White D alignment
values). Tolerance: dx: 0.002, dy: 0.002.
Repeat this step for the other color Temperatures that need
to be aligned.
When finished return to the SAM root menu and press
STANDBY on the RC to store the aligned values to the
NVM.
Table 6-1 White D alignment values
If you do not have a color analyzer, you can use the default
values. This is the next best solution. The default values are
average values coming from production (statistics).
Set the RED, GREEN and BLUE default values per
temperature according to the values in the Tint settings
table.
When finished return to the SAM root menu and press
STANDBY on the RC to store the aligned values to the
NVM.
Description
Test
Point
Specifications (V)
Diagram Min. Typ. Max.
+12VS F118 11.7 12.3 12.91 B01_DC-DC
+3V3_STBY F113 3.2 3.3 3.4 B01_DC-DC
+3V3_SW F133 3.17 3.34 3.5 B01_DC-DC
+1V25_SW F131 1.18 1.25 1.31 B01_DC-DC
+5V_SW F132 4.98 5.25 5.51 B01_DC-DC
+1V8_SW F125 1.74 1.83 1.92 B01_DC-DC
+1V1_SW F101 0.94 1.1 1.15 B01_DC-DC
+5VS F235 4.94 5.2 5.46 B02A_Tuner_IF
+2V5_SW F136 2.38 2.5 2.62 B01_DC-DC
+5VTUN_DI
GITAL
F236 4.75 5 5.25 B02_Tuner_IF
VLS_15V6 FJ 01 14.82 15.6 16.38 B08C_TCON DC/DC
VGH_35V FM02 34.0 35.0 36.0 B08F_MINI LVDS
VGL_-6V FJ 14 -7.0 -6.0 -5.0 B08C_TCON DC/DC
VCC_3V3 FJ 13 3.14 3.3 3.47 B08C_TCON DC/DC
VCC1V8 FJ 05 1.71 1.8 1.89 B08C_TCON DC/DC
Picture Setting
Dynamic backlight Off
Dynamic Contrast Off
Colour Enhancement Off
Picture Format Unscaled
Light Sensor Off
Brightness 50
Colour 0
Contrast 100
Value Cool (11000 K) Normal (9000 K) Warm (6500 K)
x 0.276 0.287 0.313
y 0.282 0.296 0.329
Alignments EN 19 L11M1.1L LA 6.
2011-Apr-29
Table 6-2 Tint settings 32"
Table 6-3 Tint settings 40"
6.4 ADC gain adjustment
Use a Quantum Data Patters Generator 802BT and apply a
PgcWrgb image (dot, cross and color bar mix pattern)
according to Figure 6-1.
Figure 6-1 PgcWrgb pattern
6.4.1 YPbPr
Following instructions result in correct alignment of ADC gain,
offset and phase, related to YPbPr input signal. Apply a signal
of format 1080i25.
Apply following signals to the YPbPr input connectors:
Pr signal of 0.7 Vp-p
1
/ 75 ohm to the red cinch
connector.
Y signal of 0.7 Vb-p
2
/ 75 ohm with a sync pulse of 0.3
Vp-p
1
to the green cinch connector.
Pb signal of 0.7 Vb-p
1
/ 75 ohm to the blue cinch
connector.
Select the input source to YPbPr input.
In SAM, initiate the Auto ADC calibration command.
Upon appearance of the Auto ADC Completed message, the
alignment is completed.
Notes:
1. Peak-to-Peak
2. Black-to-Peak.
6.4.2 PC VGA
Following instructions result in correct alignment of ADC gain,
offset and phase, related to PC VGA input signal. Apply a
signal of format DMT1060.
Apply following signals to the PC VGA input connector:
Red signal of 0.7 Vp-p
1
/ 75 ohm.
Green signal of 0.7 Vp-p
1
/ 75 ohm.
Blue signal of 0.7 Vp-p
1
/ 75 ohm.
Select the input source to PC VGA input.
In SAM, initiate the Auto ADC calibration command.
Upon appearance of the Auto ADC Completed message, the
alignment is completed.
6.5 TCON Alignment (= VCOM alignment)
New requirement for TCON on SSB project:
The purpose of VCOM alignment is to obtain an equal
voltages for both Positive and Negative LC polarity. This is
important to avoid Flicker and Image Sticking.
The P-Gamma +VCOM calibrator IC, ISL24837 is used for
VCOM adjustment.
The adjusted VCOM data will be stored inside on-chip
memory and will be automatically recalled during each
power-up.
ComPair (see 5.3.1 ComPair) will foresee in a possibility to do
this alignment.
6.6 Option Settings
6.6.1 Introduction
The microprocessor communicates with a large number of I
2
C
ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence/absence of these specific
ICs (or functions) is made known by the option codes.
Notes:
After changing the option(s), save them with the STORE
command.
The new option setting becomes active after the TV is
switched off and on again with the mains switch (the
EAROM is then read again).
6.6.2 How To Set Option Codes
When the NVM is replaced, all options will require resetting. To
be certain that the factory settings are reproduced exactly, you
must set all option numbers. You can find the correct option
numbers see sticker on the inside the cabinet.
How to Change Options Codes
An option code (or option byte) represents eight different
options (bits). All options are controlled via ten option bytes
(OP#1... OP#10).
Activate SAM and select Options. Now you can select the
option byte (OP#1... OP#10) with the CURSOR UP/ DOWN
keys, and enter the new 3 digit (decimal) value. For the correct
factory default settings, see the sticker inside the set.
Colour Temp. R G B
Cool t.b.d. t.b.d. t.b.d.
Normal t.b.d. t.b.d. t.b.d.
Warm t.b.d. t.b.d. t.b.d.
Colour Temp. R G B
Cool t.b.d. t.b.d. t.b.d.
Normal t.b.d. t.b.d. t.b.d.
Warm t.b.d. t.b.d. t.b.d.
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Circuit Descriptions EN 20 L11M1.1L LA 7.
2011-Apr-29
7. Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Supply
7.3 Video
7.3.1 Video: Front-End
7.4 Audio
7.5 Inputs
7.5.1 Inputs: HDMI
7.5.2 Inputs: USB
Notes:
Only new circuits (circuits that are not published recently)
are described.
Figures can deviate slightly from the actual situation, due
to different set executions.
For a good understanding of the following circuit
descriptions, please use chapter 9. Block Diagrams and
10. Circuit Diagrams and PWB Layouts. Where necessary,
you will find a separate drawing for clarification.
7.1 Introduction
The LC11M1.1L LA chassis is a digital chassis using a
Mediatek chipset. It covers screen sizes of 32" to 40".
The xxPFL3x06D/xx sets come with the Thriller styling, and
the xxPFL5x06D/xx come with the Berlinale styling.
Main key components are the Mediatek MT5363 integrated
System On Chip (SoC) that supports multimedia video/audio
input, and the integrated TCON (Timing Controller) part for the
LCD panel.
System SoC is based on MT5363:
NAND Flash 128 Mbyte, NumOnyx/Hynix.
DDR 128 Mbyte (32 16M, 2 pcs), Hynix.
Use internal MT5363 Stand-by micro-controller.
Tuner/Frontend configuration:
Half NIM tuner (VA1E1BF2403) from Sharp.
Toshiba Channel Decoder (TC90517).
Interfaces for debug and SW upgrade:
UART (3.5 mm jack).
USB port.
J TAG.
Refer to Figure 7-1 for details.
Figure 7-1 L11M1.1L LA Architecture
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Circuit Descriptions EN 21 L11M1.1L LA 7.
2011-Apr-29
Figure 7-2 SSB cell layout
Figure 7-3 SSB key component overview
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Circuit Descriptions EN 22 L11M1.1L LA 7.
2011-Apr-29
Figure 7-4 TCON key component overview
7.2 Power Supply
The Power Supply Unit (PSU) in this chassis is a buy-in and is
a black-box for Service. When defective, a new panel must be
ordered and the defective panel must be returned for repair,
unless the main fuse of the unit is broken. Always replace the
fuse with one with the correct specifications! This part is
commonly available in the regular market.
Refer to Figure 7-5 and Figure 7-6 for details
The power supply system consists of stand-by, switched and
regulated voltages. The stand-by voltage, +3V3STBY, will be
available once AC supply is provided to the system. As for the
other voltages, namely switched and regulated voltages, these
are available once the STANDBY signal is pulled low to allow
other supplies from the IPB to turn on. The switched supplies
are generated from the main +12VS supply, while the regulated
supplies are derived from the switched supplies. There are a
number of detection circuits to detect the following supplies:
+12VS, +12Vdisp and +3V3_SW. The +12VS is the main
supply voltage from the IPB that enables the switched voltages
to be generated. The +12Vdisp is the supply to the display
timing controller, while the +3V3_SW is powering the
microprocessor and its flash memory.
The mains power supply unit distribute the following voltages to
the TV system: +3V3STBY, 12VS, +24Vaudio, and +24Vpanel
for panel with inverter (or) high voltage (HV) for inverterless
panel. Requirement of the High Voltage depend on the
specification of the LCD panel.
Figure 7-5 Power distribution overview
Figure 7-6 Power timing overview
19130_048_110429.eps
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19130_012_110426.eps
110426
MT5363 Dig Demod
Flash
NVM
DDR2 2
+12 V
S
DCDC
Regulator
Regulator
EEPROM
USB
Tuner
+3.3 V
STBY
1.1 V 0.05 V
1.8 V 0.09 V
3.3 V 0.16 V 1.25 V 0.06 V
5.25 V 0.26 V
2.5 V
0.12 V
5.25 V 0.25 V
DCDC
DCDC
DCDC Regulator
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Circuit Descriptions EN 23 L11M1.1L LA 7.
2011-Apr-29
7.3 Video
7.3.1 Video: Front-End
Key components for the tuner section are:
Sharp Half NIM tuner VA1E1BF2403,
Toshiba channel decoder TC90517 (external ISDB-T
channel decoder).
Analog demodulator (using internal MT5363 analog
demodulator - pin AH35 VIP, AH37 VIN).
Refer to Figure 7-7 for details.
Figure 7-7 Front-end functional block diagram
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Circuit Descriptions EN 24 L11M1.1L LA 7.
2011-Apr-29
7.4 Audio
In this chassis, audio processing is done by the following key
components:
MT5363 micro-processor for input selection and audio
processing,
TPA3123D2 class-D power amplifier for 2 x 10 W
amplification.
The audio profile (optimal setting per screen size and styling) is
stored at Option 10 (bit 0 to bit 4). Profile 1 for 32-inch Dali and
profile 2 for 40-inch Dali.
Table 7-1 Microprocessor control lines - 1 -
Table 7-2 Microprocessor control lines - 2 -
Figure 7-8 Audio signal flow
7.5 Inputs
7.5.1 Inputs: HDMI
In this chassis, the main Mediatek MT5363 SoC has an on-chip
HDMI multiplexer.
Refer to Figure 7-9 for the implementation.
From uP At class D Usage
SW_MUTE SW_MUTE Will pull audio signals to LOW upon DC drops, help
to eliminate plop sound.
RESET_AUDIO A_STBY Control SHUTDOWN pin of class D amplifier:
ON/OFF the amplifier
MUTE MUTE Corresponding to the MUTE button on Remote
Control, to mute/unmute speakers
DC_PROT DC_PROT Detecting present of DC at speakers output and
feedback to uP. This will trigger TV into protection
mode. This is important to protect speakers
From uP
A_STBY
to class D Class D outputs
SW_MUTE LOW - MUTE
HIGH - Operating (unmute)
RESET_AUDIO LOW HIGH Operating (unmute)
HIGH LOW Class D shutdown (mute)
MUTE LOW - Operating (unmute)
HIGH - MUTE
DC_PROT LOW - DC detected ->set going to protection
HIGH - No DC ->normal operating
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Circuit Descriptions EN 25 L11M1.1L LA 7.
2011-Apr-29
Figure 7-9 HDMI implementation
Signal description:
TMDS: Signals that contain audio and video information.
PWR5V: Signal to detect the presence of any HDMI source
connected to the TVs HDMI input port.
SIDE_HDMI_HPD1 and HDMI_HPD2: Signal to initiate
reading of the TV EDID data by the source device.
I2C: The EDID data reading and the HDCP authentication
process runs via I2C.
CEC: Signal direct connected between inputs and uP.
EDID_WC: Signal used to disable the write protect pin of
the EEPROM. When updating, the program will temporarily
pull this pin LOW before writing new data.
7.5.2 Inputs: USB
In this chassis, the main Mediatek MT5363 SoC has an on-chip
USB processor.
Refer to Figure 7-10 for the implementation.
Figure 7-10 USB implementation
19130_015_110426.eps
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TMDS
PWR5V
SIDE_HDMI_HPD1
SIDE HDMI SCL1 HDMI SCL2
HDMI_HPD2
RX2
OPWR2_5V
ARC eHDMI+
EDID
SIDE_HDMI_SDA1
CEC
EDID WC
HDMI_CEC
_ _ _
HDMI_SDA2
GPIO 7
MT5363
TMDS
PWR5V
HDMI HPD2
EDID EDID_WC GPIO_7
HDMI HPD1
RX1
OPWR1_5V
_
HDMI_SDA2
HDMI_SDA1
HDMI_SDA1
HDMI_SCL2
_
EDID
Buffer & Selection
circuit
ASPDIF_OUT
ARC_SW
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IC Data Sheets EN 26 L11M1.1L LA 8.
2011-Apr-29
8. IC Data Sheets
This section shows the internal block diagrams and pin layouts
of ICs that are drawn as "black boxes" in the electrical diagrams
(with the exception of "memory" and "logic" ICs).
8.1 Diagram B01, Type TPS54386 (IC7116 and 7117)
Figure 8-1 Internal block diagram and pin configuration
18980_300_100402.eps
100402
PIN CONNECTIONS
1
2
3
4
14
13
12
11
PVDD2
BOOT2
SW2
BP
PVDD1
BOOT1
SW1
GND
5
6
7
10
9
8
SEQ
ILIM2
FB2
EN1
EN2
FB1
Thermal Pad
(bottomside)
HTSSOP (PWP)
(Top View)
BLOCK DIAGRAM
7 FB1
+
Soft Start
1 C
COMP
+
S Q
Q R
R
+
Current
Comparator
BP
f(I
DRAIN1
) +DC(ofst)
2
1
3
Anti-Cross
Conduction
1.2 MHz
Oscilator
Divide
by2/4
Ramp
Gen 1
Ramp
Gen 2
CLK1
CLK2
BP
CLK1
Weak
Pull-Down
MOSFET
5 EN1
6 EN2
6 A 6 A
VDD2
Internal
Control
10 SEQ
150 k
150 k
Output
Undervoltage
Detect
BP
FB1
FB2
CLK1
4 GND
8 FB2
+
Soft Start
2 C
COMP
+
S Q
Q R
R
+
Current
Comparator
BP
13
14
12
Anti-Cross
Conduction
BP
CLK2
Weak
Pull-Down
MOSFET
11 BP
9 ILIM2
150 k
150 k
BP
CLK2
4 GND
Level
Select
5.25-V
Regulator
References
BOOT1
PVDD1
SW1
BOOT2
PVDD2
SW2
f(I
DRAIN2
) +DC(ofst)
0.8 V
REF
I
MAX2
(Set to one of three limits)
f(I
DRAIN1
)
f(I
MAX1
)
Overcurrent Comp
f(I
SLOPE1
)
Level
Shift
Level
Shift
f(I
DRAIN2
)
f(I
MAX2
) f(I
SLOPE2
)
FET
Switch
TSD
PVDD2
f(I
SLOPE1
)
f(I
SLOPE2
)
SD1
SD2
UVLO
0.8 V
REF
SD2
0.8 V
REF
SD1
UDG-07124
Overcurrent Comp
R
COMP
R
COMP
IC Data Sheets EN 27 L11M1.1L LA 8.
2011-Apr-29
8.2 Diagram B01A DC-DC, Type LD1117D (IC7119)
Figure 8-2 Internal block diagram and pin configuration
F_15710_166.eps
100402
Block diagram
Pinning information
DPAK
LD1117DT
IC Data Sheets EN 28 L11M1.1L LA 8.
2011-Apr-29
8.3 Diagram B03 Class-D & muting, Type TPA3123 (IC7400)
Figure 8-3 Internal block diagram and pin configuration
18440_302_090303.eps
090318
Block diagram
Pinning information
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
TERMINAL
I/O/P DESCRIPTION
24-PIN
NAME
(PWP)
Shutdown signal for IC (low=disabled, high =operational). TTL logic levels with compliance to
SD 2 I
AVCC
RIN 6 I Audio input for right channel
LIN 5 I Audio input for left channel
GAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCC
Mute signal for quick disable/enable of outputs (high =outputs switch at 50%duty cycle, low=
MUTE 4 I
outputs enabled). TTL logic levels with compliance to AVCC
BSL 21 I/O Bootstrap I/O for left channel
PVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
LOUT 22 O Class-D 1/2-H-bridge positive output for left channel
PGNDL 23, 24 P Power ground for left-channel H-bridge
VCLAMP 11 P Internally generated voltage supply for bootstrap capacitors
BSR 16 I/O Bootstrap I/O for right channel
ROUT 15 O Class-D 1/2-H-bridge negative output for right channel
PGNDR 13, 14 P Power ground for right-channel H-bridge.
PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND 9 P Analog ground for digital/analog cells in core
AGND 8 P Analog ground for analog cells in core
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
BYPASS 7 O
external capacitor sizing.
AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Connect to ground. Thermal pad should be soldered down on all applications to properly
Thermal pad Die pad P
secure device to printed wiring board.
1 F
SD
PVCCL
PVCCR
VCLAMP
GAIN1
BYPASS
1 F
1 F
0.22 F
AGND
} Control
Shutdown
Control
LIN
RIN
BSR
BSL
PGNDR
PGNDL
0.22 F
22 H
22 H
0.68 F
470 F
0.68 F
1 F
470 F
GAIN0
AVCC
MUTE
ROUT
LOUT
IC Data Sheets EN 29 L11M1.1L LA 8.
2011-Apr-29
8.4 Diagram B04 MT5363 Power, Type MT5363 (IC7700)
Figure 8-4 Internal block diagram
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Block diagram
DVB-T ATD
CVBS/
YC Input
VADCx4
TV
Decoder
HDMI
Rx
HDMI In
I/F
Audio
Demod
Audio
Input
Audio
ADC
Panel
LVDS
CVBS
VDAC
TVE
DDR
DRAM
Controller
ARM
BIM
TS
Demux
VDO-In
PreProc
MDDi
Audio In
J PEG,MPEG
H.264
2-D Graphic
Mix andPost
Processing
OSD
scaler
Vplane
scaler/PIP
Audio DSP
IO Bus
Standby uP CKGEN
Audio I/F
Audio DAC
SPDIF, I
2
S
BScan PVR RTC UART MS,SD PWM NAND Flash
J TAG IrDA SIF USB2.0 Watchdog Serial Flash Servo ADC
IC Data Sheets EN 30 L11M1.1L LA 8.
2011-Apr-29
Figure 8-5 Internal block diagram
18850_301_100107.eps
100222
Pinning information
LT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
A
B VCC2IO
C
D RA9
E
F RA5
G
H RBA2
J
K RCKE
L
M RA13
N
P RA8
R
T RDQ19
U
V RDQM2
W
Y RDQS3
AA
AB RDQ16
AC
AD RCLK1
AE
AF VCC2IO
AG
AH GPIO44
AJ
AK J TRST_
AL
AM VCCK
AN
AP OSDA0
AR
AT POCE0_
AU
RCLK0_
VCC2IO
RA12
RA10
RBA1
RCAS_
RA11
VCC2IO
RDQ22
RDQS2_
RDQS3_
RDQ21
VCC2IO
GPIO38
J TDI
VCCK
VCCK
PDD0
POOE_
RCLK0
VCC2IO
RA7
RBA0
RWE_
RA2
RCS_
RDQ20
RDQS2
DVSS
RDQ23
RCLK1_
VCC2IO
GPIO43
J TCK
VCCK
OSCL0
POWE_
RDQ10
RDQ13
VCC2IO
RA3
DVSS
DVSS
RA0
VCC2IO
RDQ17
DVSS
RDQ29
RDQ18
VCC2IO
GPIO41
J TMS
VCCK
VCCK
PAALE
PACLE
RDQ8
RDQ5
VCC2IO
RA1
MEMTN
RA4
RRAS_
RDQ30
RDQ28
RDQ24
REXTDN
VCC2IO
GPIO37
J TDO
VCCK
VCCK
PDD1
PARB_
RDQ15
RDQS1_
RDQ2
VCC2IO
DVSS
DVSS
RODT
VCC2IO
RDQM3
DVSS
RDQ26
VCC2IO
GPIO39
GPIO42
VCCK
VCCK
POCE1_
PDD2
PDD3
RDQS1
RDQ0
RDQ7
VCC2IO
MEMTP
RA6
RVREF
RDQ25
RDQ27
RDQ31
VCC2IO
GPIO40
VCCK
VCCK
VCCK
PDD4
PDD5
RDQS0_
DVSS
DVSS
DVSS
RVREF
DVSS
VCCK
VCCK
PDD6
PDD7
RDQS0
DVSS
DVSS
DVSS
AVSS12_U
SB
AVSS33_U
SB
AVSS33_U
SB
RDQ14
RDQM1
RDQM0
DVSS
AVDD12_U
SB
USB_VRT
USB_DM
USB_DP
RDQ11
RDQ9
RDQ6
RDQ1
AVDD33_U
SB
AVDD12_H
DMI
AVSS33_U
SB
RDQ12
VCC2IO
VCC2IO
RDQ3
VCCK
HDMI_SCL
2
AVSS33_H
DMI
RX2_C
RX2_CB
VCC2IO
VCC2IO
VCC2IO
RDQ4
AVDD12_M
EMPLL
AVSS12_M
EMPLL
VCCK
VCCK
DVSS
DVSS
VCCIO33-1
AVDD33_H
DMI
RX2_0
RX2_0B
VCC2IO
VCC2IO
VCC2IO
DVSS
DVSS
VCCK
DVSS
VCCK
DVSS
VCCK
HDMI_SDA
2
HDMI_CEC
RX2_1
RX2_1B
AO0N
AO0P
AVDD33_L
VDS
AVDD33_L
VDS
DVSS
DVSS
DVSS
VCCK
DVSS
VCCK
VCCIO33-1
PWR5V_2
RX2_2
RX2_2B
AO1N
AO1P
AE0N
AE0P
AVDD12_L
VDS
VCCK
DVSS
DVSS
DVSS
DVSS
VCCK
PWR5V_1
HDMI_HPD
2
RX1_C
RX1_CB
AO2N
AO2P
AE1N
AE1P
AVSS12_L
VDS
DVSS
DVSS
DVSS
DVSS
VCCK
HDMI_SCL
1
RX1_0
RX1_0B
AOCKN
AOCKP
AE2N
AE2P
AVSS33_L
VDS
AVDD12_V
PLL
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
HDMI_HPD
1
HDMI_SDA
1
RX1_1
RX1_1B
AO3N
AO3P
AECKN
AECKP
TP_VPLL
AVSS12_V
PLL
DVSS
DVSS
DVSS
DVSS
VCCK
OPCTRL1
RX1_2
RX1_2B
AV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
IC Data Sheets EN 31 L11M1.1L LA 8.
2011-Apr-29
Figure 8-6 Internal block diagram
18850_302_100107.eps
100222
Pinning information
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RT
A 0 D X R T E 2 D X R T E 0 D X T T E 3 O I P G 1 2 O I P G 5 3 O I P G N 4 O A
AO4P
AE3N
AE3P
DVSS
DVSS
AE4N
AE4P
GPIO36
DVSS
DVSS
GPIO32
GPIO34
GPIO33
VCCIO33
GPIO28
GPIO30
GPIO29
GPIO31
GPIO26
GPIO27
GPIO24
GPIO25
GPIO22
GPIO20
GPIO19
GPIO23
GPIO17
GPIO18
GPIO16
GPIO15
GPIO11
GPIO12
GPIO14
GPIO13
GPIO9
GPIO10
GPIO8
GPIO7
GPIO4
GPIO6
GPIO5
VCCIO33
FSRC_WR
ETTXD3
ETTXEN
ETPHYCLK
VCCIO33
AOSDATA3
IF_AGC
ETTXD1
ETTXD2
ETCOL
GPIO2
ALIN
ETRXCLK
ETTXCLK
CI_MCLKO
CI_MISTR
T
ASPDIF
RF_AGC
ETRXD3
ETTXER
CI_MIVAL
OPWM0
AOBCK
ETRXD1
ETRXER
CI_MCLKI
CI_MDI0
GPIO0
AOMCLK
ETRXDV B
ETCRS C
ETMDIO D
ETMDC E
CI_MOSTR
T
F
CI_MOVAL G
CI_MDO0 H
OPWM1 J
GPIO1 K
AOSDATA0 L
AOLRCK M
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
DVSS
DVSS
DVSS
VCCK
VCCK
AVSS33_A
DAC1
OSCL2
AVDD33_A
DAC1
VCCIO33
AOSDATA4
OSDA1
AL1
OSDA2
OPWM2
AR1
TUNER_DA
TA
OSCL1
AR2
AOSDATA1
U1TX
AL2
TUNER_CL
K
U1RX
AR3
N
AOSDATA2 P
R
VCXO T
U
AL3 V
DVSS DVSS VCCK
AVDD33_R
EF_AADC
VCCIO33 VCCIO33 VCCIO33 W
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
VCCK
VCCK
AVSS33_R
EF_AADC
VMID_AAD
C
AVDD33_A
ADC
AIN1_L_AA
AIN4_L_AA
DC
AVSS33_A
ADC
AIN4_R_A
AIN5_L_AA
DC
AIN5_R_A
ADC
AIN2_R_A
AIN6_L_AA
DC
AIN6_R_A
ADC
Y
AA
AIN3_R_A
DVSS
VCCK
DVSS
DVSS
VCCK
DVSS
DVSS
DVSS
DVSS
AVDD12_T
VDPLL
AVDD12_A
DC
AIN1_R_A
ADC
AVDD12_S
ADC
AIN0_L_AA
DC
AVDD33_
ADAC0
AIN0_R_A
ADC
AVSS33_A
DAC0
AVDD33_
ADC
AIN2_L_AA
DC
AVICM
AIN3_L_AA
DC
AR0
AVSS33_D
ADC
AB
AC
AD
AE
AL0 AF
OPWRSB
OPCTRL0
ORESET_
AVDD10_L
AVSS33_V
GA_STB
AVDD12_R
AVSS12_P
LL
AVSS33_SI
F
FS_VDAC
PLL
AVSS33_D
IG
AVDD33_S
IF
AVSS12_P
LL
AVDD33_D
IG
BYPASS0
YSPLL
ADIN0_SR
V
AVDD12_A
DCPLL
ADIN1_SR
V
AF
DEMOD1
XTALO
ADIN3_SR
V
ADCINN_D
EMOD
AVDD33_X
TAL_STB
ADIN2_SR
EMOD1 AG
ADCINP_D
EMOD
AH
XTALI AJ
AVSS33_X
TAL
AK
ADIN5_SR
V
AL
ADIN4_SR
OPCTRL2
OPCTRL3
OPCTRL4
U0TX
U0RX
OIRI
HSYNC
VSYNC
DO
SOG
BP
AVDD33_V
GA_STB
COM
GP
GB
SOY1
RP
AVSS12_R
GB
COM1
Y1P
PR1P
PB1P
Y0P
SOY0
PB0P
COM0
AVDD33_V
DAC
AVSS33_V
DAC
PR0P
VDAC_OUT
1
VDAC_OUT
2
AVDD33_C
VBS
AVSS33_C
VBS
SY0
SC0
MPXP
SY1
SC1
V
CVBS2P
CVBS3P
V
AM
MPXN AN
TUNER_BY
PASS
AP
CVBS0N AR
CVBS0P AT
CVBS1P AU
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RB
IC Data Sheets EN 32 L11M1.1L LA 8.
2011-Apr-29
8.5 Diagram B06B Analog I/O - Audio, Type LM833 (IC7B01)
Figure 8-7 Pin configuration
18520_306_090325.eps
100402
Pinning information
2
(Top View)
1
3
4
8
7
6
5
Output 1
Inputs 1
Output 2
Inputs 2
V
EE
V
CC
1
2
IC Data Sheets EN 33 L11M1.1L LA 8.
2011-Apr-29
8.6 Diagram T01C TCON DC/DC, Type ISL97653 (IC7J00)
Figure 8-8 Internal block diagram and pin configuration
18770_307_100217.eps
100217
Block diagram
Pinning information
1
40
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
39 38 37 36 35 34 33 32 31
11 12 13 14 15 16 17 18 19 20
L
D
O
-
C
T
L
L
D
O
-
F
B
P
V
I
N
1
A
G
N
D
P
R
O
T
L
X
2
L
X
1
P
G
N
D
2
P
G
N
D
1
T
E
M
P
COMP
FBB
RSET
HVS
EN
CDEL
CTL
DRN
COM
POUT
PVIN2
CB
LXL1
LXL2
PGND3
PGND4
CM2
FBL
VL
VREF
F
B
N
S
U
P
N
N
O
U
T
P
G
N
D
5
C
1
P
C
1
N
C
2
P
C
2
N
S
U
P
P
F
B
P
ISL97653A
40 LD 6X6 QFN
TOP VIEW
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-

CONTROL
LOGIC
SAWTOOTH
GENERATOR
CURRENT
AMPLIFIER
CURRENT LIMIT
COMPARATOR
CURRENT LIMIT
THRESHOLD
REFERENCE BIAS
AND
SEQUENCE CONTROLLER
V
REF
GM AMPLIFIER
UVLO COMPARATOR
OSCILLATOR
0.75 V
REF
REGULATOR
SUPN
0.2V
UVLO COMPARATOR
0.4V
0.75 V
REF
V
REF
P
OUT
R
SENSE
BUFFER
CONTROL
LOGIC
V
REF
SAWTOOTH
GENERATOR
SLOPE
COMPENSATION
GM AMPLIFIER
SUPP
CURRENT LIMIT
THRESHOLD
CURRENT
LIMIT
COMPARATOR
SUPP
C1- C1+ C2+ C2- P
OUT
CTL COM
BUFFER
LX1
PGND1
CB
LXL1
CM2
FBL
FBP
FBN
N
OUT
P
VIN1,2
EN
CDEL
P
VIN1,2
VL
FBB
CM1
PGND2
LX2
CURRENT AMPLIFIER
SLOPE
COMPENSATION
V
REF
FREQ
HVS
LOGIC
RSET HVS PROT
LXL2
DRN
680kHz
VL
LDO
CONTROL
LOGIC2
LDO-CTL
LDO-FB
TEMP
SENSOR
TEMP
IC Data Sheets EN 34 L11M1.1L LA 8.
2011-Apr-29
Personal Notes:
10000_012_090121.eps
090121

Block Diagrams EN 35 L11M1.1L LA 9.
2011-Apr-29
9. Block Diagrams
Wiring Diagram 32" (Thriller)
1
1
P
1
M
9
5
9
P
1
M
9
9
2P3
1308
1
7
3
5
4
P
1
M
9
5
1
1
P
1
M
9
9
9
P
1
M
9
9
1
4
P
1G51
51P
1
M
2
0
8
P
TO DISPLAY
3
P
J
1
SSB
3139 123 6505.x
(1150)
B
MAIN POWER SUPPLY
32 PSLC-P002A
(1005)
LCD DISPLAY
(1004)
8M99
8M95
WIRING DIAGRAM 32" THRILLER
19130_044_110428.eps
110429
1M99 (B01)
1. +12VDISP
2. +12VDISP
3. GND
4. GND
5. LAMP-ON
6. BACKLIGHT-PWM
7. BACKLIGHT-BOOST
8. INV_STATUS
9. POWER-OK
1M95 (B01)
1. +3V3STDBY
2. STANDBY
3. GND
4. GND
5. GND
6. +12VS
7. +12VS
8. +12VS
9. +24VAUDIO
10. GND-AUDIO
11. ...
1735 (B03)
1. LEFT_SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT_SPEAKER
1M20 (B04c)
1. LIGHT-SENSOR
2. GND
3. RC
4. LED-2
5. +3V3STBY
6. LED-1
7. KEYBOARD
8. +5V_SW
1G51 (B04D)
1. +VDISP-INT
2. +VDISP-INT
3. +VDISP-INT
4. +VDISP-INT
|
51. GND
L N
Board Level Repair
Component Level Repair
Only For Authorized Workshop
U
S
B
H
D
M
I
HDMI
INLET
VGA
LOUDSPEAKER
(5213)
8
M
2
0
J 2
3P
J 1
8P
T
O
B
A
C
K
L
IG
H
T
IR/LED BOARD
(1112)
K
E
Y
B
O
A
R
D

C
O
N
T
R
O
L
(
1
1
1
4
)
8G51
8308
M
A
IN
S
C
O
R
D
8
1
9
1
T
U
N
E
R
8319
EN 36 L11M1.1L LA 9. Block Diagrams
2011-Apr-29
Wiring Diagram 40" (Thriller)
1
1
P
1
M
9
5
9
P
1
M
9
9
2P3
1308
1
7
3
5
4
P
1
M
9
5
1
1
P
1
M
9
9
9
P
1KA2
80P
1G51
51P
1KA1
80P
1
M
2
0
8
P
TO DISPLAY TO DISPLAY
3
P
J
1
SSB
3139 123 6505.x
(1150)
B
TCON
(1157) T
MAIN POWER SUPPLY
IPB 40 PLHE-P986A
(1005)
LCD DISPLAY
(1004)
8M99
8M95
WIRING DIAGRAM 40" THRILLER
19130_043_110428.eps
110429
1M99 (B01)
1. +12VDISP
2. +12VDISP
3. GND
4. GND
5. LAMP-ON
6. BACKLIGHT-PWM
7. BACKLIGHT-BOOST
8. INV_STATUS
9. POWER-OK
1M95 (B01)
1. +3V3STDBY
2. STANDBY
3. GND
4. GND
5. GND
6. +12VS
7. +12VS
8. +12VS
9. +24VAUDIO
10. GND-AUDIO
11. ...
1735 (B03)
1. LEFT_SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT_SPEAKER
1M20 (B04c)
1. LIGHT-SENSOR
2. GND
3. RC
4. LED-2
5. +3V3STBY
6. LED-1
7. KEYBOARD
8. +5V_SW
1KA2 (T01F)
1. GND
|
11. VLS_15V6
12. VLS_15V6
|
33. VCC_3V3
34. VCC_3V3
|
78. VGH_35V
79. VGL_-6V
80. GND
1KA1 (T01F)
1. GND
|
11. VLS_15V6
12. VLS_15V6
|
33. VCC_3V3
34. VCC_3V3
|
78. VGH_35V
79. VGL_-6V
80. GND
1N01 (T01A)
1. GND
|
47. +VDISP-INT
48. +VDISP-INT
49. +VDISP-INT
50. +VDISP-INT
|
51. GND
1G51 (B04D)
1. +VDISP-INT
2. +VDISP-INT
3. +VDISP-INT
4. +VDISP-INT
|
51. GND
L N
Board Level Repair
Component Level Repair
Only For Authorized Workshop
U
S
B
H
D
M
I
T
U
N
E
R
P
H
O
N
E
S
P
D
IF
HDMI HDMI
INLET
VGA
LOUDSPEAKER
(5213)
8
M
2
0
J 2
3P
J 1
8P
8KA1
1319
1P3
1316
1P3
HIGHVOLTAGE
T
O
B
A
C
K
L
IG
H
T
T
O
B
A
C
K
L
IG
H
T
8319
8
3
1
6
IR/LED BOARD
(1112)
K
E
Y
B
O
A
R
D

C
O
N
T
R
O
L
(
1
1
1
4
)
8KA2
8308
M
A
IN
S
C
O
R
D
8
1
9
1
1N01
51P
8
G
5
1
Block Diagrams EN 37 L11M1.1L LA 9.
2011-Apr-29
Block Diagram Video
B02A TUNER B02A DIGITAL DEMOD T01A LVDS
DISLAY
T01B TCON CONTROL
T01D P GAMMA &
VCOM & NVM
T01E MPD T01F MINI LVDS B04 MT5363: B04D LVDS DISPLAY
B06D VGA
B06C ANALOG I/O - VIDEO B06B ANALOG I/O
AUDIO
B05B USB
B05A HDMI & MUX
B04B DDR
B04C CONTROLLER
7700
MT5363BIMG
HDMI-LVDS B05
MAC-CI B04C
CONTROL B04C
AUDIO-VIDEO B06B
MT5363
19130_020_110427.eps
110427
VIDEO
AGC_IF
CI_MCLKI
CI_MDIO
G34
H33
F35
H35
M31
M33
IF_AGC
RF_AGC_SW
+5VTUN_DIGITAL
1201
VA1E1BF2403
7302
TC90517FG
TUNER
DIGITAL
DEMODULATOR
9
IF_AGC
CI_MIVAL
RESET_DEMOD
DIF_P
10
9
58
IF_OUT+
3 RF_AGC
RF_AGC
8
+B
5
2
0
8
SCL
SDA
7
6
(I2C)
4
3
2
1
USB_DM
USB_DP
USB 2.0
CONNECTOR SIDE
SW UPLOAD
JPEG
MP3
AR10
AU10
USB_DP
USB_DM
AE
AO
1D01
1
2
4
3
AGC_RF
HDMI-LVDS B05
RX1
RX2
AP19
AT19
AR16
AU16
AR18
AU18
AP17
AT17
AP15
AT15
AR12
AU12
AR14
AU14
AP13
AT13
1
9
1
1
8
2
1
1902
3
4
7
9
10
12
6
M_RX2_2
M_RX2_2B
M_RX2_1
M_RX2_1B
M_RX2_0
M_RX2_0B
M_RX2_C
M_RX2_CB
M_RX1_2
M_RX1_2B
M_RX1_1
M_RX1_1B
M_RX1_0
M_RX1_0B
M_RX1_C
M_RX1_CB
HDMI 2
CONNECTOR
1
1901
3
4
7
9
10
12
6
1
9
1
1
8
2
HDMI 1 (SIDE)
CONNECTOR
PX1
PX2
PX1
PX2
TO DISPLAY
TO DISPLAY
1KA2
72
81
61
50
13
33
34
12
11
1KA1
81
72
79
78
61
2
10
1
1
7H01
VPP1501BFG
7K00
ISL24837IRZ
VL/VH
VH
REF
VOLTAGE
GEN
7L00
ISL24016IRTZ
LEVEL
SHIFTER
CS(1-12)
ASIC_CS
VLS_15V6
VCC_3V3
12
11
VLS_15V6
VGL_-6V
VGH_35V
2
10
INTERFACE
B08A
33
34
VCC_3V3
50
13
1KA1 1N01
60
2
1
4
3
79
78
VGL_-6V
VGH_35V
VL
VH
VL
LLV(0-7)
RLV(0-7)
7218
7217
RF_AGC_SW
CI_MISTRT
TSO_VALID
11
42
30
IF_OUT-
AGCCNTI
59 TSO_SYNC
61 TSO_CLK
60 TSO_DATA0
DRAM B04B
CONTROL B04C
7708
H27U1G8F2BTR
FLASH
1Gb
RDQ
RA
PDD NAND_PDD(0-7)
A1 A1
+1V8_SW
SDRAM
512Mb
7601
H5PS5162FFR
SDRAM
512Mb
7600
H5PS5162FFR
V
D
D
V
D
D
RDQ(0-31)
R
D
Q
(
0
-
1
5
)
R
D
Q
(
1
6
-
3
1
)
RA(0-13)
PB
PR
Y
1C03
CVBS
CVBS_AV3 AP35 2
CVBS_2P
1C01
SC1_B
SC1_G SY0P
SPB0P
SPR0P
AP29
AR28
7
12
9
SC1_CVBS_OUT AU30
PR0P
Y0P
PB0P
AK22
PBR0N
PB
PR
Y
1C02
PB1P_SC2
SY1P_SC2 SY1P
SPB1P
SPR1P
SY1N
AT27
AU26
7
12
9
PR1P_SC2 AP27
PR1P
Y1P
PB1P
AR26
Y1N
SOY0-AV1
Y0P
PB0P
PR0P
Y0N AT29
SOY0
2
C
0
6
GND_CVBS AR36
CVBS_0N
2
C
0
7
5C05
5C02
5C01
5C00
5C04
5C03
3B08
3B11
3B07
3B09
SOY1-AV2 AP25
SOY1
3B02
3B05
3B03
3B01
3B00
CVI-2
CVI-1
AVIN
1
1E01
2
3
14
13
VGA_R
VGA_G
VGA_Rp
VGA_Gp
VGA_B
H-SYNC
V-SYNC
VGA_Bp
HSYNC
VSYNC
RP
GP
BP
16
10
11
5
15
VGA
CONNECTOR
AU22
AR22
AT23
AU24
AT25
RP
VSYNC
GP
BP
HSYNC
SOG
GN
AP23
SOG
AR24
COM
2
E
0
8
2
E
0
3
RXO
RXE
B04C
B04C
+VDISP-INT
49
50
60
1
47
48
+VDISP-INT
3C24
3C25
3C22
3C20
3C23
3C21
EN 38 L11M1.1L LA 9. Block Diagrams
2011-Apr-29
Block Diagram Audio
B03 CLASS-D & MUTING B06B ANALOG I/O - AUDIO
B06B ANALOG I/O - AUDIO
B06C ANALOG I/O - VIDEO
B02A TUNER B02B DIGITAL DEMOD B04 MT5363:
B05B USB
B04B DDR
B04C CONTROLLER
B05A HDMI & MUX
1B02
2
ALI_ADAC B06B
ALI_DAC B06B
MT5363
19130_038_110427.eps
110427
AUDIO
1B01
2
3
1
K33
ASPDIF
E28
ASPDIF
SPDIF_OUT
eHDMI+
ASPDIF_OUT
ARC_SW
DVI_AUL_IN
DVI_AUR_IN
1C02
AC36
AB37
AD33
AIN_AADC_0_L
AC34
AIN_AADC_0_R
AB31
AIN_AADC_1_L
AC32
AIN_AADC_1_R
AV IN
AUDIO
L/R
AV IN
AUDIO
L/R
AV IN
AUDIO
L/R
SPDIF
OUT
AA36
Y37
AIN_AADC_6_L
AIN_AADC_6_R
SAV_L_IN
SAV_R_IN
1C03
AV IN
AUDIO
L/R
5
8
5
3
1C01
5
3
V37
u36
AL_L
AR_R
AOUTL
AOUTR
PREAMPL
PREAMPR
LEFT_SPEAKER
GND-AUDIO
RIGHT_SPEAKER
7400
TPA3123D2PWP
CLASS D
POWER
AMPLIFIER
5
6
2
6
1
7
22
15
MUTE 4
1
2
1735
3
4
DC-DETECTION
SW_MUTE
RESET_AUDIO
A_STBY 2
B04C
B04C
B04C
DC_PROT
B04C
7408
STANDBY
AIN_AADC_3_L
AIN_AADC_3_R
AIN0_R-AV1
AIN0_L-AV1
AIN1_R-AV2
AIN1_L-AV2
AVIN
CVI-2
CVI-1
SPEAKER
LEFT
SPEAKER
RIGHT
7700
MT5363BHMG
MAC-CI B04C
CONTROL B04C
AGC_IF
CI_MCLKI
CI_MDIO
G34
H33
F35
H35
M31
M33
IF_AGC
RF_AGC_SW
+5VTUN_DIG
1201
VA1E1BF2403
7302
TC90517FG
TUNER
DIGITAL
DEMODULATOR
9
IF_AGC
CI_MIVAL
DIF_N
DIF_P
10
9
58
IF_OUT+
3 RF_AGC
RF_AGC
8
+B
5
2
0
7
SCL
SDA
7
6
(I2C)
AGC_RF
7218
7217
RF_AGC_SW
CI_MISTRT
TSO_VALID
11
29
30
IF_OUT-
AGCCNTI
59 TSO_SYNC
61 TSO_CLK
60 TSO_DATA0
B04C
4
3
2
1
USB_DM
USB_DP
USB 2.0
CONNECTOR SIDE
SW UPLOAD
JPEG
MP3
AR10
AU10
USB_DP
USB_DM
1D01
1
2
4
3
DRAM B04B
CONTROL B04C
7708
H27U1G8F2BTR
FLASH
1Gb
RDQ
RA
PDD NAND_PDD(0-7)
A1 A1
+1V8_SW
SDRAM
512Mb
7601
H5PS5162FFR
SDRAM
512Mb
7600
H5PS5162FFR
V
D
D
V
D
D
RDQ(0-31)
R
D
Q
(
0
-
1
5
)
R
D
Q
(
1
6
-
3
1
)
RA(0-13)
HDMI B05
GPIO B05
RX0
RX1
AP19
AT19
AR16
AU16
AR18
AU18
AP17
AT17
AP15
AT15
AR12
AU12
AR14
AU14
AP13
AT13
1
9
1
1
8
2
1
1902
3
4
7
9
10
12
6
M_RX2_2
M_RX2_2B
M_RX2_1
M_RX2_1B
M_RX2_0
M_RX2_0B
M_RX2_C
M_RX2_CB
M_RX1_2
M_RX1_2B
M_RX1_1
M_RX1_1B
M_RX1_0
M_RX1_0B
M_RX1_C
M_RX1_CB
HDMI 2
CONNECTOR
1
1901
3
4
7
9
10
12
6
1
9
1
1
8
2
HDMI 1 (SIDE)
CONNECTOR 14
7B01
RESET_DEMOD 42
B04C
2
1
4
5
3
8
7S09
74LVC00
&
+3V3
GPIO_12
Block Diagrams EN 39 L11M1.1L LA 9.
2011-Apr-29
Block Diagram Control & Clock Signals
CONTROL + CLOCK SIGNALS
B06D USB
B04C CONTROLLER
B04B DDR T01B TCON CONTROL
T01D P GAMMA & VCOM & NVM
B04 MT5363
B04C FLASH & EJTAG & DISPLAY INTERFACE
T01E MPD
CONTROL B04C
DRAM B04B
GPIO B04C
TO IR/LED PANEL
AND
KEYBOARD CONTROL
+3V3STBY
3
2
4
5
7
1M20
MT5363
7700
MT5363BIMG
OPWRSB
AT21
AP21
UART
SERVICE
CONNECTOR
1701
3
2
1
B01
STANDBY
U0_RX
U0_TX
AG6
GPIO_42
GPIO_26
GPIO_21
PDD
H29
RCLK1#
RCLK1
AD3
AD1
EDID_WC
B06 B07E
A22 LCD-PWR-ONn
B04C
AH3 LAMP-ON
B01A
DC_PROT
B03
B29
GPIO_9
RF_AGC_SW
B02A
B23
GPIO_32
BYPASS_MODE
B08C
G30
B25
A26
GPIO_5
USB_PWR_EN
B06D
E30
GPIO_6
USB_OCP
B06D
A30
GPIO_3
AN22
OIRI
RESET_DEMOD
B02B
AM35
ADIN_SRV_2
ORESET
KEYBOARD
RC
1 AL36
ADIN_SRV_5
LIGHT-SENSOR
HDMI_CEC
AN14
AL20
HDMI_CEC
B05A
OPCTRL_4
AU20 MUTE
B03
OPCTRL_3
AR20 SW_MUTE
B03
B04C
B04C
OPCTRL_0
AM21 POWER_DOWN
B04C
LED-2
2701
SDM
2700
PANEL
4
3
2
1
USB_DM0
ADIN_SRV_4
AM37
USB_DM0
AJ 5
USB_DP0
AK5 USB_DP0
USB 2.0
CONNECTOR
SIDE
1D01
3
4
2
1
USB_PWR_EN
7D00
TPS2041BD
USB_OCP
EN
OUT
OC
19130_045_110428.eps
110429
7710
CLK
CLK
J 8 J 8 K8 K8
TCK
RCLK0#
RCLK0
A2
B3
CLK
CLK
XTAL1
XTALO
1700
54M
AJ 34
AJ 36
RDQ
RA
SDRAM
512Mb
7601
H5PS5162FFR
SDRAM
512Mb
7H00
H5PS5162FFR TCON
CONTROL
7H01
VPP1501BFG
SDRAM
512Mb
7600
H5PS5162FFR
TDQ(0-15)
R
D
Q
(
0
-
1
5
)
R
D
Q
(
1
6
-
3
1
)
RA(0-13)
TA(0-12)
7708
H27U1G8F2BTR
FLASH
1Gb
NAND_PDD(0-7)
GPIO_7
E28 ARC_SW
B06B GPIO_12
GPIO_35
GPIO_43
AG4
GPIO_41
POWER-OK
B01A
+3V3STBY
AL22 ORESET
7701
BD45292G
VOUT
VDD
5
4
3
OSC_IN
OSC_OUT
SLOPE
CS
1H00
27M
B1
A1
L2
L1
T9
RST
RESET
T01D
U9
T16
RTC50_60
50Hz_60Hz
T01D
T01C
T01F
T01F
T01F
GSLOP
TCK#
P
GAMMA
7K00
ISL24837IRZ
OUT12
24
T01E
T01F
T01F
T01F
CS_L
OUT12
26 INCOM
OUTCOM
25 OUTCOM
VCOM
VH
VL
LLV(0-7)
RLV(0-7)
VCOM
BUFER
7L00
SL24016IRTZ
LEVEL
SHIFTER
CS(1-12)
ASIC_CS
RDQ(0-31)
EN 40 L11M1.1L LA 9. Block Diagrams
2011-Apr-29
Block Diagram I
2
C
IC
DIGITAL DEMOD B2B
LVDS DISPLAY T01A
TCON CONTROL T01B
P GAMMA & VCOM & NVM T01D
VGA B06D
TUNER B02A
HDMI & MUX B05A
CONTROLLER B04C CONTROLLER B04C
DDR B4B
1KQA
DEBUG ONLY
RES
RES
7700
MT5363BIMG
OSDA_0
OSCL_0
GPIO_44
CONTROL
AH1 7
AP3
AP1
AP21
AT21
SYS_EEPROM_WE
SDA-MAIN
SCL-MAIN
3
7
1
8
3
7
1
9
+3V3_SW
TUNER_DATA
TUNER_CLK
19130_011_110426.eps
110426
5 6
7702
M24C64
EEPROM
(NVM)
3
7
1
7
3
7
1
6
N34
N36
3727
3728
3
7
4
6
3
7
4
7
+3V3STBY
3
7
4
6
3
7
4
7
+3V3STBY
UART
SERVICE
CONNECTOR
3749
3748
1701
3
2
1
B04C
ERR
15
7703
16
10
11
5
15
VGA
CONNECTOR
SDA_VGA
SCL_VGA
1E01
12
15
3
E
2
1
3
E
2
2
DC_5V
3
K
4
0
3
K
4
1
VCC_3V3
3
K
5
4
3
K
5
3
VCC
5 6
7E00
M24C02
EEPROM
4E03
4E02
4818
4817
7 EDID_WC
7E01
B04C MT5363
1
2
1KQB
2
1
ROM_SDA
ROM_SCL
U8 T8
46 45
7302
TC90517FG
DIGITAL
DEMODULATOR
3
3
5
2
3
3
5
1
FE_SDA
FE_SCL
7 6
1201
VA1E1BF2403
MAIN
TUNER
ERR
16
3
2
2
8
3
2
3
0
TUNER_SDA
TUNER_SCL
12
14
7H01
VPP1501BFG
TCON
CONTROL
5 6
7K04
M24C64
EEPROM
12 13
7K00
ISL24837IRZ
VOLTAGE
GENERATOR
7 8
7
7801
PCA9540BDP
I2C
SWITCH
HDMI 2
CONNECTOR
HDMI 1 (SIDE)
CONNECTOR
1901
16
15
TO
TCON
TO
SSB
1G51
50
49
3
9
0
7
3
9
0
8
AL14
AL12
1902
16
15
3
9
1
5
3
9
1
6
HDMI_PLUGPWR2
HDMI_PLUGPWR2
AN18
AM17
SIDE_HDMI_SDA1
SIDE_HDMI_SCL1
HDMI_SDA2
HDMI_SCL2
HDMI_SCL2
HDMI_SCL1
HDMI_SDA2
HDMI_SDA1
7900
M24C02
EEPROM
7901
M24C02
EEPROM
4
3 WP_TCON
RESET
MAIN NVM
SW
Programmable via USB SW
SW Programmable via ComPair
EDID
SW
EDID
SW
EDID
SW
3
K
5
6
3
K
5
5
7708
H27U1G8F2BTR
FLASH
1Gb
PDD
U0_RX
U0_TX
NAND
SDRAM
512Mb
7601
H5PS5162FFR
SDRAM
512Mb
7600
H5PS5162FFR
RDQ(0-31)
RA(0-13)
DRAM B04B
RDQ
RA
5 6 5 6
4816
4814
SDA_VCOM
SCL_VCOM
SDA_VGA
SCL_VGA
SDA-TCON
SCL-TCON
1N01
2
3
4 BYPASS_MODE
B08A
B04C
Block Diagrams EN 41 L11M1.1L LA 9.
2011-Apr-29
Supply Lines Overview
SUPPLY LINES OVERVIEW
MAIN
POWER
SUPPLY
B01 DC - DC
T01B TCON CONTROL
B04C CONTROLLER
B06A ANOLOG I/O - HEADPHONE
B04A MTK POWER
B04B DDR
B05A HDMI & MUX
B05B USB
T01A LVDS DISPLAY
B06D VGA
B04D LVDS DISPLAY
T01E MPD
T01F MINI LVDS
B02A TUNER
B02B DIGITAL Demod
B03 CLASS-D & MUTING
T01C TCON DC/DC B06B ANALOG I/O - AUDIO
T01D P GAMMA & VCOM & NVM
1M99
1 1
6 6
7 7
8 8
1M95
+3V3STBY
19130_005_110426.eps
110426
B04d
B03,B04c,B06b
B03,B04a,c,d,
B05a
B02b,B04a,c,d,
B06a,B06b
B02a
B02a,B03.B04c,
B06d,B05a,b
B02b
B02b,B04a
B04a,b
B04a
B03
1M99
1 1
6 6
7 7
2 2
3 3
4 4
5 5
8 8
LAMP-ON
1M99
BACKLIGHT-BOOST
INV_STATUS
+12VDISP
BACKLIGHT-PWM
B04C
B04C
+12VS
9 9
GND-AUDIO
10 10
+3V3_SW
+1V1_SW
EN_1
+24VAUDIO
CONTROL
CONTROL
B04C
CONTROL
B06D
CONTROL
9 9 POWER-OK
2 2
3 3
4 4
5 5
STANDBY
B04A
CONTROL
11 11
7122
RT8283AHGSP
Synchronous
Step-down
Converter
N.C.
5117
PWR5V_2
+3V3STBY +3V3STBY
1902
18 HDMI 2
CONNECTOR
B01
+5V_SW +5V_SW
HDMI_PLUGPWR1
B01
5121
3 2
3 2
+1V8_SW
7124
RT8283AHGSP
Synchronous
Step-down
Converter
7125
RT8283AHGSP
5115 5123
3 2
7123
RT8283AHGSP
3 2
VCC_3V3 VCC_3V3
T01c
VCC_1V8 VCC_1V8
T01c
VDD3V3IO 5H03
VDD3V3LVRS 5H02
VGH_35V VGH_35V
T01c
5H04
5H06
DDR2VDD 5H05
+1V1_SW +1V1_SW
+1V25_SW +1V25_SW
B01
+3V3_SW +3V3_SW
B01
+3V3_SW +3V3_SW
B01
+3V3_SW +3V3_SW
B01
+3V3STBY +3V3STBY
B01
+3V3STBY +3V3STBY
B01
+3V3STBY +3V3STBY
B01
+3V3_SW +3V3_SW
B01
B01
B01
+1V8_SW +1V8_SW
SENCE+1V1_MT5363
B01
+1V8_SW +1V8_SW
1M20
8
5
TO
IR/LED
PANEL
+12VS +12VS
B01
+5V_SW +5V_SW
B01
+5V_SW
+5V5_TUN 5120
6122
6102
+2V5_SW
B04a
SENSE_1V8 SENSE_1V8
B04a
SENSE+1V1_MT5363 SENSE+1V0_MT5363
+5V_SW +5V_SW
B01
+VDISP-INT
+5V_SW +5V_SW
B01
B01
SENCE_1V8
B01
PWR5V_1
1901
18 HDMI 1 SIDE
CONNECTOR
HDMI_PLUGPWR2
VDD1V8PLL
1N01
+VDISP +VDISP
T01c
VREF_15V2 VREF_15V2
T01d
VLS_15V6 VLS_15V6
T01c
T01d,e
T01b,d,f
T01f,d
T01b,f
T01f
T01c
VGH_35V VGH_35V
T01c
+VDISP-INT
+12VDISP +12VDISP
7802
LCD-PWR-ONn
7800
B01
5800
5706
5801
5802
VCC_3V3 VCC_3V3
T01c
VGL_-6V VGL_-6V
B08c
B01
+5V_SW +5V_SW
+5V5_TUN +5V5_TUN
B01
+5VTUN_DIGITAL
+1V25_SW +1V25_SW
+3V3_SW +3V3_SW
B01
B01
+3V3STBY +3V3STBY
+5V_SW +5V_SW
B01
+12VS +12VS
B01
+24VAUDIO +24VAUDIO
B01
B01
+VDISP
VLS_15V6_B
VLS_15V6
+VDISP-INT +VDISP-INT
7J 00
ISL97653
10
21
T01a
5J 06 7J 01
VGL_-6V 3J 10 3J 26
VGH_35V
3,4 VCC_3V3 5J 00
T01b
39 VCC_1V8
6J 02 4J 02
4J 01
4J 04
LCD
SUPPLY
5105 5106
5225
+5VS
7216
IN OUT
COM
B01
+2V5_SW +2V5_SW
5222
6900
6901
DC_5V
1E01
9 VGA
CONNECTOR
5H01
VDD1V8 5H00
3J 12
3E13
+12VS +12VS
+3V3_SW
+3V3-ARC
+3V3_SW B01
B01
32 VREF_15V2
7K00
ISL24837IRZ
VOLTAGE
GENERA-
TOR
+VDISP +VDISP
T01c
T01e
VCC_3V3 VCC_3V3
T01c
VLS_15V6 VLS_15V6
T01c
Synchronous
Step-down
Converter
5104
Synchronous
Step-down
Converter
7120
IN OUT
COM
+1V25_SW
7120
IN OUT
COM
3130
6E05 5E03
50
48
47
49
1G51
4
2
1
3
TO 1N01
TCON
T01A
TO 1G51
SSB
B04D
EN 42 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
10. Circuit Diagrams and PWB Layouts
10-1 B01 393912365052
DC-DC
19130_016_110426.eps
110426
DC-DC
B01A B01A
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
COM
OUT IN
GND
GND HS
VIN
EN
SS
VIA
BOOT
SW
FB
COMP
GND
GND HS
VIN
EN
SS
VIA
BOOT
SW
FB
COMP
GND
GND HS
VIN
EN
SS
VIA
BOOT
SW
FB
COMP
COM
OUT IN
GND
GND HS
VIN
EN
SS
VIA
BOOT
SW
FB
COMP
8
ROUND 4.50mmSCREW HOLE
0V
ROUND 4.02mmSCREW HOLE
12V/1V0 CONVERSION
12V/1V8 CONVERSION
2
PIN
12V/3V3 CONVERSION
3V3/1V2 CONVERSION
12V
0V
7
1
1.5V
25V
0V
3V3
12V/5V CONVERSION
1M99
PIN
>1.5V
ON
12V
6
0V
STBY
0V
0V
6
SLOT SCREW HOLE
3V
0V 9
7
1M95
12V
3V3
0V
3V
1
3V 5
9
0V
ON
12V
5V/2V5 CONVERSION
STBY
0V
I136
2
1
8
9
1
0
u
1
0
n
2
1
9
7
2
2
u
2
1
5
1
33R
5105
2
2
u
2
1
3
8
22n
2158
1
0
u
2
1
6
3
R
E
S
1
%
3
1
1
2
1
5
K
RES
100n
2187
1
0
0
n
2
1
1
1
GND-AUDIO
1
0
0
n
2
1
1
0
F123
F125
I1
0
6
SS1_GND
I1
0
7
1
0
0
n
2
1
0
8 I108
3
1
3
1
4
K
7
3
1
3
0
1
K
0
LD1117DT25
7120
1
3 2
SS3_GND
68R
5127
33R
3129
2
1
4
2
1
0
0
n
F122
R
E
S
4
1
0
0
F135
3
1
1
3
6
8
K
1
%
RES
SS2_GND
F118
5
%
1
0
0
K
3
1
4
6
33R
5120
4
7
0
p
2
1
8
6
R
E
S
6122
SS36
3
1
2
51
%
5
K
1
2
2
u
2
1
3
0
2157 22n
B
Z
X
3
8
4
-C
6
V
8
6
1
0
2
2
1
2
5
1
0
0
n
2
1
4
0
SS1_GND
1
6
V
2
1
7
6
2
2
u
6
.3
V
1
0
0
n
1
0
u
100n
2123
2
1
7
7
1X02
REF EMC HOLE
1X01
REF EMC HOLE
F116 2
1
5
96
.3
V
1
0
0
u
SS4_GND
2170
100n
100K
3100
I1
3
4
+1V1_SW
2
1
4
6
2
u
2
2
1
4
7
1
0
0
n
15K
3116
1
0
0
p
2
1
2
7
3127
R
E
S
4
7
0
p
68R
+2V5_SW
2
1
1
3
2
2
u
2
1
5
2
I127
I1
1
8
+24VAUDIO
1
0
u
2
1
7
2
1
0
0
p
2
1
3
4
F132
3
1
1
51
%
2
7
K
I110
3u6
5123
5124
33R
6
7
5
49
8
3
10
2
7124
RT8283AHGSP
1
3
1
5
3
4
7
0
R
33R
5115
1
0
u
2
1
6
9
1
0
0
n
2
1
4
8
SS4_GND
5128
33R
2
1
0
2
1
0
u
I105
1
6
V
1
0
u 2
1
6
8
F105
7119
LD1117DT
1
3 2
I123
F108
F109
I1
1
2
1
0
0
n
2
1
2
6
I109 2195
22n
5
49
8
3
10
2
+12VS
RT8283AHGSP
1
6
7
I138
7122
3
1
0
51
%
1R0
1
0
0
K
5125
33R
3151
1
n
0
2
1
3
7
R
E
S
SS1_GND
SS3_GND
2
1
8
5
3
n
3
R
E
S
2
1
8
0
1
n
0
3126 68R
1
0
0
n
2
1
4
3
R
E
S 6
.3
V
5
49
8
3
10
2
2
1
0
1
1
0
0
u
RT8283AHGSP
1
6
7
F106
7125
2
1
5
4
1
0
u
1
6
V
GND-AUDIO
SS3_GND
1
0
u
2
1
7
1
1
0
R
3
1
3
8
R
E
S
I122
R
E
S
3u6
5106
SS1_GND
I1
3
9
1R0
3150
2
1
0
7
2
2
u
6
.3
V
R
E
S
1
0
R
3
1
5
5
4
7
0
R
R
E
S
3
1
1
1
6
7
8
9
4
7
0
R
3
1
5
4
1M95
1
10
11
2
3
4
5
1
n
0
2
1
4
1
1-2041145-1
R
E
S
F121
1
6
V
1
0
u 2
1
8
8
2
1
4
9
1
0
0
n
2
1
0
56
.3
V
1
0
0
u
R
E
S
R
E
S
2
2
u
2
1
5
5
2
2
u
2
1
6
6
2
1
6
1
2
2
u
5
%
DGND
F120
4
7
0
K
3
1
4
8
1
0
n
2
1
2
2
I144
I111
1
n
0
2
1
3
6
2
1
9
9
1
0
u
F136
+5V_SW
SS1_GND
EN_1
F131
3
1
4
0
4
K
7
1
%
I137
2
1
9
1
2
2
u
+5V_SW
SS4_GND
F114
+3V3STBY
1
0
u
2
1
6
4
1
n
0
2
1
4
4
1
0
0
n
SENSE+1V1_MT5363
DGND
2
1
3
9
I142
DGND DGND
4
7
0
p
I1
4
0
R
E
S
2
1
5
0
F107
SS3_GND
F117
3
K
6
3
1
4
5
3
1
0
6
1
2
K
100n
1
%
SS2_GND
SENSE_1V8
2124
2
1
7
8
1
0
0
n
EN_1
1
0
u
EN_1
F101
2
1
7
5
4
n
7
2
1
6
7
2
3
4
5
6
7
8
9
2041145-9
1M99
1
2
1
3
5
1
0
n
I1
1
3
5117
33R
SS3_GND
3
1
3
5
1
2
K
SS1_GND
1R0
3152
6
.3
V
2
1
0
6
+5V5_TUN
1
0
0
uDGND
I126
I1
3
5
1
0
0
p
2
1
3
2
1
0
0
p
2
1
3
1
3
1
0
7
1
K
5
1
%
I120
2
1
0
0
1
0
u
100K
3101
100K
3102
2
1
9
2
R
E
S
4
7
0
p
2
1
7
9
1
0
0
n
3128 68R
EN_1
2
1
8
1
1
0
u
+1V8_SW
GND-AUDIO
I141
F113
F103
2
1
4
5
1
n
0
DGND
1
%
1
2
K
3
1
1
8
2
2
u
2
1
6
5
I125
+1V25_SW
SS3_GND
2
1
2
9
+3V3_SW
100K
2
2
u
3103
1X04
EMC HOLE
3149
1R0
I132
I143
F102
2
1
5
3
1
0
u
2
7
K
1
%
I117
SS4_GND
3
1
0
9
I1
1
9
2
1
1
2
4
n
7
I131
2
1
3
3
1
0
0
p
2
1
2
8
1
0
0
p
5
49
8
3
10
2
RT8283AHGSP
1
6
7
5121
10u
7123
F119
F115
SS2_GND
GND-AUDIO
F133
SS2_GND
3
n
3
2
1
6
0
1
2
K
3
1
1
4
2
2
u
2
1
6
2
R
E
S
2
1
9
8
1
0
n
3
1
0
8
1
0
R
SS4_GND
1
6
V
4
7
u 2
1
0
9
+3V3_SW
F104
+12VDISP
SS2_GND
22n 2190
+12VS
I104
2
1
9
3
2
2
u
R
E
S
3
1
3
6
1
0
R
1X05
REF EMC HOLE REF EMC HOLE
1X03
10u
5104
2
1
8
3
2
2
u
SS2_GND
1
0
K
3
1
2
2
47K
3117
2
2
u
2
1
0
4
R
E
S
+12VS
POWER-OK
STANDBY
BACKLIGHT-PWM
LAMP-ON
BACKLIGHT-BOOST
INV_STATUS
Circuit Diagrams and PWB Layouts EN 43 L11M1.1L LA 10.
2011-Apr-29
10-2 B02 393912365052
Tuner
19130_017_110426.eps
110426
Tuner
B02A B02A
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
COM
OUT IN
M
T
M
T
0R
Near Tuner Near MTK5363
3
3
0
n AGND
220n
5230
5
2
2
8
AGND
4
7
n
2
2
9
3
KTK5132E
7218
AGND
F246
F208
AGND AGND
3270
10K
1 3
2
2
7
8
1
u
0
7216
LD29150DT50R
2
2
2
9
4
4
7
u
AGND
AGND
AGND
AGND
F207
F204
F206
A214
1
5
p
2
2
2
5
A213
1
0
0
p
2
2
6
2
R
E
S
2258 100n
2295
F213
100p
1
8 1
0
R
3
2
7
1
-1
I222 I221
3261
NC2
3
RF_AGC
6
SCL
7
SDA
10K
10
IF_OUT+
11
IF_OUT-
IF_OUT_ANALOG
12
1
3
1
4
1
5
1
6
NC1
2
4
+B
8
1
ANT_PWR
5
AS
9
IF_AGC
F236
1201
VA1E1BF2403
T
U
N
E
R
2
2
8
8
3
3
p
75R
3263
75R
3262
F203
3265
1K0
10R
3228 2
2
8
6
1
8
0
p
+5VTUN_DIGITAL
2
2
u
R
E
S
2
2
1
3
A225
AGND
AGND
AGND
2
2
2
6
1
0
0
n
2
2
8
2
1
5
p
R
E
S
1
0
u
2
2
7
9
7217
BC847BW
2
2
8
0
1
0
n
5222
10u
R
E
S
R
E
S
2
2
7
7
2
2
u
AGND
AGND
5225
10R
3230
+5V5_TUN
AGND
2
2
8
1
2
2
u
+5VTUN_DIGITAL
F201
R
E
S
F242
+5VS
R
E
S
2
7 8
3
2
7
2
-2
1
0
R
3
2
7
2
-1
1
0
R
R
E
S
1
2289
AGND
10n
F209
2285
27p
4
2
1
0
R
E
S
2287
10n
F202
2
2
u
2
2
9
6
R
E
S
3
2
6
4
A212
1
0
K
220n
5229
1
8
0
p
2
2
9
1
AGND
AGND
+5VS +5V_SW
AGND
2
2
6
3
4
7
n
3269
1K0
I255
AGND
AGND
F247
I254
27p
2290
AGND
3
2
7
2
-4
1
0
R
R
E
S
4
5
3
2
7
2
-3
1
0
R
R
E
S
3
6
30R
I220
RES 5207
R
E
S
R
E
S
4
2
0
9
4
5
1
n
0
2
2
9
7
3
61
0
R
3
2
7
1
-4 2
71
0
R
3
2
7
1
-3
+5VTUN_DIGITAL
1
0
R
3
2
7
1
-2
5208 4u7
F235
2
2
8
3
2
2
u
1
0
n
2
2
8
4
F205
5226
220n
5227
220n
RF_AGC_SW
DIF_P
DIF_N
VIN_ATV
VIP_ATV
RF_AGC_EX
DIF_N
DIF_P
FE_SDA
FE_SCL
IF_AGC
RF_AGC
EN 44 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
Digital demodulator
19130_018_110426.eps
110426
Digital demodulator
B02B B02B
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
X
XSEL
ADI_AI
ADQ_AI
AD_VREF
TSMD
TN
SLADRS
VSS
D
R
2
V
D
D
D
R
1
V
D
D VDDS
A
D
_
D
V
D
D
A
D
_
A
V
D
D
P
L
L
V
D
D
VDDC
PBVAL
RERR
RLOCK
RSEORF
SBYTE
SLOCK
SRCK
SRDT
STSFLG1
AGCCNTI
AGCCNTR
STSFLG0
SYRSTN
0
1
SCL
SDA
FIL
A
D
_
A
V
S
S
A
D
_
D
V
S
S
P
L
L
V
S
S
I
O
0
1
P
N
P
N
P
N
AD_VREF
DTCLK
DTMB
S_INFO
0
1
AGCI
CKI
SCL
SDA
25.4M
FOR DEVELOPMENT USE
DGND
AGND
AGND
+1V25_SW
+2V5_SW
+3V3_SW
F301
4311
DGND
4310
AGND
DGND
AGND
3
3
6
0
4
K
7
33R 3354
+2V5_SW
1
u
0
2
3
0
5
33R 3359
F306
DGND
3
3
4
4
2
K
7
AGND
I303
I338
1
u
0
2
3
1
3
F303
2337 100n
F300
DGND
1u0
I320
2340
3357 33R
3351 100R
4306
1n5 2335
1
8
p
2
3
3
4
+3V3_SW
DGND
1
0
0
n
2
3
0
2
DGND DGND
DGND
DGND
+3V3_SW
I318
3
7
4
4
4
7
5
0
5
7
6
2
19
18
3
2
3
6
5
6
6
3
1
3
3
5
4
9
6
4
4
1
5
3
3
61
60
51
38
42
8
12
14
1
41
1
6
1
7
53
54
55
59
45
46
6
5
52
7
11
3
4
4
8
4
3
39
40
21
58
2
0
28
2
2
2
3
3
2
3
1
26
25
24
9
10
7302
TC90517FG

29
30
27
2
3
1
7
1
0
0
n
5304
30R
DGND
I325
2339 1u0
I308
4308
DGND
1
0
0
n
2
3
0
4
DGND
1
0
K
3
3
3
5
DGND
3349 10K
2
K
7
3
3
4
3
2
3
2
1
1
0
0
n
1
0
n
2
3
2
2
AGND
2
3
3
2
1
0
0
n
2
3
2
0
1
u
0
100n 2338
3339 20K
1
u
0
2
3
1
6
30R
5306
1
u
0
2
3
1
8
AGND
I304
5302
30R
5307
30R
+1V25_SW
DGND
3
9
p
2
3
7
9
R
E
S
+3V3_SW
I316
I306
I302
2
3
0
7
1
0
0
n
2
3
0
8
2
3
0
9
1
0
0
n
1
0
0
n
F302
3
3
3
2
2
K
7
DGND
+3V3_SW
1
0
K
3
3
3
6
2377 100n
I307
R
E
S
RES
2
3
8
0
3
9
p
4
K
7
3
3
5
0
4307
4309
DGND
AGND
DGND
DGND
DGND
10K 3337
AGND
2
3
0
3
1
0
0
n
33R
5311
1
0
0
n
AGND
2
3
2
3
100n 2378
1
0
0
n
2
3
2
4
100n 2336
2
3
0
1
1
0
0
n
2
3
4
1
1
0
0
n
R
E
S
30R
5301
1
0
0
n
2
3
1
2
30R
5305
4312
4313
DEB
SML-310
6301
5310
DGND
33R
33R
5309
DGND
I305
2
3
1
4
1
u
0
3358 33R
7301
DEB
1
0
0
n
2
3
0
6
BC847BW
1
8
p
2
3
3
3
D N G A D N G A
DGND
4
1 3
I301
1301
2
I300
2
3
1
0
1
u
0
2
K
7
3
3
3
1
DGND
I317
AGND AGND
DGND
DGND
30R
5303
DEB
3356
1K0
AGND
3353 33R
3352 100R
R
E
S
DGND
1K0
DEB
5
3
0
8
1
n
2
AGND
DGND
3355
2
3
1
1
AGND
1
0
0
n
4314
AGND
DIF_N
RESET_DEMOD
IF_AGC
DIF_P
TUNER_SCL
TUNER_SDA
TSO_CLK
TSO_DATA0
TSO_SYNC
TSO_VALID
FE_SDA
FE_SCL
Circuit Diagrams and PWB Layouts EN 45 L11M1.1L LA 10.
2011-Apr-29
10-3 B03 393912365052
Class-D & muting
19130_019_110427.eps
110427
Class-D & muting
B03 B03
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
VIA VIA
VIA
VIA
VCLAMP
MUTE
IN
BSL
SD
R
AVCC
L
BSR
GND_HS
L
PGND
AGND L R
L
OUT
R
BYPASS
1
R
0
PVCC
GAIN
GNDSND
RESERVED
LEFT +
RIGHT -
DC-DETECTION
GNDSND
GND-AUDIO
I401
I413
F400
I416
1
0
0
K
R
E
S
3
4
0
5
-4
4
5
3
4
1
4
I4
2
2
2
2
K
1
K
0
3
4
1
8
+5V_SW
3422-3
100K
RES
1R0
3415
2406
47n
F413
I433
1K0
3428
1u0 2409
3
2
I403
7403
BC847BW
1
7402-2
5
3
4
BC857BS(COL)
5
4
0
1
2
2
0
R
2
4
2
0
1
0
n
I437
2
4
3
2
1
u
0
R
E
S
2
4
3
1
3427
1K0
4
n
7
2407
47n
2
4
3
3
1
u
0
3
4
0
8
R
E
S
4
7
K
1K0
3412
2
4
2
3
1
0
0
n
+24VAUDIO
+24VAUDIO
I412
GND-AUDIO
2
2
0
n
2
4
1
3
3
1
3
2
3
3
34
I423
26
35
36
37
3
8
3
9
4
0
27
28
29
3
0
VIA
7400-2
TPA3123D2PWP
2
4
0
0
2
2
0
n
2
2
0
R
5
4
0
0
7406
2SD2653K
3
4
3
0
4
7
K
R
E
S
1
8
3
4
0
6
-1
2
2
K
BC857BS(COL)
7402-1
2
6 1
GND-AUDIO
GND-AUDIO GND-AUDIO
3
4
3
9
1
0
K
I4
4
1
1
0
K
3
4
3
3
R
E
S
I434
3
4
0
5
-2
2
2
K
2
7
R
E
S
3
4
1
6
1
0
0
K
I417
F411
1K0
RES
I418
3432
F415
I431
10u 2426
220n
2411
F414
GND-AUDIO
I415
1
0
u 2
4
0
53
5
V
3426
I4
4
2
47K
2
4
2
2
2
4
1
8
2
2
0
n
4
7
0
u
1
6
V
1
4
0
3
V
_
N
O
M
2408 1u0
+12VS
R
E
S
1K8
3413
3
4
3
4
4
7
K
22u
5402
35V
I432
2415
220u
I405
F412
F409
7
2
2
K
2
+3V3STBY
3
4
0
6
-2
GND-AUDIO
2412
220n
2
4
1
9
1
0
n
GND-AUDIO
BC847BW
F410
7408
2
4
2
5
R
E
S
BAS316
4
n
7
15
2
11
6401
2
3
2
4
1
3
1
4
131
0
1
2
6
1
9
2
0
21
16
7
18
17
2
5
5
22
4
7400-1
TPA3123D2PWP
CLASS-D

AUDIO AMP
89
F405
GND-AUDIO
F402
F404
1
4
0
2
V
_
N
O
M
F417
F416
3437
3K0
2
2
0
u
I443
2
4
0
13
5
V
2
4
0
4
2
2
0
n
2
2
0
n
2
4
1
4
2
2
0
n
6402
2
4
1
7
BAT54C
I445
GND-AUDIO
3
6
GND-AUDIO
1
8
3
4
0
5
-3
2
2
K
3
4
0
5
-1
2
2
K
3
4
1
0
4401
4
K
7
4K7
3411
22u
5403
100K
3422-2
GND-AUDIO
3
4
3
8
2
2
K
GND-AUDIO
1
K
0
+12VS
3
4
5
4
GND-AUDIO
2
4
2
1
1
0
n
I424
1K0
3435 RES
RES
I4
3
0
2SD2653K
7412
7413
2SD2653K
RES
F401
4R7
3400
3
4
0
6
-3
3
6
+3V3STBY
2
2
K
100K
I406
3422-1
I4
3
5
3
4
5
1
1
K
0
I425
3431
47K
RES
B
A
T
5
4
C
6
4
0
3
1
0
K
3
4
1
7
I411
1
3
2
BC857BW
7404
1
u
0
2
4
2
7
I436
2SD2653K
7407
2
4
0
2
2
2
0
n 3
5
V
2
2
0
u 2
4
0
3
F406
4
7
K
3
4
2
1
1
K
0
3
4
5
3
1
K
0
3
4
5
2
1
2
BSS84
7405
3
2
2
K
3
4
0
6
-4
4
5
6
4
0
0
B
A
S
3
1
6
R
E
S
2
4
2
4
4
n
7
R
E
S
BC847BW
7414
2416
220u 35V
I414
I4
4
0
1
2
3
4
2041145-4
1735
4
n
7
2
4
3
0
R
E
S
1
0
K
3
4
1
9
4
7
K
3
4
2
0
56K
RES
I429
3409
100K
3422-4
F408
7411
BC857BW
RES
1
3
2
LEFT_SPEAKER
LEFT_SPEAKER
RIGHT_SPEAKER
A_STBY
RIGHT_SPEAKER
HP_ROUT
SW_MUTE
AOUTR
HP_LOUT
AOUTL
AOUTR
AOUTL
MUTE
RESET_AUDIO
A_STBY
DC_PROT
EN 46 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
10-4 B04 393912365052
MT5363 Power
19130_021_110427.eps
110427
MT5363 Power
B04A B04A
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
AVSS33
AVSS12 AVDD12
AVDD33
CVBS
DEMOD1
DIG
HDMI
LVDS
REF_AADC
SIF
USB_1
USB_2
USB_3
VDAC
VGA_STB
XTAL
LVDS
MEMPLL
PLL_1
PLL_2
RGB
USB
VPLL
AADC
ADAC0
ADAC1
USB
VPLL
AADC
ADAC0
ADAC1
CVBS
DEMOD1
DIG
HDMI
LVDS_1
LVDS_2
REF_AADC
SIF
USB
VDAC
VGA_STB
XTAL_STB
AVDD10_LDO
ADCPLL
APLL
HDMI
LVDS
MEMPLL
RGB
SYSPLL
TVDPLL
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
VCCK
VCC2IO
VCCK
VCCK
VCCK
VCCK
VCCK
VCC2IO
VCCIO33-1
VCC2IO
VCCIO33
VCC2IO
VCC2IO
1
0
0
n
2
5
2
1
2
5
0
8
1
0
0
n
1
0
0
n
2
5
0
9
2
5
4
9
1
0
0
n
30R 5503
2
5
1
4
4
u
7
1
u
0
2
5
9
7
1
0
0
n
2
5
5
8
3
0
R
5
5
0
1
1
0
0
n
2
5
1
5
2
5
3
2
1
0
0
n
2
5
4
2
1
0
0
n
2
5
3
1
1
0
0
n
1
0
0
n
2
5
1
9
1
0
0
n
2
5
4
4
1
0
0
n
2
5
4
0
2
5
5
0
4
u
7
2
5
3
6
1
0
0
n
4
u
7
2
5
0
0
1
0
0
n
2
5
3
3
2
5
7
0
1
0
0
n
2
5
2
4
1
0
0
n
4
u
7
2
5
8
8
1
0
0
n
2
5
8
0
I505
2
5
6
5
1
0
0
n1
0
0
n
2
5
1
7
+3V3_SW
30R 5502
2
5
3
8
1
0
0
n
+3V3_SW
1
0
0
n
2
5
8
4
1u0 2592
30R 5504
4u7
2598
2
5
0
7
2
2
u1
0
0
n
1
0
0
n
2
5
6
2
2
5
0
3
SENSE_1V8
1
0
0
n
2
5
3
5
5505 30R
F503
1
0
0
n
2
5
2
3
F500
1
0
0
n
4
u
7
2
5
7
9
2
5
8
2
+1V8_SW
F501
2
5
0
4
1
0
0
n
2
5
2
0
I507
2
5
2
2
1
0
0
n
1
0
0
n
5500
30R
J 18
Y29
AK29
AP9
AT9
AT11
AR30
AL24
AK37
AN26
AM9
P19
Y33
AE34
U30
AR32
AG36
AJ 30
AN12
H15
W30
AL30
AM11
AN30
AN24
AK35
P17
T13
AH29
AH31
AF29
AL10
N18
Y31
AF33
T31
AN32
AG34
AK31
AM13
F15
7700-7
MT5363BIMG
AM23
AH33
AG30
AP11
N16
P13
AM25
AG32
1
0
0
n
POWER-MISC
2
5
6
1
2
5
4
3
1
0
0
n
2
5
4
1
1
0
0
n
+3V3STBY
2
5
3
4
1
0
0
n
1
0
0
n
2
5
7
7
2
5
7
4
1
0
0
n
2
5
2
7
1
0
0
n
1
0
0
n
2
5
5
3
2
5
4
5
1
0
0
n
1
0
0
n
2
5
6
6
2
5
5
9
1
0
0
n
3500
1R0
2595
2
5
3
0
1
0
0
n
10u
1
0
0
n
2
5
2
9
5
5
0
6
3
0
R
1
u
0
2
5
7
1
1
0
0
n
2
5
7
3
2
5
1
6
1
0
0
n
1
0
0
n
1
0
0
n
2
5
3
7
2
5
8
1
2
5
2
8
1
0
0
n
1
0
0
n
2
5
6
4
2
5
5
2
1
0
0
n
2
5
9
9
1
u
0
100n 2593
Y13
Y15
AA14
AD15
AD17
AD19
N22
V13
N24
T25
V25
W24
Y25
AA24
AB25
AE20
AE22
U14
AL4
AL6
AL8
AM1
AM3
AM5
AM7
AN2
AN4
R16
AE14
AE16
AE18
AG12
AH7
AJ 6
AJ 8
AK5
AK7
AL2
E12
E14
AF13
AF15
H23
H31
J 30
V31
W32
W34
W36
AD7
AE2
AE4
AF1
AF3
C2
C12
D3
D13
E4
F13
G6
G14
H7
J 14
R2
R4
R6
AC6
B13
AD5
AC22
AC24
AD21
AD23
AD25
AE24
J 6
L4
B1
F5
V23
W20
W22
Y21
Y23
AA20
AA22
AB21
AB23
AC20
J 4
P25
R20
R22
R24
T21
T23
U20
U22
U24
V21
G10
AE8
AF9
B21
D21
E22
G22
N20
P21
P23
G8
AA16
AA18
AB13
AB15
AB17
AB19
AC14
AC16
AC18
F9
AD13
V17
V19
W4
W6
W14
W16
W18
Y3
Y17
E8
Y19
P15
R14
R18
T15
T17
T19
U16
U18
D9
V15
7700-8
MT5363BIMG
POWER-MAIN C8
L6
N14
I506
I504
2
5
0
6
1
0
0
n 2
5
7
6
1
0
0
n
2
5
0
1
1
0
0
n
2
5
1
0
1
0
0
n
2
5
1
3
1
0
0
n
2
5
0
2
1
0
0
n
+1V25_SW
2
5
6
7
4
u
7
2
5
2
6
1
0
0
n
1
0
0
n
2
5
2
5
I5
0
2
1
0
0
n
2
5
1
2
1
0
0
n
2
5
7
5
1
0
0
n
2
5
6
0
1
0
0
n
2
5
0
5
1
0
0
n
2
5
6
9
2
5
6
8
1
0
0
n
+3V3STBY
2
5
1
8
1
0
0
n
F502
2596 100n
+1V1_SW
SENSE+1V1_MT5363
2
5
6
3
1
0
0
n
2
5
5
1
1
0
0
u
6
.3
V
Circuit Diagrams and PWB Layouts EN 47 L11M1.1L LA 10.
2011-Apr-29
DDR
19130_022_110427.eps
110427
DDR
B04B B04B
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
RDQS0
RDQS1
RDQS2
RDQS3
RDQM
RDQ
RA
RBA
RVREF
11
12
13
0
1
2
RCLK0
RRAS
RCLK1
RCAS
RCKE
REXTDN
RODT
RCS
RWE
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
1
2
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
12
11
10
9
8
7
6
5
4
3
0
1
2
3
4
5
6
7
8
9
10
11
12
CK
V
D
D
L
VREF
V
S
S
D
L
14
VDDQ
Q S S V S S V
BA
A
LDQS
UDQS
NC
DQ
CKE
WE
ODT
RAS
1
CS
CAS
0
0
1
2
VDD
LDM
UDM
15
13
12
11
10
9
8
7
6
5
4
3
0
1
2
3
4
5
6
7
8
9
10
11
12
CK
V
D
D
L
VREF
V
S
S
D
L
14
VDDQ
Q S S V S S V
BA
A
LDQS
UDQS
NC
DQ
CKE
WE
ODT
RAS
1
CS
CAS
0
0
1
2
VDD
LDM
UDM
15
13
22R
3612
1%
3
6
2
1
56R 3603-3
1
K
0
1
%
3620
1K0 1%
56R
AB5
N6
P5
N8
P7
K3
3600-2
C10
V1
U6
B9
A8
B7
C6
V3
W2
Y1
AA2
AA4
G12
T5
Y7
H13
D5
F11
F7
B5
D11
E10
E6
T3
AC2
U2
AB3
Y5
T7
AA6
V7
V5
H11
A4
B11
A12
C4
A10
A6
AB1
U4
AC4
T1
J 2
H1
L2
K1
B3
A2
AD1
AD3
P3
D7
E2
M1
M3
G4
M5
F1
M7
F3
P1
D1
H3
7700-3
MT5363BIMG
DRAM
N4
H5
G2
N2
3603-2
56R
56R
1
0
0
n
2
6
0
9
3610-1
F600
3
6
1
9
1
0
0
R
1% 22R
3618
2
6
2
9
1
0
0
n
1% 1K0
3615
3606-2 56R
56R 3608-1
56R
3611-4 56R
3611-2
3610-3 56R
3609-2 56R
3600-1 56R
1
0
0
n
2
6
0
0
56R 3602-3
3606-4 56R
22R 1%
3613
1
0
0
n
2
6
2
0
56R 3606-1
3610-2 56R
56R 3607-1
1
0
0
n
2
6
0
3
1
0
0
n
2
6
0
1
56R
3609-4
56R 3611-1
1
0
0
n
2
6
3
0
56R 3608-4
1
K
0
3
6
1
6
56R 3600-4
1
%
2
6
2
5
1
0
0
n
1
K
0 3
6
2
31
%
1
0
0
n
2
6
2
4
3605-2 56R
K3
3602-4 56R
J
7
A
7
H
8
B
2
B
8
D
2
D
8
E
7
F
2
F
8
H
2
E
9
G
1
G
3
G
7
J 2
A
3
E
3
J
3
N
1
P
9
E
1
J
9
M
9
R
1
J
1
A
9
G
9
C
1
C
3
C
7
C
9
R3
R7
R8
K9
K7
B3
B7
A8
A
1
H9
F1
F9
C8
C2
F3
F7
E8
A2
E2
L1
G2
D7
D3
D1
D9
B1
B9
H7
H3
H1
P2
P8
P3
L2
L3
L7
J 8
K2
K8
L8
G8
M8
M3
M2
P7
R2
M7
N2
N8
N3
N7

SDRAM
H5PS5162FFR-G7C
7601
3601-4
56R
3606-3
56R
3602-2 56R
1
0
0
n
2
6
0
7
2
6
0
6
1
0
0
n
2
6
2
3
1
0
0
n
1
0
0
n
2
6
2
2
2
6
0
5
1
0
0
n
1
0
0
n
2
6
0
4
56R 3605-1
3603-1 56R
+1V8_SW
3604-1
56R
56R 3601-2
2
6
2
7
1
0
0
n
1
0
0
n
2
6
2
6
56R 3609-1
1
0
0
R
3
6
1
4
3601-3 56R
3607-3
F601
56R
56R 3607-4
3600-3
56R
1% 1K0
3622 F602
3609-3 56R
56R 3602-1
3607-2 56R
2
6
0
8
4
7
u
1
6
V
56R
+1V8_SW
3610-4
56R 3604-4
3611-3 56R
1%
2
6
2
1
1
0
0
n
3617
22R
1
6
V
4
7
u 2
6
2
8
3603-4 56R
3605-3 56R
56R 3605-4
3604-2
3601-1
56R
56R
3
6
2
4
1
0
0
R
3604-3 56R
3608-3 56R
3608-2 56R
2
6
0
2
1
0
0
n
+1V8_SW
+1V8_SW
D
2
D
8
E
7
F
2
F
8
H
2
K3
J 2
A
3
E
3
J
3
N
1
P
9
J
7
A
7
H
8
B
2
B
8
A
9
G
9
C
1
C
3
C
7
C
9
E
9
G
1
G
3
G
7
K7
B3
B7
A8
A
1
E
1
J
9
M
9
R
1
J
1
F7
E8
A2
E2
L1
R3
R7
R8
K9
B1
B9
H7
H3
H1
H9
F1
F9
C8
C2
F3
L7
J 8
K2
K8
L8
G8
G2
D7
D3
D1
D9
M7
N2
N8
N3
N7
P2
P8
P3
L2
L3
7600
H5PS5162FFR-G7C
SDRAM
M8
M3
M2
P7
R2

+1V8_SW
RCS#
RDQ(12)
RDQ(11)
RDQ(10)
RDQ(9)
RDQ(8)
RDQ(7)
RA(2)
RA(6)
RRAS#
RDQ(5)
RDQ(14)
RDQ(13)
RDQS(0)
RDQ(4)
RDQ(3)
RDQ(2)
RDQ(1)
RDQ(0)
RDQ(6)
RA(10)
RDQ(15)
RDQM(1)
RDQM(0)
RDQS(1)#
RDQS(1)
RDQS(0)#
RA(1)
RA(11)
RA(7)
RA(0)
RA(4)
RDQM(2)
RCAS#
RWE#
RODT
RCKE
RCLK1#
RCLK1
RCLK0#
RA(9)
RCLK0
RBA(1)
RBA(0)
RA(13)
RA(12)
RA(8)
RA(5)
RA(3)
RDQS(3)#
RDQS(3)
RDQS(2)#
RDQS(2)
RDQM(3)
RDQ(24)
RDQ(23)
RDQ(22)
RDQ(21)
RDQ(20)
RDQ(19)
RDQ(18)
RDQ(17)
RDQ(16)
RBA(2)
RDQ(31)
RDQ(30)
RDQ(29)
RDQ(28)
RDQ(27)
RDQ(26)
RDQ(25)
RDQ(25)
RDQ(26)
RDQ(27)
RDQ(28)
RDQ(29)
RDQ(30)
RDQ(31)
RA(0)
RA(1)
RA(2)
RA(3)
RA(4)
RA(5)
RA(6)
RA(7)
RA(8)
RA(9)
RA(10)
RA(11)
RA(12)
RCAS#
RBA(2)
RA(13)
RBA(0)
RBA(1)
RCKE
RWE#
RCS#
RODT
RRAS#
RA(8)
RA(9)
RA(10)
RA(11)
RA(12)
RA(13)
RBA(1)
RBA(2)
RDQ(1)
RDQ(2)
RDQ(3)
RDQ(4)
RDQ(5)
RDQ(6)
RDQ(7)
RDQ(8)
RDQ(9)
RDQ(10)
RDQ(11)
RDQ(12)
RDQ(13)
RDQ(14)
RDQ(15)
RDQ(16)
RDQ(17)
RDQ(18)
RDQ(19)
RDQ(20)
RDQ(21)
RDQ(22)
RDQ(23)
RDQ(24)
RA(0)
RBA(0)
RCAS#
RCKE
RCLK0
RCLK0#
RCLK1
RCLK1#
RCS#
RDQM(0)
RDQS(0)
RODT
RRAS#
RWE#
RDQ(0)
RDQS(1)
RDQS(0)#
RDQS(2)
RDQS(3)
RDQS(1)#
RDQS(2)#
RDQS(3)#
RDQM(1)
RDQM(2)
RDQM(3)
RA(1)
RA(2)
RA(3)
RA(4)
RA(5)
RA(6)
RA(7)
EN 48 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
Controller
19130_023_110427.eps
110427
Controller
B04C B04C
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
CLE
7
6
5
4
3
2
1
0
VCC
R
SE
WP
WE
RE
CE_
ALE
NC
IO
B
VSS
ETRX ETTX
CI CI
D0
D1
D2
D3
ER
EN
CLK
ETMDC
ETMDIO
MCLKO
MDO0
MOVAL
MOSTRT MISTRT
D0
D1
D2
D3
DV
ER
CLK
ETPHYCLK
ETCOL
ETCRS
MCLKI
MDI0
MIVAL
GPIO GPIO
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
18
19
20
21
22
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SUB
ER
GND
VOUT
VDD
SCL
ADR
0
1
2 SDA
WC
PDD
USB
ADIN_SRV
OSDA
OSCL
TUNER
OPCTRL
OPWM
U0
RX
TX
U1
POCE
HDMI
AGC
DEMOD
CLK
DATA
BYPASS
BYPASS0
ADCINP
ADCINN
IF
RF
3
4
5
6
7
0
1
PARB
PAALE
PACLE
POWE
POOE
RX
TX
PWR5V
SCL2
0
1
2
OIRI
0
1
2
3
4
OPWRSB
CEC
SDA1
SCL1
SDA2
0
1
2
ORESET
FSRC_WR
MEMTN
MEMTP
TP_VPLL
J TCK
J TDO
J TRST
J TDI
J TMS
0
1
2
0
1
2
0
1
2
3
4
5
DP
DM
VRT
XTALI
XTALO
VCXO
0
ONLY
0
AOSDATA0
R
E
S
AOBCK
XTAL 54MHZ
UART (SERVICE)
RES FOR ITV
OPCTRL3(0)
OPWM1
AOLRCK ASPDIF
PDWNC Normal
S
D
M
0
1 0
TRAP2
0
1
0
P
A
N
E
L
ICE mode +ROMmode
PWMDIMMING
FOR DEBUGGING
TRAP1
TRAP0
ICE mode +Serial Boot 0
I713
3741
1K0
3730
10K
RES
+3V3STBY
3781
4700
100R
+3V3STBY
+3V3STBY
+3V3_SW
I757
+3V3STBY
F758
1
0
K
3
7
2
9
3717 22R
BC847BW
7703
3
7
5
4
4
K
7
F757
+3V3_SW
3
7
2
1
4
K
7
2
7
2
3
R
E
S
1
n
0
F706
I750
I753
+3V3_SW
+3V3_SW
1
0
p
2
7
1
7
1
0
p
2
7
0
3
F746
2
7
0
9
4
u
7
2
7
1
6
1
0
p
R
E
S
2
7
1
1
1
0
0
n
3
7
6
8
6K8
1
K
0
F743
3798
I744
F705
I727
3732 100R
1
0
K
2
6
1
3
7
3
3
7709-1
BC847BS(COL)
3711
4K7
100R RES
3794
I756
1
0
p
2
7
2
9
R
E
S
I741
F756
3770
1K0
D
E
B
1
0
K
3
7
5
9
I754
4
K
7
3
7
0
2
3
7
7
7
4
K
7
10R
3795
3
7
A
6
R
E
S
1
0
K
15
8
7
6
1
2
3
7
1
3
3
6
18
19
40
45
46
47
48
3
4
5
10
11
14
25
26
27
28
33
2
34
35
38
39
41
42
43
44
1
20
21
22
23
24
17
9
16
29
30
31
32
+3V3_SW
7708
H27U1G8F2B
100R 3744
1
0
K
R
E
S
3
7
A
7
3705
F759
100R
3704 100R
2
7
2
0
4
7
n
F765
30R
R
E
S
5706
+3V3_SW
1
0
0
K
3
7
9
0
3712
33R
30R
5701
1
0
0
n
2
7
3
0
1
0
K
2
7
1
0
3
7
6
3
-4
D
E
B
4
u
7
4
K
7
+3V3_SW
3
7
5
6
B
Z
X
3
8
4
-C
6
V
8
6
7
0
0
+3V3_SW
1
0
K
3
7
7
8
1
0
0
n
2
7
2
7
100R
3709
+3V3STBY
3748 33R
1700
54M
F741
I731
I716
F721
I745
1
0
K
3
7
0
0
3785 10K
+3V3STBY
I725
1
0
n
R
E
S
2
7
0
5
B
Z
X
3
8
4
-C
3
V
3
6
7
0
8
R
E
S
E32
B31
D31
E34
B33
A36
B35
A34
C34
B37
D35
D33
A32
C32
H37
H33
G34
F37
G36
G32
C36
E36
D37
F31
7700-6
MT5363BIMG
MAC-CI
F35 F33
H35
6
7
0
1
B
Z
X
3
8
4
-C
6
V
8
G30
E30
H29
F29
B29
A22
C22
AF5
AG2
AE6
C30
AF7
AG4
AG6
AH3
AH1
H25
B25
D25
C24
G24
A30
E24
J 24
B23
F23
D23
H27
F27
B27
D27
G26
J 32
E26
A26
C26
J 26
F25
K35
K37
D29
C28
E28
J 28
G28
1
7
0
6
7700-4
MT5363BIMG
GPIO
1
0
0
n
2
7
1
3
3751 100R
6709
BZX384-C8V2
3791
100R
+3V3_SW
4
K
7
3
7
1
9
3
7
1
0
4
K
7
4708 RES
I737
BC847BW
7710
3
7
6
3
-2
1
0
K
D
E
B
R
E
S
1
K
0
3
7
4
3
3745
4K7
1
u
0
1
7
0
5
2
7
0
6
9
12 13
3
7
A
A
4
K
7
1
10
11
2
3
4
5
6
7
8
DEB
1702
502382-1170
3716
+3V3_SW
+3V3_SW
+3V3_SW
22R
100R 3787
F747
2
7
2
2
1
n
0
I738
100R RES
1
0
K
3
7
6
3
-3
3788
D
E
B
F718
I747
F
7
1
9
I755
+3V3_SW
1
0
K
3
7
1
5
I7
1
4
4
K
7
I761
3784
R
E
S
3
7
2
0
10K
10K
3761
4
K
7
F748
3
7
4
6
3
7
5
3
4
K
7
2
7
0
1
R
E
S1
0
0
n
4
F701
+3V3_SW

1
3 2
5
I715
BD45292G
7701
2
1
3
MSJ -035-29DPPO
1701
4
K
7
3749 33R
3
7
4
7
I760
1
0
K
3
7
5
7
2
7
0
4
R
E
S
R
E
S
1
0
p
3
7
A
9
1
0
K
3726
RES
4K7
F766
3737 100R
F738
3
7
0
3
1
0
K
7705
3
7
0
1
BC847BW
4
5
6
7
8
1
0
K
2041145-8
1M20
1
2
3
RES
+3V3_SW
10K
3731
3
7
4
2
6
8
0
R
2
7
0
0
1
0
0
n
R
E
S
F704
F716
3735 100R
100R 3734
3739
1R0
100R 3727
100R 3796
F740
3
7
7
1
1
K
0
1
0
K
3
7
6
0
D
E
B
I726
3
7
0
6
4
K
7
I735
4K7 3783
1
2
3
6
5
8
4
7 (8K 8)

EEPROM
7702
M24C64-WDW6
3
7
A
5
4
K
7
F724
7709-2
5
3
4
220R
BC847BS(COL)
+5V_SW
5705
3765
33R
DEB
10K 3758
F750
+3V3_SW
I739
4
K
7
3
7
3
6
1
0
K
3
7
8
0
D
E
B
R
E
S
3
7
7
9
4
K
7
+3V3STBY
F742
F753
F760
I759
F763
1
0
0
n
2
7
2
8
1
0
0
K
I746
3
7
6
9
F754
2
7
2
6
1
0
0
n
3793
RES 4707
I733
100R
I743
F739
2
2
0
n
2
7
2
1
AP21
R36
T35
AR10
AU10
AN10
T37
AJ 36
AJ 34
AN6
AU2
AT3
AL16
AM15
M33
M19
AP37
N36
N34
AT21
AU4
AT5
AR2
AP5
AR6
AU6
AP7
AT7
AR8
AU8
AT1
T33
AL20
AL22
AP3
R34
P31
AP1
R32
P33
AR4
K5
K7
AN22
AM21
AM19
AN20
AR20
AU20
J 34
J 36
AN14
AM17
AL12
AN18
AL14
M31
AK3
AJ 2
AH5
AJ 4
AK1
MT5363BIMG
AH35
AH37
AL32
AK33
AM35
AL34
AM37
AL36
AM31
L30
CONTROL
7700-1
100R 3728
6
7
0
7
B
A
S
3
1
6
I734
F755
+3V3_SW
+3V3_SW
I711
F702
F737
D
E
B
1
0
K
3
7
6
3
-1
1
0
K
3
7
1
3
F707
F751
I700
2702 100n
+3V3_SW
F745
I758
I7
3
2
3792
2
K
2
100R
+3V3_SW
3
7
A
8
I749
1
0
0
n
2
7
1
2
F749
3
0
R
5
7
0
0
F761
2
7
2
4
1
n
0
2
7
1
9
4
7
n
F717
R
E
S
3
7
7
5
4
K
7
4
K
7
3
7
7
4
1
%
3
7
8
9
R
E
S
5
K
1
100R 3738
3764
1K0
3
7
1
4
1
0
K
+5V_SW
F708
3
7
2
4
1
R
0
I708
I701
+3V3STBY
+3V3STBY
1
0
K
3
7
A
B
R
E
S
F725
3
7
6
2
1
K
0
D
E
B
3767
15K
3
7
1
8
4
K
7
I742
3
7
0
7
4
K
7
3
7
8
6
1
0
K
1
0
K
3
7
8
2
10K
R
E
S
3722
10K 3723
R
E
S
1
0
K
3
7
4
0
6
7
0
6
B
A
S
3
1
6
3
7
7
6
4
K
7
F736
+3V3STBY
+3V3_SW
+3V3_SW
R
E
S
+12VS
1
n
0
2
7
2
5
F744
LIGHT-SENSOR
RESET_AUDIO
RC
NAND_PDD(0)
NAND_PARB
NAND_POCE
NAND_POWE
NAND_PALE
NAND_PCLE
SCL-DISP
SDA-DISP
TUNER_SDA
TUNER_SCL
RF_AGC_SW
NAND_POOE
NAND_PDD(7)
NAND_PDD(6)
NAND_PDD(5)
NAND_PDD(4)
NAND_PDD(3)
NAND_PDD(2)
NAND_PDD(1)
ARC_SW
INV_STATUS
BYPASS_MODE
RESET_DEMOD
VIN_ATV
VIP_ATV
IF_AGC
RF_AGC
BACKLIGHT-PWM
LAMP-ON
STANDBY
BACKLIGHT-BOOST
POWER-OK
POWER_DOWN
J TMS
MUTE
DC_PROT
SW_MUTE
SDA-MAIN
SCL-MAIN
NAND_POCE
SYS_EEPROM_WE
LED-2
BOOST_CONTROL
POWER_DOWN
KEYBOARD
J TDO
J TDO
LIGHT-SENSOR
LED-1
ORESET
J TDI
LED-1
KEYBOARD
J TCK
J TRST
SDA-LCD
PWR5V_1
HDMI_CEC
BACKLIGHT_CONTROL
USB_OCP
USB_PWR_EN
SCL-LCD
USB_DM
USB_DP
PWR5V_2
SIDE_HDMI_SCL1
SIDE_HDMI_SDA1
HDMI_SCL2
HDMI_SDA2
NAND_POWE
NAND_PARB
NAND_POOE
LED-2
J TRST
VCOM_SW
RC
EDID_WC
LCD-PWR-ONn
SDA-MAIN
SCL-MAIN
NAND_PALE
NAND_PCLE
TSO_CLK
TSO_DATA0
TSO_SYNC
TSO_VALID
J TMS
J TDI
J TCK
NAND_PDD(0)
NAND_PDD(1)
NAND_PDD(2)
NAND_PDD(3)
NAND_PDD(4)
NAND_PDD(5)
NAND_PDD(6)
NAND_PDD(7)
Circuit Diagrams and PWB Layouts EN 49 L11M1.1L LA 10.
2011-Apr-29
LVDS Display
19130_024_110427.eps
110427
LVDS Display
B04D B04D
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
-BUS
CTRL
FIL
I 2 C
INP
-
Y
-
Y
Y
PCA5940
Y
Y
-
-
PCA9515 - (RES)
4820
-
4822
4821
-
Y
4817
4818
4810
-
4816
4814 Y
LVDS#1
-
Y
Y
4811
-
4819
-
-
4813
Y
4815
4812
Y
-
Y
Y
-
33R
5800
3803
F801
47R
+3V3STBY
F805
4816
1
0
0
n
2
8
0
5
61
53
54 55
56 57
58 59
60
48
49
5
50
51
6
7
8
9
52
39
4
40
41
42
43
44
45
46
47
28
29
3
30
31
32
33
34
35
36
37
38
19
2
20
21
22
23
24
25
26
27
1
10
11
12
13
14
15
16
17
18
FI-RNE51SZ-HF-R1500
1G51
3
8
0
5
4
7
K
F800
4
8
0
1
R
E
S
I801 5801
33R
R
E
S
R
E
S
4
8
1
5
4813
4
8
2
3
RES
F813
F812
4
8
0
0
R
E
S4
8
0
4
RES
4820
I809
4
8
0
5
I800
F808
4817
+5V_SW
R
E
S
4
8
2
2
4
8
1
0
R
E
S
4
8
1
1
4824
4814
RES
4818
6
7
8
4
1
2
3
SI4835DDY
5
1
0
0
u
1
6
V
7800
2
8
0
4
1
5
K
3
8
0
6
7803
3807
10K
BC857BW
F823
F821
4812 RES
F814
4821 RES
1u0
2806
1
K
0
3
8
1
0
I808
I807
10K
3808
7802-2 5
3
4
BC847BS(COL)
33R
5802
F809
2
6
1
BC847BS(COL)
7802-1
+VDISP-INT
+VDISP-INT
F833
F827
F815
F825
F834
F832
F811
I802
4806 RES
I806
2
2
0
n
2
8
0
7
BZX384-C6V8
6800
F831
F829
F828
47K
4
8
0
3
3802
4808 RES
F810
+12VDISP
+3V3_SW
F807
F806
F822
4
8
0
2
R
E
S
4807 RES
F820
F819
F817
F824
F826
10n 2803
RES
2802
100n
1K0
3809
VSS
6
F818
SC0 5
8 SC1
SCL 4 0 D S 1
SD1 7 SDA 2
VDD
3 PCA9540B
7801
F816
4819
SCL-DISP
SDA-DISP
SDA-VCOM
LCD-PWR-ONn
SDA_VGA
VCOM_SW
SCL-VCOM
BYPASS_MODE
SCL_VGA
PX2A-
PX2A+
PX2C-
PX2C+
PX2B-
PX2B+
PX2E-
PX2E+
PX2D-
PX2D+
PX2CLK-
PX2CLK+
PX1D+
PX1D-
PX1CLK+
PX1B-
PX1A+
PX1A-
PX1E+
PX1E-
PX1CLK-
PX1C+
PX1C-
PX1B+
EN 50 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
10-5 B05 393912365052
HDMI & Multiplexer
19130_025_110427.eps
110427
HDMI & Multiplexer
B05A B05A
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
SCL
ADR
0
1
2 SDA
WC
SCL
ADR
0
1
2 SDA
WC
AE
0P
0N
1P
1N
2P
2N
3P
3N
4P
4N
CKP
CKN
AO
RX1
0
0B
1
1B
2
2B
C
CB
RX2
0B
1
1B
2
2B
C
CB
HDMI_HPD1
HDMI_HPD2
3N
4P
4N
CKP
CKN
0P
0N
1P
1N
2P
2N
3P
0
H : WRITE
HDMI PORT 2 (SIDE)
L : WP
HDMI PORT 1
F906
F913
F907
4900
F904
HDMI_PLUGPWR2
4902
4 5
6916
3
8
6 7 9 10
2 1
IP4281CZ10
RES
F912
HDMI_PLUGPWR2
PWR5V_2
10K
3904
7900
1
2
3
6
5
8
4
7
EEPROM

(256 8)
M24C02-WMN6
10K
3901
F902
3
9
1
3
1
0
0
K
2
9
0
2
1
0
p
F903
HDMI_PLUGPWR1
+3V3STBY
4903
RES
+3V3STBY
3
9
0
6
2
7
K
4901
HDMI_PLUGPWR1
RES
3
9
2
4
6
8
K
D
E
B
HDMI_PLUGPWR1
MMBT3904
7903
+5V_SW
F905
I906
MMBT3904
7902
3
K
3
F900
3
9
1
6
3
9
0
7
3
K
3
F901
3
K
3
1
0
0
K
3
9
2
0
3
9
0
8
HDMI_PLUGPWR1
8
6 7 9 10
2 1
4 5
IP4281CZ10
RES
6913
3
4904
PWR5V_1
5900 30R
I905
+5V_SW
3
9
0
0
1
0
K
7907
MMBT3904
RES
3
K
3
3
9
1
5
I916
1
K
0
F911
3
9
1
2
2
9
0
0
1
0
0
n
F915
F914
6
8
K
3
9
2
3
D
E
B
I902
F909
F908
HDMI_PLUGPWR2
BSH111
7908
RES
9
20 21
22 23
6902
RB521S-30
16
17
18
19
2
3
4
5
6
7
8
1
10
11
12
13
14
15
8
4
7
47266-9002
1902
7901
M24C02-WMN6
1
2
3
6
5
(256 8)

EEPROM
3
9
0
5
4
K
7
8
6 7 9 10
2 1
4 5
RES
IP4281CZ10
6915
3
R
E
S
3
9
1
4
4
K
7
C
D
S
2
C
0
5
H
D
M
I2
5
.6
V
9 10
2 1
4 5
R
E
S
6
9
1
7
IP4281CZ10
6914
3
8
6 7
I915
RES
1
0
0
n
2
9
0
1
AU12
AP19
AT19
AR16
AU16
AP13
AT13
AR14
AU14
AP15
AT15
AR12 D19
A20
C20
A18
C18
AL18
AN16
AP17
AT17
AR18
AU18
H21
F19
H19
B15
D15
A16
C16
B17
D17
B19
E16
G16
F17
H17
E18
G18
E20
G20
F21
7700-5
MT5363BIMG
HDMI-LVDS
1
0
K
3
9
0
3
4
K
7
3
9
0
2
1
K
0
3
9
1
9
7905
RES
MMBT3904
4
K
7
3
9
2
1
R
E
S
HDMI_PLUGPWR2
6
9
0
1 B
A
T
5
4
C
1
2
3
1
2
3 B
A
T
5
4
C
6
9
0
0
5
.6
V
7
8
9
20 21
22 23
C
D
S
2
C
0
5
H
D
M
I2
6
9
0
3
15
16
17
18
19
2
3
4
5
6
1
10
11
12
13
14
PX1D-
M_RX1_1
M_RX2_C
1901
47266-9002
PX2D+
PX2E+
PX2E-
PX2CLK+
PX2CLK-
PX2D- M_RX2_C
M_RX2_CB
PX2A-
PX2B+
PX2B-
PX2C+
PX2C-
HDMI_HPD2
M_RX1_0
M_RX1_0B
M_RX1_1
M_RX1_1B
M_RX1_2
M_RX1_2B
M_RX1_C
M_RX1_CB
M_RX2_0
M_RX2_0B
M_RX2_1
M_RX2_1B
M_RX2_2
M_RX2_2B
PX1C-
PX1C+
PX1B-
PX1B+
PX1A-
PX1A+
PX2A+
SIDE_HDMI_HPD1
PX1CLK-
PX1CLK+
PX1E-
PX1E+
PX1D+
PWR5V_2
SIDE_HDMI_SCL1
SIDE_HDMI_SDA1
HDMI_SCL2
HDMI_SDA2
HDMI_CEC
PWR5V_1
HDMI_CEC_A
HDMI_HPD2
EDID_WC
EDID_WC
M_RX2_2B
M_RX2_2
M_RX2_2
M_RX2_1B
M_RX2_1B
M_RX2_1
M_RX2_1
M_RX2_0B
M_RX2_0B
M_RX2_0
M_RX2_0
eHDMI+
SIDE_HDMI_HPD1
M_RX1_CB
M_RX1_C
M_RX1_C
M_RX1_2B
M_RX1_2B
M_RX1_2 M_RX1_1B
M_RX1_1B M_RX1_1
M_RX1_0B
M_RX1_0B
M_RX1_0
M_RX1_0
M_RX2_CB
M_RX2_CB M_RX2_C
M_RX2_2B
HDMI_CEC_A
ARC_eHDMI+
SIDE_HDMI_SCL1
SIDE_HDMI_SDA1
HDMI_SCL2
HDMI_SDA2
M_RX1_CB
M_RX1_2
M_RX1_2
M_RX1_2B
M_RX1_CB
M_RX1_C
M_RX1_0B
M_RX1_0
M_RX1_1B
M_RX1_1
M_RX2_2
M_RX2_2B
M_RX2_CB
M_RX2_C
M_RX2_0B
M_RX2_0
M_RX2_1B
M_RX2_1
HDMI_CEC_A
Circuit Diagrams and PWB Layouts EN 51 L11M1.1L LA 10.
2011-Apr-29
USB
19130_026_110427.eps
110427
USB
B05B B05B
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
1
2
IN
1
2
3
OUT
USB
FD03
1
D
0
5
FD01 1
2
3
4
5 6
USB-01-PBT-B-30-CU2
1D01
1
D
0
4
+5V_SW
FD05
FD06
1
G
N
D
2
3
5
OC_
6
7
8
7D00
EN_
4
TPS2041BD
1
0
u
2
D
1
1
FD02
16V
100u
B
Z
X
3
8
4
-C
6
V
8
2D14
FD00
6
D
0
0
5D00
33R
1
D
0
3
100n
2D12
FD07
USB_DP
FD04
5V
USB_DP
USB_DM
USB_DM
USB_OCP
USB_PWR_EN
EN 52 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
10-6 B06 393912365052
Analog I/O - Headphone
19130_027_110427.eps
110427
Analog I/O - Headphone
B06A B06A
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
VIA
GND_HS
VO
IN-
VDD
1
SHUTDOWN
BYPASS
2
GND
2
1
RIGHT
RESERVED
HEADPHONE
LEFT
RES
3A09
22K
IA08
10K 3A16
3A04
1R0
RES
RES
33R
RES 3A12
2A11
1u0
RES
IA02
2A09
100u 4V
FA09
RES
3A15
RES
IA10
10K
+3V3_SW
RES
33R
3A13
R
E
S
4
7
n
2
A
0
4
RES 3A17
10K
1
n
0
2
A
1
2
FA07
R
E
S
8
10
11
1
7
F
A
0
4
3
49
2
6
5
R
E
S
RES
7A00
TPA6111A2DGN
AMPLIFIER

2
A
0
5
4
7
n
1u0
2A07
RES
RES
2A08
1u0
R
E
S
IA01
1
A
0
2
3A19 10K
3A18 10K
RES
RES
FA02
IA00
IA03
1
n
0
4V 100u
2A06
RES
2
A
0
2
R
E
S
R
E
S
2
A
1
3
1
n
0
IA04
22K
RES
3A10
33R
4A03
RES
FA08
RES
3A11
3
IA09
1A01
RES 2
1
MSJ -035-12D-B-AG-PBT-BRF
FA03
1
A
0
3
R
E
S 6
A
0
1
P
E
S
D
5
V
0
S
1
B
A
R
E
S
R
E
S
P
E
S
D
5
V
0
S
1
B
A
6
A
0
0
1R0
3A03
RES
FA06
2
A
1
0
1
u
0
R
E
S
RES
33R
3A14
1
n
0
2
A
0
1
R
E
S
4A02
RES
HP_ROUT
HP_LOUT
HP_LOUT
HP_ROUT
PBS_HPR
PBS_HPL
HPOUTR
HPOUTL
RESET_AUDIO
Circuit Diagrams and PWB Layouts EN 53 L11M1.1L LA 10.
2011-Apr-29
Analog I/O - Audio
19130_028_110427.eps
110427
Analog I/O - Audio
B06B B06B
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
&
&
&
&
PR
0P
1P
PB
0P
1P
Y
COM
SOY
SY
SC
CVBS
VDAC
MPX
AIN_AADC
AOSDATA
AR
0
1
2
3
AL
AOMCLK
0
1
2
3
4
ASPDIF
ALIN
0
1
2
3
AVICM
HSYNC
VSYNC
SOG
RP
GP
BP
COM
0P
1P
FS_VDAC
0
1
0
1
0
1
0
1
0N
0P
1P
2P
3P
OUT1
OUT2
AF
P
N
0_L
0_R
1_L
1_R
2_L
2_R
3_L
3_R
4_L
4_R
5_L
5_R
6_L
6_R
VMID_AADC
AOBCK
AOLRCK
NEAR CONNECTOR
SPDIF
DEB
AUDIO IN
+3V3_SW
FB01
5
6
7
8
4
7B01-2
LM833
10u 2B17
10n 2B01
74LVC00APW
7B05-1
1
2
7
1
4
3
D
E
B
7
5
R
3
B
5
8
4
7
K
3
B
5
3
4
7
K
3
B
4
9
2
B
5
2
8
2
0
p
2B37
10u
10u
2B55
3B06 1R0
+12VS
9
10
7
1
4
8
4
5
7
1
4
6
74LVC00APW
7B05-3
7B05-2
74LVC00APW
5
6
0
R
3
B
4
7
IB02
RES
FB06
10u 2B24
3
B
4
4
4
7
K
100n
2B42
3B14
100R
4
7
K
3
B
4
8
3B50
5K1
IB14
IB13
3
2
1
8
4
IB12
+12VS
7B01-1
LM833
1R0
3B32
1
B
0
3
IB25
IB23
IB50
IB16
33p 2B20
+3V3-ARC
+3V3-ARC
3
B
1
7
4
7
K
R
E
S
+3V3_SW
4K7
3B38
4K7
3B37
10u 2B25
1B02
MTJ -032-21B-43-NI
1
2
2
1
3
+3V3-ARC
MSJ -035-29DPPO
1B01
+3V3_SW
2B15
1u0
IB24
1
n
0
2
B
3
8
IB31
R
E
S
IB53
2B11 10n
13
7
1
4
11
5K1
3B52
7B05-4
74LVC00APW
12
IB61
1
0
0
n
2
B
4
4
2
B
4
1
1
u
0
10K
3B41
2
B
5
3
1
u
0
IB63
R
E
S
IB15
3
B
1
8
4
7
K
IB66
6
B
0
0
P
E
S
D
5
V
0
S
1
B
A
R
E
S
3B36 4K7
2
2
0
p
2
B
5
7
2
B
5
0
2
2
0
p
FB02
IB26
IB27
IB10
2
B
5
4
1
0
u
1R0
3B33
IB19
IB39
IB74
+3V3-ARC
FB00
IB51
1
B
0
5
4K7
3B39 RES
3
0
R
3
B
4
2
180R
3B56
+3V3_SW
1
u
0
2
B
4
3
3B40
22K
2B08
IB48
10n
IB18
3B03 68R
IB49
+3V3_SW
2
B
6
0
1
0
0
n
FB07
IB17
68R
30K
3B34
3B09
3B01 68R
4K7 3B35
3B45
10K
IB22
2B51
10u
100R 3B02
3
B
4
3
4
7
K
R
E
S
1
B
0
4
IB52
1
n
0
2
B
3
9
2
B
3
5
1
n
0
R
E
S
3
B
5
5
1
0
K
FB04
+3V3_SW
IB29 10n 2B05
4
7
K
3
B
5
1
R
E
S
P
E
S
D
5
V
0
S
1
B
A
6
B
0
1
10u
2B34
240R 3B15
47n
2B14
AP25
AP33
AR34
AP31
AT31
AA30
AU22
AR28
AU26
IB47
AN34
AP29
AT27
AU30
AP27
AT25
AT33
AU34
AP23
AU28
AR26
AR36
AT37
AU36
AP35
AT35
AM29
AU24
AR22
AN36
K31
N32
AE36
V33
U34
U36
K33
AF35
AT23
AR24
AT29
AF37
U32
V35
V37
L32
L34
M37
M35
L36
P35
P37
AD35
AB35
AC36
AB37
AA32
AB33
AA34
Y35
AA36
Y37
AM33
AD33
AC34
AB31
AC32
68R 3B07
AUDIO-VIDEO
MT5363BIMG
7700-2
IB03
IB41
2
B
1
9
IB67
2B00 1n5
3
3
p
3B46
22K
FB03
1n5 2B06
IB45 3B08 100R
10n 2B03
30K
3B31
2B02 10n
1R0
3B05 68R
3B54
IB01
+3V3_SW
2B61
100n
FB09
8
2
0
p
2
B
5
6
10u
2B59
3
B
5
7
6
8
R
IB70
2
B
4
0
1
0
0
n
2B09 10n
IB43
IB33
2B63
100n
68R 3B11
100n
2B62
IB08 10n 2B07
2B16 10u RES
IB71
IB72
1 2 B I 0 2 B I
IB09
IB00
3B16 100R
FB08
2
B
3
6
1
n
0
R
E
S
10u
2B58
1R0 3B00
IB35
IB37
DVI_AUR_IN
DVI_AUL_IN
HPOUTL
HPOUTR
AOUTL
PREAMPR
GND_CVBS
SPB1P
eHDMI+ ARC_SW
AOUTR
Y0P
SPB0P
SY1P
SPR1P
PREAMPL
AIN0_L-AV1
PR0P
SY0N
SOG
SOY0
PB0P
GN
BP
RP
VSYNC
HSYNC
GP
CVBS_AV3
AIN1_R-AV2
AIN0_R-AV1
ASPDIF_OUT
SPR0P
SY0P
Y0N
PREAMPR
PREAMPL
AIN1_L-AV2
SPDIF_OUT
SPDIF_OUT
SOY1-AV2
SY1N
SAV_L_IN
SAV_R_IN
SOY0-AV1
ASPDIF_OUT
EN 54 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
Analog I/O - Video
19130_029_110427.eps
110427
Analog I/O - Video
B06C B06C
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
RIGHT
CVBS
NEAR CONNECTOR
CVI 2
(WHITE)
NEAR CONNECTOR
LEFT
NEAR CONNECTOR
SIDE AV
(YELLOW)
CVI 1
(RED)
IC05
60R
5C00 3C20
18R
1
C
1
5
18R
3C21
18R
3C22
FC04
FC05
R
E
S
1
n
0
2
C
0
3
3
C
1
7
5
6
R
FC11
2C25
10u
1R0
3C18
1R0
3C06
3C19
7
5
R
3
C
0
8
30K
1
C
1
4
2C24
10u
IC02
5
6
R
3
C
0
5
6
C
0
7
P
E
S
D
5
V
0
S
1
B
A
2
C
1
7
R
E
S
1
5
p
60R
5C01
P
E
S
D
5
V
0
S
1
B
A
R
E
S
6
C
0
8
FC08
5
6
R
3
C
1
6
60R
5C05
2C23
10u
2C22
10u
3C29
30K
3C28
30K
3C27
30K
3C26
30K
P
E
S
D
5
V
0
S
1
B
A
6
C
0
1
R
E
S
3
C
0
4
5
6
R
FC13
1
n
0
R
E
S
2
C
2
1
P
E
S
D
5
V
0
S
1
B
A
6
C
0
6
R
E
S
R
E
S
2
C
1
0
1
n
0
1
C
1
8
5C03
60R
1R0
3C11
R
E
S
FC07
6
C
0
5
P
E
S
D
5
V
0
S
1
B
A
30K
3C10
R
E
S
2
C
0
8
1
5
p
RES P
E
S
D
5
V
0
S
1
B
A
6
C
1
9
IC17
IC19
6
C
0
4
IC18
IC03
P
E
S
D
5
V
0
S
1
B
A
R
E
S
R
E
S
IC09
6
C
0
0
P
E
S
D
5
V
0
S
1
B
A
1
C
0
7
2
C
1
9
1
n
0
R
E
S
6
C
1
0
R
E
S
P
E
S
D
5
V
0
S
1
B
A
FC02
10u
2C09
IC01
1
5
p
2
C
0
4
1
5
p
2
C
1
6
2
C
1
5
1
5
p
IC21
IC22
FC03
18R
IC20
3C23
1
C
1
9
2
C
0
5
1
5
p
1
C
1
7
IC04
60R
5C04
1
C
0
6
FC12
1
2
18R
3C24
1C03-1
YELLOW
MTJ -032-37BAA-432 NI
4
7
p
IC13
2
C
0
7
1
C
1
0
FC15
1R0
3C01
3C13
1R0
5
60R
5C02
1C03-2
WHITE
MTJ -032-37BAA-432 NI
64
1R0
3C00
FC10
IC14
1R0
3C12
4
5
6
7
8
9
1C01
MSP-636H1-01-NI 1
10
11
12
2
3
2C14
10u
6
C
0
2
P
E
S
D
5
V
0
S
1
B
A
R
E
S
6
C
0
9
P
E
S
D
5
V
0
S
1
B
A
3
4
5
6
7
8
9
R
E
S
1
10
11
12
2
MSP-636V1-01
1C02
1
n
0
2
C
2
0
R
E
S
5
6
R
3
C
0
2
2
C
0
0
1
n
0
R
E
S
R
E
S
FC14
2
C
1
1
1
n
0
IC07
1
C
0
5
P
E
S
D
5
V
0
S
1
B
A
R
E
S
6
C
0
3
R
E
S
1
n
0
2
C
0
1
1
C
0
9
FC01
1
C
0
8
R
E
S
6
C
2
0
P
E
S
D
5
V
0
S
1
B
A
R
E
S
1
n
0
2
C
1
3
1
n
0
2
C
1
2
FC00
R
E
S
FC06
1
n
0
2
C
1
8
R
E
S
3C09
1R0
FC09
18R
3C25
IC10
IC11
0
0
0
1
1
5
p
2
C
0
6
R
E
S
1
2
0
2
1
n
0
2
C
0
2
1
C
1
6
3
C
1
4
5
6
R
8
1C03-3
RED
MTJ -032-37BAA-432 NI
97
IC16
IC15
1R0
3C07
SPB0P
SY1P
SPR1P
GND_CVBS
SPB1P
AIN1_L-AV2
CVBS_AV3
AIN1_R-AV2
AIN0_R-AV1
SPR0P
SY0P
AIN0_L-AV1
SY0N
PB_CVI1
PR_CVI2
PB_CVI2
SY_CVI1 SY_CVI2
PR_CVI1
SOY1-AV2
SY1N
SAV_L_IN
SAV_R_IN
SOY0-AV1
Circuit Diagrams and PWB Layouts EN 55 L11M1.1L LA 10.
2011-Apr-29
VGA
19130_030_110427.eps
110427
VGA
B06D B06D
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
SCL
ADR
0
1
2 SDA
WC
2
E
1
1
1
n
0
4E04
3E25
10K
FE07
4E03
2E04
10n
7
5
R
3
E
1
6
BAS316
6E05
1
%
R
E
S
10n
3
E
1
9
6
K
2
2E05
2E03
1n5
2E00
10n 60R
5E00
7E01
BC847BW
DC_5V
1
E
0
3
IE00
FE09
3
E
1
4
7
5
R
3E03
1R0
5
p
6
2
E
0
9
FE04
FE06
FE15
1R0
3E10
3E00
68R
5E04
30R
68R
6
E
0
1
P
E
S
D
5
V
0
S
1
B
A
R
E
S
3E02
R
E
S
6
E
0
2
P
E
S
D
5
V
0
S
1
B
A
FE01
2E16
100n
2
K
2
R
E
S
R
E
S
3
E
1
7
6
8
K
3
E
2
7
FE10
1
E
0
2
0
0
0
1
FE08
2
E
1
3
5
p
6
1
E
0
4
1
0
0
n
2
E
1
0
3
3
0
p
2
E
1
4
R
E
S
2
K
2
3
E
1
8
DC_5V
+5V_SW
8
9
16 17
FE12
13
14
15
2
3
4
5
6
7
1E01
1216-02D-15L-2EC
1
10
11
12
6
E
0
0
P
E
S
D
5
V
0
S
1
B
A
R
E
S
7
3
E
1
5
7
5
R
M24C02-WMN6
1
2
3
6
5
8
4
(256 8)

EEPROM
7E00
10n
2E02
4E02
DC_5V
6
E
0
3
P
E
S
D
5
V
0
S
1
B
A
R
E
S
1
E
0
0
FE03
FE13
10K
3E26
3E24
6K2 1%
RES
FE14
5
p
6
2
E
0
7
60R
5E01
60R
5E02
5E03
60R
DC_5V
30R
3
E
2
2
1
0
K
5E05
2
E
0
8
5
p
6
FE02
P
E
S
D
5
V
0
S
1
B
A
R
E
S
FE16
6
E
0
4
FE05
6
K
2
1
%
R
E
S
3
E
2
3
3
3
R
3
E
2
0
100R
3E04
1
E
0
5
0
0
0
1
2
E
1
2
5
p
6
150R
3E13
3E05
68R
BAS316
6E06
FE11
2
E
1
5
3
3
0
p
1
0
K
3
E
2
1
H_SYNC
VGA_B
VGA_G
VGA_R
VGA_Gp
VGA_Rp
VSYNC
VSYNC
HSYNC
VGA_Bp
SCL_VGA
GN
BP
RP
GP
SOG
EDID_WC
VGA_Gn
SDA_VGA
EN 56 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
10-7 B07 393912365052
Hospitality
19130_031_110427.eps
110427
Hospitality
B07 B07
2011-01-31 2
2011-01-13 1
3139 123 6505
PCB SB SSB
THRILLER BRZDIG
DMMC3
DMMC1
FF02
FF11
FF12
FF01
1
n
0
2
F
0
1
R
E
S
2
F
0
0
1
n
0
R
E
S
2
3
4
5
6 7
1F00
502382-0570
RES
1
RES
5
100R 3F00
502382-0370
1F01
RES
1
2
3
4
FF04
FF03
FF13
100R RES3F01
RES
FF00
5F01 33R
33R 5F00 RES +3V3STBY
+5V_SW
SCL_CLOCK
SDA_CLOCK
PBS_HPR
PBS_HPL
SCL-LCD
SDA-LCD
Circuit Diagrams and PWB Layouts EN 57 L11M1.1L LA 10.
2011-Apr-29
10-8 313912365052 SSB Layout
Overview top side
19130_040_110428.eps
110428
2011-01-31 2
3139 123 6505
SSB Layout Top
1201
1202
1402
1403
1
7
0
0
1701
1702
1705
1706
1
7
3
5
1901
1902
1A01
1
A
0
2
1
A
0
3
1B01
1
B
0
21
B
0
3
1B04
1B05
1C01
1C02
1C03
1
C
0
5
1
C
0
6
1
C
0
7
1C08
1
C
0
9
1C10
1C14
1C15
1C16 1C17
1C18
1C19
1C20
1D01
1
D
0
4
1
D
0
5
1E00
1E01
1E02
1
E
0
3
1
E
0
4
1E05
1F00
1F01
1G51
1
M
2
0
1
M
9
5
1
M
9
9
1X02
1X03
1X04
1X05
2
1
0
0
2
1
0
1
2104
2
1
0
5
2
1
0
6
2109
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2
1
4
0
2141
2142
2
1
4
3
2144
2145
2146
2147
2148
2
1
4
9
2151
2152
2
1
5
3
2
1
5
42155
2159
2161
2162
2
1
6
3
2
1
6
4
2
1
6
8
2169
2
1
7
1
2
1
7
2
2
1
7
5
2
1
7
6
2180
2
1
8
1
2183
2
1
8
8
2
1
8
9
2191
2198
2199
2258
2285 2286 2287 2288 2289
2290
2291
2
2
9
4
2295
2
2
9
6
2297
2400
2401
2402
2403
2
4
0
5
2
4
1
1
2
4
1
2 2
4
1
5
2
4
1
6
2419
2420
2421
2
4
2
2
2
5
1
4
2
5
5
1
2
6
0
8
2609
2
6
2
8
2700
2701
2702
2703 2704
2716
2717
2719
2720
2722
2723
2724
2725
2726
2727
2728
2729
2
8
0
2
2803
2804
2805
2A01
2A02
2
A
0
6
2
A
0
9
2B00
2B01
2B02
2B03
2B05
2B06
2B07
2B08
2B09
2B11
2B16
2B17
2B19
2B20
2B24
2B25
2B
34
2B35
2B36
2B
37
2B38
2B39
2B40
2B
41
2B43 2B44
2B50
2B52
2B55 2B56
2B57
2B60
2B61
2B62
2B63
2C00
2C01
2C02
2C032C04
2C052C06
2C07
2C08
2C
09
2C10
2C11
2C12
2C13
2C
14
2C15
2C16 2C17
2C18
2C19
2C20
2C21
2C22
2C23
2C24 2C25
2D14
2E00
2E02
2E04
2E05
2E07
2E08
2E09
2E10 2E11
2E12
2E13
3126
3127
3128
3129
3600 3602 3605
3606
3607
3608
3609
3610 3611
3612
3613
3614
3615
3617
3618
3619
3706
3707
3709
3711
37123713
3715
3716 3717
3718
3719
3726
3731 3735
3737
3748 3749
3753
3754
3757
3758
3759
3760
3762
3763
3765
3780
3784
3785
3787
3788
3790 3791
3792
3793
3794
3795
3796
3798
37A8
37A9
37AA
3A03
3A04
3A11
3A12
3A13
3A14
3B00
3B01
3B02
3B03
3B05
3B06
3B07
3B08
3B09
3B11
3B15 3B16
3B17
3B18
3B31
3B32 3B33
3B34
3B37
3B40
3B45
3B46
3B48
3B49
3B50
3B52
3B54
3B55
3B56
3B57
3C00
3C013C02
3C043C05
3C06
3C07
3C08
3C09
3C10
3C11
3C12
3C13
3C14
3C163C17
3C18
3C19
3C20
3C21
3C22
3C23
3C24
3C25
3C263C27
3C283C29
3E00
3E02
3E04
3E05
3E10
3E13
3E14 3E15
3E16
3E17
3E18
3F00
3F01
4100
4306
4700
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
5104
5
1
0
5
5106
5
1
1
5
5
1
1
7
5
1
2
0
5121
5123
5207
5
2
0
8
5226 5227 5
2
2
8 5229 5230
5309
5311
5
4
0
0
5
4
0
1
5
4
0
2
5
4
0
3
5506
5700
5706
5C
00
5C
01
5C02
5C
03
5C
04
5C
05
5E00
5E
01
5E
02
5E03
5E04
5E05
5
F
0
0
5
F
0
1
6
1
2
2
6700 6701
6913 6914
6
9
1
5
6
9
1
6
6917
6A00
6A01
6B00 6B01
6
C
0
0
6
C
0
1
6
C
0
2
6
C
0
3
6
C
0
4
6C05
6C06
6C07
6
C
0
8
6
C
0
96
C
1
0
6
C
1
9
6
C
2
0
6E00
6E01 6
E
0
2
6
E
0
3
6E04
6
E
0
5
7120
7
1
2
2
7
1
2
3
7
1
2
4
7
1
2
5
7216
7
4
0
0
7600
7601
7700
7
7
0
2
7703
7801
7
A
0
0
7
B
0
1
7B05
U2
U23
U4
U5
1X01
EN 58 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
Overview bottom side
19130_041_110428.eps
110428
2011-01-31 2
3139 123 6505
SSB Layout Bottom
1301
1
D
0
3
2102
2
1
0
7
2108
2110
2111
2112
2113
2122 2123
2124
2139
2150
2157
2158
2160
2165
2
1
6
6
2167
2170
2177 2178 2179
2185
2186 2187
2190
2192
2
1
9
3
2195
2197
2
2
1
3
2225
2226
2262
2263
2277
2278
2
2
7
9
2280
2
2
8
1
2282
2
2
8
3
2284
2293
2301
2302
2303
2304
2305
2306
2307 2308
2309
2310
2311
2312
2313
2314
2316
2317
2318
2320
2321
2322 2323
2324
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2377
2378
2379
2380
2
4
0
4
2
4
0
62
4
0
7
2
4
0
8
2
4
0
9
2413
2414
2417
2418
2423
2424 2425
2
4
2
6
2427
2430
2431
2432
2433
2500
2501
2502
2503
2504 2505
2506
2507
2508 2509
2510
2512
2513
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2540
2541
25422543
2544
2545
2549
2
5
5
0
2552
2553
2558
2559 2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2
5
7
1
2573
2574
2575
2576
2577
2579
2580
2581
2582
2584
2
5
8
8
2592
2593
2
5
9
5
2596
2597
2
5
9
8
2599
26002601
2602
2603
2604
2605 2606
2607
2620
2621
2622
2623
2624
2625
2626
2627
2629
2630
2705
2706
2
7
0
9
2
7
1
0
2711
2712
2713
2
7
2
1
2730 2
8
0
6
2807
2900
2901
2902
2A04
2A05
2A07
2A
08
2A
10
2A
11
2A12
2A13
2B14
2B15
2B42
2B51
2B
53
2
B
5
4
2B
58
2B
59
2D
11
2D12
2E03
2E14
2E15
2E16
2F00
2F01
3100
3101
3102
3103
3105
3106
3107
3108
3109
3111
3112
3113
3114
3115
3116
3117
3118
3122
3125
3130
3131
3135
3136
3138
3140
3145
3146
3148
3149
3150
3151
3152
3153
3154
3155
3228
3230
3261
3262
3263
3264
3265
3269
3270
3271 3272
3331
3332
3335
3336
3337
3339
3343
3344
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3400
3405
3406
3408
34093410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3426
3427
3428
3430
3431
3432
3433
3434
3435
3437
3438
3439
3451
3452
3453
3454
3500
3601
3603
3604
3616
3620
3621
3622
3623
3624
3700
3701
3702
3703
3704
3705
3710
3714
3720
3721
3722 3723
3724
3727
3728
3729
3730
3732
3733
3734
3736
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3751 3756
3761
3764
3767
3768
3769
3770
3771
3774
3775
3776
3777
3778
3779
3781
3782
3783
3786
3789
37A5
37A6 37A7
37AB
3802
3803
3805
3806
3807
3808
3809
3810
3900
3901
3902
3903
3904
3905
3906
3907
3908
3912
3913
3914
3915
3916
3919
3920
39213
9
2
3
3924
3A09
3A10
3A15
3A16
3A17
3A18
3A19
3B14
3B35
3B36
3B38
3B39
3B41
3B42
3B43
3B44
3B47
3B51
3B53
3B58
3E03
3E19
3E20
3E21
3E22
3E23
3E24
3E25
3E26
3E27
4209
4210
4
3
0
7
4
3
0
8
4
3
0
9
4310
4311
4312
4313
4314
4401
4707
4708
4
8
0
0
4
8
0
1
4
8
0
2
4
8
0
3
4
8
0
4
4
8
0
5
4
8
0
6
4
8
0
7
4
8
0
8
4900
4901
4902
4903
4904
4A02
4A03
4E02
4E03
4E04
5
1
2
4
5
1
2
5
5
1
2
7
5
1
2
8
5
2
2
2
5225
5301 5302
5303
5304
5305
5306
5307
5308
5
3
1
0
5500
5501
5502
5503
5504
5505
5701
5
7
0
5
5
8
0
0
5
8
0
1
5
8
0
2
5900
5D
00
6102
6301
6
4
0
0
6401
6402
6
4
0
3
6706
6707
6708
6709
6800
6900
6
9
0
1
6902
6903
6
D
0
0
6E06
7119
7
2
1
7
7
2
1
8
7
3
0
1
7302
7402
7403
7404
7
4
0
5
7
4
0
6
7407
7
4
0
8
7
4
1
1
7412
7413
7
4
1
4
7
7
0
1
7
7
0
5
7708
7709
7
7
1
0
7
8
0
0
7802
7803
7
9
0
0
7901
7
9
0
2
7903
7
9
0
5
7
9
0
7
7908
7D00
7E00
7
E
0
1
A212
A213
A214
A225
C400
CXXX
F101
F102
F103
F104
F105
F106
F107
F108
F109
F113
F114
F115
F116
F117
F118
F119
F120
F121
F122
F123
F125
F131
F132
F133
F135
F136
F201
F202
F203
F204
F205
F206
F207
F208
F209
F213
F235
F236
F242
F246
F247
F300
F301
F302
F303
F306
F400
F401
F402
F404
F405
F406
F408
F409
F410
F411
F412
F413
F414
F415
F416
F417
F500
F501
F502
F503
F600
F601
F602
F701
F702
F704
F705
F706
F707
F708
F716
F717
F718
F719
F721
F724
F725
F736
F737
F738
F739
F740
F741
F742
F743
F744
F745
F746
F747
F748
F749
F750
F751
F753
F754
F755
F756
F757
F758
F759
F760 F761
F763
F765
F766
F800
F801
F805
F806
F807
F808
F809
F810
F811
F812
F813
F814
F815
F816
F817
F818
F819
F820
F821 F822
F823 F824
F825 F826 F827 F828
F829
F831
F832
F833 F834
F900
F901
F902
F903
F904
F905 F906
F907
F908
F909
F911
F912
F913
F914
F915
FA02
FA03
FA04
FA06
FA07
FA08
FA09
FB00
FB01
FB02
FB03
FB04
FB06
FB07
FB08
FB09
FC00
FC01
FC02
FC03
FC04 FC05
FC06
FC07
FC08
FC09
FC10 FC11 FC12
FC13
FC14 FC15
FD00
FD01
FD02
FD03
FD04 FD05
FD06
FD07
FE01
FE02
FE03
FE04
FE05
FE06
FE07
FE08
FE09
FE10
FE11
FE12
FE13
FE14
FE15
FE16
FF00 FF01 FF02 FF03
FF04
FF11
FF12 FF13
I104
I105
I106
I107
I108
I109
I110
I111
I112
I113
I117
I118
I119
I120
I122
I123
I125
I126
I127
I131
I132
I134
I135
I136
I137
I138
I139
I140
I141
I142
I143
I144
I220
I221
I222
I254
I255
I300
I301
I302
I303
I304
I305
I306
I307 I308
I316
I317
I318
I320
I325
I338
I401
I403
I405
I406
I411
I412
I413
I414
I415
I416
I417
I418
I422
I423
I424
I425
I429
I430
I431
I432
I433
I434
I435
I436
I437 I440
I441
I442
I443
I445
I502 I504
I505
I506
I507
I700
I701
I708
I711 I713
I714
I715
I716
I725
I726
I727
I731 I732
I733
I734
I735
I737
I738
I739
I741
I742
I743
I744
I745
I746
I747
I749
I750
I753I754
I755
I756
I757
I758
I759
I760
I761
I800
I801
I802
I806
I807
I808
I809
I902
I905
I906
I915
I916
IA00 IA01
IA02
IA03
IA04
IA08
IA09 IA10
IB00
IB01
IB02
IB03
IB08IB09
IB10
IB12
IB13
IB14
IB15
IB16
IB17
IB18
IB19
IB20
IB21
IB22
IB23
IB24 IB25
IB26 IB27
IB29
IB31 IB33
IB35
IB37
IB39
IB41
IB43
IB45
IB47
IB48
IB49
IB50
IB51
IB52
IB53
IB61
IB63
IB66
IB67
IB70
IB71
IB72
IB74
IC01
IC02
IC03
IC04
IC05
IC07
IC09 IC10
IC11
IC13
IC14
IC15
IC16
IC17 IC18
IC19
IC20
IC21
IC22
IE00
U1
U3
Circuit Diagrams and PWB Layouts EN 59 L11M1.1L LA 10.
2011-Apr-29
10-9 T01 393912365071
LVDS Display
19130_032_110427.eps
110427
LVDS Display
T01A T01A
2010-06-29 1
3139 123 6507
PCB SB
THRILLER BRZTCON
NC
LVDS#1
59
60
9
52
61
53
54 55
56 57
58
46
47
48
49
5
50
51
6
7
8
36
37
38
39
4
40
41
42
43
44
45
27
28
29
3
30
31
32
33
34
35
17
18
19
2
20
21
22
23
24
25
26
1
10
11
12
13
14
15
16
FI-RE51S-HF
1N01
FN32
FN28
FN26
FN27
FN25
FN20
FN18
FN19
FN17
10n 2N03
RES
FN14
FN13
FN11
FN12
+VDISP-INT
FN01
FN33
1X02
REF EMC HOLE
FN31
1X01
REF EMC HOLE
FN29
FN24
FN23
FN21
FN22
FN16
FN15
FN07
FN08
FN06
FN05
2
N
0
1
1
0
0
u
1
6
V
1
0
0
n
2
N
0
2
FN10
FN09
SCL-TCON
SDA-TCON
PX2CLK+
PX2CLK-
BYPASS_MODE
PX2D+
PX2D-
PX2E+
PX2E-
PX1A-
PX1C-
PX1B+
PX1B-
PX1A+
PX1D+
PX1D-
PX1CLK+
PX1CLK-
PX1C+
PX2A+
PX2A-
PX1E+
PX1E-
PX2C+
PX2C-
PX2B+
PX2B-
EN 60 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
TCON Control
19130_033_110427.eps
110427
TCON Control
T01B T01B
2010-06-29 1
3139 123 6507
PCB SB
THRILLER BRZTCON
C1
Q
Q
R
S
1D
1
1
C1
Q
Q
R
S
1D
12
11
10
9
8
7
6
5
4
3
0
1
2
3
4
5
6
7
8
9
10
11
12
CK
V
D
D
L
VREF
V
S
S
D
L
14
VDDQ
Q S S V S S V
BA
A
LDQS
UDQS
NC
DQ
CKE
WE
ODT
RAS
1
CS
CAS
0
0
1
2
VDD
LDM
UDM
15
13
DQ
A
BA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LDQS
UDQS
CAS
WE
CK
CKE
ODT
0
1
RESIMP
0
1
2
3
4
5
6
7
8
9
10
11
12
CS
RAS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD18PLL
VSS
VDD18
VDD18
VDD18
VDD18
VDD33LVML
VDD33IO
VDD18
VDD18
VDD18
VDD18
NC
DB
EE
OSC
OUT
IN
0
1
2
3
TESTSE
RST
SCL
SDA
ATTN
RTC50_60
SCL
SDA
TESTAGN
TESTMOD
RXE RXO
RXO RXE
4N
CLKP
CLKN
0P
0N
1P
0P
0N
1P
1N
2P
2N
3P
3N
4P
4N
CLKP
CLKN
1N
2P
2N
3P
3N
4P
CS
LLV
LLV
STH
B1
B2
STH
0P
0N
1P
1N
2P
2N
3P
3N
4P
4N
5P
5N
6P
6N
7P
7N
CKP
CKN
RLV
RLV
1
2
3
4
5
6
7
8
9
10
11
12
RESPI
F1
F2
POL
TP
CPV
OE
STVU
STVD
SLOPE
GP01
GP02
L|R_
U|D_
SELLVOS
0P
0N
1P
1N
2P
2N
3P
3N
4P
4N
5P
5N
6P
6N
7P
7N
CKP
CKN
FH06
FH00
1
0
0
n
2
H
3
8
1
0
0
n
2
H
3
9
2
H
3
6
1
0
0
n
FH35
DDR2VDD
DDR2VDD
2
H
5
0
DDR2VDD VCC1V8
5H05
1
0
u
VCC1V8
60R
100R
3H23
33R
3H21
RES
2K2
3H22
74LVC1G74DC
2
1
4
5
3 6
7
8
4
7H03
7H05
2
1
3
5 74LVC1G86GW
2
H
4
2
1
0
0
n
4H04
3
H
0
4
1
6
K
3
H
0
3
1
5
0
K
4H05
VCC_3V3
2H54
VDD3V3IO
1u0
7
8
VDD1V8
VDD1V8PLL VDD3V3LVRS
2
1
4
5
3 6
3
2
5
4
7H04
74LVC1G74DC
6
7H02-2
74LVC2G04
74LVC2G04
7H02-1
1
2
5
FH02
FH01
FH03
1
0
0
n
FH05
1
0
0
n
2
H
2
9
2
H
2
7
2
H
2
8
1
0
0
n
1
0
0
n
2
H
3
1
2
H
3
0
1
0
0
n
1
0
0
n
2
H
3
5
2
H
3
2
1
0
0
n
2
H
3
4
1
0
0
n
1
0
u
VCC1V8
60R
5H01
2
H
4
4
2
H
4
3
1
0
u
60R
5H00
1
0
u
2
H
5
1
60R
5H06
1
0
0
n
2
H
5
3
R
E
S
3H20
100R
F
8
H
2
K3
P
9J7
A
7
H
8
B
2
B
8
D
2
D
8
E
7
F
2
C
9
E
9
G
1
G
3
G
7
J 2
A
3
E
3J3
N
1
A
1
E
1
J9M
9
R
1
J1A
9
G
9
C
1
C
3
C
7
E2
L1
R3
R7
R8
K9
K7
B3
B7
A8
H1
H9
F1
F9
C8
C2
F3
F7
E8
A2
L8
G8
G2
D7
D3
D1
D9
B1
B9
H7
H3
N7
P2
P8
P3
L2
L3
L7
J 8
K2
K8

M8
M3
M2
P7
R2
M7
N2
N8
N3
SDRAM
H5PS5162FFR-S6C
7H00
VGH_35V
3
VCC_3V3
VCC_3V3
DSX321G
1H00
27M
2 4
1
1
0
0
R
3
H
1
5
1
0
0
R
3
H
1
6
1
0
0
R
P14
U4
D10
D11
3
H
1
7
N13
N14
P5
P6
P8
P9
D9
P10
P11
P12
P13
M8
M9
M12
M13
N4
D8
N5
N8
N9
N12
K6
K7
K10
K11
L4
D7
L6
L7
L10
L11
M5
J 1
J 2
J 4
J 5
J 8
D6
J 9
J 12
J 13
J 14
J 16
G6
G7
G10
G11
D5
H5
H8
H9
H12
H13
E8
E9
E12
E13
C4
E14
F6
F7
F10
F11
G4
E15
J 15
N15
R13
C3
D12
D13
D14
E2
E4
E5
E10
E11
F5
C6
R6
R9
R12
C8
C11
C13
N3
N6
N7
N10
N11
P15
R5
E6
R8
R11
E7
L3
L5
L8
L9
L12
L13
M6
E3
M7
M10
M11
J 6
J 7
J 10
J 11
K5
K8
D15
K9
K12
K13
G5
G8
G9
G12
G13
H6
C9
H7
H10
H11
J 3
C7
C10
C12
G3
C5
F8
F9
F12
F13
C2
C1
M2
POWER
VPP1501BFG
7H01-5
K1
K4
H1
H4
D3
D2
G2
G1
M4
M3
E1
N2
H3
H2
F3
F2
F1
F4
D1
D4
K3
K2
R3
U1
T4
U2
P1
P2
N1
L2
M1
L1
P4
R2
R1
T3
U3
P3
T1
R4
T2
DRAM
VPP1501BFG
7H01-4
1
0
0
n
2
H
1
0
1
0
0
n
2
H
0
8
2
H
0
7
1
0
0
n
1
0
0
n
2
H
0
9
1
0
0
n
FH34
1
0
0
n
2
H
4
7
2
H
4
8
R
E
S
2
H
0
3
FH04
2
H
1
3
1
0
0
n
2
H
2
6
1
0
0
n
1
0
0
n
1
0
0
n
2
H
2
5
1
0
0
R
3
H
0
7
2
H
3
7
VCC_3V3
DDR2VDD
1
0
0
n
1
0
0
n
5H03
2
H
3
3
VDD3V3LVRS
VDD3V3IO
60R
VDD1V8
VDD1V8PLL
3H00
2
H
5
2
1K0
VCC1V8
1
0
0
n 60R
5H04
3
H
1
9
RES
1
0
0
R
3H06
1K0
3H05
2K4
1
M
0
3
H
0
2
3H01
560R
2
H
4
1 1
0
p
2
H
4
0
1
0
p
3
H
1
8
1
0
0
R
1
0
0
R
3
H
1
3
1
0
0
R
3
H
1
4
U15
U14
U12
T12
U13
U10
K16
L15
L14
L17
L16
M15
M14
T17
T16
H15
H14
F17
F16
G15
G14
G17
G16
H17
H16
K15
K14
K17
D17
D16
E17
E16
F15
F14
T10
U11
T13
J 17
A17
A16
B15
B14
B17
B16
C15
C14
C17
C16
N17
P16
P17
R14
R15
R16
U16
U17
A15
A14
LCD
T11
M16
R17
T14
T15
M17
N16
A8
B8
A10
B10
VPP1501BFG
7H01-3
B2
A4
B4
A13
B13
A12
B12
A11
B11
A9
B9
VPP1501BFG
LVDS
A7
B7
A6
B6
A5
B5
A3
B3
A2
U6
T6
U7
7H01-2
R7
T8
U8
A1
B1
T9
U9
R10
U5
T5
MISC
VPP1501BFG
7H01-1
T7
P7
1
0
0
n
2
H
0
5
2
H
0
4
1
0
0
n
1
0
0
n
2
H
0
6
2
H
0
2
1
0
0
n
2
H
0
1
1
0
0
n
3
H
1
2
1
0
0
R
1
0
u
2
H
4
5 60R
5H02
1
0
u
2
H
4
6
1R0 3H27
1R0 3H28 RES
RES
1R0 3H26 RES
1R0 3H25 RES
3
H
1
0
1
0
0
R
3
H
1
1
1
0
0
R
3
H
0
9
1
0
0
R
1
0
0
R
3
H
0
8
FH36 FH40 FH39 FH38 FH37
REV
SCL-TCON
SDA-TCON
U_D_INV
RESET
GSP2
GSP1
GCK
U_D
TDQ4
TDQ5
TDQ6
TDQ7
TDQ8
TDQ9
TDQ0
TDQ1
TDQ10
TDQ11
TDQ12
TDQ13
TDQ14
TDQ15
TDQ2
TDQ3
TA10
TA11
TA12
TCAS#
TCKE
TWE#
TBA0
TBA1
TODT
TCS#
TRAS#
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TA7
TA8
TA9
RESET
TCK#
TCK
TLDQS
TLDQS#
TUDQS
TUDQS#
OSCIN
OSCOUT
ROM_SDA
SDA-TCON
PX1CLK+
REV
OSCIN
OSCOUT
50Hz_60Hz
ROM_SCL
SCL-TCON
PX1D-
PX1C+
PX1C-
PX1B+
PX1B-
PX1A+
PX1A-
TLDQS
TLDQS#
TODT
TRAS#
TUDQS
TUDQS#
TWE#
PX1E+
PX1E-
PX1D+
TA12
TA2
TA3
TA4
TA5
TA6
TA7
TA8
TA9
TBA0
TBA1
TCAS#
TCK
TCKE
TCK#
TCS#
TDQ0
TDQ1
TDQ10
TDQ11
TDQ12
TDQ13
TDQ14
TDQ15
TDQ2
TDQ3
TDQ4
TDQ5
TDQ6
TDQ7
TDQ8
TDQ9
LCK-
LCK+
SELLVDS
GSLOP
RDIO1
RDIO2
LDIO1
LDIO2
GSP1
GSP2
LS
U_D
TA0
TA1
TA10
TA11
LLV2+
LLV1-
LLV1+
LLV0-
LLV0+
LLV7-
LLV7+
LLV6-
LLV6+
LLV5-
LLV5+
LLV4-
LLV4+
LLV3-
LLV3+
LLV2-
RLV1+
RLV0-
RLV0+
RLV7-
RLV7+
RCK-
RCK+
R_L
GOE
RLV5+
RLV4-
RLV4+
RLV3-
RLV3+
RLV2-
RLV2+
RLV1-
RESET
PX1CLK-
GCK
ASIC_CS1
ASIC_CS11
ASIC_CS3
ASIC_CS5
ASIC_CS7
ASIC_CS9
RLV6-
RLV6+
RLV5-
PX2B-
PX2A+
PX2A-
PX2CLK+
PX2CLK-
PX2E+
PX2E-
PX2D+
PX2D-
PX2C+
PX2C-
PX2B+
Circuit Diagrams and PWB Layouts EN 61 L11M1.1L LA 10.
2011-Apr-29
TCON DC/DC
19130_034_110427.eps
110427
TCON DC/DC
T01C T01C
2010-06-29 1
3139 123 6507
PCB SB
THRILLER BRZTCON
VIA VIA
VIA
VIA
DRN
COM
VREF
FBN
NOUT
CB
1
2
FBL
LDO-CTL
LDO-FB
TEMP
FBP
C1
P
N
C2
LX
LXL
PGND
PVIN
SUPP
S
U
P
N
A
G
N
D
G
N
D
_
H
S
COMP
HVS
EN
PROT
P
N
CTL
CDEL
VL
CM2
1
2
FBB
RSET
POUT
FOR DEBUG ONLY
DISPLAY INTERFACING - VDISP
cK00
FJ 14
FJ 55
FJ 01
+VDISP
LTST-C190KGKT
6J 07
7
3J 28
2K2
1 8
4J 04-2 2
4J 04-1
VCC_3V3
2
2N7002
7J 05
3
1
3
J
2
3
RES
R
E
S
3
K
6
3
J
2
2
1
0
K
P
M
E
G
1
0
3
0
E
J
6
J
0
0
SGND1
SGND1
R
E
S
RES 2
K
2
3
J
1
6
3
J
1
5
2
K
2
4
7
u
2
J
5
1
R
E
S
SGND1
RES
SGND1
R
E
S
2
J
5
2
4
7
u
2K2
RES
3
J
1
9
R
E
S
3J 09
SGND1 2
K
2
1
0
u
2
J
0
9
FJ 04
6
2
J
0
5
1
0
u
4 5
4J 04-3 3
3 6
4J 02-4
2 7
4J 02-3
4J 02-2
FJ 13
4
J
0
3
2
K
2
3
J
1
3
RES
R
E
S
3J 08 2K2
RES
2K2
3J 06
SGND1
10K 3J 11
2
J
3
9
2
u
2
VCC_3V3
1
2
31
9
10
R
E
S
13
3
2
3
356
1
4
21
36
3
8
1
28
11
20
4
1
27
40
39
34
35
3
4
17
2 25
7
22
30
24
23
26
29
8
7J 00-1
ISL97653AIRZ

3
7
16
15
18
43
44
45
4
6
4
7
4
8
4
9
50
42
51
52
53
5
4
5
5
5
6
5
7 ISL97653AIRZ
7J 00-2
VIA
2
3
R
E
S
1
0
0
K
3
J
0
5
5
6
7
8
4
1
4 5
RES 7J 02
FDS9435A
4J 01-4
2
0
K
3
J
2
4
S
S
2
4
6
J
0
5
2J 35
1u0
2
J
4
12
2
u
1
6
V
VGL_-6V
240K 3J 26
2
2J 40 1u0
RB550EA
6J 01
1
3
5
4
+VDISP-INT
2J 34 220n
SGND1
39K 3J 10
2J 32 220n
2
J
0
3
2
u
2
10K
3J 01
RES 2 7
VGH_35V
4J 00-1 RES 1 8
4J 00-2
2
K
2
R
E
S
3
J
2
1
2 3
RES
2
J
2
6
1
2
0
p
RES
2SB1767
7J 04
1
2
J
3
1
1
0
0
n
R
E
S
2
J
3
0
4
u
7
0
.5
%
2
4
K
3
J
1
4
VLS_15V6
RES 2J 16 100n
2
J
1
4
2
u
2
7
5
0
K
3
J
1
8
2
7
K
3
J
1
7
2
J
2
9
1
0
0
p
R
E
S
2
J
2
8
1
0
0
n
5J 00
4u5
2J 17 100n
SGND1
2J 15
4n7 1% 10K
3J 07
2J 19 220n
SGND1
V
L
S
_
1
5
V
6
_
B
+
V
D
IS
P
2J 21 4n7
3
J
0
2
R
E
S
VLS_15V6_B
3
9
K
2
J
2
2
2
u
2
2J 18 100n
2
J
1
1
1
n
0
R
E
S
SGND1
SGND1
3J 12 13K
0.5%
VLS_15V6
SGND1
R
E
S
2
J
1
0
2
u
2 2
5
V
2
J
3
8
2
2
u
R
E
S
2
J
0
8
4
7
u
1
0
u
V
G
L
_
-6
V
2
J
0
1
4J 01-3 3 6
+VDISP
2
J
0
0
2
u
2
2 7
4J 01-1 1 8
4J 01-2
R
E
S
2
J
0
6
1
0
n
2
K
2
3
J
2
7
6J 02
1
3
5
4
2
RB550EA
RES 2J 33 820p
3
9
K
3
J
0
3
2
J
0
4
1
0
u
SS34
6J 06
6u8
5J 06
2J 20 4u7
FJ 59
4J 00-4 RES 4 5
4J 00-3 RES 3 6
FJ 56
5
6
7
8
4
1
2
3
1 8
7J 01
FDS9435A
4J 02-1
3
2
u
2
2
J
2
4
R
E
S
KTB1124-C
7J 03
1
2
2
K
2
VCC_3V3
3
J
2
0
R
E
S
VLS_15V6
2
J
1
3
4
u
7
R
E
S
SGND1
1
n
0
2
J
3
6
2
J
3
7
1
n
0
3
J
2
5
SGND1
R
E
S
1
2
K
2
5
V
4
7
u 2
J
4
9
2
u
2
2
J
4
4
4J 04-4 4 5
3.0A 32V T
1J 00 RES
1J 01
3.0A 32V T
RES
5J 08 RES
30R
5J 07 RES
30R
1
n
0
2
J
1
2
SGND1
FJ 09
R
E
S
FJ 07
3
K
3
3
J
0
4
2
J
2
3
1
0
n
FJ 05
FJ 02
FJ 03
2
J
0
7
1
0
u
3
J
0
0
RES
2
K
2
+VDISP
2
J
0
2
1
0
0
n
FJ 06
R
E
S
2
J
4
7
1
0
u
SGND1
RES
4J 05
1
0
0
n
2
J
5
0
R
E
S
2
2
u
2
J
4
2
R
E
S
1
0
u
2
J
4
3
FJ 57
FJ 58
VCC1V8
2
J
2
5
2
2
u
1
6
V
FJ 60
FJ 10
3
J
2
9
2
K
2
R
E
S
FJ 11
SGND1
FJ 00
1
2
0
p
2
J
2
7
RES
GSLOP
GSLOP
EN 62 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
P Gamma & Vcom & NVM
19130_035_110427.eps
110427
P Gamma & Vcom & NVM
T01D T01D
2010-06-29 1
3139 123 6507
PCB SB
THRILLER BRZTCON
SCL
ADR
0
1
2 SDA
WC
INPCOM|DVR_OUT
REFIN_INN
REFIN
SET
SCL
SDA
SET_COMP
V_THERM
BANKSEL
GND_HS
VIA
GND
OUT10
OUT11
OUT12
OUTCOM
INNCOM
AVDD
OUT1
OUT2
OUT3
OUT4
OUT5
INN5
OUT6
INN6
OUT7
INN7
OUT8
INN8
OUT9
VSD
SSB-TCON EEPROM
DEBUG ONLY
4K04
4K09
4K13
VCOM BUFFER
ASIC OPTIONS
J UMPER
J UMPER
J UMPER
J UMPER
J UMPER
4K02
4K03
4K01
NC
40" 32" ITEM NO.
-
-
-
-
-
10K
NC
NC
4K18
4K16
J UMPER
J UMPER
J UMPER
3K51
-
-
-
- 5K1
NC
-
NC
3K45
FK53
1
0
0
R
3
K
6
2
FK52
FK01
FK03
FK02
1
0
K
VCC_3V3
S
E
R
S
E
R
3
K
3
5
1
0
K
3
K
3
6
4
5 6
1KQB
RES
1
2
3
3
4
5
6
7
8
9
1011
502382-0470
502382-0970
RES
1
2
1KQA
1
0
K
3
K
0
8
R
E
S
7K02
PBSS5330X
PBSS4540X
7K01
FK46
FK33
FK44
FK42
FK40
VCC
VCC
1
0
K
3
K
6
1
R
E
S
3
K
6
0
1
0
K
3K56 2K0
3
K
5
2
2
K
2
VCC_3V3
8
4
7
100n
2K28
1
2
3
6
5
FK00
M24C64-WDW6
7K04
EEPROM

(8K 8)
6
K
8
FK05
3
K
4
1
FK04
R
E
S
2
K
2
3
K
0
7
FK24
FK20
FK14
FK19
FK10
VCC_3V3
3
K
1
0
1
0
K
4K05
RES 4K21
4K20 RES
FK51
4
K
0
6
-2
2
7
FK47
FK29
FK28
FK27
FK38
R
E
S
1
n
0
2
K
3
0
R
E
S
2
K
2
4
1
n
0
FK36
FK35
FK37
VCC_3V3
3
K
5
0
K
0
1
K
0
1
3
K
4
6
R
E
S
3
K
5
4
M
S
S
1
P
4
6
K
0
0
6
K
8
6
K
8
3
K
5
3
2K0 3K55
3
K
4
9
K
0
1
K
0
1
3
K
4
4
6
K
8
3
K
4
0
R
E
S
3
K
1
2
-1
1
0
R
1
8
2
7
3
6
1
0
R
3
K
1
2
-2
3
K
1
2
-3
1
0
R
FK08
FK06
4
K
0
6
-1
1
8
FK07
FK22
FK23
2
K
2
1
1
0
0
n
2
K
1
9
1
0
u
2
K
1
8
6
8
p
FK11
VCC_3V3
FK18
FK16
FK15
VLS_15V6
5
%
1
8
K
3
K
0
4
5
%
2
2
K
3
K
0
3
c
K
0
1
2
K
2
3
K
3
4
RES
4K01
4K10
4K09
2
K
0
4
VLS_15V6
RES
1
0
0
n
4
5
2
K
0
3
1
0
0
n
3
6
4
K
0
6
-4
4
K
0
6
-3
4K18
4K04
RES
R
E
S
2
K
2
6
1
n
0
R
E
S
1
n
0
2
K
2
5
4K16 RES
RES
RES 4K13
4K02
4K12
RES 4K11
1
0
K
5
4
K
3
1
5
K
3
5
K
1
0
.5
%
R
E
S
2
K
1
1
1
0
0
n
1
0
0
n
2
K
1
0
1
0
0
n
2
K
1
2
2
K
2
0
2
2
u
1
6
V
+VDISP
3
K
1
5
5
R
60
.5
%
0
.5
%
5
R
6
3
K
1
4
5% 560R
3K16
5
K
1
3
K
1
7
3
K
1
3
-2
1
0
R
2
7
0
.5
%
3
6
4
5
1
0
R
3
K
1
3
-3
3
K
1
3
-4
1
0
R
1
0
0
n
2
K
1
7
2
K
0
2
1
0
0
n
5% 3K3
3K06
1
0
0
n
2
K
0
6
2
K
0
7
1
0
0
n
1
0
0
n
2
K
0
8
3
K
1
1
-1
1
0
R
1
8
4K08
VLS_15V6
RES
4K19 RES
RES 4K07
4K22 RES
4K00
VREF_15V2
4K17 RES
4K03
4K15 RES
RES 4K14
1
u
0
2
K
0
0
2
K
0
1
1
u
0
0
.5
%
1
0
0
K
3
K
0
0
0
.5
%
6
K
2
3
K
0
1
0
.5
%
1
0
K
3
K
0
2
30
34
35
36
37
38
39
40
41
29
31
16
18
19
25
32
1
13
12
28
26
27
2
22
23
24
3
4
7
8
10
2
1
14
6
2
0
3
3
9
11
15
17
5
7K00
ISL24837IRZ-T13 5
1
0
R
3
K
1
2
-4
4
2
K
1
3
1
0
0
n
FK57
FK56
2
K
1
4
1
0
0
n
1
0
0
n
2
K
1
5
2
K
1
6
1
0
0
n
1
0
R
3
K
1
3
-1
1
8
2
7
3
6
1
0
R
3
K
1
1
-2
4
5
3
K
1
1
-3
1
0
R
1
0
R
3
K
1
1
-4
2
K
0
9
1
0
0
n
FK55
VLS_15V6
FK54
2
K
2
3
K
0
55
%
2
K
0
5
1
0
u
SDA-TCON
SCL-TCON
BYPASS_MODE
WP_TCON
WP_TCON
ROM_SCL
ROM_SDA
50Hz_60Hz
RESET
SDA-TCON
SELLVDS
R_L
U_D
OUTCOM
INNCOM
VCOM
SCL-TCON
VL127
VL31
VH31
VH159
VL95
VH63
VH247
VH95
VL95
VL63
VH63
VL127
VH127
VL247
VH127
VL31
VL159
VL127
VL63
OUTCOM
SCL-TCON
SDA-TCON
VH127
VH95
VH31
VH0
VL0
INNCOM
VH255
VL191
CS_L
VH191
Circuit Diagrams and PWB Layouts EN 63 L11M1.1L LA 10.
2011-Apr-29
MPD
19130_036_110427.eps
110427
MPD
T01E T01E
2010-06-29 1
3139 123 6507
PCB SB
THRILLER BRZTCON
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
+
REFL
REFH
7
6
5
4
3
2
1
AVDD
VIA
-
GND_HS GND
NC
OUTB
OUTA
-
INA
+
INB
IN
OUT1
ITEM NO.
3L12 47K 68K
2K2
56K
2K
82K
3L13
3L14
NC
FOR 32" / 40"
NC
NC
4L02-2
2 7
4L02-3
3 6
RES
4L02-4
4 5
RES
RES
FL13
FL12
4L00-1
1 8
4L00-2
2 7
RES
4L00-3
3 6
RES
4L00-4
4 5
RES 2
L
1
3
1
0
0
n
RES
FL08
FL07
FL06
FL05
FL04
2
L
1
1
1
0
0
n
1
0
0
n
2
L
1
0
8
3
L
0
2
-1
1
0
R
1
3
L
0
1
-3
3
6
1
0
R
2
7
1
0
R
1
8
3
L
0
1
-2
1
0
R
3
L
0
1
-1
1 8
FL15
3
6
RES
4L02-1
3
L
0
0
-3
1
0
R
1
0
R
3
L
0
0
-2
2
7
3
L
0
0
-1
1
0
R
1
8
VREF_15V2
1 8
FL14
2 7
RES
4L01-1
3 6
RES
4L01-2
4 5
RES
4L01-3
+VDISP
RES
4L01-4
0.5% 33R
3L15 3L16
33R 0.5%
3
L
1
7
1
R
0
1
0
0
n
2
L
1
6
3
L
1
2
6
2
K
FL10
FL11
FL09
FL02
FL03
FL01
2
L
0
9
1
0
0
n
1
0
0
n
2
L
0
8
4
5
3
6
1
0
R
3
L
0
2
-4
2
7
3
L
0
2
-3
1
0
R
1
0
R
3
L
0
2
-2
36
37
38
39
40
41
42
20
21
22
23
24
18
17
10
11
34
35
9
1
2
3
4
5
6
7
8
19
31
30
29
27
26
25
13
14
15
16
ISL24016IRTZ
7L00
2
8
1
2
3
3
32
1
0
0
n
2
L
0
7
2
L
0
6
1
0
0
n
1
0
0
n
2
L
0
5
1
0
R
4
5
2
L
0
4
1
0
0
n
3
L
0
1
-4
2
L
0
3
1
0
0
n
1
0
0
n
2
L
0
0
3
L
0
0
-4
4
5
FL16
1
0
R
1
n
0
2
L
1
2
3
L
1
3
1
0
K
0
.5
%
3
L
1
4
8
2
K
0
.5
%
+VDISP
NJ M2125F
7L01
1
3
4
5
2
1
6
V
2
2
u 2
L
1
5
2
L
1
4
1
0
0
n
FL00
7L02
2SC5886A
1
2
3
1
0
0
n
2
L
0
2
2
L
0
1
1
0
0
n
VCOM
ASIC_CS9
ASIC_CS11
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
CS11
CS12
CS_L
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
CS12
CS11
ASIC_CS1
ASIC_CS3
ASIC_CS5
ASIC_CS7
32" 40"
EN 64 L11M1.1L LA 10. Circuit Diagrams and PWB Layouts
2011-Apr-29
Mini LVDS
19130_037_110427.eps
110427
Mini LVDS
T01F T01F
2010-06-29 1
3139 123 6507
PCB SB
THRILLER BRZTCON
FM98
FM97
FM89
FM90
FM87
FM86
FM84
FM85
FM83
FM82
FM71
FM70
FM69
FM53
FM54
FM52
FM67
FM68
FM43
FM42
FM40
FM41
FM38
FM35
FM36
FM34
4 5
FM00
3 6
RES 4M00-4
2 7
RES 4M00-3
1 8
RES 4M00-2
RES 4M00-1
RES
2M01
100n
68R 3M10
3M09
3M07
68R
68R
3 6
68R 3M02
2 7
4M04-3
1 8
4M04-2
4 5
4M04-1
4M04-4
FM73
FM72
FM01
FM02
FM65
FM96
FM94
FM95
FM93
FM91
FM92
3M16 68R
68R 3M15 RES
RES
100n
2M02
FM81
FM79
FM80
FM78
80
9
81 82
71
72
73
74
75
76
77
78
79
8
61
62
63
64
65
66
67
68
69
7
70
51
52
53
54
55
56
57
58
59
6
60
41
42
43
44
45
46
47
48
49
5
50
32
33
34
35
36
37
38
39
4
40
23
24
25
26
27
28
29
3
30
31
13
14
15
16
17
18
19
2
20
21
22
1KA1
501559-8093
1
10
11
12
FM51
FM50
FM48
FM49
FM47
FM45
FM46
FM44
FM33
FM32
FM30
FM31
3M08 68R
68R 3M03
68R 3M01
68R 3M00
R
E
S
2
M
0
3
1
0
u
3
M
1
7
2
0
R
68R 3M14
3M13 68R
4 5
RES
3 6
RES 4M13-4
4M13-2 2 7
RES 4M13-3
4M13-1 1 8
RES
FM77
RES
FM76
FM75
FM74
FM06
FM04
FM05
FM03
77
78
79
8
80
9
81 82
VGH_35V
68
69
7
70
71
72
73
74
75
76
58
59
6
60
61
62
63
64
65
66
67
48
49
5
50
51
52
53
54
55
56
57
39
4
40
41
42
43
44
45
46
47
3
30
31
32
33
34
35
36
37
38
2
20
21
22
23
24
25
26
27
28
29
1
10
11
12
13
14
15
16
17
18
19
1KA2
501559-8093
VCC_3V3
VLS_15V6
VGH_35V
VGL_-6V
2
0
R
3
M
1
8
R
E
S
1
0
u
2
M
0
4
4M11
4 5
3 6
4M08-4
2 7
4M08-3
1 8
4M08-2
4M08-1
VGL_-6V
VCC_3V3
VLS_15V6
LLV7+
LLV7-
LS
GSP1
GSP2
LDIO2
R_L
LDIO1
LLV6+
LLV6-
CS5
CS4
VL95
CS3
CS2
CS1
U_D
GOE
GCK
GSP1
GSP2
VL63
VL31
VH191
VH247
VH255
VL127
VCOM
CS12
CS11
CS10
CS9
CS8
CS7
CS6
LCK-
LCK+
VL159
VH0
VH31
VH63
VH95
VH127
VH159
VL247
REV
LLV0-
LLV0+
LLV1-
LLV2-
VL191
LLV2+
VL0
GSP2
LLV1+
LLV3-
LLV3+
LLV4-
LLV4+
LLV5-
LLV5+
LS
GSP1
RLV7+
RLV7-
RLV6+
RLV6-
RDIO2
R_L
RDIO1
CS6
CS5
CS4
VL95
CS3
CS2
CS1
U_D_INV
GOE
GCK
GSP1
GSP2
VL63
VL31
VH95
VH127
VH159
VH191
VH247
VH255
VL127
VCOM
CS12
CS11
CS10
CS9
CS8
CS7
REV
VL191
VL159
VH0
VH31
VH63
RCK+
RLV3-
RLV3+
RLV4-
RLV4+
RLV5-
RLV5+
VL247
VL0
RLV0-
RLV0+
RLV1-
RLV1+
RLV2-
RLV2+
RCK-
Circuit Diagrams and PWB Layouts EN 65 L11M1.1L LA 10.
2011-Apr-29
10-10 313912365071 TCON Layout
Overview top/bottom side
19130_042_110428.eps
110428
2011-04-28 1
3139 123 6506
TCON THRILLER
1X02 1X01
1H00
1J 00
1J 01
1KA1 1KA2
1
K
Q
A
1
K
Q
B
1N01
2H40
2H41
2H54
2J 00 2
J
0
1
2J02
2J 03
2
J
0
4
2
J
0
5
2J 06
2J 07
2J 08
2J 09
2J 10
2J 11 2J 12
2J 13
2J 14
2J 15
2
J1
6
2J 17
2J 18
2J19
2
J2
0
2J21
2
J2
2
2
J2
3
2
J2
4
2
J
2
5
2J26
2J27
2J 28
2J29
2J 30
2J 31
2J 32
2J33
2J 34
2J 35
2J36
2J37
2J 38
2J 39
2J 40
2
J
4
1
2
J
4
2
2J 43 2
J4
4
2J 47
2J 49
2J 50
2
J
5
1
2
J
5
2
2K00
2K01
2K02
2K03
2K04
2K05
2K06
2K07
2K08
2K09
2K10
2K11
2K12
2K13
2K14
2K15
2K16
2K17
2K18
2
K
1
9
2K20
2K21
2K26
2K28
2K30
2M
01
2M
02
2M03
2N01
2N02
2N03
3H01
3
H
0
2
3H05
3H07 3H08
3H09 3H10
3H11
3H12 3H13
3H14
3H15 3H16
3H17 3H18
3H21
3H22 3H23
3J00
3J01
3J 02
3J 03 3J 04
3J 05
3J063J 07
3J08
3J09
3J 10
3J 11
3J 12
3
J1
3
3J 14
3J15
3J16
3J17
3J 18
3J19
3
J2
0
3J 21
3J 22
3
J
2
3
3J24
3J25
3J 26
3J 27
3J 28
3J 29
3K00
3K01
3K02
3K03
3K04
3K05
3K06
3K07
3K08
3K10
3K11
3K12
3K13
3K14 3K15
3K16
3K17
3K34
3K35
3K36
3K40
3K41
3K46
3K50
3K52 3K53
3K54
3K55
3K56
3K60
3K61
3K62
3M13
3M14
4H05
4J00
4J01
4J02
4
J0
3
4J04
4J05
4K00
4K01
4K02
4K04 4K05
4K06
4K07
4K08
4K09
4K10
4K11
4K12
4K13
4K17
4K18
4K19
4K21
4K22
4L00
4L01
4L02
4M00 4M04 4M08 4M13
5J 00
5J 06
5J 07
5J 08
6
J
0
0
6J 01
6J 02
6J 05
6
J
0
6
6J 07
6
K
0
0
7
H
0
0
7H01
7
H
0
2
7H03
7H04
7
H
0
5
7J 00
7J 01
7J 02
7J 03 7J 04
7J 05
7K00
7
K
0
1 7K02
7
K
0
4
CK00
cK01
2H01
2H02
2H03
2H04
2H05
2H06
2H07
2H08
2H09
2H10
2H13
2H25
2H26
2H27 2H28
2H29
2H30
2H31
2H32
2H33
2H34
2H35
2H36
2H37
2H38
2H39
2H42
2H43
2H44
2H45
2H46
2H47
2H48
2H50
2H51
2H52
2H53
2K24
2K25
2L00
2L01
2L02
2L03 2L04
2L05 2L06
2L07
2
L
0
8
2
L
0
9
2
L
1
0
2
L
1
1
2L12
2
L
1
3
2
L
1
4
2L15
2
L
1
6
2M04
3H00
3H03
3H04
3H06
3H19
3H20
3H25
3H263H27
3H28
3K44
3K45
3K49
3K51
3L00
3L01
3L02
3
L
1
2
3L13
3
L
1
4
3L15
3L16
3
L
1
7
3M00
3M01
3M02
3M03
3M07
3M08
3M09
3M10
3M15
3M16
3M17
3M18
4H04
4K03 4K14
4K15 4K16
4K20
4M11
5H00
5H01
5H02 5H03
5H04
5H05
5H06
7L00
7L01
7L02
FH00
FH01
FH02 FH03
FH04
FH05
FH06
FH34
FH35
FH36
FH37
FH38
FH39
FH40
FJ 00
FJ 01
FJ 02
FJ 03
FJ 04
FJ 05
FJ 06
FJ 07
FJ 09
FJ 10
FJ 11
FJ 13
FJ14
FJ 55
FJ 56
FJ 57
FJ 58 FJ 59
FJ 60
FK00
FK01
FK02
FK03
FK04
FK05
FK06
FK07
FK08
FK10
FK11 FK14 FK15
FK16
FK18
FK19
FK20
FK22
FK23
FK24
FK27
FK28
FK29
FK33
FK35
FK36
FK37
FK38
FK40
FK42
FK44
FK46
FK47
FK51
FK52
FK53
FK54
FK55
FK56
FK57
FL00 FL01 FL02 FL03
FL04
FL05
FL06 FL07
FL08
FL09 FL10
FL11
FL12
FL13
FL14 FL15
FL16
FM00
FM01
FM02
FM03
FM04
FM05
FM06
FM30
FM31
FM32
FM33
FM34
FM35
FM36
FM38
FM40
FM41
FM42
FM43
FM44
FM45
FM46
FM47
FM48
FM49
FM50
FM51
FM52
FM53
FM54
FM65
FM67
FM68
FM69
FM70
FM71 FM72
FM73
FM74
FM75
FM76
FM77
FM78
FM79
FM80
FM81
FM82
FM83
FM84
FM85
FM86
FM87
FM89
FM90
FM91
FM92
FM93
FM94
FM95
FM96
FM97
FM98
FN01
FN05
FN06
FN07
FN08
FN09
FN10
FN11
FN12
FN13
FN14
FN15
FN16
FN17
FN18
FN19
FN20
FN21
FN22
FN23 FN24
FN25
FN26
FN27
FN28
FN29
FN31
FN32
FN33
EN 66 L11M1.1L LA 11. Styling Sheets
2011-Apr-29
11. Styling Sheets
Styling Sheet Thriller 32"
19130_039_110428.eps
110428
THRILLER 32"
Pos No. Description Remarks
0004 Front Cabinet
0012 Back Cover
0021 Side IO Bracket
0024 BottomIO Bracket
0154 Speaker Bracket
0260 Stand
1004 Display panel
1005 Power Supply Unit
1112 IR/LED
1114 Keyboard +
1150 Board SSB
5213 Loudspeaker box
8191 Mainscord 1.8m Not Displayed
8G51 Cable LVDS FFC Not Displayed
1085 Remote Control Not Displayed
0004
1004
0012
0260
0021
1150
0024
1005
1114
1112
0154
5213
Styling Sheets EN 67 L11M1.1L LA 11.
2011-Apr-29
Styling Sheet Thriller 40"
19130_046_110429.eps
110429
THRILLER 40"
Pos No. Description Remarks
0004 Front Cabinet
0012 Back Cover
0021 Side IO Bracket
0024 BottomIO Bracket
0154 Speaker Bracket
0260 Stand
1004 Display panel
1005 Power Supply Unit
1112 IR/LED
1114 Keyboard +
1150 Board SSB
1157 TCON module
5213 Loudspeaker box
8191 Mainscord 1.8m Not Displayed
8G50 Cable LVDS FFC Not Displayed
8KA1 Cable LVDS FFC Not Displayed
8KA2 Cable LVDS FFC Not Displayed
1085 Remote Control Not Displayed
0004
1004
0012
0260
0021
1150
1157
0024
1005
0154
1114
1112
5213