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INTRODUCTION
High speed smart pixel arrays (SPAs) hold great promise as an enabling
technology for board-to-board interconnections in digital systems. SPAs may be
considered an extension of a class of optoelectronic components that have existed
for over a decade, that of optoelectronic integrated circuits (OEICs). The vast
majority of development in OEICs has involved the integration of electronic
receivers with optical detectors and electronic drivers with optical sources or
modulators. In addition, very little of this development has involved more than a
single optical channel. But OEICs have underpinned much of the advancement in
serial fiber links. SPAs encompass an extension of these optoelectronic
components into arrays in which each element of the array has a signal
processing capability. Thus, a SPA may be described as an array of
optoelectronic circuits for which each circuit possesses the property of signal
processing and, at a minimum, optical input or optical output (most SPAs will
have both optical input and output).
Figure 1
employing free-space optical beams connecting SPAs located on the ends of
printed circuit boards in place of the current state-of-the-art, multi-level electrical
interconnected boards. 3-D systems, on the other hand, are distributed board-to-
board optical interconnects, exploiting the third dimension and possibly
employing holographic interconnect elements to achieve global connectivity
(very difficult with electrical interconnects).
Most work in high speed SPAs has involved the use of either multiple-
quantum-well (MQW) modulators or vertical-cavity surface-emitting lasers
(VCSELs) as the optical source, and each of these has taken one of two
approaches, monolithic and hybrid (e.g., monolithic VCSELs/GaAs and hybrid
Figure 2
The conventional way of doing this is to bond both to the base substrate
with their device sides up and then to electrically connect them by wire bonding
both chips to the microstrips and their associated bonding pads on the base
substrate. For large array sizes, an unrealistic amount of space on the chips and
on the base substrate will be devoted to bonding pads, and the length of the
electrical connections between the chips will defeat much, if not all, of the
advantage of the optical interconnects. Borrowing a technique from the emerging
technology of multi-chip module (MCM) fabrication, the chips can be placed
device-side down (called flip-chip) and bump bonded to the carrier. Bump
bonding has the distinct advantage that chip connections can be made anywhere
on the surface of the chip rather than being confined to the chip's periphery as is
the case for wire bonding. This most often leads to a shortening of interconnect
lengths, thereby enabling higher speed operation. Furthermore, bump bonding
can establish all chip connections in parallel, thus reducing production time for
large arrays. Flip-chip bonding of the optoelectronic chip to the base substrate
leads to an important constraint on this substrate. Since the optical sources now
face the substrate, it must be transparent to permit the optical beams to pass
through to the outside of the hybrid structure.
Figure 3.
Glass is the material that can be used due to cost considerations, but the
superior thermal properties of sapphire make it very appealing from all but the
cost viewpoint. A packaged SPA based on the flip-chip bonding of both the
VCSEL array and the electronic array (containing the detectors, processing
elements and laser drivers) to a transparent base substrate is shown in figure 3. A
hole is drilled in the well of a conventional ceramic package to allow passage of
both the incoming and outgoing light beams. Note that the transparent substrate
provides a convenient base on which to mount both refractive and diffractive
optical devices. Although only shown in the path of the outgoing beams, such
beam forming and directing devices could be used in the path of the incoming
beams also (e.g., to focus the beams onto the detectors).
Figure 4.
Each PE is a 1-bit wide processor that can operate at 20 MHz and consists
of an arithmetic logic unit, a logic circuit which can perform 16 logic functions, a
full adder, a 32-bit shift-register, 6 static registers, and some control circuits.
Although the PEs are capable of general purpose processing, they were designed
SPA PACKAGING
Thermosonic flip-chip bonding to mount both the VCSEL chip and the
CMOS chip to the glass substrate. The principles of thermosonic flip-chip
bonding are the same as those for conventional ultrasonic wire bonding except
that all of the bonds must be made simultaneously. This new flip-chip technique
was developed in place of the conventional techniques used in multi-chip module
(MCM) fabrication because of the different environment that exists in working
with optoelectronic chips. For example, solder reflow involves "dirty" processes
such as solder deposition and flux during reflow, and it is very difficult to deposit
solder on a chip once it has been diced. Also, the aluminum pads usually found
on CMOS chips are incompatible with most solder technologies used in MCM
fabrication. Conductive epoxy attachment is not feasible since the conductive
particles interfere with the optical paths. Finally, thermocompression bonding
involves higher temperatures and pressures, which could possibly damage the
mechanical stress sensitive VCSEL chip. Thermosonic bonding uses ultrasonic
energy to help "soften" the bonding material, thereby achieving bonding at lower
temperature and pressure than thermo-compression bonding. For the fabrication
of our smart pixel arrays, the VCSEL chips are flip-chip bonded to the base
substrates by first plating gold bumps (30 µm diameter by 20 µm high) onto the
gold surface contact pads of the VCSEL array. These plated contacts are then
accurately positioned relative to the contacts on the substrate. The parts are then
joined by a combination of heat, normal force, and ultrasonic energy.
Since the CMOS chips are received already diced, plating the bumps is not
feasible. Gold balls are bonded to the aluminum contacts by a conventional wire
bonding process, and the wires are subsequently removed. The remainder of the
Figure 5
The figure is of one of SPAs as viewed through the hole in the ceramic
package. The small square is the 8x8 VCSEL array, and the large rectangle is the
CMOS chip (top sides of both chips visible through the glass substrate). Intra-
package electrical interconnect traces on the glass are also visible. This picture
was taken before the lenslet and hologram arrays were added.
OPTOELECTRONIC COMMUNICATION
Figure 6
Figure 7
Figure 8.
Figure 9.
OPTOMECHANICS
Figure 10.
There are three system modules that are integrated and aligned by the
optomechanics: the Fourier transform lens and the two SPAs. The lens is held
tightly by the ring and lens housing. The lens housing is screwed into the inner
cylinder at an appropriate "z" position so that the focal length of the lens falls on
to the detector plane. In a similar fashion, the outer cylinder is installed. This
assembly forms the lens module with a defined "z" position for location of the
FUTURE DIRECTIONS
The major goals will be to achieve more compact packaging and to scale
the SPAs to larger array dimensions. The former not only leads to smaller
components, but shortens electrical connections within the SPA, thereby leading
to higher potential speeds. It also supports the second goal since scaling can lead
to excessively long electrical connections within the SPA for the current
packaging methodology.
Future development will enable tighter coupling between the VCSEL and
the Si chips than is possible with the transparent substrate scheme currently used.
If the VCSEL chip is made to emit light in the opposite direction (i.e., in the
direction of its substrate), it becomes possible to flip-chip this chip directly onto
the Si chip, thereby minimizing the length of the electrical connections between
the processing elements and the VCSELs (the two device surfaces are now facing
one another). This is necessary if large-dimension high-speed (GHz) SPAs are to
be realized. Since high-speed operation also necessitates a higher performance
Figure 11.
The flip-chip bonding of two separate chips onto the CMOS chip still
leads to the separation of devices within each pixel. The ultimate goal is to co-
locate the VCSEL, photodetector, and logic circuitry for each pixel. This can be
accomplished by integrating each VCSEL with a photodetector and providing a
bonding pad for each. An array of these integrated VCSELs and photodetectors is
then flip-chip bonded on to the CMOS chip as shown below such that the
circuitry associated with each VCSEL/detector pair is located directly beneath the
pair on the CMOS chip.
Figure 12.
The optical input, optical output, and pixel circuitry are in a single
location, thereby minimizing the electrical connections between the three. Future
smart pixel array development should consider one other aspect of integration,
that of integrating the lenslet arrays, either with the glass substrate (original
scheme) or with the GaAs substrate (future scheme). At present, commercial
lenslet arrays are used which are poorly matched to the VCSEL beam profiles
and which are difficult to align. Smaller alignment errors will allow smaller
photodetectors, resulting in faster systems.
CONCLUSIONS
BIBLIOGRAPHY
2. www.sandialabs.gov
3. www.Lightreading.com
4. www.Colorado.edu
5. http://physics.montana.edu
6. www.optoelectronics.com
CONTENTS
1. INTRODUCTION 1
6. OPTOELECTRONIC COMMUNICATION 10
7. OPTOMECHANICS 13
8. FUTURE DIRECTIONS 15
9. CONCLUSIONS 19
10. BIBLIOGRAPHY 20
ACKNOWLEDGEMENT
ABSTRACT