MALLA REDDY ENGINEERI Maisammaguda, Dhulapally, (post via Hakimpet)
Department Of Electronics and Communication Engineering
OBSERVATIONAL RECORD For SIMULATION LAB
ECE I M.Tech - I Sem
Designed by B.SRINIVAS Asst. Prof., ECE Dept.
MALLA REDDY ENGINEERINGCOLLEGE (Autonomous) Maisammaguda, Dhulapally, (post via Hakimpet) Secunderabad-500014.AP.
NOVEMBER - 2011 Department Of Electronics and Communication OBSERVATIONAL RECORD Asst. Prof., ECE Dept. NGCOLLEGE Maisammaguda, Dhulapally, (post via Hakimpet)
Simulation Lab Dept of ECE MREC
MALLA REDDY ENGINEERING COLLEGE MAISAMMAGUDA, DHULAPALLY, SECUNDERABAD-500014
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
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Simulation Lab Dept of ECE MREC
SIMULATION LAB
S.No. LIST OF EXPERIMENTS Page No 1 Logic gates 1-5 2 A Half adder 6-9 B Full adder 10-15 C Serial adder behavioral model 16-20 D Parallel adder structural model 21-24 E Carry look ahead adder 25-30 3 A 2 x 4 decoder dataflow model 31-34 B 3 x 8 decoder behavioral model 35-37 C 4 x 16 decoder structural model 38-41 D 4:1 multiplexer dataflow & behavior model 42-45 E 16:1 multiplexer structural model 46-49 F 8 x 3 Priority encoder structural model 50-56 4 A JK Flip Flop 57-62 B RS Flip Flop 63-66 C D Flip Flop 67-70 D T Flip Flop 71-74 5 A Ring Counter 75-78 B Johnson Counter 79-83 C Up- Down Counter 84-89 6 A N- bit Register of Serial- in Serial out 90-93 B N- bit Register of Serial in parallel out 94-97 C N- bit Register of Parallel in Serial out 98-102 D N- bit Register of Parallel in Parallel Out 103-107 7 A FSM Melay machine 108-112 B FSM Moore machine 113-117 8 A 4 bit multiplier 118-125 9 ALU 126-132 10 Real time clock 133-140
Exp. No : 1 Logic gates 1
Simulation Lab Dept of ECE MREC
AIM: To design all logic gates using dataflow model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.2d Xilinx ISE 9.2 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
NOT GATE:
AND GATE: OR GATE:
Exp. No : 1 Logic gates 2
Simulation Lab Dept of ECE MREC
NAND GATE: NOR GATE:
XOR GATE: XNOR GATE:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model
Exp. No : 1 Logic gates 3
Simulation Lab Dept of ECE MREC
PROGRAM: module allgates(A, B, not1, or2, and3, nor4, nand5, xor6, xnor7); input A; input B; output not1; output or2; output and3; output nor4; output nand5; output xor6; output xnor7; reg not1; reg or2; reg and3; reg nor4; reg nand5; reg xor6; reg xnor7; always@(A or B) begin not1 = ~ A; or2 = A | B; and3 = A & B; nor4 = ~ (A | B); nand5 = ~ (A & B); xor6 = (A ^ B); xnor7 = ~ (A ^ B); end endmodule
RTL SCHEMATIC DIAGRAM:
Exp. No : 1 Logic gates 4
Simulation Lab Dept of ECE MREC
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "p74" ; NET "b" LOC = "p76" ; NET "c_and" LOC = "p84" ; NET "d_or" LOC = "p85" ; NET "e_not" LOC = "p86" ; NET "f_nand" LOC = "p87" ; NET "g_nor" LOC = "p89" ; NET "h_xor" LOC = "p90" ; NET "i_xnor" LOC = "p92" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
RESULT: All logic gates using dataflow model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 1 Logic gates 5
Simulation Lab Dept of ECE MREC
Exp. No : 2a Half adder 6
Simulation Lab Dept of ECE MREC
AIM: To design half adder using dataflow,structural & behavioural model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.2 d Xilinx ISE 9.2i FPGA device (Family: Spartan3, Device: XC3S400, Package: TQ144) CIRCUIT DIAGRAM:
TRUTH TABLE: A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
BOOLEAN EXPRESSIONS: S = a b b C = a . b PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG + Exp. No : 2a Half adder 7
Simulation Lab Dept of ECE MREC
Download program into kit Verify the function of design model
PROGRAM(data flow model): module halfadder(a, b, sum, carry); input a; input b; output sum; output carry; reg sum,carry; always@(a or b) begin sum=a^b; carry=a&b; end endmodule
PROGRAM(behavioural model): module halfadder(a, b, sum, carry); input a; input b; output sum; output carry; reg sum,carry; always@(a or b) begin sum=a^b; carry=a&b; end endmodule
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "p74" ; NET "b" LOC = "p76" ; NET "c" LOC = "p84" ; NET "s" LOC = "p85" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
RESULT: Half adder using three models of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 2a Half adder 9
Simulation Lab Dept of ECE MREC
Exp. No : 2b Full adder (dataflow model) 10
Simulation Lab Dept of ECE MREC
AIM: To design full adder using dataflow model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.2 d Xilinx ISE 9.2i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
BOOLEAN EXPRESSIONS: S um= ain bin cin C = ain . bin + bin . cin + cin. ain
PROCEDURE:
Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model
PROGRAM(behavioural model): module fulladder(a, b, cin, sum, cout); input a; input b; input cin; output sum; output cout; reg sum,cout; always@(a or b or cin) begin sum=a^b^cin; cout=(a&b)|(b&cin)|(cin&a); end endmodule
+ + Exp. No : 2b Full adder (dataflow model) 12
Simulation Lab Dept of ECE MREC
PROGRAM(structural model): Module fa(a,b,cin,sum,cout) Input a,b,cin; Output sum,cout; Wire s1,t1,t2,t3; Xor X1(s1,a,b); X2(sum,s1,cin); And A1(t1,a,b), A2(t2,b,cin), A3(t3,cin,a); Or 01(cout,t1,t2,t3); Endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "ain" LOC = "p74" ; NET "bin" LOC = "p76" ; NET "cin" LOC = "p77" ; NET "cout" LOC = "p84" ; NET "sum" LOC = "p86" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
Full adder using dataflow model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 2b Full adder (dataflow model) 14
Simulation Lab Dept of ECE MREC
Exp. No : 2b Full adder (dataflow model) 15
Simulation Lab Dept of ECE MREC
Excersice: Simulate & synthesis half subtractor & Full subtractor using verilog
Exp. No : 2c Serial Adder 16 Simulation Lab Dept of ECE MREC
AIM: To design serial adder using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
CIRCUIT DIAGRAM:
PROCEDURE: Check syntax. View RTL schematic. View Technology schematic. Perform simulation. Exp. No : 2c Serial Adder 17 Simulation Lab Dept of ECE MREC
Write ucf file. Implement design. View the synthesis report. Configure target device using iMPACT. Initialize JTAG. Download program into kit. Verify the function of design model.
Verilog code for serial adder: module serial_adder(clk,addr,load,clear,data_in,calc,result); input clk,clear,calc,load; input [2:0]addr;input [11:0]data_in; output reg [11:0]result; reg [11:0]ram[7:0]; reg [11:0]temp; always@(negedge clk) begin if(clk)temp = ram[0] + ram[1]; temp = (temp + ram[2]); temp = (temp + ram[3]); temp = (temp + ram[4]); temp = (temp + ram[5]); temp = (temp + ram[6]); temp = (temp + ram[7]); end always@(posedge clk) begin if(~clear) begin ram[0]=12'b0; ram[1]=12'b0; ram[2]=12'b0; ram[3]=12'b0; ram[4]=12'b0; ram[5]=12'b0; ram[6]=12'b0; ram[7]=12'b0; end else if(~load) begin result=data_in; ram[addr] = data_in; end else if(~calc) result = temp; else result = ram[addr]; end endmodule
Exp. No : 2c Serial Adder 18 Simulation Lab Dept of ECE MREC
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a_i" LOC = "p84" ; NET "b_i" LOC = "p86" ; NET "c_i" LOC = "p87" ; NET "c_o" LOC = "p89" ; NET "CLK" LOC = "p74" ; NET "I<0>" LOC = "p76" ; NET "I<10>" LOC = "p102" ; Exp. No : 2c Serial Adder 19 Simulation Lab Dept of ECE MREC
NET "I<11>" LOC = "p103" ; NET "I<12>" LOC = "p104" ; NET "I<13>" LOC = "p105" ; NET "I<14>" LOC = "p107" ; NET "I<15>" LOC = "p108" ; NET "I<1>" LOC = "p77" ; NET "I<2>" LOC = "p78" ; NET "I<3>" LOC = "p79" ; NET "I<4>" LOC = "p80" ; NET "I<5>" LOC = "p82" ; NET "I<6>" LOC = "p83" ; NET "I<7>" LOC = "p98" ; NET "I<8>" LOC = "p99" ; NET "I<9>" LOC = "p100" ; NET "Load" LOC = "p112" ; NET "O<0>" LOC = "p90" ; NET "O<1>" LOC = "p92" ; NET "O<2>" LOC = "p93" ; NET "O<3>" LOC = "p95" ; NET "O<4>" LOC = "p96" ; NET "O<5>" LOC = "p97" ; NET "O<6>" LOC = "p113" ; NET "O<7>" LOC = "p116" ; NET "s_o" LOC = "p118" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary (estimated values)
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT: Serial adder using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
Exp. No : 2c Serial Adder 20 Simulation Lab Dept of ECE MREC
Exp. No : 2d PARALLEL ADDER 21
Simulation Lab Dept of ECE MREC
AIM: To design parallel adder using structural model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
STRUCTURAL MODEL DIAGRAM:
BOOLEAN EXPRESSIONS FOR FULL ADDER: S um= ain bin cin C = ain . bin + bin . cin + cin. ain
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model + + Exp. No : 2d PARALLEL ADDER 22
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a<0>" LOC = "p74" ; NET "a<1>" LOC = "p76" ; NET "a<2>" LOC = "p77" ; NET "a<3>" LOC = "p78" ; NET "b<0>" LOC = "p79" ; NET "b<1>" LOC = "p80" ; NET "b<2>" LOC = "p82" ; NET "b<3>" LOC = "p83" ; NET "ci" LOC = "p98" ; NET "co" LOC = "p84" ; Exp. No : 2d PARALLEL ADDER 23
Simulation Lab Dept of ECE MREC
NET "s<0>" LOC = "p86" ; NET "s<1>" LOC = "p87" ; NET "s<2>" LOC = "p89" ; NET "s<3>" LOC = "p90" ;
#PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT:
Parallel adder using structural model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 2d PARALLEL ADDER 24
Simulation Lab Dept of ECE MREC
Exp. No : 2e Carry Look Ahead Adder 25
Simulation Lab Dept of ECE MREC
AIM: To design carry look ahead adder using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) CIRCUIT DIAGRAM:
BOOLEAN EXPRESSIONS: Pi = Ai Bi Carry propagate Gi = AiBi Carry generate Si = Pi Ci-1 Ci+1= Gi + PiCi
PROCEDURE: Check syntax View RTL schematic Exp. No : 2e Carry Look Ahead Adder 26
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a<0>" LOC = "p74" ; NET "a<1>" LOC = "p76" ; NET "a<2>" LOC = "p77" ; NET "a<3>" LOC = "p78" ; NET "b<0>" LOC = "p79" ; NET "b<1>" LOC = "p80" ; NET "b<2>" LOC = "p82" ; NET "b<3>" LOC = "p83" ; NET "ci" LOC = "p98" ; NET "co" LOC = "p84" ; NET "sum<0>" LOC = "p86" ; NET "sum<1>" LOC = "p89" ; NET "sum<2>" LOC = "p90" ; NET "sum<3>" LOC = "p92" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
Exp. No : 2e Carry Look Ahead Adder 28
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT: Carry look ahead adder using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 2e Carry Look Ahead Adder 29
Simulation Lab Dept of ECE MREC
EXERCISE: Simulate & synthesis Multi Precession Adder using verilog.
Exp. No : 2e Carry Look Ahead Adder 30
Simulation Lab Dept of ECE MREC
Exp. No : 3a 2x4 Decoder (data flow model) 31
Simulation Lab Dept of ECE MREC
AIM: To design 2 x 4 decoder using dataflow model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
BOOLEAN EXPRESSIONS: Z(0) = ) 0 ( . ) 1 ( . 1 A A EN Z(1) = ) 0 ( ). 1 ( . 1 A A EN Exp. No : 3a 2x4 Decoder (data flow model) 32
Simulation Lab Dept of ECE MREC
Z(2) = ) 0 ( ). 1 ( . 1 A A EN Z(3) = ) 0 ( ). 1 ( . 1 A A EN
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a<0>" LOC = "p74" ; NET "a<1>" LOC = "p76" ; NET "en1" LOC = "p77" ; NET "z<0>" LOC = "p84" ; Exp. No : 3a 2x4 Decoder (data flow model) 33
Simulation Lab Dept of ECE MREC
NET "z<1>" LOC = "p86" ; NET "z<2>" LOC = "p87" ; NET "z<3>" LOC = "p89" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT: 2 x 4 Decoder using dataflow model of VerilogHDL program is designed and simulation, synthesis, place & route an d implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 3a 2x4 Decoder (data flow model) 34
Simulation Lab Dept of ECE MREC
Exp. No : 3b 3x8 decoder (Behavioral model) 35
Simulation Lab Dept of ECE MREC
AIM: To design 3 x 8 decoder using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model PROGRAM: module decoder(a, en, y); input[2:0] a; input en; output[7:0] y; reg[7:0] y; always@(en or a) begin if(!en) y= 4'b0000; else case(a) 3'b000 : y = 8'b00000001; 3'b001 : y = 8'b00000010; 3'b010 : y = 8'b00000100; 3'b011 : y = 8'b00001000; 3'b100 : y = 8'b00010000; 3'b101 : y = 8'b00100000; 3'b110 : y = 8'b01000000; 3'b111 : y = 8'b10000000; default :y = 8'b00000000; endcase end endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "A<0>" LOC = "p74" ; Exp. No : 3b 3x8 decoder (Behavioral model) 37
Simulation Lab Dept of ECE MREC
NET "A<1>" LOC = "p76" ; NET "A<2>" LOC = "p77" ; NET "G1" LOC = "p78" ; NET "G2a_l" LOC = "p79" ; NET "G2b_l" LOC = "p80" ; NET "Y<0>" LOC = "p84" ; NET "Y<1>" LOC = "p86" ; NET "Y<2>" LOC = "p87" ; NET "Y<3>" LOC = "p89" ; NET "Y<4>" LOC = "p90" ; NET "Y<5>" LOC = "p92" ; NET "Y<6>" LOC = "p93" ; NET "Y<7>" LOC = "p96" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT: 3 x 8 decoder using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 3c 4x16 decoder (Structural model) 38
Simulation Lab Dept of ECE MREC
AIM: To design 4 x 16 decoder using structural model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) TRUTH TABLE:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design mode. Exp. No : 3c 4x16 decoder (Structural model) 39
Simulation Lab Dept of ECE MREC
PROGRAM: module mux_16to1(y,in,en); input [15:0] in; input [3:0] sel; wire lo8,hi8,out1; // Instantiate the 8-1 muxex and the 2-1 mux Mux_8to1 mux_lo(lo8,in[7:0],sel[2:0]); Mux_8to1 mux_hi(hi8,in[15:8],sel[2:0]); Mux_2to1 mux_out(out1,lo8,hi8,sel[3]); Assign y=out1; End module
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "d<0>" LOC = "p74" ; NET "d<10>" LOC = "p87" ; NET "d<11>" LOC = "p89" ; NET "d<12>" LOC = "p90" ; NET "d<13>" LOC = "p92" ; NET "d<14>" LOC = "p93" ; NET "d<15>" LOC = "p95" ; NET "d<1>" LOC = "p76" ; NET "d<2>" LOC = "p77" ; NET "d<3>" LOC = "p78" ; NET "d<4>" LOC = "p79" ; NET "d<5>" LOC = "p80" ; NET "d<6>" LOC = "p82" ; Exp. No : 3c 4x16 decoder (Structural model) 40
Simulation Lab Dept of ECE MREC
NET "d<7>" LOC = "p83" ; NET "d<8>" LOC = "p84" ; NET "d<9>" LOC = "p86" ; NET "en" LOC = "p96" ; NET "s<0>" LOC = "p97" ; NET "s<1>" LOC = "p98" ; NET "s<2>" LOC = "p99" ; NET "s<3>" LOC = "p100" ; NET "y" LOC = "p102" ; NET "yn" LOC = "p103" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT: 4 x 16 decoder using structural model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 3c 4x16 decoder (Structural model) 41
Simulation Lab Dept of ECE MREC
Exp. No : 3d 4:1 Multiplexer (dataflow & behavioural model) 42
Simulation Lab Dept of ECE MREC
AIM: To design 4 : 1 Multiplexer using dataflow & behavioural model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) TRUTH TABLE:
S1 S0 Y 0 0 I(0) 0 1 I(1) 1 0 I(2) 1 1 I(3)
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model
Exp. No : 3d 4:1 Multiplexer (dataflow & behavioural model) 43
Simulation Lab Dept of ECE MREC
PROGRAM(BEHAVIOURAL MODEL): module mux(en, a, y,sel); input en; input [3:0] a; input[1:0] sel; output y; reg y; always@(en or a) begin if(!en) y=1'b0; else case(sel) 2'b00 : y = a[3]; 2'b01 : y = a[2]; 2'b10 : y = a[1]; 2'b11 : y = a[0]; Endcase end endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "i<0>" LOC = "P74" ; NET "i<1>" LOC = "P76" ; NET "s" LOC = "P77" ; NET "y" LOC = "P86" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
Exp. No : 3d 4:1 Multiplexer (dataflow & behavioural model) 44
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT:
Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT: 4 : 1 Multiplexer using dataflow & behavioural model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 3d 4:1 Multiplexer (dataflow & behavioural model) 45
Simulation Lab Dept of ECE MREC
Exp. No : 3e 16x1 Multiplexer (Structural model) 46
Simulation Lab Dept of ECE MREC
AIM: To design a 16x1 Multiplexer using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
TRUTH TABLE:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model
Exp. No : 3e 16x1 Multiplexer (Structural model) 47
Simulation Lab Dept of ECE MREC
PROGRAM: module mux_16to1(y,in,en); input [15:0] in; input [3:0] sel; wire lo8,hi8,out1; // Instantiate the 8-1 muxex and the 2-1 mux Mux_8to1 mux_lo(lo8,in[7:0],sel[2:0]); Mux_8to1 mux_hi(hi8,in[15:8],sel[2:0]); Mux_2to1 mux_out(out1,lo8,hi8,sel[3]); Assign y=out1; End module
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "en8" LOC = "p74" ; NET "i<0>" LOC = "p76" ; NET "i<1>" LOC = "p78" ; NET "i<2>" LOC = "p79" ; NET "i<3>" LOC = "p80" ; NET "i<4>" LOC = "p82" ; NET "i<5>" LOC = "p83" ; NET "i<6>" LOC = "p77" ; Exp. No : 3e 16x1 Multiplexer (Structural model) 48
Simulation Lab Dept of ECE MREC
NET "i<7>" LOC = "p100" ; NET "s3<0>" LOC = "p102" ; NET "s3<1>" LOC = "p103" ; NET "s3<2>" LOC = "p104" ; NET "y8" LOC = "p85" ; NET "y8l" LOC = "p86" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT:
A 16x1 Multiplexer using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Exp. No : 3e 16x1 Multiplexer (Structural model) 49
Simulation Lab Dept of ECE MREC
Expt. No: 3f 8-BIT PRIORITY ENODER 50
Simulation Lab Dept of ECE MREC
AIM: To design an 8-Bit Priority Encoder using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) TRUTH TABLE:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAGDownload program into kit Verify the function of design model
USER CONSTRAINTS FILE: #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "A_L<0>" LOC = "P85" ; NET "A_L<1>" LOC = "P86" ; NET "A_L<2>" LOC = "P87" ; NET "E0_L" LOC = "P89" ; NET "EI_L" LOC = "P74" ; NET "GS_L" LOC = "P90" ; NET "I_L<0>" LOC = "P76" ; NET "I_L<1>" LOC = "P77" ; Expt. No: 3f 8-BIT PRIORITY ENODER 52
Simulation Lab Dept of ECE MREC
NET "I_L<2>" LOC = "P78" ; NET "I_L<3>" LOC = "P79" ; NET "I_L<4>" LOC = "P80" ; NET "I_L<5>" LOC = "P82" ; NET "I_L<6>" LOC = "P83" ; NET "I_L<7>" LOC = "P84" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
RESULT: An 8-Bit Priority Encoder using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt. No: 3f 8-BIT PRIORITY ENODER 53
Simulation Lab Dept of ECE MREC
Expt. No: 3f 8-BIT PRIORITY ENODER 54
Simulation Lab Dept of ECE MREC
EXERSICE: Simulate and synthesis 8X 1 demux using verilog HDL in Three modeling styles. Simulate and synthesis ENCODER using verilog HDL in Three modeling styles.
Expt. No: 3f 8-BIT PRIORITY ENODER 55
Simulation Lab Dept of ECE MREC
Expt. No: 3f 8-BIT PRIORITY ENODER 56
Simulation Lab Dept of ECE MREC
Expt.No:4a JK-FlipFlop 57
Simulation Lab Dept of ECE MREC
AIM: To design JK-flipflop with asynchronous reset using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
BLOCK DIAGRAM:
TRUTH TABLE:
PROCEDURE:
Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using IMPACT Initialize JTAG Download program into kit Verify the function of design model Expt.No:4a JK-FlipFlop 58
Simulation Lab Dept of ECE MREC
PROGRAM: module JK_FF (JK, clock, q, qb); input [1:0] JK; input clock; output reg q, qb; always @ (posedge clock) begin case (JK) 2'b00 : q = q; 2'b01 : q = 1'b0; 2'b10 : q = 1'b1; 2'b11 : q =~ q; endcase qb =~ q; end endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE: #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p74" ; NET "j" LOC = "p76" ; NET "k" LOC = "p78" ; NET "q" LOC = "p79" ; NET "qn" LOC = "p85" ; NET "reset" LOC = "p80" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
RESULT: JK-flipflop with asynchronous reset using behavioral model of VHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:4a JK-FlipFlop 60
Simulation Lab Dept of ECE MREC
Expt.No:4a JK-FlipFlop 61
Simulation Lab Dept of ECE MREC
EXERSICE: Simulate and synthesis MASTER SLAVE JK FF using VerillogHDL .
Expt.No:4a JK-FlipFlop 62
Simulation Lab Dept of ECE MREC
Expt no: 4b SR-FlipFlop 63
Simulation Lab Dept of ECE MREC
AIM: To design RS-flipflop with using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
BLOCK DIAGRAM:
TRUTH TABLE:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using IMPACT Initialize JTAG Download program into kit Verify the function of design mode Expt no: 4b SR-FlipFlop 64
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p74" ; NET "j" LOC = "p76" ; NET "k" LOC = "p78" ; NET "q" LOC = "p79" ; NET "qn" LOC = "p85" ; NET "reset" LOC = "p80" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
RESULT: An Asynchronous RS-flipflop using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt no: 4b SR-FlipFlop 66
Simulation Lab Dept of ECE MREC
Expt.No:4c D-FlipFlop 67
Simulation Lab Dept of ECE MREC
AIM: To design a D-flipflop with Asynchronous reset using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
BLOCK DIAGRAM:
TRUTH TABLE:
PROCEDURE:
Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using IMPACT Initialize JTAG Download program into kit Expt.No:4c D-FlipFlop 68
Simulation Lab Dept of ECE MREC
Verify the function of design model PROGRAM: module dff (reset, clock, d, q, qb); input reset, clock, d; output q, qb; reg q; wire qb; always @ (posedge clock) begin if (reset) q<=1'b0; else q<=d; end assign qb=~q; endmodule
RTL SCHEMATIC DIAGRAM:
Expt.No:4c D-FlipFlop 69
Simulation Lab Dept of ECE MREC
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p74" ; NET "D" LOC = "p76" ; NET "q" LOC = "p77" ; NET "qbar" LOC = "p78" ; NET "rst" LOC = "p79" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
RESULT:
A D-flipflop with Asynchronous reset using behavioral model of VHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:4c D-FlipFlop 70
Simulation Lab Dept of ECE MREC
Expt.No:4d T-FlipFlop 71
Simulation Lab Dept of ECE MREC
AIM: To design a T-Flip Flop with Synchronous reset using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
BLOCK DIAGRAM:
TRUTH TABLE:
PROCEDURE:
Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model
Expt.No:4d T-FlipFlop 72
Simulation Lab Dept of ECE MREC
PROGRAM: module t_ff (clock, reset, T, q); input clock, reset, T; output reg q; always @ (posedge clock) begin if(reset) q<=1'b0; else if (T) q<=~q; else q<=q; end endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE: #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p74" ; NET "q" LOC = "p76" ; NET "qout" LOC = "p77" ; NET "rst" LOC = "p78" ; NET "t" LOC = "p79" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
Expt.No:4d T-FlipFlop 73
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
RESULT: A T-Flip Flop with Synchronous reset using behavioral model of VHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:4d T-FlipFlop 74
Simulation Lab Dept of ECE MREC
Expt.No:5a Ring Counter 75
Simulation Lab Dept of ECE MREC
AIM: To design a Ring Counter using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) BLOCK DIAGRAM:
Configure target device using IMPACT Initialize JTAG Download program into kit Verify the function of design model PROGRAM: Module ring_counter(count,enable,clk,reset); Output [7:0] count; Input enable,reset,clk;reg count; Always @(posedge reser or clk) If(reset==1b1) Count<=8b00000001; Else if(enable==1b1) Count<={count[6:0],count[7]}; End module
RTL SCHEMATIC DIAGRAM:
Expt.No:5a Ring Counter 77
Simulation Lab Dept of ECE MREC
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p74" ; NET "q<0>" LOC = "p85" ; NET "q<1>" LOC = "p86" ; NET "q<2>" LOC = "p87" ; NET "q<3>" LOC = "p89" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
RESULT:
A Ring Counter using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:5a Ring Counter 78
Simulation Lab Dept of ECE MREC
Expt.No:5b Johnson Counter 79
Simulation Lab Dept of ECE MREC
AIM: To design a Johnson Counter using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) LOGIC DIAGRAM:
TRUTH TABLE: Expt.No:5b Johnson Counter 80
Simulation Lab Dept of ECE MREC
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using IMPACT Initialize JTAG Download program into kit Verify the function of design model
Always @(posedge clk) Begin Reg run, dir; If (goright ==0)) begin Dir=1b0; Run=1; End If (goleft ==0)) begin Dir=1b1; Run=1; End If (stop ==0)) begin Run=0; End If (run) begin Casez (dir) 1b1:begin G[3:1]<=q[2:0]; G[0]<=(!q[3]); End Default:begin G[2:0]<=q[3:1]; G[3]<=(!q[0]); End Endcase End End Endmodule
Expt.No:5b Johnson Counter 81
Simulation Lab Dept of ECE MREC
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "P74" ; NET "q<0>" LOC = "P76" ; NET "q<1>" LOC = "P85" ; NET "q<2>" LOC = "P86" ; NET "q<3>" LOC = "P89" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
Expt.No:5b Johnson Counter 82
Simulation Lab Dept of ECE MREC
RESULT: A Johnson Counter using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:5b Johnson Counter 83
Simulation Lab Dept of ECE MREC
Expt.No:5c UpDown Counter 84
Simulation Lab Dept of ECE MREC
AIM: To design an updown Counter using behavioral model of VerilogHDL program and to erform simulation, synthesis, place & route and implementation of the design using FPGA device.
Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p74" ; NET "cout<0>" LOC = "p76" ; NET "cout<1>" LOC = "p77" ; NET "cout<2>" LOC = "p78" ; NET "cout<3>" LOC = "p79" ; NET "cout<4>" LOC = "p80" ; NET "cout<5>" LOC = "p82" ; NET "cout<6>" LOC = "p83" ; NET "cout<7>" LOC = "p84" ; NET "rstn" LOC = "p86" ; NET "ud" LOC = "p87" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE Expt.No:5c UpDown Counter 86
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
RESULT: An updown Counter using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:5c UpDown Counter 87
Simulation Lab Dept of ECE MREC
Expt.No:5c UpDown Counter 88
Simulation Lab Dept of ECE MREC
EXERSICE:
Simulate & synthesis Binary ripple counter using Verilog HDL language.
Expt.No:5c UpDown Counter 89
Simulation Lab Dept of ECE MREC
Expt.No:6a SISO Shift Register 90
Simulation Lab Dept of ECE MREC
AIM: To design a Serial in serial out shift register using structural model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
LOGIC DIAGRAM:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model
Expt.No:6a SISO Shift Register 91
Simulation Lab Dept of ECE MREC
PROGRAM: module Shiftn(clk, sIn, sOut); parameter n = 60; //number of stages input sIn, clk; output sOut; reg sOut; reg [n-1:0]state; always @(posedge clk) //sIn -> [0|1|...|n-1] -> sOut begin sOut <= state[n-1]; state <= {state[n-2:0], sIn}; endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "P74" ; NET "inp" LOC = "P76" ; NET "output" LOC = "P85" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
Expt.No:6a SISO Shift Register 92
Simulation Lab Dept of ECE MREC
RESULT: A SISO Shift Register using structural model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:6a SISO Shift Register 93
Simulation Lab Dept of ECE MREC
Expt.No:6b SIPO Shift Register 94
Simulation Lab Dept of ECE MREC
AIM: To design a Serial in Parallel out Shift Register using structural model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) LOGIC DIAGRAM:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model PROGRAM: module serial_in_parallel_out#(parameter wIDTH=8) ( input clk,data_in output [width-1:0] data_out); reg [width-1:0] shift_reg); always @ (posedge clk) shift_reg <= {data_in,shift_reg[width-1:1]}; assign data_out= shift_reg; endmodule Expt.No:6b SIPO Shift Register 95
Simulation Lab Dept of ECE MREC
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "P74" ; NET "inp" LOC = "P76" ; NET "outp<1>" LOC = "P85" ; NET "outp<2>" LOC = "P86" ; NET "outp<3>" LOC = "P87" ; NET "outp<4>" LOC = "P89" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
RESULT: A SIPO Shift Register using structural model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed. Expt.No:6b SIPO Shift Register 96
Simulation Lab Dept of ECE MREC
SIMULATION RESULT:
Expt.No:6b SIPO Shift Register 97
Simulation Lab Dept of ECE MREC
Expt.No:6c PIPO Shift Register 98
Simulation Lab Dept of ECE MREC
AIM: To design a Parallel in Parallel out Shift Register using structural model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device. TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) LOGIC DIAGRAM:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model PROGRAM: module pipo(din,clk,rst,dout); input [3:0] din; input clk,rst; output [3:0] dout; wire [3:0] din; wire clk,rst; reg [3:0] dout; always @(posedge clk or negedge rst) Expt.No:6c PIPO Shift Register 99
Simulation Lab Dept of ECE MREC
begin if(!rst) begin dout <= 4'b0; end else begin dout <= din; end end endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "P74" ; NET "din<1>" LOC = "P76" ; NET "din<2>" LOC = "P77" ; NET "din<3>" LOC = "P78" ; NET "din<4>" LOC = "P79" ; NET "q<1>" LOC = "P84" ; Expt.No:6c PIPO Shift Register 100
Simulation Lab Dept of ECE MREC
NET "q<2>" LOC = "P85" ; NET "q<3>" LOC = "P86" ; NET "q<4>" LOC = "P87" ; NET "serialin" LOC = "P80" ; NET "shift" LOC = "P82" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
RESULT: A PIPO Shift Register using structural model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:6c PIPO Shift Register 101
Simulation Lab Dept of ECE MREC
Expt.No:6c PIPO Shift Register 102
Simulation Lab Dept of ECE MREC
Expt.No:6d PISO Shift Register 103
Simulation Lab Dept of ECE MREC
AIM: To design a Parallel in Serial Out register using structural model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) LOGIC DIAGRAM:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using iMPACT Initialize JTAG Download program into kit Verify the function of design model
USER CONSTRAINTS FILE: #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p74" ; NET "d<1>" LOC = "p76" ; NET "d<2>" LOC = "p77" ; NET "d<3>" LOC = "p78" ; NET "d<4>" LOC = "p79" ; NET "output" LOC = "p84" ; NET "serialin" LOC = "p80" ; NET "shift" LOC = "p82" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
RESULT: A parallel in serial out shift register using structural model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
Expt.No:6d PISO Shift Register 106
Simulation Lab Dept of ECE MREC
SIMULATION RESULT:
Expt.No:6d PISO Shift Register 107
Simulation Lab Dept of ECE MREC
Expt.No:7a Mealy detector 108
Simulation Lab Dept of ECE MREC
AIM: To design a Mealy Detector using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) STATE DIAGRAM:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using IMPACT Initialize JTAG Download program into kit Verify the function of design model
Expt.No:7a Mealy detector 109
Simulation Lab Dept of ECE MREC
PROGRAM: module fsmmealy1011( clk,rst,inp,outp); input clk,rst,inp; output outp; reg [1:0]state; reg outp; always@(posedge clk or posedge rst) if(rst) begin state=2'b00; outp=0; end else begin case(state) 2'b00:if(inp) begin state=2'b01; outp=0; end else begin state=2'b00; outp=0; end 2'b01:if(inp) begin state=2'b01; outp=0; end else begin state=2'b10; outp=0; end 2'b10:if(inp) begin state=2'b11; outp=0; end else begin state=2'b00; outp=0; end 2'b11:if(inp) begin state=2'b01; outp=1; end else begin Expt.No:7a Mealy detector 110
Simulation Lab Dept of ECE MREC
state=2'b10; outp=0; end default: begin state=2'b00; outp=0; end endcase end endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE: #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p74" ; NET "rst" LOC = "p76" ; NET "x" LOC = "p77" ; NET "z" LOC = "p85" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
Used Available Utilization Number of Slices Number of 4 input LUTs
Number of bondedIOBs Number of Slice Flip Flops
Number of GCLKs
Expt.No:7a Mealy detector 111
Simulation Lab Dept of ECE MREC
RESULT: A Mealy Detector using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:7a Mealy detector 112
Simulation Lab Dept of ECE MREC
Expt.No:7b Moore detector 113
Simulation Lab Dept of ECE MREC
AIM: To design a Moore Detector using behavioral model of VHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) STATE DIAGRAM:
Configure target device using IMPACT Initialize JTAG Download program into kit Verify the function of design model PROGRAM: module fsmmoore1011( clk,rst,inp,outp); input clk,rst,inp; output outp; reg [2:0]state; reg outp; always@(posedge clk or posedge rst) if(rst) begin state=2'b000; outp=0; end else begin case(state) 3'b000:if(inp) begin state=3'b001; outp=0; end else begin state=3'b000; outp=0; end 3'b001:if(inp) begin state=3'b001; outp=0; end else begin state=3'b010; outp=0; end 3'b010:if(inp) begin state=3'b011; outp=0; end else begin state=3'b000; outp=0; end 3'b011:if(inp) Expt.No:7b Moore detector 115
Simulation Lab Dept of ECE MREC
begin state=3'b100; outp=0; end else begin state=3'b010; outp=0; end 3'b100:if(inp) begin state=3'b001; outp=1; end else begin state=3'b011; outp=1; end default: begin state=3'b000; outp=0; end endcase end endmodule RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE: #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "P74" ; NET "rst" LOC = "P76" ; NET "x" LOC = "P77" ; NET "z" LOC = "P85" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
Expt.No:7b Moore detector 116
Simulation Lab Dept of ECE MREC
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
RESULT:
A Moore Detector using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:7b Moore detector 117
Simulation Lab Dept of ECE MREC
Expt.No:8 4-bit Multiplier 118
Simulation Lab Dept of ECE MREC
AIM: To design a 4-Bit Multiplier using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144)
CIRCUIT DIAGRAM:
PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using IMPACT Initialize JTAG Download program into kit Verify the function of design model
Expt.No:8 4-bit Multiplier 119
Simulation Lab Dept of ECE MREC
PROGRAM: module HA(sout,cout,a,b); output sout,cout; input a,b; assign sout=a^b; assign cout=(a&b); endmodule module FA(sout,cout,a,b,cin); output sout,cout; input a,b,cin; assign sout=(a^b^cin); assign cout=((a&b)|(a&cin)|(b&cin)); endmodule module multiply4bits(product,inp1,inp2); output [7:0]product; input [3:0]inp1; input [3:0]inp2; assign product[0]=(inp1[0]&inp2[0]); wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17; HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1])); FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1); FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3); HA HA2(x6,x7,(inp1[1]&inp2[3]),x5); HA HA3(product[2],x15,x2,(inp1[2]&inp2[0])); FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15); FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16); FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17); HA HA4(product[3],x12,x14,(inp1[3]&inp2[0])); FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12); FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11); FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10); endmodule
Expt.No:8 4-bit Multiplier 120
Simulation Lab Dept of ECE MREC
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "P74" ; NET "done" LOC = "P84" ; NET "mpcand<0>" LOC = "P76" ; NET "mpcand<1>" LOC = "P77" ; NET "mpcand<2>" LOC = "P78" ; NET "mpcand<3>" LOC = "P79" ; NET "mplier<0>" LOC = "P80" ; NET "mplier<1>" LOC = "P82" ; NET "mplier<2>" LOC = "P83" ; NET "mplier<3>" LOC = "P98" ; NET "product<0>" LOC = "P86" ; NET "product<1>" LOC = "P87" ; Expt.No:8 4-bit Multiplier 121
Simulation Lab Dept of ECE MREC
NET "product<2>" LOC = "P89" ; NET "product<3>" LOC = "P90" ; NET "product<4>" LOC = "P92" ; NET "product<5>" LOC = "P93" ; NET "product<6>" LOC = "P96" ; NET "product<7>" LOC = "P95" ; NET "st" LOC = "P99" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
RESULT: A 4-Bit Multiplier using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:8 4-bit Multiplier 122
Simulation Lab Dept of ECE MREC
Expt.No:8 4-bit Multiplier 123
Simulation Lab Dept of ECE MREC
EXERSICE: Simulate and synthesis 4-bit divider using veriogHDL language.
Expt.No:8 4-bit Multiplier 124
Simulation Lab Dept of ECE MREC
Expt.No:8 4-bit Multiplier 125
Simulation Lab Dept of ECE MREC
Expt.No:9 ALU(16-bit) 126
Simulation Lab Dept of ECE MREC
AIM: To design ALU using behavioral model of VerilogHDL program and to perform simulation, synthesis, place & route and implementation of the design using FPGA device.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using IMPACT Initialize JTAG Download program into kit Verify the function of design model
PROGRAM: module alu(a,b,cin,alu,carry,zero,ctl);
input [3:0] a,b; // port A,B input cin ; // carry input from carry flag register output [3:0] alu; // the result output carry; // carry output output zero ; // zero output input [3:0] ctl ; // functionality control for ALU wire [4:0] result; // ALU result
assign result = alu_out(a,b,cin,ctl); assign alu = result[3:0]; assign carry = result[4] ; assign zero = z_flag(result) ;
function [4:0] alu_out; input [3:0] a,b ; input cin ; input [3:0] ctl ; case ( ctl ) 4'b0000: alu_out=b; // select data on port B 4'b0001: alu_out=b+4'b0001 ; // increment data on port B Expt.No:9 ALU(16-bit) 127
Simulation Lab Dept of ECE MREC
4'b0010: alu_out=b-4'b0001 ; // decrement data on port B 4'b0011: alu_out=a+b; // ADD without CARRY 4'b0100: alu_out=a+b+cin; // ADD with CARRY 4'b0101: alu_out=a-b ; // SUB without BORROW 4'b0110: alu_out=a-b+(~cin); // SUB with BORROW 4'b0111: alu_out=a&b; // AND 4'b1000: alu_out=a|b; // OR 4'b1001: alu_out=a^b; // EXOR 4'b1010: alu_out={b[3:0],1'b0}; // Shift Left 4'b1011: alu_out={b[0],1'b0,b[3:1]}; // Shift Right 4'b1100: alu_out={b[3:0],cin}; // Rotate Left 4'b1101: alu_out={b[0],cin,b[3:1]}; // Rotate Right default : begin alu_out=9'bxxxxxxxxx; $display("Illegal CTL detected!!"); end endcase /* {...,...,...} is for the concatenation. {ADD_WITH_CARRY,SUB_WITH_BORROW}==2'b11 is used to force the CARRY==1 for the increment operation */ endfunction // end of function "result"
function z_flag ; input [4:0] a4 ; begin z_flag = ^(a4[0]|a4[1]|a4[2]|a4[3]) ; // zero flag check for a4 end endfunction
endmodule
RTL SCHEMATIC DIAGRAM:
USER CONSTRAINTS FILE:
#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "s<0>" LOC = "p74" ; Expt.No:9 ALU(16-bit) 128
Simulation Lab Dept of ECE MREC
NET "s<1>" LOC = "p76" ; NET "s<2>" LOC = "p77" ; NET "s<3>" LOC = "p111" ; NET "s<4>" LOC = "p101" ; NET "w<0>" LOC = "p78" ; NET "w<10>" LOC = "p90" ; NET "w<11>" LOC = "p92" ; NET "w<12>" LOC = "p93" ; NET "w<13>" LOC = "p95" ; NET "w<14>" LOC = "p96" ; NET "w<15>" LOC = "p97" ; NET "w<16>" LOC = "p98" ; NET "w<17>" LOC = "p99" ; NET "w<18>" LOC = "p100" ; NET "w<19>" LOC = "p102" ; NET "w<1>" LOC = "p79" ; NET "w<20>" LOC = "p103" ; NET "w<21>" LOC = "p104" ; NET "w<22>" LOC = "p105" ; NET "w<23>" LOC = "p107" ; NET "w<24>" LOC = "p108" ; NET "w<25>" LOC = "p1" ; NET "w<26>" LOC = "p2" ; NET "w<27>" LOC = "p4" ; NET "w<28>" LOC = "p5" ; NET "w<29>" LOC = "p6" ; NET "w<2>" LOC = "p80" ; NET "w<30>" LOC = "p7" ; NET "w<31>" LOC = "p8" ; NET "w<3>" LOC = "p82" ; NET "w<4>" LOC = "p83" ; NET "w<5>" LOC = "p84" ; NET "w<6>" LOC = "p85" ; NET "w<7>" LOC = "p86" ; NET "w<8>" LOC = "p87" ; NET "w<9>" LOC = "p89" ; NET "x<0>" LOC = "p10" ; NET "x<10>" LOC = "p23" ; NET "x<11>" LOC = "p24" ; NET "x<12>" LOC = "p25" ; NET "x<13>" LOC = "p26" ; NET "x<14>" LOC = "p27" ; NET "x<15>" LOC = "p28" ; NET "x<1>" LOC = "p11" ; NET "x<2>" LOC = "p12" ; NET "x<3>" LOC = "p13" ; NET "x<4>" LOC = "p14" ; NET "x<5>" LOC = "p15" ; NET "x<6>" LOC = "p17" ; NET "x<7>" LOC = "p18" ; NET "x<8>" LOC = "p20" ; NET "x<9>" LOC = "p21" ; Expt.No:9 ALU(16-bit) 129
Simulation Lab Dept of ECE MREC
NET "y<0>" LOC = "p30" ; NET "y<10>" LOC = "p47" ; NET "y<11>" LOC = "p50" ; NET "y<12>" LOC = "p51" ; NET "y<13>" LOC = "p52" ; NET "y<14>" LOC = "p53" ; NET "y<15>" LOC = "p55" ; NET "y<1>" LOC = "p31" ; NET "y<2>" LOC = "p32" ; NET "y<3>" LOC = "p33" ; NET "y<4>" LOC = "p35" ; NET "y<5>" LOC = "p36" ; NET "y<6>" LOC = "p40" ; NET "y<7>" LOC = "p41" ; NET "y<8>" LOC = "p44" ; NET "y<9>" LOC = "p46" ; NET "z<0>" LOC = "p56" ; NET "z<10>" LOC = "p73" ; NET "z<11>" LOC = "p112" ; NET "z<12>" LOC = "p113" ; NET "z<13>" LOC = "p116" ; NET "z<14>" LOC = "p118" ; NET "z<15>" LOC = "p119" ; NET "z<1>" LOC = "p57" ; NET "z<2>" LOC = "p58" ; NET "z<3>" LOC = "p59" ; NET "z<4>" LOC = "p60" ; NET "z<5>" LOC = "p63" ; NET "z<6>" LOC = "p65" ; NET "z<7>" LOC = "p68" ; NET "z<8>" LOC = "p69" ; NET "z<9>" LOC = "p70" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs
Number of Slice Flip Flops
Number of GCLKs
Expt.No:9 ALU(16-bit) 130
Simulation Lab Dept of ECE MREC
ESULT: ALU using behavioral model of VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.
SIMULATION RESULT:
Expt.No:9 ALU(16-bit) 131
Simulation Lab Dept of ECE MREC
Expt.No:9 ALU(16-bit) 132
Simulation Lab Dept of ECE MREC
Expt.No:10 REAL TIME CLOCK 133
Simulation Lab Dept of ECE MREC
AIM: To design a Real Time Clock (2 digits, 7 segment LED displays each for Hours,Minutes and Seconds) and demonstrate its working on the FPGA Board.
TOOLS REQUIRED: Model sim III 6.0 d Xilinx ISE 8.1 i FPGA device (Family: Spartan3 Device: XC3S400 Package: TQ144) PROCEDURE: Check syntax View RTL schematic View Technology schematic Perform simulation Write ucf file Implement design View the synthesis report Configure target device using IMPACT Initialize JTAG Download program into kit Verify the function of design model PROGRAM:
module real_time_clk_verilog (clk,clear,hour1,hour2,minute1,minute2,second1, second2, hour_A2, min_A1, sec_A0, load, data_in); input clk,clear; output reg [6:0]hour1,hour2,minute1,minute2,second1,second2; input load; input hour_A2,min_A1,sec_A0; input [7:0]data_in; reg clk_sec,clk_msec; reg [7:0]sec,min,hr; integer timer_count1=0,timer_count2=0; always@(posedge clk) 47 begin if(timer_count1==3999) begin timer_count1=0; clk_msec=1'b1; end else begin timer_count1=timer_count1+1; clk_msec=1'b0; end end Expt.No:10 REAL TIME CLOCK 134
Simulation Lab Dept of ECE MREC
always@(posedge clk_msec) begin if(timer_count2==999) begin timer_count2=0; clk_sec=1'b1; end else begin timer_count2=timer_count2+1; clk_sec=1'b0; end end always@(negedge clk_sec) begin if(~clear) begin sec=0; min=0; hr=0; end else if(~load) begin if(hour_A2) begin if(hr[7:4] == 4'b0010) begin if(hr[3:0] < 4'b0100) hr = data_in; end 48 else if(hr[7:4] < 4'b0010) hr = data_in; else hr = 8'b0; end if(min_A1) begin if(min[7:4] < 4'b0110) min = data_in; else min = 8'b0; end if(sec_A0) begin if (sec[7:4] < 4'b0110) sec = data_in; else sec = 8'b0; end end Expt.No:10 REAL TIME CLOCK 135
Simulation Lab Dept of ECE MREC
else begin if(sec[3:0]==4'b1001) begin sec[3:0]=4'b0; if(sec[7:4]==4'b0101) begin sec[7:4]=4'b0; if(min[3:0]==4'b1001) begin min[3:0]=4'b0; if(min[7:4]==4'b0101) begin min[7:4]=4'b0; if(hr==8'b00100011) hr=0; else if(hr[3:0]==4'b1001) begin hr[3:0]=4'b0; hr[7:4]=hr[7:4]+1; end else 49 hr[3:0]=hr[3:0]+1; //hours count completed end else min[7:4]=min[7:4]+1; end else min[3:0]=min[3:0]+1; // minutes count completed end else sec[7:4]=sec[7:4]+1; end else sec[3:0]=sec[3:0]+1; //seconds count completed end end always@(sec) begin case (sec[3:0]) 4'b0000: second1=7'b1111110; 4'b0001: second1=7'b0110000; 4'b0010: second1=7'b1101101; 4'b0011: second1=7'b1111001; 4'b0100: second1=7'b0110011; 4'b0101: second1=7'b1011011; 4'b0110: second1=7'b1011111; 4'b0111: second1=7'b1110000; 4'b1000: second1=7'b1111111; 4'b1001: second1=7'b1111011; Expt.No:10 REAL TIME CLOCK 136
always@(hr) begin case(hr[3:0]) 4'b0000: hour1=7'b1111110; 4'b0001: hour1=7'b0110000; 4'b0010: hour1=7'b1101101; 4'b0011: hour1=7'b1111001; 51 4'b0100: hour1=7'b0110011; 4'b0101: hour1=7'b1011011; 4'b0110: hour1=7'b1011111; 4'b0111: hour1=7'b1110000; 4'b1000: hour1=7'b1111111; 4'b1001: hour1=7'b1111011; default: hour1=7'b1111110; endcase end always@(hr) begin case(hr[7:4]) 4'b0000: hour2=7'b1111110; 4'b0001: hour2=7'b0110000; 4'b0010: hour2=7'b1101101; default: hour2=7'b1111110; endcase end end module
UCF File(User Constraint File):
NET "clear" LOC = "p137" ; NET "clk" LOC = "p52" ; NET "data_in<0>" LOC = "p92" ; NET "data_in<1>" LOC = "p96" ; NET "data_in<2>" LOC = "p74" ; NET "data_in<3>" LOC = "p76" ; NET "data_in<4>" LOC = "p77" ; NET "data_in<5>" LOC = "p79" ; NET "data_in<6>" LOC = "p84" ; NET "data_in<7>" LOC = "p85" ; NET "hour1<0>" LOC = "p95" ; NET "hour1<1>" LOC = "p97" ; NET "hour1<2>" LOC = "p98" ; NET "hour1<3>" LOC = "p99" ; NET "hour1<4>" LOC = "p104" ; NET "hour1<5>" LOC = "p125" ; NET "hour1<6>" LOC = "p122" ; NET "hour2<0>" LOC = "p112" ; NET "hour2<1>" LOC = "p116" ; NET "hour2<2>" LOC = "p119" ; NET "hour2<3>" LOC = "p118" ; NET "hour2<4>" LOC = "p123" ; Expt.No:10 REAL TIME CLOCK 138
Simulation Lab Dept of ECE MREC
NET "hour2<5>" LOC = "p131" ; NET "hour2<6>" LOC = "p93" ; NET "hour_A2" LOC = "p78" ; NET "load" LOC = "p83" ; NET "min_A1" LOC = "p82" ; NET "minute1<0>" LOC = "p14" ; NET "minute1<1>" LOC = "p15" ; NET "minute1<2>" LOC = "p17" ; NET "minute1<3>" LOC = "p18" ; NET "minute1<4>" LOC = "p21" ; NET "minute1<5>" LOC = "p23" ; NET "minute1<6>" LOC = "p24" ; NET "minute2<0>" LOC = "p129" ; NET "minute2<1>" LOC = "p132" ; NET "minute2<2>" LOC = "p135" ; NET "minute2<3>" LOC = "p140" ; NET "minute2<4>" LOC = "p1" ; NET "minute2<5>" LOC = "p12" ; NET "minute2<6>" LOC = "p13" ; NET "sec_A0" LOC = "p80" ; NET "second1<0>" LOC = "p32" ; NET "second1<1>" LOC = "p35" ; NET "second1<2>" LOC = "p36" ; NET "second1<3>" LOC = "p40" ; NET "second1<4>" LOC = "p41" ; NET "second1<5>" LOC = "p56" ; NET "second1<6>" LOC = "p60" ; NET "second2<0>" LOC = "p26" ; NET "second2<1>" LOC = "p27" ; NET "second2<2>" LOC = "p6" ; NET "second2<3>" LOC = "p7" ; NET "second2<4>" LOC = "p8" ; NET "second2<5>" LOC = "p11" ; NET "second2<6>" LOC = "p10" ;
SYNTHESIS REPORT: Device Utilization Summary
Logic Utilization
Used Available Utilization Number of Slices
Number of 4 input LUTs
Number of bonded IOBs Number of Slice Flip Flops Number of GCLKs
Expt.No:10 REAL TIME CLOCK 139
Simulation Lab Dept of ECE MREC
RESULT: Real time clock using VerilogHDL program is designed and simulation, synthesis, place & route and implementation of the design using FPGA device is performed.