Analog Cmos Amplifiers

1
Analog CMOS 1
Chapter 3
Fundamental Building Blocks
Course home page: http://www.fysel.ntnu.no/courses/tfe4185/
Trond Ytterdal, Department of Electronics and Telecommunication, NTNU, Norway
NTNU
September 2004
MOS Fundamental Building Blocks
CMOS Current Mirrors
Simple
Source-Degenerated
High-Output-Impedance
CMOS Single Transistor Amplifiers
Common-Source
Source-Follower (Common-Drain)
Common-Gate
Cascode Gain Stage
MOS Differential Pair and Gain Stage
2
NTNU
September 2004
BJ T Fundamental Building Blocks
Bipolar Current Mirrors
Simple
Base current compensated
Emitter-Degenerated
Bipolar Gain Stages
Emitter Follower
Differential Pair
NTNU
September 2004
I ntroduction to Amplifiers
2 1
2
2 1 0
) ( ) ( ) ( ) (
in in in
n
in n in in out
V V V t V a t V a t V a a t V + + + + = K
A
V
out
V
in
The input-output characteristic of an
amplifier is generally a non-linear function
that can be approximated by a its truncated
Taylor series over some signal range:
The signal is shown here as a voltage. It can also be current or charge.
For a sufficiently small input signal range, we can keep the constant
and the first order terms only:
) ( ) (
1 0
t V a a t V
in out
+ =
Here, a
0
can be considered the operating point and a
1
the small-signal
gain.
3
NTNU
September 2004
Amplifier Performance Parameters
Gain
Speed
Noise
Linearity
Supply voltage
Voltage swing
Power dissipation
Input/output impedance
Most of these parameters
trade with each other.
Such trade-offs lead to
many challenges in the
design of high-
performance amplifiers.
NTNU
September 2004
Common- Source Amplifier
with Resistive Load
V
in
Q
1
V
out
V
DD
R
D
2
) (
2
tn in
ox n
D DD out
V V
L
W C
R V V
=
Assuming that the transistor is biased in
strong inversion, active region:
Here we have neglected channel length
modulation.
Taking the derivative of V
out
with respect to
V
in
, we get
D m
tn in ox n D
in
out
v
R g
V V
L
W
C R
dV
dV
A
=
= = ) (
4
NTNU
September 2004
CS Amplifier with Resistive Load
v
in
v
in
g
m1
v
in
R
D
~
v
out
Finding the gain using the small-signal equivalent circuit
D m
in
out
v
D in m out
R g
v
v
A
R v g v
= =
=
All the current in the current source go through the resistor:
NTNU
September 2004
CS Amplifier
with Ideal Current Source as Load
V
in
Q
1
V
out
V
DD
I
b
v
in
g
m1
v
in
g
ds
v
out
Effect of channel length modulation included.
ds m
ds
m
v
r g
g
g
A = =
The quantity g
m
/g
ds
is called the intrinsic gain
of a transistor. Represents the maximum gain
that can be achieved using a single device.
5
NTNU
September 2004
Example of I ntrinsic Gain
for a 0.35m CMOS technology
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Veff [V]
-0
200
400
600
800
I
n
t
r
i
n
s
i
c

g
a
i
n
W/L =5m/1.05m
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Veff [V]
0u
50u
100u
150u
200u
250u
300u
D
r
a
i
n

c
u
r
r
e
n
t

[
A
]
NTNU
September 2004
Simple CMOS Current Mirror
Assume transistors in active
region, =0, and same size
I
out
=I
in
I
in
I
out
r
out
V
1
v
y
v
gs1
g
m1
v
gs1
r
ds1
v
1
Q
1
Q
2
~
i
y
1 1
1 1
1
1 1
||
m m
ds
y
y
y m
ds
y
y
g g
r
i
v
v g
r
v
i = + =
Q
1
v
1
1/g
m1
Q
1
6
NTNU
September 2004
Simple CMOS Current Mirror
1/g
m1
Q
1
v
gs2
g
m2
v
gs2
r
ds2
Q
1
Q
2
r
out
r
ds2
Small Signal Equivalent Circuit (Low Frequency )
NTNU
September 2004
Current Mirror Design Example
Design a current mirror such that V
eff
is >0.5 V and
r
out
>300 k at an input current of 100A.
Given:
n
C
ox
=92 A/V
2
; V
tn
=0.8 V;
r
ds
=1/I
D
=8000L(m)/I
D
(mA)
m 34
m 8 . 34
V 25 . 0
V
A
92
m 4 2 A 100
2
m 4
m 75 . 3
8000
1 . 0 k 300
k 300
) mA (
) m ( 8000 1
2
2
2
=
=

<
=
=
=

> > =
= =
W
W V
L
W C
I
L
L
I
L
I
r r
eff
ox n
D
D D
ds out
Solution:
7
NTNU
September 2004
CS with Active Load
r
out V
in
Q
1
I
bias
V
out
Q
2
Q
3
v
in
v
gs1
g
m1
v
gs1
R
2
= r
ds1
|| r
ds2
~
R
in
v
out
) || (
2 1 1 ds ds m
in
out
v
r r g
v
v
A = =
Active load
NTNU
September 2004
Source- Follower ( Common- Drain)
Voltage gain close to unity
Used as voltage buffers
Can provide current gain
I
bias
Q
3
Q
2
V
in
Q
1
V
out
v
gs1
g
m1
v
gs1
r
ds1
v
out
v
in
r
ds2
g
s1
v
out
2 1 1 1
1
1 1 2 1
0 ) ( ) (
ds ds s m
m
in
out
out in m s ds ds out
g g g g
g
v
v
v v g g g g v
+ + +
=
= + +
Writing the nodal equation at v
out
:
8
NTNU
September 2004
Common- Gate Amplifier
r
out V
bias
Q
1
I
bias
V
out
Q
2
Q
3
V
in
v
gs1
g
m1
v
in
r
ds1
v
in
g
s1
v
in
Used for:
Low input impedance stages
Amplifying current
v
out
+
+ +
+
= =
+ + =
1 1 1 1 1
1
1 1 1
1
1
1
) (
ds
L
m ds s m
L
ds
in
in
in
ds out in in s in m in
r
R
g g g g
G
g
i
v
r
g v v v g v g i
r
in
1
1
1
1 1 1
1 1 1
0 ) ( ) (
ds L
m
ds L
ds s m
in
out
in m s out L ds in out
g G
g
g G
g g g
v
v
v g g v G g v v
+
+
+ +
=
= + +
Voltage gain: Input impedance:
R
L
Assumes zero R
S
NTNU
September 2004
Source- Degenerated Current Mirror
I
in
I
out
I
x
V
s
Q
1
Q
2
R
s
R
s
s x s gs
s x s
R i v v
R i v
= =
=
) 1 (
2 2
2
2
2
2
m s ds
x
x
out
ds
s x x
s m x
ds
s x
gs m x
g R r
i
v
r
r
R i v
R g i
r
v v
v g i
+ =
+ =
+ =
i
x
is equal to the total current through g
m2
v
gs2
and g
ds2
:
Note: To include the body effect, replace g
m2
with g
m2
+g
s2
9
NTNU
September 2004
Cascode Current Mirror
I
in
V
out
r
out
Q
3
Q
4
Q
1
I
out
Q
2
[ ]
[ ]
[ ]
4 2 4
4 4 2 4
4 4 4 2 4
4 4 4 4
) ( 1
) ( 1
) ( 1
m ds ds
s m ds ds
ds s m ds ds
ds s m s ds out
g r r
g g r r
g g g r r
g g g R r r
+ +
+ + + =
+ + + =
Serious disadvantage:
V
out
must be larger than 2V
eff
+V
tn
to keep all transistors in the active
region
NTNU
September 2004
Wilson Current Mirror
I
in
V
out
r
out
Q
3
Q
4
Q
1
I
out
Q
2
r
in
2
1 1
4
ds m
ds out
r g
r r
About one-half of the output
impedance for that of a cascode
current mirror
Serious disadvantage:
V
out
must be larger than 2V
eff
+V
tn
to keep all transistors in the active
region
10
NTNU
September 2004
Cascode Gain Stages
r
d2
V
in
Q
1
V
out
Q
2
V
bias
I
bias
Telescopic-cascode amplifier
V
in
Q
1
I
bias1
Q
2
V
out
V
bias
Folded-cascode amplifier
I
bias2
r
L
NTNU
September 2004
Cascode Gain Stages
Analysis
2 1 2 2
2
||
ds ds m d
L d out
r r g r
r r r
=
=
Assume that r
l
is of a similar form
and that all transistors are matched.
Dropping the indices, we get:
2
2
ds m
out
r g
r
Output impedance
Looking into the source of the common-gate, or
cascode, transistor Q
2
we get:
Voltage Gain
ds
m ds
ds
m
L
ds
m
L
ds
ds s m
in
g
g g
g
g
g
g
g
g
g
g g g
y
+
=
+
+
+ +
=
/
1 1 1
2
2
2
2
2 2 2
2
ds
m
in ds
m
in
s
g
g
y g
g
v
v
2
2 1
1 2

+
=
2
2
2
2
2
2
1
2

+
=
ds
m
ds L
m
ds
m
s
out
in
s
v
g
g
g g
g
g
g
v
v
v
v
A
11
NTNU
September 2004
MOS Differential Pair
Q
1
I
D2
Q
2
V
+
V
I
bias
I
D1
v
+
v
i
d1
=i
s1
i
d2
=i
s2
i
s1
i
s2
in
m
d
in
m
m m
in
s s
in
s d
m m m
in
v
g
i
v
g
g g
v
r r
v
i i
g g g
v v v
2
2 / 1 / 1
2
2
2 1 2 1
1 1
2 1
=
=
+
=
+
= =
= =

+
in m out
d d out
v g i
i i i
=

2 1
NTNU
September 2004
MOS Diff- Pair with Active Load
Q
1
Q
2
V
+
V
I
bias
i
s1
Q
3
Q
4
i
d4
V
out
out m v
in out m out d s out
s d d
in
m
s d
r g A
v r g r i i v
i i i
v
g
i i
1
1 4 1
1 3 4
1
1 1
) (
2
=

= =
= =
= =
v
in
g
m1
v
in
r
out
v
out
+
-
C
L
i
s1
Differential-input, single-
ended output gain stage
Voltage Gain
12
NTNU
September 2004
Output resistance
i
s1
i
s2
i
s1
i
s2
v
x
~
i
x
r
ds1
r
ds2
r
ds3
|| r
s3 r
ds4
g
m4
v
a
+
-
v
a
r
s2
r
s1
i
x2
i
x3
i
x1
i
x4
i
x5
NTNU
September 2004
Output resistance analysis
4 2
2 4
4 3 2 1
3 2 1 4
5 4
2
2 1
2
2
4
1
||
2
ds ds out
ds
x
ds
x
x
x x x x
x
x
x
out
x s s x
x x
ds
x
s s
ds
x
x
ds
x
x
r r r
r
v
r
v
v
i i i i
v
i
v
r
i i i i
i i
r
v
i i
r
v
i
r
v
i
=
+
=
+ + +
= =
= = =
=
= =
=
(assuming r
ds1
, r
ds2
>>r
s1
, r
s2
)
(assuming r
s1
=r
s2
)
(current mirror)
13
NTNU
September 2004
Bipolar Current Mirrors
Simple
I
in
r
out
Q
1
Q
2
I
out
in out
I I
2
/ 2 1
1
+
=
Better
I
in
r
out
Q
1
Q
2
I
out
in out
I I
+
=
/ 2 1
1
r
out
=r
o
NTNU
September 2004
Emitter- Degenerated Current
Mirrors
I
in
I
out
I
x
Q
1
Q
2
R
e
R
e
) 1 (
2 2 e m o out
R g r r +
Almost identical to the MOS version:
One additional condition:
<< r R
e
One advantage over MOS:
No body effect
Cascode versus Wilson:
For the bipolar case, Wilson
is preferred because base
current is supplied from
both input and output sides.
14
NTNU
September 2004
Bipolar Gain Stages
Emitter Follower
Q
2
R
E
V
in
R
S
V
out
i
b
i
e
r
o
r
e
R
S
R
E
=R
E
|| r
o
v
out
v
in
i
b
R
b
R
e
v
b
r
b
ignored
NTNU
September 2004
Bipolar Emitter Follower
Voltage Gain
m E
E
S E e
E e
in
out
m E
E
b
out
S b
b
in
b
E e
b
b
b
E e b E e e b
b e
g R
R
R R r
R r
v
v
g R
R
v
v
R R
R
v
v
R r
i
v
R
R r i R r i v
i i
/ 1 ) )( 1 (
) )( 1 (
/ 1
;
) )( 1 (
) )( 1 ( ) (
) 1 (
'
'
'
'
'
'
'
' '
+ + + +
+ +
=
+
=
+
=
+ + = =
+ + = + =
+ =
Impedance reflection rule: At low frequencies,
resistances in series with the emitter appear +1
times larger when seen looking into the base.
15
NTNU
September 2004
Bipolar Emitter Follower
Output Impedance
i
b
i
e
r
e
R
S
R
e
i
x
v
x
=v
e
Shall find:
e x
S
x
e x S b
e x b x
r i
R
i
r i R i
r i v v
+
+
=
+ =
+ =
1
v
b
1 1 +
=
+
=
x e
b
i i
i
x
x
e
i
v
R =
e
S
x
x
e
r
R
i
v
R +
+
= =
1
(R
E
excluded)
NTNU
September 2004
Bipolar Differential Pair
Small Signal
Q
1
I
C2
Q
2
V
+
V
I
EE
I
C1
Voltage gain same as for MOS
differential pair. However,
input resistance is not infinite.
i
c1
=i
e1
i
c2
=i
e2
i
e1
i
e2
) )( 1 (
2 1 e e id
r r r + + =
r
e2
r
e1
r
id
Using the impedance
reflection rule, we get:
16
NTNU
September 2004
Frequency Response
Common-Source Amplifier
Full coverage
Source-Follower Amplifier
Important results only
Cascode Gain Stage
Full coverage
SPICE Simulation Example
Simulating frequency response
NTNU
September 2004
Frequency Response
v
in g
m1
v
1
R
2
~
R
in
v
out
C
gs1
C
gd1
C
2
v
1
b s sa
g
C
s R g
v
v
v g sC v sC sC G v
sC v G v sC sC G v
m
gd
m
in
out
m gd gd out
gd out in in gd gs in
2
1
1
2 1
1 1 1 1 2 1 2
1 1 1 1
1
1
0 ) (
0 ) (
+ +

=
= + + +
= + +
Writing the nodal equations at v
1
and v
out
:
C
2
=C
db1
+C
db2
+C
L
R
2
= r
ds1
|| r
ds2
[ ]
( )
2 1 2 1 1 1 2
2 1 2 2 1 1 1
) ( ) 1 (
C C C C C C R R b
C C R R g C C R a
gd gs gs gd in
gd m gd gs in
+ + =
+ + + + =
17
NTNU
September 2004
3 dB Frequency
) ( )] 1 ( [
1
)} ( )] 1 ( [ { 1 1
2 1 2 2 1 1 1
dB 3
2 1 2 2 1 1 1
2 1 2 1
C C R R g C C R
C C R R g C C R s
R g
sa
R g
v
v
gd m gd gs in
gd m gd gs in
m m
in
out
+ + + +

+ + + + +

=
+
At frequencies where the gain has started to decrease, but is still much greater
than unity, we can write:
If the first term in the denominator dominates:
)] 1 ( [
1
1 1
dB 3
A C C R
gd gs in
+ +

Miller capacitance
NTNU
September 2004
SPI CE Example
V
in
Q
1
I
bias
V
out
Q
2
Q
3
Common-Source Amplifier
V
b
MOS Common-Source Amplifier
.lib mos025u.mdl
vdd vdd 0 dc 2.5
vss vss 0 dc 0
m1 vout vin 0 0 n1 l=2u w=10u
m2 vout vb vdd vdd p1 l=2u w=10u
m3 vb vb vdd vdd p1 l=2u w=10u
ib vb vss 10u
cl vout vss 2p
* setting DC operating point
l1 vout vin 1g
* AC decoupling
c1 vinc vin 1g
vac vinc vss dc 0 ac 1
18
NTNU
September 2004
Source- Follower Amplifier
Frequency Response
I
bias
Q
1
R
in
C
in
V
out
C
L
I
in
The transfer function can be written as:
2
0
2
0
2
1 1
1
) (
) 0 ( ) (
+
=
+ +
+
= =
s
Q
s
s N
A
c s sb a
g sC
i
v
s A
m gs
in
out
Note that when Q >0.5,
poles will be complex
conjugate, and the circuit
will exhibit overshoot
NTNU
September 2004
Source- Follower Amplifier
Q factor and pole frequency
Q factor and pole frequency
0
:
1 1 1
'
1
1 1 1 1
'
1
'
1 1 1
1
'
1
1 1
0
; ;
) (
)] ( )[ (
) (
) (
s s gd in in L sb s
s gs s m in s in
s gs in s gs s m in
s gs in s gs
s m in
g G C C C C C C
G C G g C C G
C C C C C G g G
Q
C C C C C
G g G
+ = + =
+ + +
+ + +
=
+ +
+
=
If C
s
, C
in
, or both become large, Q becomes small =>we are safe
When C
in
and G
s1
become small, Q will be large =>large ringing
19
NTNU
September 2004
Cascode Gain Stage
V
in
Q
1
V
out
Q
2
V
bias
I
bias
v
in
g
m1
v
g1
r
ds1
R
in
v
out
C
gs1
C
gd1
C
s2
v
g1
g
m2
v
s2
v
s2
r
ds2
C
d2 G
L
C
s2
=C
db1
+C
sb2
+C
gs2
C
d2
=C
gd2
+C
db2
+C
L
+C
bias
NTNU
September 2004
The Zero- Value Time- Constant
Analysis Method
Set all independent sources to zero
Calculate a time constant for each capacitor by
assuming all other capacitors are zero, replacing
the capacitor in question with a voltage source,
and then calculating the resistance seen by that
capacitor by taking the ratio of the voltage source
to the current flowing from the voltage source.
The -3-dB value is estimated to be 1 divided by
the sum of all the individual capacitor time
constants.
20
NTNU
September 2004
Capacitance Time Constants
g
m1
v
g1
R
d1
R
in
~
-
v
x
+
i
x
R
d1
is the parallel combination
of r
ds1
and the impedance seen
looking into the source of Q
2
~
v
x
R
d1
R
in
v
y
v
g1
i
x
g
m1
v
y
Cgd1
NTNU
September 2004
Capacitance Time Constants
Analysis
[ ]
[ ]
) 1 (
2
) 1 (
2
) 2 ( 1
2
) ( 1
) ( ;
1 1 1
1 1 1
1 1 1 1
1 1
in m
ds
gd Cgd
in m
ds
m ds in
ds
Cgd
m d in d
x
x
Cgd
y m d y x x in x y
R g
r
C
R g
r
g g R
r
r
g G R R
i
v
r
v g G v v i R i v
+
+ + +
+ + = =
= =
(3.52)] [see 2
1 ds d
r R
2
2
2
2 2
2 2
1 1
ds m
d Cd
ds
s Cs
in gs Cgs
r g
C
r
C
R C

=
total dB
Cd Cs Cgd Cgs total

+ + + =
1
3
2 2 1 1

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