Thit k b so snh 2 s nh phn 4 bit

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sosanh4bit is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
x1 : out STD_LOGIC;
x2 : out STD_LOGIC;
x3 : out STD_LOGIC
);
end sosanh4bit;
}} End of automatically maintained section
architecture sosanh4bit of sosanh4bit is
begin
x1<=1 when a>b else 0;
x2<=1 when a=b else 0;
x3<=1 when a enter your statements here
end sosanh4bit;

Thit k mch DEMUX 1_8
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DEMUX1_8 is
port(
x : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(2 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
);
end DEMUX1_8;
}} End of automatically maintained section
architecture DEMUX1_8 of DEMUX1_8 is
begin
with sel select
y<=ZZZZZZZ&x when 000,
ZZZZZZ&x&Z when 001,
ZZZZZ&x&ZZ when 010,
ZZZZ&x&ZZZ when 011,
ZZZ&x&ZZZZ when 100,
ZZ&x&ZZZZZ when 101,
Z&x&ZZZZZZ when 110,
x&ZZZZZZZ when 111,
unaffected when others;
end DEMUX1_8;

Thit k b m ha nh phn Gray
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NhiPhan_Gray is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
G : out STD_LOGIC_VECTOR(3 downto 0)
);
end NhiPhan_Gray;


--}} End of automatically maintained section

architecture NhiPhan_Gray of NhiPhan_Gray is
begin

with A select
G<= "0000" when "0000",
"0001" when "0001",
"0010" when "0011",
"0011" when "0010",
"0100" when "0110",
"0101" when "0111",
"0110" when "0101",
"0111" when "0100",
"1000" when "1100",
"1001" when "1101",
"1010" when "1111",
"1011" when "1110",
"1100" when "1010",
"1101" when "1011",
"1110" when "1001",
"1111" when "1000",
"XXXX" when others;
end NhiPhan_Gray;
Thit k b ALU 4 bit
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
q : out STD_LOGIC_VECTOR(3 downto 0)
);
end alu;

architecture alu of alu is
begin
with sel select
q <= a+b when 00,
a-b when 01,
a and b when 10,
a or b when others;
end alu;

Thit k mch ghi dch 8 bt vo ni tip ra ni tip
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nt_nt is
port(
C : in std_logic;
SI : in BIT;
SO : out BIT
);
end nt_nt;
architecture nt_nt of nt_nt is
signal tmp: bit_vector(7 downto 0);
begin
process (C)
begin
if (Cevent and C=1) then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end nt_nt;

Thit k b ghi dch 8 bit vo ni tip ra song song
ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ghidich8bit_vnt_rss is
generic (n:integer:=8);
port(
d : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(n-1 downto 0)
);
end ghidich8bit_vnt_rss;
architecture ghidich8bit_vnt_rss of ghidich8bit_vnt_rss is
signal temp:std_logic_vector (n-1 downto 0);
begin
process(clk,rst,d)
begin
if (rst=1) then
temp<=(others=>0);
elsif(clkevent and clk=1) then
temp<=temp((n-2) downto 0)&d;
end if;
output<=temp;
end process;
end ghidich8bit_vnt_rss;

Thit k mch iu kin n giao thng

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
entity den_GT is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
v : out STD_LOGIC;
x : out STD_LOGIC;
d : out STD_LOGIC;
ht : out STD_LOGIC_VECTOR(7 downto 0)
);
end den_GT;
}} End of automatically maintained section
architecture den_GT of den_GT is
signal z: std_logic_vector(4 downto 0);
begin
process(clk,rst)
variable a:integer range 0 to 17;
begin
if rst=1 then
a:=0;
elsif rising_edge(clk) then
if a=17 then
a:=0;
else
a:=a+1;
end if;
if a>0 and a<9 then
v<=0 ;
d<=1;
x<=0;
elsif a>8 and a<15 then
v<=0 ;
d<=0;
x<=1;
elsif a>14 and a<18 then
v<=1 ;
d<=0;
x<=0;
end if;
end if;
case a is
when 0=>ht<=01000000;
when 1=>ht<=01111001;
when 2=>ht<=01000100;
when 3=>ht<=00110000;
when 4=>ht<=00011001;
when 5=>ht<=00010010;
when 6=>ht<=00000001;
when 7=>ht<=01111000;
when 8=>ht<=00000000;
when 9=>ht<=01000000;
when 10=>ht<=01111001;
when 11=>ht<=01000100;
when 12=>ht<=00110000;
when 13=>ht<=00011001;
when 14=>ht<= 00010010;
when 15=>ht<=01000000;
when 16=>ht<=01111001;
when 17=>ht<=01000100;
when others =>ht<=XXXXXXXX;
end case;
z<=conv_std_logic_vector(a,5) ;
end process;
end den_GT;

Thit k b m theo m Gray 4 bit hin th kt qu trn LED0LED3
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity demgray is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
y : out STD_LOGIC_VECTOR(3 downto 0)
);
end demgray;

--}} Copyright Thanh pham

architecture demgray of demgray is
begin
process(clk,rst)
variable x: integer range 0 to 15;
begin
if rst ='0' then x:=0;
else
if rising_edge(clk) then
if x=15 then x:=0;
else
x:=x+1;
end if;
end if;
end if;
case x is
when 0 =>y<="0000";
when 1 =>y<="0001";
when 2 =>y<="0011";
when 3 =>y<="0010";
when 4 =>y<="0110";
when 5 =>y<="0111";
when 6 =>y<="0101";
when 7 =>y<="0100";
when 8 =>y<="1100";
when 9 =>y<="1101";
when 10=>y<="1111";
when 11=>y<="1110";
when 12=>y<="1010";
when 13=>y<="1011";
when 14=>y<="1001";
when others =>y<="1000";
end case;
end process;
end demgray;