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Emerging Technologies in Nano-electronics Area

Adersh Miglani
In the semiconductor industry, miniaturization of features
is led by rapid improvements in integration, cost, speed,
power, compactness and functionality of integrated circuits.
These scaling improvements are largely inuenced by the
advancing research in nanotechnology. Research in nanotech-
nology inuence all stages starting from modication of atom
and modular structure to system and package level integrated
circuit, an end-product. Broadly interpreted, capabilities of
CMOS process should be augmented by devising new semi-
conductor devices which provides properties in addition to
traditional CMOS devices.
In this text
, we attempt to describe primarily the emerging
research in semiconductor devices which is primarily led
by the rise of the realm of nanotechnology. The CMOS
dimensional scaling techniques would end when current nan-
otechnology of 22 nm will scale to around 7 nm by 2020.
There are multiple techniques to further scale CMOS beyond
7 nm technology. Few important ones are discussed here.
With all those changes in the CMOS devices, the electrical
properties are altered and should be investigated in detail. Most
of the research in nanoscale MOSFET for CMOS is to alter
its channel to achieve scale improvements.
The compound semiconductor materials offering higher
mobility and higher quasi-ballistic-carrier velocity should re-
place strained silicon MOSFET channel and source and drain
region too. This impose few challenges such as heterogeneous
fabrication of selected materials for channel. Band-to-band
tunneling should be minimized due to narrow bandgap channel
materials. The dielectric interface between channel and gate
should not have Fermi level pinning. Since, these CMOS
gates scaled and doping concentrations are also altered, the
leakage current and power dissipation current should not be
The Ferroelectric FET (FeFET) has an integrated ferroelec-
tric capacitor within the gate stack. Due to this capacitance,
the charges in the channel modify the FET output charac-
teristics. Carbon Nanotube FETs (CNT FET) have highly
mobile charger carriers and minimum short channel effects.
Graphene Nanoribbon FETs has carrier mobilities higher than
CNT FET. The main problem in using graphene as transistor
channel is that it has zero bandgap energy. The bandgap energy
was increased by enabling carrier transport through graphene
nanoribbons with 2-nm width.
Another technique is to use semiconductor nanowire with
diameter 0.5 nm in place of established MOSFET channel.
The compound semiconductors from III-V and II-VI groups
Referred from ITRS http://itrs.net
can be used to form this nanowire. The off-chip interconnect
capacitance puts a limitation on the operating speed in circuits
designed using nanowire devices.
Use of III-V compound semiconductors has much better
electron mobility. These materials are right candidates for us-
ing as a n-type channel in MOSFETs. This impose a challenge
in hetro-integration on silicon substrate. Devices with these
changes are called heterostructure FETs (HFETs). Addition-
ally, low EOT gate dielectric and low resistivity junctions.
Germanium can also be used as channel in MOSFETs but this
reduces electron mobility. The bottleneck was high interface
state density near conduction band edge. This problem is xed
by using Ges oxide at the Ge-dielectric interface. Additional
efforts in reducing equivalent oxide thickness (EOT) and in
scaling gate-length are in progress.
The transition from I
to I
should be quick. This abrupt
transition is measured by low subthreshold swing limit at
the room temperature and controlled by thermal injection
of carriers from the source to the channel. Less than 60
mV/decade subthreshold, which is a limit for conventional
MOSFETs, is achieved in Tunnel FETs with gate reversed
biased p-i-n junctions. Therefore, Tunnel FETs can work with
lower V
which results in low power dissipation. Impact
ionized based FETs (IFET) has steeper I
to I
transition at room temperature.
Low operating voltage and power is achieved by replacing
insulator from MOSFET gate stack by ferrorlectric insulator.
This leads to subthreshold limit to below 60 mV/decade
without modifying physics in FET. Thus, higher I
levels are
achieved at lower voltages with suitable ferroelectric materials
with minimal hysteresis. The negative capacitance matching
with device capacitance shows steep subthreshold transition
is achieved with no hysteresis. Since, capacitance varies with
voltage, a thin double gate structure solve the purpose.
The number of choices to improve performance of MOSFET
include multiple gates in FET (FinFETs) and silicon-on-
insulator (SOI) MOSFET. Research on reducing equivalent
gate oxide thickness and on incorporating high-channel doping
to control short-channel effects are still in progress. These
techniques including ultra-thin body FD-SOI should be con-
sidered to improve planar MOSFETs.
The short term challenges are conned to scaling of Si
CMOS. The long term challenges comprise incorporating
advanced non-planar multi-gate MOSFETs with short gate
length, controlling short-channel effects, controlling parasitic
resistance involving source and drain and enhancing thermal
velocity and quasi-ballistic transport.