THE EVOLUTION OF ARCHITECTURE EXPLORATION

OF PROGRAMMABLE DEVICES
Jonathan Rose
The Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto
ABSTRACT
As integrated circuit fabrication processes continue to provide exponential increases in density of transistors with each
generation, the question of what to do with those transistors becomes ever more interesting. The most fundamental part of that
question is the global organization of the structures created from the transistors, most commonly referred to as the
*architecture* of the device.
Most IC architecture exploration that is done is quite empirical, with example uses driving through tools to experimentally
test new ideas for structures and organizations. This method is used in both programmable logic hardware such as FPGAs, and
in programmable instruction set processors. As the processor world now seeks to gain performance through parallelism, its
architecture questions have begun to look more similar to those in the FPGA domain.
In this talk I discuss the evolution of the architecture exploration processes that we have worked on at the University of
Toronto, and of the new levels that we are currently trying to build. The current effort focusses on HDL-level circuits as
"example uses" and this turns out to be rather intricate in the face of the kinds of architecture questions that could be posed. In
the future, it may well be that some form of software is the input "example use," thus bringing the processor and FPGA world
closer together. For this to work, there needs to be an effective CAD/compiler flow from software to the HDL level. I will give
perspective on the state of this art, and discuss what kind of commonality might evolve in architecture exploration tools for
FPGAs and processors.
BIOGRAPHY
Jonathan Rose is a Professor in the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the
University of Toronto . He received the Ph.D. degree in Electrical Engineering in 1986 from the University of Toronto. From
1986 to 1989, he was a Post-Doctoral Scholar and then Research Associate in the Computer Systems Laboratory at Stanford
University. In 1989, he joined the faculty of the University of Toronto. He spent the 1995-1996 year as a Senior Research
Scientist at Xilinx, in San Jose, CA, working on the Virtex FPGA architecture. From 1989 until 1999 he was an NSERC
University Research Fellow.
He is the co-founder of the ACM FPGA Symposium, and remains part of that Symposium on its steering committee. In
October 1998, he co-founded Right Track CAD Corporation, which delivered architecture for FPGAs and Packing,
Placement and Routing software for FPGAs to FPGA device vendors. He was President and CEO of Right Track until May
1, 2000. Right Track was purchased by Altera, and became part of the Altera Toronto Technology Centre, where Rose was
Senior Director until April 30, 2003. His group at Altera Toronto shared responsibility for the development of the
architecture for the Altera Stratix, Stratix II, Stratix GX and Cyclone FPGAs. His group was also responsible for placement,
routing, delay annotation software and benchmarking for these devices, and for the placement and routing software for the
Altera Apex 20K and Flex 10K FPGAs. From May 1, 2003 to April 30, 2004 Rose held the part-time position of Senior
Research Scientist at Altera Toronto. He has worked for Bell-Northern Research and a number of FPGA companies on a
consulting basis.
He served as Chair of the Edward S. Rogers Sr. Department of Electrical and Computer Engineering from January 2004
through June 2009. A paper co-authored with Steve Brown won a distinguished paper award at the 1990 ICCAD
Conference. He is a Senior Fellow of Massey College in the University of Toronto, a Fellow of the IEEE, and a Fellow of
the ACM, and a Fellow of the Canadian Academy of Engineering.
His research covers all aspects of FPGAs including their architecture, Computer-Aided Design (CAD), Field-
Programmable Systems, Soft Processors, and graphics, vision and bio-informatic applications of programmable hardware.
978-1-4244-3892-1/09/$25.00 2009 IEEE 3