XUPV5-LX110T Bord !"U#$E DE$!#%PT%"& Embedded Systems Development brings experienced FPGA designers up to speed on the capabilities and characteristics of the Xilinx Microla!e" #$%bit soft processor core and the Embedded Development &it 'ED&( design environment) Developing embedded systems using the Microla!e and a set of soft peripherals is also included in the lectures and labs) 1' %ns(ll Xilin) so*(wre Professors may submit the online donation re*uest form at +++)xilinx)com,univ to obtain the latest Xilinx soft+are) -he +or.shop +as tested on a P/ running MicroSoft 0indo+s XP professional edition) Debug is verified using hyperterminal) 122)$ ED& 122)$ 3SE Foundation Soft+are 122)$ /hipscope%Pro +' $e(,p hrdwre /onnect X4P15%6X227- oard a. /onnect programming cable bet+een configuration port of X4P15%6X227- oard and P/ b. /onnect 8S$#$ serial cable bet+een X4P15%6X227- oard and P/ serial ports c. /onnect the po+er supply and po+er on the board 3. %ns(ll dis(rib,(ion 4n!ip on your P/ according to the listed directory structure a) 6ecture slides 'slides)!ip(9 :embedded:slides b) 6ab exercises 'labdocs)!ip(9 :embedded:labdocs c) 6ab solutions 'solutions)!ip(9 :embedded:solutions d) 4ser source files 'source)!ip(9 :embedded:source e) S support pac.age 'Xilinx;X4P15;6X227-)!ip(9 <ED&;3nstall;Directory=: board:Xilinx:boards: -' .e( $(r(ed 8evie+ the presentation slides 'see course agenda( and step through the lab exercises 'see lab descriptions( to complete the labs) 5' Version $pe/i*i/ %n*orm(ion 3n version 22)$ of the soft+are tools> the debug feature of SD& does not +or. properly unless couples of patches are made to the installation) ?btain and apply first patch using http9,,+++)xilinx)com,support,ans+ers,#$@5@)htm and then obtain and apply second patch using http9,,+++)xilinx)com,support,ans+ers,##7A@)htm lin.s) README !"U#$E 0.E&D0 Day 1 Agenda Day 1 Materials /lass 3ntro 22;class;intro)ppt ED& ?vervie+ 2$;ed.;overvie+)ppt 6ab 29 asic Bard+are Design 2$a;lab2;intro)ppt 6ab2)doc Bard+are Design 2#;hard+are;design)ppt Bard+are Design 4sing ED& 2C;B0;design;ed.)ppt 6ab $9 Adding 3P to a Bard+are Design 2Ca;lab$;intro)ppt 6ab$)doc Adding Dour ?+n 3P to the ?P us 25;adding;ip)ppt 6ab #9 Adding /ustom 3P 25a;lab#;intro)ppt 6ab#)doc Day 2 Agenda Day 2 Materials Soft+are Development %asic $2;soft+are;design;basic)ppt Soft+are Development %Advanced $$;soft+are;design;advanced)ppt 6ab C9 0riting asic Soft+are Application $$a;labC;intro)ppt 6abC)doc Address Management $#;address;management)ppt Soft+are Development and Debug using SD& $C;debug)ppt 6ab 59 Advanced Soft+are 0riting $Ca;lab5;into)ppt 6ab5)doc 6ab A9 /ross Debug $Cb;labA;intro)ppt 6abA)doc LAB DESCRIPTIONS 6ab 2 % asic Bard+are Design9 /reate an XPS proEect using ase System uilder to develop a basic system for a target board) 6ab $ % Adding 3P to a Microla!e Design9 6earn to add 3P such as bridges> P6 peripherals> P6 bus> and others to the basic hard+are design) 6ab # % Adding /ustom 3P9 Explore adding a custom 3P to your design> using the /reating,3mporting Peripheral 0i!ard) 6ab C % 0riting asic Soft+are Application9 0rite a basic / application that utili!es the 4A8- and GP3?) 6ab 5 % Advanced Soft+are 0riting9 4se the XPS -imer and the interrupt service routine) 6ab A % 1erification9 Perform cross debug +ith /hipscope%Pro and GD debugger via SD& 1' !on(/( XUP Send an email to xupFxilinx)com for *uestions or comments