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6.1 Introduction

Ch6 CMOS Inverters:

Switching Characteristics and Interconnect Effects I CMOS Inverters – Dynamic Analysis and Design

Goals

Understand the detail dynamic analysis of the CMOS inverter.

Understand one set of design from CMOS equations.

Understand the basic CMOS design process using the CMOS static and CMOS design form dynamic equations.

CMOS Dynamic Analysis: Capacitance Model for CMOS V DD Cgs,p
Csb,p
Cdb,p
V
V
in
Cgd,p
out
Cgd,n
FO
Cdb,n
Cint
Cg
Cgs,n
Csb,n

3 Fig. 6.1 Cascoded CMOS Inverter stages

CMOS Dynamic Analysis: Capacitance Model for CMOS The aggregate capacitance driven by the output node of a CMOS inverter is in detail working from left to right,

C load = C input + C int + C g

in which

C input = C gd,n + C gd,p + C db,n + C db,p (intrinsic

component)

C int = interconnect capacitance C g = thin-oxide capacitance over the gate area

(extrinsic component)   CMOS Dynamic Analysis: Delay-Time Definitions Vin Vout
τ PHL
τ PLH

idealized

step input

VOH

V50%

VOL

VOH

V50%

V 50 % = V OL +(V OH -V OL )/2

. = (V OH +V OL )/2

 t τ PHL = t 1 -t 0 τ PLH = t 3 -t 2 τ P = (τ PHL +τ PLH )/2 t Fig. 6.3 V 10% = V OL +0.1(V OH -V OL ) V 90% = V OL +0.9(V OH -V OL ) τfall = t B -t A t τrise = t C -t D

Fig. 6.4

VOL t0
t1
t2
t3
Vout
τ fall
τ rise
V90%
V10%
tA
tB
tC
tD

6

6.3 Calculation of Delay Times CMOS Dynamic Analysis Delay-Time Calculation (First Order Estimates) The simplest approach of calculating the propagation delay is based on estimating the average capacitance current during charge down/up.

7

where

I

I

avg HL

,

avg LH

,

=

=

1

2

1

2

[

(

i V

C

in

[

(

i V

C

in

=

=

τ PHL

τ PLH

=

=

( V

OH

V

50%

)

I

( V

avg HL

,

)

V

OL

50%

I

avg LH

,

V

OH

,

V

out

=

V

)

OH

+

i ( V

C

in

V , V

OL

out

=

V

50%

)

+

i ( V

C

in

=

=

V

OH

,

V

out

V , V

OL

out

=

=

V

50%

)

)]

V

OL

]

CMOS Dynamic Analysis Delay-Time Calculation (More Accurate)(1/4) The propagation delay can be found more accurately by solving the state equation of the output node. The current flowing through C load is a function V out as

dV

out

C

out

C

out

dt

dV

dt

= i =

C

out

i

D p

,

= i =−

C

i

D n

,

i

D n

, i D,p
i
C
V in
i D,n

V

out

τ PHL : PMOS is off. The equivalent circuit during high-to-

low output transition is

8

V in i D,n
nMOS V out

Fig. 6.5

CMOS Dynamic Analysis: Delay-Time Calculation (2/4) The nMOS operates in two regions, saturation and linear, during the interval of τ PHL . τ
P HL
V out
V OH =V DD
V OH -V T,n
nMOS in saturation
nMOS in linear region
V 50%
t
t 0
t 1
t 1 ’
Fig. 6.6

Saturation Region

i D,n =(k n /2)(V in -V T,n ) 2 =(k n /2)(V OH -V T,n ) 2

» Plug i D,n into C load dV out /dt=-i D,n , and integrate both sides, we get

9

t 1 -t 0 = 2C load V T,n /[k n (V OH -V T,n ) 2 ]

CMOS Dynamic Analysis: Delay-Time Calculation (3/4) Linear Region i D,n = (k n /2)[2(V in - V T,n )V out - V out 2 ] = (k n /2)[2(V OH - V T,n )V out - V out 2 ]

»Plug i D,n into C load dV out /dt=-i D,n , and integrate both

sides, we have

t

1

'

t =

1

C

4( V

DD

V

T n

,

)

κ

n

(

VV

DD

T n

,

)

V

50%

ln

τ

P

HL

=

C

2 V

T n

,

4(

VV

DD

T n

,

)

κ

n

(

VV

DD

T , n

)

VV

DD

T , n

+− ln

V

D D

1

⎞⎤

⎠⎦ ⎟⎥ • Finally, since V OH =V DD and V OL =0, we have
Vout
τ PHL
VOH
nMOS in saturation
VOH -VT,n
nMOS in linear region
V50%
t Fig. 6.6
10
t 0
t 1 ’
t 1

CMOS Dynamic Analysis: Delay-Time Calculation (4/4) τ PLH : NMOS is off. The equivalent circuit during low-to-

high output transition is

V in V DD pMOS
i
D,p
V out • With the similar way (t 0 →t 1 ’ →t 1 ∕0→|V T,p |→V 50% ∕
saturation → linear ), we can have
2
⎛ 4(
)
C
V
VV
T p
,
DD
T p
,
τ
=
+− 1 ⎟ ⎥
ln ⎜
P L H
κ
(
VV
)
VV
V
11
p
DD
T p
,
D D
Tp
,
D D
⎠ ⎦

6.4 Inverter Design with Delay Constraints CMOS Inverter Design Design for Performance

12

Keep capacitance small

Increase V DD   CMOS Inverter Design: Delay as a Function of V DD V DD increases τ PHL /τ PLH decreases. However, the power consumption also increases. 5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
τ pHL (normalized)

14

V DD (V)

CMOS Inverter Design: Device Sizing (1/5) 15 x 10 -11
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.
2
4
6
8
10
12
14
0
S
τ
p (sec)

Intrinsic capacitances dominate

CMOS Inverter Design: Device Sizing (2/5) NMOS/PMOS Ratio

-11

x 10 5
τ
τ
4.5
PLH
PHL
4
τ
P
3.5
3
1
1.5
2
2.5
3
3.5
4
4.5
5
R
τ p (sec)

16

R = W p / W n

CMOS Inverter Design: Device Sizing (3/5) small  C load = C gd,n (W n ) + C gd,p (W p ) + C db,n (W n ) + C db,p (W p ) + C int +C g

= f(W n ,W p )

• Using the junction capacitance expressions in Chapter 3, we have

C db,n = (W n D drain +x j D drain )C j0,n K eq,n +(W n +2D drain )C jsw,n K eq,n

C dp,n = (W p D drain +x j D drain )C j0,p K eq,p +(Wp+2D drain )C jsw,p K eq,p

• Therefore, C load can be rewritten as

where

C load = α 0 + α n W n + α p W p

α 0 = D drain (2C jsw,n K eq,n +2C jsw,p K eq,p +x j C j0,n K eq,n +x j C j0,p K eq,p )+C int +C g

α n = K eq,n (C j0,n D drain +C jsw,n )

α p = K eq,p (C j0,p D drain +C jsw,p )

17

CMOS Inverter Design: Device Sizing (4/5) 18

Therefore, τ PHL and τ PLH are +
+
α
4 (
)
αα
⎞⎤
W ⎞
L
V
− V
0
nn W
p
p
n
T , n
DD
T , n
τ
=
×⎜ ⎜
⎟×+⎢ 2 V −
ln
−⎟⎥ 1 ⎟
PHL
μ
(
V
)
W
n ⎠
CV
V
V
V
n
ox
DD
T n
,
⎠ ⎟
⎣ ⎢
DD
T n
,
⎝ ⎜ ⎜
DD
⎠⎥ ⎦
⎛⎞
+
+
2
4
(
)
α α
W n
L
V
V
V
0
n
α pp W
T , p
DD
T , p
p
τ
= ⎜
× ⎜
⎟ ×+
ln ⎜⎟
− 1
P LH
W
μ
(
)
CV
VV
⎜⎟ ⎥
V
p
DD
T , p
DD
n
ox
DD
V T p
,
⎠⎝
• The ratio between the channel widths W n and W p is
usually dictated by other design constraints such as
noise margins and the logic inversion threshold.
Let’s this transistor aspect ratio be defined as R ≣
W p /W n . Then, the propagation delay can be
represented as
αα
+
(
+
R
α
)
W ⎞
0
n
pn
τ
=
Γ
PHL
n
W
n ⎠
α
n
α
0 +
(
+
α
)
W p
p
R
=
Γ
τ PLH
p
W
p

CMOS Inverter Design: Device Sizing (5/5) As we continue increase the values of W n and W p , the propagation delay will asymptotically approach a limit value for lager W n and W p ,

limit

τ PHL

τ limit P L H

=

=

Γ

n

(

α

n

+

R

α

p

Γ

p

α

(

n

R

+

α

p

)

)

The propagation delay times cannot be reduced beyond the above limits, and the limit is independent of the extrinsic capacitances.

19

CMOS Inverter Design: Impact of Rise Time on Delay  0.35
0.3
0.25
0.2
0.15
0
0.2
0.4
0.6
0.8
1
τ
pHL (n ecs
)

20

τ PHL

τ P LH

τ rise (nsec) 2
2
()
τ
r
τ
+
= PHL (step input)
2
2
2
()
τ
f
τ
+
= PLH (step input)
2

Propagation delay increases

since both PMOS and

NMOS are on during the

charge-up and charge-down events.

CMOS Inverter Design Impact of Channel Velocity Saturation The drain current is linearly dependent on V GS

I sat = κW n (V GS -V T )

Propagation delay only has a weak dependence on the supply voltage V DD

21

τ

PH L

C V

50%

I

sat

=

C

(

V

DD

/2

)

(

W V V

κ

n

D D

T

)

CMOS Dynamic Analysis: Dynamic Power Dissipation (1/2) The dynamic power dissipation can be derived as follows.

P dyn,avg = V DD I DD,avg

With I DD,avg taken over one clock period T. The capacitance current which equals the current from the power supply (assuming I Dn = 0 during charging) is

I

D

=

dV out

dt

C

Rearranging and integrating over one clock period T

Gives

22

T

I

0

D

dt =

V

0

DD C dV

out

I DD,avg T = C load V DD

CMOS Dynamic Analysis: Dynamic Power Dissipation (2/2) Solving for I DD,avg and substituting in P avg :

Pavg

=

1

T

C V

2

=

C V

2

f

In terms of SPICE simulation, the authors offer a circuit called power meter.

It should be noted here the our simple Cload may underestimate the power dissipated.

In terms of SPICE simulation, it offers a circuit called power meter.

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