Learning Objectives:: Topic 2.2 - Sequential Systems. 2.2.2 - Binary Counters

Topic 2.2 Sequential Systems.
2.2.2 Binary Counters

Learning Objectives:
At the end of this topic you will be able to;
explain, and illustrate, how a D-type flip-flop can be set up to produce
a divide-by-two function;
complete timing diagrams for a 1-bit counter;
sho ho to !"type #lip"#lops can be connecte$ together to
#orm a 2"bit binary up counter%
complete timing $iagrams #or a 2"bit counter%
realise that counters are available in a number of formats e.g.
up/down, binary/!D/decade;
design and analyse simple systems that use a counter and
combinational logic to produce a se"uence of events;
ma#e a counter reset at a given value.
1
D Q
Q
!loc#
$nput
%utput
CK
&CS' 'lectronics.
(nit '2 : )pplications o# 'lectronics
%ften we need to count events, such as the number of boxes moving along a
conveyor belt or the number of cars entering a car par#. &e can use
electronic counters to perform the counting.
&e have already loo#ed at the D-'ype flip-flop being used(
for data transfer
as a latch
$n this section we will examine how the D-'ype can be used to ma#e a
counting system. )irst, we adapt it to produce a divide-by-two function. &e
show later that this is an important part of electronic counting.
Con#iguring the !"Type #lip"
#lop to pro$uce a $ivi$e"by"
to #unction
*otice that the only connection is the lin# between
Q
and D.
A pulse generator is connected to the cloc# input.
2
$nitially, Q and !loc# are at logic +, and
Q
, and D at logic 1. 'he timing
diagram follows(
,emember( changes occur only on the rising edge of the cloc# pulse, and then
the value of D is copied to Q.
3
Q
Clock
D
1 2 3 4
Q
&CS' 'lectronics.
At the first rising edge -1., input D is at logic 1, since it is connected to
Q
.
'his changes the Q output to logic 1, and so
Q
-and hence D. change to logic
+.
'he outputs remain li#e this until the next rising edge of the cloc# -/..
4
Q
Clock
D
1 2 3 4
Q
'he D input is now at logic +, which is copied to the output Q. 'his causes
Q

-and D. to change to logic 1 as shown below.
0ou should now start to see a pattern emerging in the diagram1
5
Q
Clock
D
1 2 3 4
Q
&CS' 'lectronics.
At the next rising edge -2., the logic 1 present on the D input which is copied
to the output Q, and so
Q
-and D. change to 3ogic + as shown below.
6
Q
Clock
D
1 2 3 4
Q
At the next rising edge -4., there is now a logic + present on the D input. 'his
is copied to the output Q, and
Q
-and D. change to logic 1 as shown below.
'his pattern would continue in the same way for further cloc# cycles.
*otice that the output from Q has exactly half the fre"uency of the cloc#
pulse, so this circuit could also be used as a simple fre"uency divider - the
divide-by-two function.
'he divide-by-two action forms the basic building bloc# of a binary counter.
Another name for this circuit is a *"bit counter.
7
Q
Clock
D
1 2 3 4
Q
!loc#
$nput
%utput A
D
A
Q
A
A
Q
D
B
Q
B
B
Q
%utput
CK CK
&CS' 'lectronics.
) 2"bit binary up counter
'wo 1-bit counters can be 5oined together as shown below to form a /-bit
binary up counter(
*otice that the cloc# input of the second counter is connected to the
Q

output of the first. 'he timing diagram for this system is shown opposite.
8
$nitially Q
A
and Q
B
are at logic +, Clock In 6 logic +, A
Q
6 D
A
6 logic 1, B
Q
6 D
B
6 1.
9
A
Q
Q
A

D
A
Clock In
1 3 4 2
D
B
Q
B
B
Q
&CS' 'lectronics.
At the first rising edge of Clock In -1. 7
D
A
6 logic 1 and so Q
A
becomes logic 1,
and so A
Q
becomes +.
*o change to Q
B
, as the cloc# input to flip-flop has gone from logic 1
to logic +, a falling edge
10
Q
A

D
A
Clock In
1 3 4 2
D
B
Q
B
A
Q
B
Q
At the second rising edge of Clock In -/. 7
Q
A
becomes logic +, since D
A
was logic +.
A
Q
is the opposite of Q
A
and so becomes logic 1,
Q
B
becomes logic 1 as the cloc# input to flip-flop has gone from logic +
to logic 1, a rising-edge, which copies D
B
to Q
B
.
11
Q
A

D
A
Clock In
1 3 4 2
D
B
Q
B
A
Q
B
Q
&CS' 'lectronics.
At the third rising edge of Clock In -2. 7
Q
A
becomes logic 1, since D
A
was logic 1,
A
Q
becomes +,
Q
B
remains logic 1 as the cloc# input to flip-flop B went through a falling-
edge.
12
Q
A

D
A
Clock In
1 3 4 2
D
B
Q
B
A
Q
B
Q
At the fourth rising edge of Clock In -4. 7
Q
A
A
was logic +,
A
Q
becomes 1,
Q
B
copies D
and changes to logic + as the cloc# input to flip-flop B has

gone from logic + to logic 1, a rising-edge.
13
Q
A

D
A
Clock In
1 3 4 2
D
B
Q
B
5 6
A
Q
B
Q
&CS' 'lectronics.
At the fifth rising edge of Clock In -8. 7
Q
A
becomes logic 1, since D
A
6 logic 1,
A
Q
becomes +,
Q
B
remains at logic + as the cloc# input to flip-flop B has gone from
logic 1 to logic +, a falling-edge.
14
Q
A

D
A
Clock In
1 3 4 2
D
B
Q
B
5 6
A
Q
B
Q
At the sixth rising edge of Clock In -9. 7
Q
A
A
6 logic +,
A
Q
becomes 1,
Q
B
changes to logic 1 as the cloc# input to flip-flop B has gone from
logic + to logic 1, a rising-edge.
15
Q
A

D
A
Clock In
1 3 4 2
D
B
Q
B
5 6
A
Q
B
Q
&CS' 'lectronics.
)or further cloc# pulses, it is simply a case of repeating the patterns as
follows.
3oo#ing at the values of :
and :
A
after each cloc# pulse shows us that we
are counting up in binary(
inary +1 1+ 11 ++ +1 1+
count
16
Q
A

D
A
Clock In
1 3 4 2
D
B
Q
B
B
Q
5 6
A
Q
$n the example we have 5ust loo#ed at, there were a lot of graphs drawn but
there was really no need to draw them all. 3oo# at the final graphs.
*otice(
i. 'he D
x
input graphs are identical to x
Q
graphs so one of them could be
removed.
ii. Q
B
changes on the falling edge of Q
A
-which is the rising edge of A
Q
.
iii. 'he output at Q
B
is half the fre"uency of Q
A
, or a "uarter of the
fre"uency of the cloc#, so the counter is a very good fre"uency divider.
&e have made a /-bit counter, with A as the least significant bit, because it
changes the most fre"uently, and B the most significant bit.
17
Q
A

Clock In
1 3 4 2
Q
B
5 6
&CS' 'lectronics.
)ctivity * : To investigate a *"bit counter
1a. ;et up the circuit shown below.
1b. As# for a circuit chec#. $f approved, switch on the power supply. $n this
activity we use a push switch to simulate cloc# operation. 'he switch is
outputs logic level + until pressed.
1c. $f the : indicator is on, then press the cloc# push switch to switch it
off .
<se the switch to generate the se"uence shown in the table. )ill in the
: output level in each case. =>? indicates a press and =,? a release of the
pulse button.
18
1d. Assume that you provide the cloc# pulses, shown below. )ill in the
corresponding : output levels.
1e. 0our graph should show that the : output changes its state with every
rising edge of the cloc# pulse.
'he : output only changes to logic 1 on the odd numbered -decimal.
cloc# pulse. 'he circuit is effectively dividing by /. 'his forms the basis
of a binary counter.
)ctivity 2:
/a. @odify your circuit to the one shown below. 'he switch is now
connected to the reset input of the D-'ype.

;witch on the simulation. 'he cloc# indicator 3AD and the output
indicator 3AD should be flashing.
/b. &hen the push switch is pressed, the output of the D-'ype will go to
logic + and the output 3AD will be off.
19
&CS' 'lectronics.
/c. &hen the cloc# 3AD is off release the switch and count 1+ cloc# pulses
while a partner counts the number of times the : output indicator
comes on during this interval. ,ecord the value in following table. ,epeat
for the other values given.
*umber of cloc# pulses. *umber of output pulses -:.
1+
/+
2+
4+
!omment on your result.
......................................................................................................................................
......................................................................................................................................
......................................................................................................................................
......................................................................................................................................
......................................................................................................................................

20
)ctivity +: To investigate a 2"bit up counter
2a. &e will now use the
Q
output from the first flip-flop to act as a cloc#
input for the second flip-flop on a 4+12 D-'ype.
2b. ;et up the circuit as shown below.
2c. As# for a circuit chec#. $f approved, start the simulator. 0ou should
now have a binary counter that counts up to 11 -binary. then resets to
Bero.
2d. >ressing the push switch at any time during the counting se"uence will
reset both D-'ype flip-flops and stop the count ta#ing place.
21
&CS' 'lectronics.
)ctivity ,: To investigate a 2"bit $on counter
4a. $n activity 2 you made a /-bit up counter. 0ou are now as#ed to ma#e a
down counter.
!omplete the following table by filling in the values for the
Q
outputs.
2
Q
1
Q
2
Q
1
Q
+ +
+ 1
1 +
1 1
4b. )illing in the table should give you a clue as to how to set up a
/-bit down counter.
!omplete the following diagram to show a down counter.
4c. ;how your diagram to
your teacher. $f
approved, set it up and try it out.
4d. Did you have to ma#e any modifications to your design. $f so, what were
theyC
......................................................................................................................................
22
......................................................................................................................................
......................................................................................................................................
$f you made modifications draw the correct version of your circuit in
the space below.
23
&CS' 'lectronics.
-omeor. /uestions *
1. A D-type flip-flop can be used to ma#e up a counter. 'he following bloc#
diagram shows the basic outline re"uired to build a two bit binary up
counter from two D-'ype flip flops. Dowever three connections are
missing.
a. !omplete the diagram by adding the missing connections.
[3]
b. !omplete the following timing diagram for a / bit counter. Assume
the flip-flops are rising edge triggered.
E2F
24
c. Draw a diagram to show how you could use 2 D-'ype flip-flops to
ma#e a 2 bit binary down counter.
E4F
25
&CS' 'lectronics.
Counter 0Cs
$n the previous section we made a simple 1-bit counter and extended it to /-
bits, and then 2-bits. $n principle we could #eep adding D-type flip-flops to
extend the counter to 8, 9, G or H bits. $n practice, this re"uires a lot of
connections, which ta#e up a lot of space in a circuit.
$nstead, these counters are available as single chip devices called counter
$!s.
A / bit counter is probably easier to build from D-type flip-flops. )or 2 bits
or more, counter $!s will be more suitable, as fewer connections will need to
be made.
'he circuit symbol for a 4-bit counter $! is as follows(
*otice(
i. the single cloc# input.
ii. the outputs A, B, C, D, with A the least significant bit.
iii. the C
out
terminal which provides a cloc# pulse to a second counter
should more bits be needed.
iv. the reset terminal which is active lo, i.e. a logic + causes the
counter to reset. -Alternatively if the reset terminal is labelled 1
then it is active high2 i.e. a logic 1 is needed to cause the counter to
reset.
26
A B C D
C
out
R
CK
'he output of a 4 bit binary counter is shown below.
0nput Binary Output
'vent 3o: ! C B )
+ + + + +
1 + + + 1
/ + + 1 +
2 + + 1 1
4 + 1 + +
8 + 1 + 1
9 + 1 1 +
G + 1 1 1
H 1 + + +
I 1 + + 1
1+ 1 + 1 +
11 1 + 1 1
1/ 1 1 + +
12 1 1 + 1
14 1 1 1 +
18 1 1 1 1
19 + + + +

'he binary digit in the =A? column is referred to as the least significant bit
-3;., it is the one that changes the most often.
'he binary digit in the =D? column is referred to as the most significant bit
-@;., it is the one that changes the least often.
27
&CS' 'lectronics.
Types o# Counter
'he number of bits -binary digits. in the counter determines the highest
number it can count up to before resetting. A 4-bit counter can count from +
-18 in binary whereas an H-bit counter can count from + to /88 in binary.
Different varieties of counter are available( - up, down, up/down, rising edge
triggered, falling edge triggered, binary coded decimal -!D., decade
counters etc. !D and Decade counters are covered in our next topic. 'he list
provided here should help you when choosing one for your practical wor#.
;ometimes we need a counter that counts only up to five or six for example.
$n this case we need to apply an external reset to the $!. As# yourself; what
is the biggest number that we want to be displayed before the reset ta#es
placeC
3et?s have a loo# at an example to illustrate this.
&hat is the biggest number that can be displayed on the following system C
28
A B C D
C
out
R
a
b
c
d
e
f
g
Decoder /
Driver
'he inputs to the *A*D gate, come from counter outputs and !. 'he
output of the *A*D gate goes to logic +, and resets the counter, only when
both outputs go to logic 1. 'he first time this happens is when the count
reaches +11+ in binary -i.e. decimal 9., is the first occasion when the and !
outputs are high at the same time.

'he output of the *A*D gate changes to logic +, approximately 8
nanoseconds later -that?s about 8 thousand millionth?s of a second1., the
counter resets, outputting =++++?, all in the space of a few nanoseconds.
'he effect this has on the display is that it does not have time to show the
number 9

before it is reset to Bero. 'he se"uence shown on the display will
be, +, 1, /, 2, 4, 8, +, 1, / etc.
'he following example shows a similar system, but using a counter with an
active high reset. &hat is the largest number displayed in this caseC
'he correct answer is decimal H. 'he counter resets when outputs A and D
are on, this corresponds to a counter output of binary 1++1, which is I in
decimal, so the last number displayed will be one less than this, i.e. H.
29
A B C D
C
out
R
a
b
c
d
e
f
g
Decoder /
Driver
&CS' 'lectronics.
*ote( &ith a counter that resets on an active high -logic 1. signal, no logic
gate is needed when you want it to count up to 2 and reset on 4 or count up to
G and reset on H. 'he reset can be ta#en directly from the !, or D output
respectively as shown below.
'his arrangement causes the counter to count in the following se"uence(
++++, +++1, ++1+, ++11, ++++, +++1, etc
Beare: 0# the counter resets ith an active lo 4Logic 56 signal an$ you
ant to count up to + or 7 then a 3OT gate ill be nee$e$ beteen the
C an$ ! output an$ the R input.
)or the rest of this section we will concentrate on the up counter described
earlier, based on the !@%; 4819 inary counter.
30
A B C D
C
out
R
a
b
c
d
e
f
g
Decoder /
Driver
)ctivity 8: To investigate a ,"bit binary counter 0C 4,8*96
8a. ;et up the following circuit.

8b. ;tart the simulation and operate the switch =;&1? several times.
0ou should observe that the led?s light up in different patterns each
time the switch is pressed.
8c. Jeep pressing the switch =;&1? until all the 3AD?s are off.
31
&CS' 'lectronics.
8d. !omplete the table below by copying down the state of the 3AD?s each
time the push switch =;&1? and then released.
*o. of
>resses
;tate of
3ADs
+ + + + +
1 + + + 1
/
2
4
8
9
G
H
I
1+
11
1/
12
14
18
19

8e. @odify your circuit so that the switch input to the cloc# is replaced
with a pulse generator set at 1DB as shown below.
32
8f. %bserve the counter, counting up to 1111 -binary. then resetting to Bero
before repeating the count.
8g. *ow ma#e a further modification to bring the ,A;A' function into
operation, as shown below.
8h. $nvestigate what happens when =;&1? is pressed and released when the
counter is running and the 3ADs are coming on.
!omment( ....................................................................................................................
........................................................................................................................................
8i. $nvestigate what happens when =;&1? is pressed and held on when the
counter is running and the 3ADs are coming on.
!omment( ....................................................................................................................
........................................................................................................................................
33
&CS' 'lectronics.
1esetting the counter automatically
0ou should have observed that when =;&1? is pressed the counter resets and
starts counting again. 'he counter will not respond when the reset pin is at
logic 1. %nce the reset pin is returned to logic +, counting continues.
$n the next activity, we ma#e use of this feature to change the maximum
count of the counter.
)ctivity 9 : 1esetting a binary counter
9a. ;et up the following circuit.
9b. ,un the simulation and watch the 3ADs carefully. &hat is the count
se"uence nowC
...................................................................................................................................
...................................................................................................................................
...................................................................................................................................
9c. 3ogic gates can be used in various combinations to reset the counter on
any number to suit the application involved.
34
Combining Counters an$ Logic Circuits
%ne of the most common uses for counters is to automate certain electronic
systems that have a continuously repeating pattern, e.g. traffic lights. $n this
final section of this topic we use a combinational logic circuit lin#ed to a cloc#
and counter to produce these fully automatic systems.
An Automatic 'raffic 3ight Display(
'he traffic light se"uence is as follows.
'o design the system we proceed in the following way.
;'A> 1(
&e decide how many output displays we re"uire. $n this case it is three
-,AD, A@A,, K,AA*.
;'A> /(
&e decide how many inputs the logic system re"uires. 'here are four
different settings of outputs. 'o provide these, we need / inputs.
35
&CS' 'lectronics.
;'A> 2(
&e now form a truth table for the logic system. 'he inputs come from
the two least significant bits of a binary counter, and A. 'he traffic
light se"uence is given in the table(
0nputs Outputs
B ) 1e$ )mber &reen Commentary
+ + 1 + + ,ed %nly
+ 1 1 1 + ,ed and Amber
1 + + + 1 Kreen %nly
1 1 + 1 + Amber %nly
%ur system is shown in the following diagram(
&hen 6 + and A 6 +, the ,AD only is to be on -row 1..
&hen 6 + and A 6 1, the ,AD A*D A@A, are on -row /..
&hen 6 1 and A 6 +, the K,AA* only is to be on -row 2..
&hen 6 1 and A 6 1, the A@A, only is to be on -row 4..
36
;'A> 4(
&e now loo# at the logic functions needed for each output.
i. 'he ,AD output is the inverse of the input, and therefore
ii. 'he A@A, column is the same as the A input.
iii. 'he K,AA* is only on when A is *%' 1 -i.e. +. A*D 6 1. 'his
could be written down in oolean notation as follows.
'he logic circuit for the green would be made up as follows.
;'A> 8(
&e now #now which logic gates are needed to produce the outputs.
&e can draw the full logic system.
37
&CS' 'lectronics.
;'A> 9(
Adding a counter and cloc# to the logic system gives the full circuit diagram(
*otice that we only need the / least significant bits of the 4-bit counter.
38
!esigning Simple Sequential Logic Systems
)ctivity 7: Tra##ic light system
*ow consider the same se"uence starting with the K,AA*.
$t follows the se"uence given below(
Ga. Dow many output displays are re"uired C ......................
Gb. Dow many different output patterns are re"uired C .........................
Dow many inputs are re"uired to cover this number of combinationsC .....
Gc. !omplete the following truth table.
$nputs %utputs
A ,ed Amber Kreen
+ + Kreen %nly
+ 1 Amber %nly
1 + ,ed %nly
1 1 ,ed and Amber
Gd. i. ;tudy the ,AD column. $s it the same, or the inverse, of an inputC
!omplete the oolean expression for the ,AD.
,AD 6 ................................................................
39
&CS' 'lectronics.
ii. ;tudy the A@A, column and complete its oolean expression.
A@A, 6 ................................................
iii. ;tudy the K,AA* column and then complete its oolean
expression.
K,AA* 6 ................................................
Ge. Draw a diagram for the logic system using A*D, %, and *%' gates.
Gf. Add a counter to your system so that it will automatically step through
all four states continuously. !omplete the circuit diagram of your
solution in the space below(
Gg. !hec# your circuit then set it up and try it out.
Describe any modification you had to ma#e. .............................................
................................................................................................................................
................................................................................................................................
40
)ctivity :: !isco Lights
Design a system to produce the following se"uence of lights.
Ha. Dow many outputs are re"uired C .......................
Hb. Dow many different output patterns are re"uired C ......................
Dow many inputs are re"uired to generate this number of combinationsC
LLLLL
41
&CS' 'lectronics.
Hc. !omplete the following truth table.
$nputs %utputs
A M 0 N
+ + *o 3ights on
+ 1

1 +

1 1

Hd. i. ;tudy the M %utput column and complete the oolean expression
for the M %utput.
M 6 .......................................................
ii. ;tudy the 0 %utput column and complete its oolean expression.
0 6 .......................................................
iii. ;tudy the N %utput column and then complete its oolean
expression.
N 6 .......................................................
He. Draw a diagram for the logic system using A*D, %, and *%' gates.
42
Hf. Add a counter to your system so that it will automatically steps through
all four states continuously. !omplete circuit diagram of your solution in
the space below
Hg !hec# your circuit then set it up and try it out.
Describe any modification you had to ma#e. .............................................
................................................................................................................................
................................................................................................................................
................................................................................................................................
................................................................................................................................
43
&CS' 'lectronics.
-omeor. /uestions 2
1. 'he diagram below shows a circuit which ma#es three 3AD?s glow in a
se"uence. 'he cloc# feeds one pulse every second into the /-bit binary
counter. 'he counter outputs -A and . are fed into logic gates. 'hese
control three 3ADs.
-a. !omplete columns A and of the following truth table to show how
the output state of the binary counter changes. A is the least
significant bit.
-b. !omplete columns ,, 0 and K of the truth table to show how the
state of the 3ADs change in response to the binary se"uence.
44
>ulse *o A , 0 K
+
1
/
2
4
-c. ;tudy the ,, 0 and K outputs carefully and see if you can produce
a circuit diagram for the re"uired output using a less complex logic
sub-system than the original one.

45
&CS' 'lectronics.
Solutions to -omeor. /uestions
-omeor. /uestions *
1. a.
b.
c)
46
Solutions to -omeor. /uestions 2
1. -b.
-c.
47
>ulse *o A , 0 K
+ + + + + +
1 + 1 + + 1
/ 1 + + 1 1
2 1 1 1 1 1
4 + + + + +
&CS' 'lectronics.
Examination Style Questions
1. (a) Te fo!!o"i#g diagra$ %o"% &e %'$bo! for a D(&')e f!i)(f!o). Te f!i)(f!o) i% ri%i#g
edge &riggered.
Te D(i#)*& %&a&e i% &ra#%ferred &o &e + o*&)*& "e# &e c!oc, ri%e% fro$ &e !ogic !eve! 0
&o 1.
-o$)!e&e &e fo!!o"i#g diagra$ b' %o"i#g &e + o*&)*& %&a&e.
[3]
(b) . D(&')e f!i)(f!o) ca# a!%o be %e& *) a% a 1(bi& co*#&er.
/# &e fo!!o"i#g diagra$ of a D(&')e f!i)(f!o)0
(i) Dra" i# &e co##ec&io#(%) #eeded &o $a,e i& i#&o a 1(bi& co*#&er1
[1]
(ii) !abe! "i& &e "ord 23456T7 &e co##ec&io# "ere &e i#)*& )*!%e% e#&er &e f!i)(
f!o)1
[1]
(iii) !abe! "i& &e "ord 2/6T56T7 &e co##ec&io# "ere &e o*&)*& )*!%e% !eave &e
f!i)(f!o).
[1]
48
2. . bi#ar' co*#&er ca# be b*i!& fro$ a %erie% of D(&')e f!i)(f!o)%8 or ca# be ob&ai#ed a% a dedica&ed
co*#&er 3-.
(a) Te diagra$ %o"% a )*!%e ge#era&or a#d a ri%i#g(edge &riggered D(&')e f!i)(f!o).
Dra" o# &e diagra$ &e &"o co##ec&io#% re9*ired &o co#ver& &e D(&')e i#&o a 1(bi&
co*#&er8 co##ec&ed &o &e )*!%e ge#era&or.
[2]
(b) Te #e:& diagra$ %o"% a co*#&er 3-8 "i& i&% re%e& co#&ro!!ed b' a# .4D ga&e.
-o$)!e&e &e &ab!e &o %o" &e %e9*e#ce of o*&)*&% )rod*ced8 i#c!*di#g &e effec& of &e
.4D ga&e.

[3]
49
5*!%e
4*$ber
/*&)*&%
- ; .
0 0 0 0
1
2
3
4
5
6
7
&CS' 'lectronics.
3. .# i!!*$i#a&ed adver&i%e$e#& a% &ree %ec&io#% <8 = a#d > "ic !ig& *) i# a )rede&er$i#ed
%e9*e#ce. . b!oc, diagra$ of &e co#&ro! %'%&e$ i% %o"# be!o".
. !ogic %'%&e$ i% re9*ired &a& "i!! )rod*ce &e fo!!o"i#g %e9*e#ce.
(a) -o$)!e&e &e fo!!o"i#g &r*& &ab!e for &e !ogic %'%&e$. =o* $a' a%%*$e a )ar&ic*!ar
%ec&io# of &e adver&i%e$e#& %ig# i% !i& *) "e# &e corre%)o#di#g o*&)*& i% ig.
[3]
50
3#)*&% /*&)*&%
; . < = >
0 0
0 1
1 0
1 1
(b) ?&*d' &e < o*&)*&. 3& i% &e i#ver%e of o#e of &e i#)*&%.
@ri&e do"# a# e:)re%%io# &o de%cribe &i% o*&)*&.
< A ..............................................................................
[1]
(c) ?&*d' &e = o*&)*&. Tere i% o#e &')e of ga&e &a& "i!! )rod*ce &i%.
@a& &')e of ga&e i% i&B
< A ..............................................................................
[1]
(d) @a& &')e of ga&e "i!! )rovide &e re9*ired o*&)*& for >B
.....................................................................................
[1]
(e) =o* ave a %e!ec&io# of 4/T8 .4D8 /R8 4.4D a#d 4/R ga&e% avai!ab!e. Dra" a
!abe!!ed diagra$ i# &e %)ace be!o" %o"i#g o" &e !ogic %'%&e$ ca# be $ade *) b'
coo%i#g fro$ &e ga&e% avai!ab!e.
[4]
51
&CS' 'lectronics.
4. . bi#ar' co*#&er i% *%ed &o co#&ro! a %e& of $o&ori%ed va!ve% i# a "a&er )*$)i#g %&a&io#.
Te b!oc, diagra$ for &e %'%&e$ i% %o"# be!o".
. va!ve o)e#% "e# i& receive% a !ogic 1 %ig#a!8 a#d c!o%e% "e# i& receive% a !ogic 0 %ig#a!.
(a) Cere i% a )ar&!' co$)!e&ed &r*& &ab!e &o %o" "e# &e va!ve% o)e# a#d c!o%e.
5*!%e #*$ber
-o*#&er o*&)*&% Da!ve% Open or Closed
1 2 3
?&ar& -!o%ed /)e# -!o%ed
1
2
3
4
6%e &e o*&)*&% of &e co*#&er a#d &e !ogic ga&e% &o decide "e# eac va!ve o)e#% a#d
c!o%e%.
-o$)!e&e &e &ab!e b' %&a&i#g "e&er va!ve% 18 2 a#d 3 are o)e# or c!o%ed a& eac %&age of
&e %e9*e#ce.
[3]
(b) @a& a))e#% &o &e co*#&er o*&)*&% "e# )*!%e #*$ber 4 i% )roce%%ed b' &e co*#&erB
[1]
.................................................................................................................................................
.................................................................................................................................................
52
5. (a) . %&*de#& i% a%,ed &o b*i!d a $i#ia&*re %e& of &raffic !ig&% for a $ode! vi!!age.
Cere i% &e b!oc, diagra$ for &e co#&ro! %'%&e$.
5*!%e
ge#era&or
-o*#&er
Eogic
%'%&e$
Traffic
!ig&%
Te circ*i& diagra$ for &e co*#&er i% %o"# be!o".
- ; .
R
To &e red!ig&
To &e 'e!!o" !ig&
To &e gree# !ig&
5*!%e% fro$
)*!%e ge#era&or
Te &ab!e %o"% &e )o%%ib!e o*&)*& %&a&e% for &e co*#&er.
Pulse
number
Counter outputs Traffic lights
Red light Yellow light reen light
(i) Te co*#&er re%e&% "e# &e re%e& i#)*& R receive% a !ogic 1 %ig#a!.
@ic )*!%e #*$ber "i!! ca*%e &e co*#&er &o re%e&B....................
[1]
(ii) 6%e &e co*#&er o*&)*&% &o decide "a& %ig#a!% are %e#& &o &e &raffic !ig&%.
-o$)!e&e &e first four rows of &e &ab!e &o %o" "e&er !ogic 0 or !ogic 1 %ig#a!%
are %e#& &o &e red8 'e!!o" a#d gree# !ig&%.
[4]
53
&CS' 'lectronics.
6. . c'c!i%& "a#&% &o co*#& o" $a#' !a)% %e co$)!e&e%.
Tere i% a )re%%*re )ad o# &e &rac,. Ti% ac&% a% a %e#%or "ic o*&)*&% a )*!%e a% eac "ee! goe%
over i&.
(a) @' i% a divide(b'(&"o circ*i& #eeded be&"ee# &e )re%%*re )ad a#d &e !a) co*#&erB
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF..
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF..
[1]
(b) . D(&')e f!i)(f!o) i% *%ed &o $a,e &e divide(b'(&"o circ*i&.
Godif' &e diagra$ of &e D(&')e f!i)(f!o) &o $a,e i& )erfor$ &e divide(b'(&"o ac&io#.
=o* $*%& %o"0
o" &e )re%%*re )ad i% co##ec&ed &o &e D(&')e f!i)(f!o)1
o" &e o*&)*& of &e D(&')e i% co##ec&ed1
a#' o&er co##ec&io#(%) #eeded.
[3]
54
(c) Te fir%& gra) %o"% &e o*&)*& of &e )re%%*re )ad %e#d direc&!' i#&o &e divide(b'(&"o
circ*i&.
6%e &e a:e% )rovided &o dra" &e %ig#a!% a& + a#d
+
o*&)*&%.
The Q output is initially at logic !"
Te D(&')e f!i)(f!o) i% ri%i#g edge(&riggered.
[4]
7. . 4(bi& bi#ar' co*#&er %o"# be!o". Te co*#&er $*%& re%e& "e# co*#&er o*&)*& reace% &"e!ve.
Te co*#&er i% re%e& b' &a,i#g &e re%e& )i# &o !ogic 0.
-o$)!e&e &e diagra$ be!o" &o %o" o" &i% ca# be do#e.
;i& . of &e co*#&er i% &e !ea%& %ig#ifica#& bi&.
[3]
55
&CS' 'lectronics.
8. Te D(&')e f!i)(f!o) ca# be *%ed for da&a &ra#%fer8 *#der &e co#&ro! of &e c!oc,.
Te D(&')e f!i)(f!o) i% ri%i#g(edge(&riggered.
Te %ig#a! %o"# i# &e fir%& gra) i% %e#& i#&o &e D i#)*&.
Te %eco#d gra) %o"% &e )*!%e% %e#& i#&o &e c!oc, i#)*&.
6%e &e a:e% )rovided &o dra" &e %ig#a!% a& &e + a#d
+
o*&)*&%.
Te + o*&)*& i% i#i&ia!!' a& !ogic 1.
[3]
56
(b) . bi#ar' co*#&er ca# be b*i!& fro$ a %erie% of D(&')e f!i)(f!o)%8 or ca# be ob&ai#ed a% a
dedica&ed co*#&er 3-.
(i) Te fo!!o"i#g diagra$ %o"% a )*!%e ge#era&or a#d &"o ri%i#g(edge &riggered D(
&')e f!i)(f!o)%.
Dra" o# &e diagra$ &e co##ec&io#% re9*ired &o $a,e a 2(bi& *)(co*#&er8
co##ec&ed &o &e )*!%e ge#era&or.
[3]
(ii) Te gra) %o"% c!oc, )*!%e% a))!ied &o &e 2(bi& *)(co*#&er.
6%e &e a:e% )rovided &o dra" &e %ig#a!% "ic "o*!d a))ear a& &e o*&)*&% of &e
&"o f!i) f!o)%.
3#i&ia!!' &e +
.
o*&)*& a#d +
;
o*&)*& are bo& a& !ogic 0.
[3]
57
&CS' 'lectronics.
9. . D(&')e f!i)(f!o) ca# be *%ed a% a 1(bi& co*#&er.
(a) Dra" o# &e diagra$ &e &"o co##ec&io#% re9*ired &o co#ver& &e D(&')e i#&o a 1(bi& co*#&er8
co##ec&ed &o &e )*!%e ge#era&or.

[1]
(b) Te D(&')e f!i)(f!o) i% ri%i#g(edge &riggered.
(i) Eabe! a ri%i#g(edge o# &e )*!%e ge#era&or o*&)*& gra) be!o".
[1]
(ii) The Q output is initially at logic #"
-o$)!e&e &e gra) &o %o" &e %ig#a! a& &e + o*&)*&.
[2]
(iii) Dra" &e gra) &o %o" &e %ig#a! a& &e
+
o*&)*&.
[1]
(c) Te %'%&e$ i% a!%o ,#o"# a% a divide(b'(&"o circ*i&.
Te )*!%e ge#era&or a% a fre9*e#c' of 10 CH.
(i) @a& i% &e fre9*e#c' of &e %ig#a! a& &e + o*&)*&B ................................
(ii) @a& i% &e fre9*e#c' of &e %ig#a! a& &e
+
o*&)*&B ................................
[2]
10. Te diagra$ %o"% a 3(bi& co*#&er receivi#g )*!%e% fro$ a )*!%e ge#era&or.
58
/*&)*& - i% &e $o%& %ig#ifica#& bi& ($%b).
-o$)!e&e &e &ab!e &o %o" &e co*#&er o*&)*&%8 -8 ; a#d .8 "e# &e 2
#d
a#d 3
rd
)*!%e% are
co*#&ed.
[2]
59
5*!%e
4*$ber
/*&)*&%
- ; .
0 0 0 0
1 0 0 1
2
3
&CS' 'lectronics.
11. (a) -o$)!e&e &e fo!!o"i#g diagra$ &o %o" o" &e &"o D(&')e f!i)(f!o)% (;i(%&ab!e%) ca# be
co##ec&ed &oge&er &o for$ a 2(bi& bi#ar' co*#&er.
[2]
(b) -o$)!e&e &e fo!!o"i#g &i$i#g diagra$% for &e o*&)*&% +
.
a#d +
;
.
Te D(&')e% are ri%i#g(edge &riggered.
[4]
60
12. Te fo!!o"i#g diagra$ %o"% a )*!%e ge#era&or a#d a ri%i#g(edge &riggered D(&')e f!i)(f!o).
(a) Dra" o# &e diagra$ &e &"o co##ec&io#% re9*ired &o co#ver& &e D(&')e i#&o a o#e(bi&
co*#&er8 co##ec&ed &o &e )*!%e ge#era&or.
[2]
(b) Te fo!!o"i#g gra)% %o" &e )*!%e ge#era&or o*&)*&8 a#d fo*r )o%%ib!e %ig#a!%.
@ic gra) %o"% &e correc& o*&)*& fro$ +B ...............................
[1]
61
&CS' 'lectronics.
Sel# 'valuation 1evie
Learning Objectives
@y personal review of these ob5ectives(

explain, and illustrate, how a D-type
flip-flop can be set up to produce a
divide-by-two function;
complete timing diagrams for a 1-bit
counter;
sho ho to !"type #lip"#lops
can be connecte$ together to #orm
a 2"bit binary up counter%
complete timing $iagrams #or a 2"
bit counter%
realise that counters are available in
a number of formats e.g. up/down,
binary/!D/decade;
design and analyse simple systems
that use a counter and combinational
logic to produce a se"uence of
events;
ma#e a counter reset at a given
value.
'argets( 1. LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL
LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL
/. LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL
LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL
62

Learning Objectives:: Topic 2.2 - Sequential Systems. 2.2.2 - Binary Counters

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Topic 2.2 Sequential Systems.

2.2.2 Binary Counters

and changes to logic + as the cloc# input to flip-flop B has

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