Presentation 01

F.
Maloberti : Design of CMOS Analog Integrated Circuits - The MOS Transistor

Design of CMOS Analog
Integrated Circuits
Franco Maloberti
THE MOS TRANSISTOR
F. Maloberti : Design of CMOS Analog Integrated Circuits - The MOS Transistor 2 1/
ELECTRICAL CONDUCTION IN SOLIDS
The allowed energy levels for electron in solids are described by the
band diagram.
The lower filled band is named Valence Band, the upper vacant band is
named conduction band.
The distance between valence and Conduction band is the energy gap
Energy Gap in solids
Fermi Dirac Statistics
Gives the probability of occupations of energy levels :
Material Energy gap
Metal none
Semiconductor 0.5 - 3 eV
Insulator > 3 eV
( )
( ) kT / E E
F
e 1
1
E F

+
Where E
F
is the Fermi Level
Fermi-Dirac distribution function for three different values of temperature.
At the Fermi level F(E
F
) = 1/2.
Let Z(E) be the energy level distribution; the number of electrons in the
energy interval E, E + dE is given by :
N(E)dE = Z(E)F(E)dE
The number of electrons in the conduction band is :
similarly the number of holes, p, in the valence band :
If the Fermi level is in the middle of the energy gap, the material is referred
to as intrinsic, and we have :
n = p = n
i
( ) ( ) ( )
( )

+

c
F
c
t
c
E
kT / E E
E
e
E
E
e
1 e
dE
E Z dE E N dE E N n
( ) ( )
( )
( )
( )

+

v
F
F
v v
b
E
kT / E E
kT / E E
E
h
E
E
h
dE E Z
1 e
e
dE E N dE E N p
N
i
is strongly dependent on the temperature. For the silicon (empirical
relationship) :
at room temperature n
i
= 1.42 x 10
10
cm
-3
If donor or acceptor impurities are added to the semiconductor, localized
energy levels are set in the forbidden gap. The activation energy are :
kT 2 / q 21 . 1 2 / 3 16
i
e T 10 954 . 3 n

III Group
B
Al
Ga
In
Activation
Energy
0.045 eV
0.067 eV
0.072 eV
0.160 eV
V Group
P
As
Sb
Activation
Energy
0.045 eV
0.054 eV
0.039 eV
[ ] [ ]; V doping n for
n
N
ln
q
kT
; V doping p for
N
n
ln
q
kT
i
D
F
A
i
F

Because of extremely low activation energy, even a low temperature is
enough to ionize the donor or the acceptor atoms (kT = 0.025 eV at 300 K).
The electrons (or holes) concentration increases in the conduction or
valence band.
At room temperature :
n = N
D
for n-type
p = N
A
for p-type
n x p = n
i
2
The Fermi level is shifted with respect to the intrinsic level of the amount :
~
~
PROPERTIES OF THE MATERIALS
SILICON :
<100> or <111> oriented slides
Property
Atomic density
Density
Atomic Weight
Reticular constant
Thermal Conductivity
Intrinsic resistivity (@ 300
o
K
Relative dielectric constant,
r
Absolute dielectric constant,
o
Value
5 10
22
2.330
28.1
.543
1.41
2.5 10
5
11.9
8.858 10
-14
Dimension
atoms/cm
3
g/cm
3
g/mole
nm
/cm
o
C
cm
-
F/cm
Conductivity :
=
n
+
p
= q(n
n
+ p
p
)
At room temperature :
n = N
D
for n-doping
p = N
A
for p-doping
n x p = n
i
2
hence :
= qN
D
n
for n-doping
= qN
A
p
for p-doping
~
~
The following figures depict the mobility of electrons and holes as a function
of the doping (at room temperature) and a resistivity as a function of the
doping (at room temperature).
Sheet resistance :
Considering a thin layer of resistive material; its resistance is
a)
h
W
L
b)
h
W
L
( ) [ ] ( )

,
_
h
0
dz z
L
W
R
1
G z ;
W
L
R
hW
L
R with non homogeneous layers
POLYSILICON
Grow from pyrolytic decomposition of silane (SiH
4
) at about 600
o
C.
The polycrystalline structure is made of monocrystal grains size in the
range of 0.1 - 1 m.
The typical layer are 200 - 600 nm thick with long term standard
deviation in the 2% range.
The mobility is low because of the grain border resistance (30 - 40
cm
2
/Vsec).
In order to have a low sheet resistance the polysilicon must be strongly
doped (10
20
- 10
21
at./cm
3
). Part of the doping saturates the localized
levels due to the grain border. The sheet resistance is in the range 20 -
40 /
The sheet resistance can be reduced by using sandwich layers
(polysilicide) made of 200 nm of polysilicon covered with a film of
refractory metal silicide (WSi
2
, MoSi
2
). The sheet resistance is reduced
to 1 - 5 /
SILICON DIOXIDE
Thermally grown from silicon in dry or wet conditions at 800 - 1100
o
C
The silicon dioxide frown determine a silicon consumption : if d is the
thickness of grown oxide, 0.44d of silicon is consumed.
Property
Density
Dielectric strength
Resistivity (@ 300
o
K)
Relative dielectric constant
Value
2.22
2 - 8 10
6
10
15
- 10
17
2.7 - 4.2
Dimension
g/cm
3
V/cm
cm
Grow speed :
Silicon dioxide can also be grown from chemical vapox depositation
(CVD) :
SiH
4
+ 2O
2
--> SiO
2
+ 2H
2
O
by pyrolytic decomposition of silane in the presence of oxygen.
At atmospheric pressure (AP-CVD)
At low pressure (LP-CVD)
The temperature ranges from 300 to 500
o
C
Growth speed, about one order of magnitude larger than the one of
termal dioxide.
Charge voltage hysteresis effect when deposited on silicon (not suitable
for capacitors).
For surface protection p-doped to compensate the sodium ions action.
Long standard deviation 5 - 6%
Property
Density
Dielectric strength
Resistivity (@ 300
o
K)
Relative dielectric constant
Value
2.22
2 - 8 10
6
10
15
- 10
17
2.7 - 4.2
Dimension
g/cm
3
V/cm
cm
SILICON NITRIDE
Its major use is to protect surface.
By decomposition of silane or dichlorosilane and ammonia at 700 - 800
o
C.
3SiH
4
+ 4NH
3
--> Si
3
H
4
+ 12H
2
3SiH
2
Cl
2
+ 4NH
3
--> Si
3
N
4
+ 6HCl + 6H
2
Speed growth : 10 - 20 nm/min
Resistivity : 10
4
- 10
6
/cm
Dielectric strength : 5 - 10 MV.cm
Long term standard deviation : 3 - 4%
THE CMOS TECHNOLOGY
Symbols of the MOS transistors
TYPICAL CMOS PROCESS
MOS technology integrates both n-
channel and p-channel transistors on the
same chip.
If the substrate of the circuit is n-doped,
the p-channel transistors sit directly on
the substrate, whereas the n-channel
devices need a well.
Modern technologies use twin-well to
make the two type of transistors inside
wells regardless of substrate doping.
This approach optimize the electrical
behavior at the expense of additional
step.
THE MOS THRESHOLD
VOLTAGE
The threshold voltage is the
voltage required at the gate to
generate a conductive channel
between source and drain.
A conductive channel is
generated when the oxide-
semiconductor interface is in
strong inversion (bandbending =
2
F
)
In order to evaluate V
th
, the
following points must be taken
into account :
Contact potential of the MOS structure.
The energy gap E
g
.
Fixed charge trapped at the oxide-semiconductor interface.
For an ideal MOS structure (without interface charge) the contact
potential is neutralized by the so called flat band voltage V
FB
(the band
diagram in the semiconductor is flat).
In a real MOS structure, within a thin oxide layer at the semiconductor
oxide interface, a charge Q
SS
is trapped
FS
g
FS FG FB
q 2
E
V + +
> <

111 for cm / coul 10 2 Q
2 8
SS
> <

100 for cm / coul 10 4 Q
2 9
SS
The flat band voltage becomes :
The bending of the bands is get by depleting the semiconductor :
ox
SS
FS
g
real , FB
C
Q
q 2
E
V +
depletion gate
Q Q
( )
depl A ox FS FB th
x qN C 2 V V +
FS SB
A
d
2 V
qN
2
x

where is the body coefficient. If V
SB
= 0
The Threshold voltage can be expressed as :
( )
FS SB
ox
imp SS
FS
g
Th
2 V
C
Q Q
q 2
E
V +
+

ox
A
C
N q 2

FS FS real , FB 0 , Th
2 2 V V +
{ }
FS FS SB 0 , Th Th
2 2 V V V +
I-V CHARACTERISTICS
Weak inversion region V
GS
< V
Th
Linear (or Triode) V
Th
< V
GS
> V
DS
+ V
Th
Saturation region V
Th
< V
GS
< V
DS
+ V
Th
Weak inversion region :
The band diagram indicates that the structure in equivalent to two back to
back p-n diodes where the saturation current depends on the barrier height.
nkT / qV nkT / qV
0 D S
B G
e e I I

[ ]
kT / qV nkT / qV nkT / qV
0 D D
DS B G
e 1 e e I I

Linear (or Triode) region :
The voltage exceeding the
threshold determines an
accumulation of mobile charge on
the channel (inversion region)
V(x) is the drop voltage from source to x.
The resistance of an incremental element x, x + dx in the channel is :
The drop voltage across the element is :
{ } ) x ( V ) x ( V V C ) x ( Q
Th GS ox inv

W ) x ( Q
dx
A
dx
dR
inv

W ) x ( Q
dx I
dR I dV
inv
D
D

V
Th
changes along the channel due to the body effect :
We get :
if the second term can be neglected
{ }
FS SB FS 0 , Th Th
2 ) x ( V V 2 V V + +
dx V V
L
0
DS

( ) [ ]
'
,
_
+
2 / 3
F DB
2 / 3
F SB
2
DS DS F 0 , Th GS ox D
2 V 2 V
3
2
V
2
1
V 2 V V
L
W
C I
( )
1
]
1
,
_

2
DS DS Th GS ox D
V
2
1
V V V
L
W
C I
Saturation region :
As V(x) increases Q
inv
(x) decreases. Its minimum is at the drain
Q
inv
(L) = C
ox
[ V
GS
- V
Th
- V
DS
]
if
V
DS
= V
sat
= V
GS
- V
Th
Q
inv
(L) = 0
the drain is in the pinch-off condition.
If V
DS
> V
sat
, the pinch-off point moves toward the source; the part of the V
DS
voltage exceeding V
sat
drops along the depleted region, L, extending from
the pinch-off to the drain.
( )
sat DS
A
V V
qN
2
L

The structure can be assumed equivalent to a transistor with the pinch-
off at the drain but with length reduced of L. It results :
having neglected V
sat
with respect of V
DS
= channel length modulation parameter
1 2
V 10 5

A
7
A
2
N L
10
N qL

( )
( )
DS sat DS
2
A
sat DS
2
A
V 1 V V
L qN
1
V V
L qN
2
1
1
L L
L
+

( ) ( )
L L
L
V V
L
W
C
2
1
V V
L L
W
C
2
1
I
2
Th GS ox
2
Th GS ox D

hence in saturation :
for getting continuity in the derivative of I
D
even in the linear region the
term (1 + V
DS
) is added :
C
ox
is often represented by the symbol k
n
(k
p
) that is called the process
transconductance parameter. For a given CMOS technologies we can
use the following figures t
ox
= 15 nm,
n
= 520 cm
2
/V
2
sec and
p
= 180
cm
2
/V
2
sec. Therefore we have :
2
ox n n
V / A 108 C k
( ) [ ]
DS
2
DS DS Th GS ox D
V 1 V
2
1
V V V
L
W
C I +
1
]
1
,
_

( ) [ ]
DS
2
DS DS Th GS ox D
V 1 V
2
1
V V V
L
W
C
2
1
I +
1
]
1
,
_

2
ox p p
V / A 38 C k
LARGE SIGNAL EQUIVALENT CIRCUIT
Non linear Linear (1
st
approximation)
- Current source - Resistors
- Diodes - C
GS, ov
; C
GD, ov
- C
GS
, C
BG
, C
GD
, C
BS
, C
BD
Typically :
Diodes reversely biased; the reverse current is dominated by

generation recombination term
A : area of the junction
x
j
: depletion region width
o
: mean lfetime for minority
carriers
I
GR
doubles for an increase of 10
K typically at room temperature
I
GR
/A = 10
-15
A/m
2
.
0
j i
GR
2
x qn
A I
50 10 R R
S D
ox ov ov , GD ov , GS
C Wx C C
SMALL SIGNAL EQUIVALENT CIRCUIT
Obtained by a linearization of the large signal equivalent circuit.
The linearization of the current source I
D
= I
D
(V
GS
, V
DS
, V
BS
)
generate three voltage controlled
current sources :
g
m
= I
D
/V
GS
transconductance
g
ds
= I
D
/V
DS
drain output conductance
g
mb
= I
D
/V
BS
substrate transconductance
Transconductance :
In the subthreshold region (like a bipolar transistor) :
In the linear region :
In the saturation region :
q
kT
n
I
g g
D
mb m

DS ox m
V
L
W
C g

,
_

( )
( )
D ox
Th GS
D
Th GS ox m
I
L
W
C 2
V V
I 2
V V
L
W
C g

,
_
,
_

In the real situation g
m
is smaller
than the value predicted by the
giving simple equation. Moreover
g
m
changes because of the
dependence of from the
temperature, the trasversal and the
mean lateral electric field.
SPICE uses a fitting equation :
1
1
1
1
]
1
+
1
]
1
,
_

sat
DS
m
crit
y
2
3
0
0
LE
V
1
1
E
E
1
T
T
( )
exp
u
DS tra on GS ox
si crit
0
V u V V C
u
1
]
1

Drain output conductance (gds) :
In the linear region
In the saturation region (first order)
Second order effects
The channel length reduction has been calculated taking into account only
the lateral drop voltage. A more accurate analysis gives :
( )
DS Th GS ox ds
V V V
L
W
C g
,
_

D ds
I g
( )
( ) ( )
1
]
1
sat DS
sat GS GS DS
S
ox
st
V V
V V V V C
order 1 L
1
L
1
The threshold voltage depends on the V
DS
(short channel)
The mobility depends on the lateral mean field V
DS
/L
The avalanche effect increases I
D
.
Avalanche current :
Mobile charges, accelerated by electric field in the drain depleted region,
creates, by impact ionization, electron-holes pair.
It appears an increase of the drain current I
D
and a substrate current I
B
The substrate current may contribute to latch-up
The device noise increases
The output impedance decreases
Carriers can be trapped on the oxide and the V
Th
changes (hot electron
effect)
Avalanche current worse in n-channel
More accurate expression of the output conductance :
(first order) (short channel) (velocity saturation) (avalanching)
DS
S
DS
D
DS
Th
m D ds
V
I
V
I
V
V
g I g
,
_

Capacitances
In the linear region
WL C C
ox i

WL
x
C
dep
si
dep

2
C
C C
i
gsov gs
+
2
C
C C ;
2
C
C C ;
2
C
C C
dep
jd db
dep
js sb
i
gdov gd
+ + +
In the saturation region
gdov gd
C C
3
C 2
C C
dep
js sb
+
i gb jd db
C
10
1
C ; C C
,
_
2
i
D
T
T
0 j
j
n
NA N
ln
q
KT
;
V
1
C
C
3
C 2
C C
i
gsov gs
+
m
2
nTh
g
1
kT 4
3
2
f
V
,
_
2
1
f
f
m
2
nTh 2
n
BW
g
kT
4
3
2
f
f
V
V
Thermal noise :
Due to the finite output resistance if
reffered to the input, as shown in
figure
for I
D
= 50 A, (V
GS
- V
Th
) = 300 mV,
V
nTh
= 5.6 nV/ H
z
If the bandwidth BW of the system
is f
2
- f
1
the input referred noise
voltage is :
Flicker noise :
Due to the trapping and detrapping of carriers by surface states at different
energy levels.
Modeled as :
Typically : @ 1 kHz with WL = 1000
2
k
ox
2
f D
2
nf
C L f
K I
f
V
WL
1
C f 2
k
g C L f
k I
fg
i
f
V
1 kc
ox
f
2
m
kc
ox
2
f D
2
m
2
nf
2
nf

+
1 f SS f
k N to al proportion k 1

z
nf
H
nV
40 V
The power of the flicker noise is concentrated at low frequency
Noise spectra for n-channel Boron implanted p-MOS hal
and p-channel transistor low 1/f noise (buried channel)
,
_
,
_
1
2
1 kc
ox
f
f
f
2
nf
2
n
f
f
ln
WL C 2
k
df
f
V
V
1
2
Avalanche noise :
Due to the statistical fluctuation in the number of carriers of the avalanche
current (shot noise)
If referred to the input :
if we compare thermal noise with avalanche noise, we have
AV
2
nAV
ql 2
f
i
D ox
AV
2
m
2
nAV
2
nAV
I
L
W
C
ql
fg
i
f
V
,
_

we get comparable boise if I
D
/I
AV
is of the same order of (V
GS
- V
Th
)/(kT/q).
The avalanche current at V
DS
= 5 V can be of the order of 0.5 - 1 A.
To minimize the Noise
Thermal noise :
Use large g
m
(large W/L)
Use low series resistance (connection and gate resistance)
( )
AV
D
Th GS AV
m
2
nAV
2
nTh
I
I
V V
q
kT
3
8
ql 2
kTg 4
3
2
V
V

Flicker noise :
Use large device area (WL)
Use thin oxide (high C
ox
)
Use clean technology (low N
SS
)
Try to get burried channel
Use p-channel devices
Avalanche noise :
Reduce V
DS
Use of p-channel devices
LAYOUT
Rules :
Use poly connection only for signal, never for current because the
offset RI = 15 mV.
Minimize the line length, especially for lines connecting high
impedance nodes (if they are not the dominant node).
Use matched structure. If necessary common centroid arrangement.
Respect symmetries (even respect power devices).
Only straight-line transistors.
Separate (or shield) the input from the output line, to avoid feedback.
Shielding of high impedance nodes to avoid noise injection from the
power supply and the substrate.
Regular shape
LAYOUT OF TRANSISTORS
MOS transistor is a overlap of two rectangles : active area (not
protected, to originate the source and the drain) and polysilicon gate.
The key point to consider :
parasitic resistance at source and
drain must kept as low as possible
parasitic capacitances must be
minimized
matching between paired elements
is very imporant
Use multiple contact. Many contacts placed close to one another
make the surface of metal connection smoother than when we use
only one contact; this prevents microcraks in metal;
Splitting the transistor in a number of equal part connected in parallel
permits to reduce the area of each transistor and so reduces parasitic
capacitances by two; the one on the right reduces the parasitic
capacitances by four.
Matching is very important when we design current mirrors and
differential pairs. Bad matching produces high offset.
Transistors with different orientation match badly (fig. A); moreover we
can suffer mismatch if the current in transistors flowing in opposite
direction (fig. b). In addition, we can effect a change in physical and
technological parameters in points of the chip that are relatively far away
The best method of achieving good matching is shown in the following
figure :
Each transistor is split in four equal parts interleaved in two by twos.
So that for one pair of pieces of the same transistor we have currents
flowing in opposite direction.
Any noisy signal affecting the substrate or the well should be sunk by
the biasing and should not affect the circuit itself.

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F.

Maloberti : Design of CMOS Analog Integrated Circuits - The MOS Transistor

F. Maloberti : Design of CMOS Analog Integrated Circuits - The MOS Transistor 23 1/

Diodes reversely biased; the reverse current is dominated by

F. Maloberti : Design of CMOS Analog Integrated Circuits - The MOS Transistor 46 1/

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