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Shift Microoperations

Shift microoperations perform shift operations on data stored in registers.



There are three types of shifts
Logical shift
Circular shift
Arithmetic shift

The following table describes the valid shift microoperations:
OPERATION
SYMBOL
DESIGNATION DESCRIPTION
SHL R2 < shl R2 Shift left bits in R2
SHR R2 < shr R2 Shift right bits in R2
CIL R2 < cil R2 Circular shift left bits in R2
CIR R2 < cir R2 Circular shift right bits in R2
ASHL R2 < ashl R2 Arithmetic shift left bits in R2
ASHR R2 < ashr R2 Arithmetic shift right bits in R2

Logical shift
The standard logical shifts (SHL, SHR) shift all bits one bit position to the left or right and place a 0
in the leftmost or rightmost position, respectively.
Circular shift

The circular shifts (CIL, CIR) operate the same as a logical shifts except that instead of shifting a 0
into the end bit, the leftmost bit is shifted into the rightmost bit postion on a CIL, and the rightmost
bit is shifted into the leftmost bit position on a CIR.
Arithmetic shift
.
The arithmetic shifts (ASHL, ASHR) operate the same as a logical shifts except that instead of
shifting a 0 into the end bit, the leftmost (sign) bit always remains unchanged.
On an ASHL, the most significant digit other than the sign bit is shifted out of the register, and a 0
is shifted into the rightmost bit.
On an ASHR, the most significant digit other than the sign bit gets the value of the sign bit, and the
least significant (rightmost) bit is shifted out of the register.









































In the basic computer each instruction cycle consists of thefollowing phases:1) Fetch an instruction from memory.2)
Decode the instruction3) Read the effective address from memory if the instructionhas an indirect address.4) Execute
the instruction.


F
etch and Decode

Initially, the program counter PC is loaded with the address of the first instruction in the program. The sequence
counter SC is cleared to 0, providing a decode timing signal T0.
After each clock pulse, SC is incremented by one, so that thetiming signal go through a sequence T0, T1, T2, and so
on.
The micro operations for the fetch and decode phases can bespecified by the following register transfer statements.
T0: AR <- PC
T1: IR <- M[AR]. PC <- PC +1

T2: D0,....,D7<-Decode IR(12-14),AR<-IR(0-11),I<-IR(15)

Since only AR is connected to the address inputs of thememory, it is necessary to transfer the address from PC
to AR during the clock transition association with timing signal T0.
The instruction read from memory is then placed in theinstruction register IR with the clock transition associated
withtiming signal T1.
As the same time, PC is incremented by one to prepare it forthe address of the next instruction in the program.
At time T2, the operation code in IR is decoded, the indirectbit is transferred to flip-flop I, and the address part of
theinstruction is transferred to AR. Fig shows how the first two registers transfer statements areimplemented in the
bus system. To provide the data path for the transfer of PC to AR must apply timing signal T0 to achievethe
following connection:-1) Place the content of PC onto the bus by making the busselection inputs S2S1S0 equal to
010.2) Transfer the content of the bus to AR by enabling the LD inputof The next clock transition
initiates the transfer from PC to AR since T0 = 1.T1 = IR <- M[AR], PC<- PC+1.It is necessary to use
timing signal T1 to provide the following connections in the bus system.Enable the read input of memory.
Place the content of memory onto the bus bymaking S2S1S0 = 111
Transfer the content of the bus to IR byenabling the LD input of IR.

Increment PC by enabling the INR input of PC.The next clock transition initiates the readand
increment operations since T=11.


De
t
erm
in
e
th
e
typ
e
of Inst
r
uction

The timing signal that is active after the decoding is T3. Duringtime T3, the control unit determines the type of
instructionthat was just read from memory.

The flowchart initiates an initial configuration for theinstruction cycle and shows how the control determines
theinstruction type after the decoding.

Decoder output D7 is equal to 1 if the operation code is equalto binary 111.If D7 is equal to 0 the operation code must
oneof the other seven values 000 through 110, specifying amemory reference instruction.

The micro operation for the indirect address condition can besymbolized by the register transfer statement:AR <-
M[AR]

Initially, AR holds the address part of the instruction. Thisaddress is used during the memory read
operation. The wordat the address given by AR is read from memory and placedon the common
bus.
The three instruction types are subdivided into four separatepaths. The selected operation is
activated with the clocktransition associated with timing signal T3.

: AR <- M[AR]

: Nothing

: Execute a register- reference instruction

D7IT3 : Execute an input- output instruction

When a memory reference instruction with I=0 isencountered, it is not necessary to do anything
since theeffective address is already in AR.



However, the sequence counter SC must be incrementedwhen so that the execution of
the memory-reference instruction can be continued with timing variableT4.
If SC is incremented, we will not write the statement SC<- SC+1, but it will be implied that the
control goes to thenext timing signal in sequence.
When SC is to be cleared, we will include the statement SC<-0.