IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO.
5 , MAY 1981 523
Analysis and Modeling of Dual-Gate MOSFETs Abstract-Dual-gate MOS transistors (both as discrete devices and as circuit elements) are extremely attractive for a variety of applications where electronic gain control capability, low feedback parameters, low noise and cross modulation, reduced short-channel effects, or high breakdown voltage are required. In this paper, the operation and physi- cal characteristics of dualgate MOSFETs are investigated. An accurate model is developed, which enables the simulation of behavior of the device with respect to bias conditions, by means of a simple iterative algorithm. Using this model, the static characteristics are analyzed in detail, special emphasis being directed toward the properties of the drain conductance and transconductances in the various operational modes. Second-order effects, not taken into account in the model, are discussed. The boundaries of the operating regions also are calculated by means of simple analytic models. Extensive experimental verifica- tion is made through measurements conducted on various dual-gate transistor structures fabricated by a shadowed-gap/lift-off process. T I. INTRODUCTION HE INTEGRATED cascode arrangement of two MOS transistors-the MOS tetrode [I ] -is widely used in appli- cations requiring low Miller feedback capacitance, or electronic gain control capability. The low noise and reduced cross- modulation characteristics also are used to advantage in VHF and UHF applications [2], [3] , The dual-gate MOSFET (also referred to as inversion-charge transistor [4] or zero-overlapping-gate MOST [5]) differs from the cascode-type MOS tetrode in that the drain for the first gate is actually the inversion or depletion layer under the second gate. This direct coupling of the two transistor chan- nels, resulting from the elimination of the intermediate dif- fused island, leads to many advantages for dual-gate devices over conventional tetrode structures. First, there is obviously a reduction of device area [6] . Second, the Miller capacitance and output conductance are further reduced, making the dual- gate MOSFET a useful device for analog integrated circuits [7] , [SI . The reduced feedback and the resulting increase in power gain and stability, in conjunction with the increased functional capabilities stemming from the presence of two independent control gates [9] , are the major beneflts of dual- gate MOS transistors used in integrated circuits. Third, by proper design, the breakdown voltage can be made very high [l o] . Fourth, short-channel effects are considerably diminished [ 1 I ] . Since the dual-gate MOSFET has no intermediate island, proper coupling of the two channels can be achieved only if Manuscript received August 25, 1980; revised December 1, 1980. The author is with the R&D Center for Semiconductors, Str. Erou Iancu Nicolae 32 B, Bucharest 72996, Romania. vs vG1 vG2 VD METAL 7 P SOURCE c--, L1 L2- DRAIN SI LI CON SUBSTRATE Fig. 1. Cross section through the channel region of a dual-gate MOSFET, showing devant dimensions and applied voltages. Both channels are assumed to be pinched off. The gap size is negligibly small. the separation between the adjacent gates is small enough (<1 ym). Therefore, dual-gate MOS transistors require either overlapping gate, or other kinds of submicron-gap technologies. This paper investigates the operation and static characteris- tics of dual-gate MOSFETs by means of accurate device model- ing and detailed experimental verifications. 11. OPERATION OF DUAL-GATE MOSFETs A schematic cross section through a dual-gate MOS transistor with coplanar gates is shown in Fig. 1. The closely spaced electrodes can be obtained by an overlapping-gate process, such as double-level polysilicon [4] , [l I ] , or refractory gate. An alternative approach is a nonoverlapping submicron-gap process, such as the shadow-etch technique [SI, [12], which has been used to fabricate the structures considered in this work. Devices made by this method, using aluminum, showed typical gaps of 0.5 pm between gates G1 and G2. The advantages of this approach compared to overlapping-gate tech- niques are process simplicity and reduced parasitic capacitance between the two gates. Dual-gate MOSFET integrated circuits with gap regions about 1 cm long have been successfully fabri- cated by this method [SI . In order to understand the operation of the dual-gate MOSFET, let us begin by examining the drain current charac- teristics shown in Fig. 2. The device is a p-channel high- threshold (about 5 V) structure and has channel lengths L1 =16.4ym and L2 =3.3 ym. The parameter on each dia- gram is the voltage on the first gate VGl, and the second-gate voltage, V G ~ , is varied from 0 V to 40 \I on Fig. 2(a) through (f). For zero second-gate bias, the region under G2 is Although the devices used for exemplification in this work are p-channel and all applied voltages are negative with respect to the substrate, the negative sign has been dropped for convenience through- out the paper. Therefore, it should be kept in mind that all voltages and potentials represent absolute values. 0018-9383/81/0500-0523$00.75 0 1981 IEEE 524 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 5 , MAY 1981 punched through as soon as VD exceeds about 20 V. Fig. 2(a) clearly shows punchthrough characteristics. When VG2 in- creases but remaining below or near threshold, the punch- through behavior is still visible, with a corresponding reduction of the punchthrough voltage. The transition from punch- through to normal MOSFET behavior is further illustrated in Fig. 3, where VG, is taken as parameter. Above threshold, an inversion channel appears under G2. This channel may or may not be pinched off (at the drain end), depending on the magni- tude of the drain voltage. If VD is high enough, VG, is no longer able to maintain inversion in the vicinity of the drain, the channel pinches off, and the current saturates (Fig. 2(d)). As VG2 increases, so does the channel potential under G2. This potential acts as drain bias for the first channel (under G 1). It follows that at higher second-gate biases the first chan- nel pinches off too, provided VG] is not too high to force inversion. This is evidenced in Fig. 2(e) and (f) by the very flat saturation characteristics of the device. Fig. 3. Drain characteristics of dualgate MOSFET of Fig. 2 with second-gate bias voltage as parameter. V G ~ =16 V. First trace: vG2 =0 v. Punchthrough only occurs in short-channel (G2) devices fabricated on highresistivity substrates. Neglecting this regime, it follows from the previous preliminary discussion that four BARSAN: DUAL-GATE MOSFETs 5 2 5 different operationalmodes exist for dual-gate devices, depend- ing on the bias conditions. Labeling S (saturated) a pinched- off channel and L (linear) a nonpinched-off channel, the four characteristic modes are: L- S (second channel pinched off), S-L (first channel pinched off), S-S (both pinched off), L-L (none pinched off). The boundaries of these operating regions can be determined from classical MOSFET theory, assuming that the carrier mobility is constant (no velocity saturation) and that the gradual channel approximation is valid. Under these conditions the drain current of an MOS transistor is 2 - -k 3 [(VD t 2 $ ~ ) ~ / ~ - (VS t 2@~) ~/ 1} (1) where is the gain factor, V& =VG - V, is the effective gate voltage (VFB is the flatband voltage), @F is the Fermi potential of the substrate, and the body factor k is given by FIRST GATE VOLTAGE, Vb , ( V ) (a) SECOND GAT E VOL T AGE . V~2( V) 1 k =__ (2 e, 4ND) 1/ 2 @) cox (2) Fig. 4. Operating regions of dual-gate MOSFET, for: (a) v G2 fixed and; (b) v G1 fixed. Broken lines show the variation of the boundaries where C,,-oxide capacitance per unit area, ND-substrate when modifying vG2 or v G1 , respectively. Device parameters doping concentration, e,-semiconductor permittivity. are: Cox= 2.5 X 10-4 pF/pm2, N o = 15 X 1015 cm, p2/ p1 =2.2, The corresponding drain saturation voltage is vs=ov. VDsat= V&- 2 @F+- k [ 1 - ( 1 +2 4kyd)]i2 . 2 The dual-gate MOSFET saturates whenever either channel pinches off. The drain voltage corresponding to the pinch-off condition for the second channel VDsat2 is a function of Vd2 only and is given by (3) in which V& is replaced by Vd2, Let V, be the difference between the quasi-Fermi potentials at the intermediate point in the channel, just under the gap (whose width is assumed to be zero). VI can be imagined to represent both the drain voltage for the first channel and the source bias for the second channel. The first channel pinches off when VI reaches a value VIsatl given by (3) in which V& is replaced by Vdl (it is assumed that VF, is the same for both devices). The drain voltage for which the first channel pinches off VDsatl can then be calculated from An even simpler model, which ignores the variation of deple- tion charge with position, is derived in the Appendix. Note that both models assume the output conductance in satura- tion to be zero. The drain saturation voltages VDsatl and V&t2 define the characteristic operational modes of a dual-gate MOSFET, as illustrated in Fig. 4. I n Fig. 4(a) it is visible that since the first- gate bias voltage is only able to control the behavior of the first channel, by varying VG alone the dual-gate MOSFET has only two alternatives. Unlike VG 1 , the second-gate bias volt- age is capable of controlling the behavior of both channels and, as a result, the device can pass through three different operating regions by varying V G 2 , as illustrated in Fig. 4(b). An additional characteristic feature of dual-gate MOSFETs concerns the dependence of the drain breakdown voltage on the equationrol(VIsat1)=rD2(V;)sat1). the applied gate biases. For thin (<15OO-A) gate oxide layers (i.e., devices not optimized for very high breakdown voltage) breakdown occurs at the semiconductor surface or along the drain junction curvature. For V G ~ below 40 V, surface break- down with multiplication of the drain current is illustrated in Fig. 2 . The breakdown voltage decreases as the first gate potential (and hence the drain current) increases. The depen- dence of the breakdown voltage on the second-gate bias volt- age is shown in Fig. 5 . The increase of the breakdown voltage with increasing VG, can be explained by the redistribution of the field at the drain junction, as a function of v G2 [I O], [13] . For small and moderate VG2 values, breakdown occurs at the surface in the vicinity of the drain junction (Fig. 5(a)). Increasing VG2 increases the breakdown voltage since the surface field in the depleted pinch-off region near the drain decreases. When the second channel reaches the drain, the breakdown process along the junction curvature dominates over corner breakdown and the breakdown voltage increases only slightly with V G 2 . 111. DEVICE MODEL We shall derive in this section an accurate physical model for the dual-gate MOSFET. Let us first consider the region under the first gate and assume that the channel is pinched off, as illustrated in Fig. 1. The region under consideration is essen- tially an MOS transistor with an inverted drain. The loca- tion of this drain is somewhere underneath the intergate gap (which is assumed to be neglibibly small). The exact position is determined by the two-dimensional distribution of the fring- ing fields associated with the two gate electrodes. However, since the surface longitudinal field directly under the gap is very high and decreases rapidly at a very short distance from 526 IEEE TRANSACTIONS ON ELECTRON DEVI CES, VOL. ED-28, NO. 5, MAY 1981 n 4 VG, 2 15 v B o DEVICE 7 - 16 W 0 30 60 90 SECOND GATE VOLTAGE ( V ) (b) Fig. 5. (a) ID-VD characteristics of dual-gate MOSFET with vG2 as parameter. Vcl =40 V. (b) Measured breakdown voltage of the same device, as a function of vG2. this point, we can safely assume the position of the inverted drain to be at y =L1 . The validity of this assumption can become questionable only for very short channels (<3 pm), or very thick gate oxide layers. By taking the mobility dependence on the normal and longi- tudinal fields of the form where 4, is the surface potential, / t o the low-field surface mobility, E, the critical field, and rC, a constant potential de- scribing the dependence of mobility upon normal field, the drain current of an MOS transistor with channel length L and width W can be expressed [14] as -u c - -- 1 2 (5) where =Vs t 2 @F and GD =VD t 2 @IF. The short-channel effect can be incorporated in V& in the form of a threshold re- duction term y(VD - vs) [15], 1161, where y is a factor depending on the channel length and junction depth. To avoid the discontinuity which results from the definition of the pinch-off point by a particular value of either the normal or the longitudinal field, we consider, following Rossel et al. [14], the pinch-off point to be defined by a quasi-Fermi potential separation Vp and a longitudinal field Ep , which are determined by the continuity of the longi- tudinal field and of its derivative. Letting Zdl be the length of the depleted region near the hwerted drain, the current is given by where I Ds at l =ID(vS, VGl , Vpl ). The effective drain potential VI can be determined from Poissons equation which is subject to the boundary conditions dV dY v= fi, aty=L 1. V = Vpl and - - =Epl , aty=L 1 - l d l Solving (7) for VI yields I n the above equations X 1 is a constant which models the drift of carriers through the drain depletion region [14] , [17]. I n the case of the inverted-drain MOSFET, the car- riers are assumed to travel at limit velocity uL within a sheet of uniform thickness d, so that (9) The thickness d is expected to be much larger than the usual thickness of an inversion layer [14] because throughout the drain space-charge region the normal field pushes the carriers away from the surface, so that they spread to a much larger average depth [ 181 . The pinch-off voltage and field can be determined by equating the longitudinal surface field and its derivative in the gradual channel at the pinch-off point to the corresponding quantities in the depletion region at the same point. The re- sults are -1 EP1 =[ - (1 0) I D BARSAN: DUAL-GATE MOSFETs 521 where ( ppl =V t 2~45~. Substitution of (10) into (1 1) yields an equation whch can be solved for (pp 1. Consequently, Vp and Ep can be determined as functions of VG and I D. The depletion length l dl can now be calculated using (6) and finally the inverted-drain voltage Vz given by (8) can be deter- mined as a function of Vs , VG , and I D. A similar model applies to the region under the second gate, when the second channel is pinched off. Here VI represents the effective voltage of the inverted source, V,, and Ep? are the pinch-off voltage and field, respectively, and Za2 1s the length of the depletion region extending from the pinch- off point to the metallurgical drain. The set of equations dis- cussed above, with the exception of (9), also applies to this region, provided subscript 1 is replaced by 2 and Vz is substi- tuted for Vs. The behavior of carriers near the drainis modeled according to the triangular hypothesis [17] , i.e., carriers are assumed to spread over a depth ranging from d at the pinch- off point, to X i at the drain. As a consequence, the factor multiplying the current in Poissons equation is given in this region by the expression p? Using the procedure previously described with regard to the first channel, the drain voltage can be calculated as a function of V,, V G 2 , and ID, where VI is itself a function of Vs, VG 1, and I D. This means that the drain voltage VD can be deter- mined for given drain current and source and gates biases. When one of the two channels is below pinch off, ( 5 ) in which the proper voltages are included, directly yields the relation- ship between drain voltage (V, or VD) and current. The model discussed above gives the drain voltage as a func- tion of current. However, in order to be useful for calculating static characteristics, as well as incremental device parameters, the mathematical algorithm must yield the drain current as a function of applied voltages. Consequently, an iterative pro- cedure is needed. For given terminal voltages, an initial estimate of the drain current is calculated (e.g., using the simple analysis given in the Appendix). Using this value, the drain voltage is calculated with the aid of the model described and then compared with the specified value V . If the. computed value is less than VD the current is increased and if it exceeds VD the current is reduced. The new ID value is again used to compute the drain voltage and the process continues until the desired accuracy for the drain voltage is reached in this work). The amount by which I D is modified at each iteration step is halved each time the difference between the computed drain voltage and VD changes sign. Within any iteration step each channel is first assumed to be pinched off and the depletion length is calculated. If the depletion length is less than or equal to zero, the channel in question at that particular itera- tion step is not pinched off and ( 5) is solved directly for the drain voltage. An alternative to the approach presented here would be to separately solve for I D the systems of equations of the regions TABLE I CHANNEL DIMENSIONS OF DUAL-GATE MOSFETs USED JN EXPERIMENTS J * l 16-7 3-16 16-3, 7-4 4-7 7-16 Device 3-16 16-3, 7-4 4-7 7-16 16-7 L1 (pm) 3.3 1 6 . 4 7 . 4 4.5 7 . 4 1 6 . 4 L2 (p) 1 6 . 4 3.3 4. 5 7 . 4 1 6 . 4 7 . 4 W (pm) 6 2 . 7 6 2 . 7 6 2 . 7 6 2 . 7 6 2 . 7 6 2 . 7 L2 (p) 1 6 . 4 3.3 4. 5 7 . 4 1 6 . 4 7 . 4 W (pm) 6 2 . 7 6 2 . 7 6 2 . 7 6 2 . 7 6 2 . 7 6 2 . 7 under the two gates, using iterated values for the internal volt- age &. Each system would then yield a different current value and the process would be stopped when the difference be- tween the two currents were within the desired accuracy. This procedure is less suitable because at each iteration step it re- quires the solution of up to two different systems of nonlinear equations in I D (when both channels are pinched off), i.e., additional internal iteration cycles. The approach used here only requires the solution of one nonlinear equation for each channel. The mobility parameters po and 11/ can be determined as for single-gate MOS transistors [19], by connecting together the gates of dual-gate devices. The parameter d was determined by a best fitting procedure applied to the drain current character- istics of the dual-gate MOSFETs. The values of the model parameters used in this work (p-channel devices) are: po =200 cm2/V s, $ =34 V, E, =10 V/pm, uL =6.5 X lo4 m/s, and d =4500 A. Iv. RESULTS OF ANALYSIS AND EXPERIMENTS Several dual-gate MOSFETs were built on the same chip in order to investigate the device characteristics of a variety of structures. The channel dimensions (after processing) of the transistors referred to in this work are given in Table I ~ together with the oxide thickness, junction depth, and substrate doping concentration. The devices are labeled according to the lengths of their channels, the two numbers representing the rounded values of L l and Lz , respectively. The measuring setup consisted of a wafer prober, a desk-top calculator-monitored measuring and data acquisition system, a plotter, and a printer. To avoid negative resistance effects due to local channel heating [8], after each measurement the structure under test was allowed to cool for a time period equal to the time during which data acquisition was made (typically 10 ms) plus a relaxation time proportional to the ID VD product. All measurements reported in this study were performed with source and substrate grounded. Fig. 6 shows the ID(VD) characteristics of a dual-gate MOSFET with VG2 fixed. The boundaries between opera- tional modes, as indicated by computer calculations, are superimposed as brokenlines. Note the qualitative resemblence between these boundaries and those of Fig. 4(a), when the I D axis is taken as the VG axis. Having gained confidence in the accuracy of the theoretical model from the excellent agreement between calculated and measured drain current characteristics, we can now use the 528 I EEE TRANSACTI ONS ON ELECTRON DEVICES, VOL. ED-28, NO. 5 , MAY 1981 DEVICE 16-7 2 1 2 - ~ L - L L - s E 0 5 10 15 20 25 30 3 5 LO L 5 50 DRAI N VOLTAGE , Vo ( V ) Fig. 6. Measured (full lines) and calculated (circles) ID-VD character- istics of device 16-7. 0 5 10 15 20 25 30 35 40 DRAI N VOL TAGE , VD ( V I (a) DRAI N VOL TAGE Vg ( V) (b) Fig. 7. (a) Internal voltage VI versus drain voltage. (b) Depletion lengths Id1 (solid lines) and 1d2 (broken lines), versus drain voltage, for device 16-7. model to analyze the internal parameters. The calculated inverted drain voltage and depletion lengths are plotted in Fig. 7 as functions of VD. For small VD neither channel is pinched off. By increasing VD, channel 1 pinches off first; the smaller VG,, the sooner. l dl increases now with increas- ing VD up to the point when the second channel pinches off too. From then on the drain terminal loses control upon VI, so that both 6 and saturate. In this region (s-S) almost Fig. 8. Measured (full lines) and calculated (circles) ZD-VG~ istics of device 16-7. SECOND GATE VOLTAGE, V G ~ ( V ) (a) VD 30V v, , 510 v character- 10 15 20 25 30 35 40 45 50 SECOND GATE VOLTAGE, VG,(V) cb) Fig. 9. (a) Internal voltage VI versus V G ~ . (b) Depletion lengths ldl (solid lines) and l d2 (broken lines), versus V G ~ , for device 16-7. the entire excess drain voltage is taken over by the space- charge region adjacent to the drain junction. Comparison between theory and experiment is further illustrated in Fig. 8, concerning the I D ( V ~ ~ ) characteristics. The boundaries of the operating regions are, here too, super- imposed. Note that when the first channel pinches off, the second-gate voltage no longer affects the current which is controlled in this case by the first gate alone. The dependence of the internal voltage and of the depletion lengths on the second-gate bias voltage is shown inFig. 9. As VG, increases, BARSAN: DUAL-GATE MOSFETS 529 TABLE I1 DEPENDENCE OF PINCH-OFF VOLTAGES AND FIELDS ON GATE BIASES I vG1=l ov VG2=30V 2. 22 19. 77 0. 906 0. 951 i 28.96 18. 69 27. 83 0. 929 3. 525 3. 637 0. 986 3. 202 3. 345 the first channel pinches off and the dual-gate MOSFET passes from the L-S region to theS-S region. The fact that VG, acts (through Vj ) as drain bias for the first channel is clearly visible in Fig. 9(a). The length of the intermediate depletion region l dl increases with increasing VG,, whereas l d2 decreases much like in a single-gate device. When the second channel reaches the drain junction, the influence of the second gate is considerably diminished while the drain takes over control of the internal voltage. With regard to the pinch-off potentials and fields, the effects of the gate voltages are disclosed in Table 11, for V, =30 V. I t is visible that Vpl and Epl are only slightly affected by VG, and similarly Vp2 is only slightly influenced by VG 1 . Both Vpl and Ep increase with increasing VG,. An unexpected behavior is exhibited by Ep2 which depends only slightly on VG, and instead is considerably affected by VG 1 . This can be explained by observing in Fig. 8 that in the S-S mode the cur- rent is practically controlled by VGl only and an increase of the current results in an increase of the pinch-off field (pro- vided the pinch-off potential does not change significantly), as indicated by (10). It is also worth noting in Table I1 that the pinch-off fields show values appreciably lower than the critical field (10 V/pm). v. OUTPUT CONDUCTANCE For many analog applications (of both discrete devices and integrated circuits) using dual-gate MOSFETs, the drain con- ductance gds is a major consideration. This parameter clearly reveals the operational features of dual-gate transistors. The ID(V) characteristics in Fig. lO(a) visibly show a breakpoint in the saturation region. The abrupt decrease of gd, beyond a certain drain voltage value also is evidenced by the theoretical plots in Fig. 1O(b). The three distinct operating regions dis- cussed with reference to Figs. 4 and 7 can now readily be recognized. For small drain voltages both channels operate in the linear region and g,, is very large. By increasing V,, the device enters the S-L region where gds is much smaller. Further increase of V forces the transistor into the S-S region where gds is dramatically reduced because the drain is very effectively isolated from the source. When only the first channel is pinched off, gds has a larger value since the charge control from the drain side, through the second channel, is still active. Also note in Fig. 10(b) that gds is weakly depen- dent on V G ~ when both channels are pinched off, whereas - 0 t: 20 VG2 =40 v W z v 1 5 u 10 n z z B O 15 30 45 DRAI N VOL TAGE, VD ( V ) @) Fig. 10. (a) Drain characteristics of dual-gateMOSFET for VGZ =40 V. First trace: V G ~ =8 V. (b) Calculated output conductance of the same device, as a function of drain voltage. 7 1 V D = 2 5 V DEVI CE 7-4 E, - A S- S 0 5 10 15 20 25 30 35 SECOND GA T E VOL T A GE, VGZ ( V) Fig. 11. Measured (full lines) and calculated (symbols) output conduc- tance, as a function of second-gate bias voltage. V,, has an appreciable effect when only the first channel is pinched off and VG, controls the single space-charge region laying between source and drain. Similar considerations make possible the interpretation of the dependence of gds on V G ~ , which is illustrated in Fig. 11. Also referring to Figs. 4(b) and 9, for small second-gate volt- ages, gds increases with increasing VG, since only the second channel is pinched off. This behavior is similar to that of a normal MOSFET. After entering the S-S operational mode,gd, decreases with increasing VG,. This is a result of the drain- voltage effect of VG, on the region under the first gate. Once the second channel has reached the drain junction, gd, 5 30 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO..5, MAY 1981 I I 1 I DEVICE 1 6 - 7 / O I 0 10 20 30 40 0 10 20 30 40 V(j 2 ( V ) (a) (c) 5 5 I DEVICE 16 - 7 DEVICE 3- 16 - cn 0 0 vo = 4 5 v 10 20 30 40 0 10 20 30 40 VG2 ( V ) VGZ ( v) @) ( 4 Fig. 12. Measured (full lines) and calculated (circles) output conduc- tance versus secondgate bias voltage. The broken lines in Fig. 12(a) and (b) show the saturation drain conductance of the corresponding normal MOSFET (the two gates connected together). again increases with VG, since the effectiveness of the feed- back from the drain increases. This mechanism now dominates over the drain-voltage effect of VG2 (i.e., VI is controlled by VD rather than by VG2). Fig. 12 shows the saturation output conductance of two dual-gate MOSFETs, for two different drain voltages in each case. The plots in Fig. I2(a) can be interpreted in the light of the previous considerations: by increasing VGZ the device crosses three different operating regions. The higher VG 1, the higher the VG2 value for which the first channel pinches off too. As a consequence, the peak of gds moves toward higher VG2 values when V G ~ increases. If VG is very large the first channel does not pinch off at all. In Fig. 12(b) the behavior of gds for a higher drain voltage is presented. In this case, the VG2 bias required to bring the second channel in the linear region is very high so that the convergence of thegds plots in the S-S mode can be observed. The output resistance in this region, for sufficiently high VG,, shows values in excess of 10 Ma. In the same range of applied voltages, the output conduc- tance of a device with a first channel 3.3 pm long, is shown in Fig. 12(c) and (d). Because the second gate is much longer than the first, gds of the dual-gate transistor, for moderate VD values (L-S region), is practically given by the second- channel length modulation. It increases thus rapidly with increasing VG,, exactly like for anormal MOSFET (Fig. 12(c)). Only if V, is large enough (Fig. 12(d)), does gas show a de- creasing region (5-S mode) for low V G ~ and a rapidly increas- ing region (L-L mode) for higher VG 1 . The dependence of gds on the first-gate bias voltage can be assessed from the plots in Fig. 13. For a device with com- parable channel lengths (Fig. 13(a)),gds increases rapidly with increasing VGl for large VG2 (S-L and L-L modes) and grad- ually levels off for low VG2 values (S-S and L-S modes). The very weak dependence of gds on V, in the L-S region is evident in the case of a device with G2 much longer than GI (Fig. 13(b)). VI. TRANSCONDUCTANCES Two transconductances can be defined for a dual-gate MOSFET: one,gml ,withrespect tothe first gate, and another, gmz, with respect to the second gate. The dependence of gml on the applied gate voltages is shown in Fig. 14. This transconductance is of interest in the majority of gain control applications. gml decreases with in- creasing VGl when the device operates in the L-S mode (Fig. 4(a)) and the current is mainly controlled by the second channel. This is more evident in the case of a device with G2 much longer than G 1 (Fig. 14(c)), whose gml shows a very sharp peak and then rapidly falls to very small values. However, for very large VG 1, gml starts increasing again slightly, a fact not predicted by the theoretical model. This effect is due to a small excess current showing up at high first- gate bias voltages. The slight increase of the current with in- BARSAN: DUAL-GATE MOSFET's 531 0 10 20 30 40 50 F I RS T GATE VOLTAGE , vG1 ( v ) 2 1 0 I 5 DEVICE 3- 16 1 0 10 20 30 40 50 FI RST GATE VOLTAGE, V G ~ ( V I (a) (b) Fig. 13. Output conductance as a function of fust-gate bias, for two different dual-gate MOSFET's. Solid lines represent measurements and circles show calculated values. Broken lines correspond to the normal MOSFET connection. I DEVI CE 1 6 - 3 0 -e 5. - 100 - rn E 50 0 - 150 0 c E, - 1oc - P, E 50 0 DEVI CE 16-3 I 0 10 20 30 40 200 150 - - 0 c 5 100 - E - E 0 50 - 0 200 150 - 0 c E .3100 - CII E 50 0 Fig. 14. Transconductance with respect to the first gate, as a func- tion of gate biases, for two different (complementary with respect to channel lengths) dual-gate transistors. Full lines show experimental results and circles represent theoretical values. creasing V,, , for large VG values, could be explained by the extension of the first channel under the second gate. This results in a reduction of the effective length of the second channel which is the one controlling the current. The second-gate voltage modifies g,, only when the second channel is pinched off (Fig. 14(b)). The point when gml saturates, approximately corresponds to the second channel reaching the drain. In the case of a dual-gate device with a much shorter first channel, the drain current is controlled by VG, up to much higher values (Fig. 14(d)). From the plots in Fig. 14 it can be concluded that gain (gml) control can bemost effectively achieved via Vcl (in the down- ward going region of g,,-Fig. 14 (a)) for a device with L z <L1, and via VG, (in the upward going region-Fig. 14(d)) for the case when L <L 2 . If gain linearity is a major require- ment [9] , electronic control viaG2 is best suited. 532 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 5, MAY 1981 200 200 DEVICE 16- 3 DEVICE 3 -16 150 - 0 c - 100 - 5 N E 0 50 - 0 - 0 vg = 35 v & 200 20 0 I DEVI CE 16-3 DEVICE 3 - 16 150 - x 5 I 100 - N E 0 50 - vg = 35 v 0 10 20 30 40 0 10 20 30 40 VG2 ( v) vG2 (v) (b) ( 4 Fig. 15. Measured (full lines) and calculated (circles) gm2 as a function of applied gate voltages, for the same two devices as in Fig. 14. Experimental and calculated results for the transconductance with respect to the second gate are included in Fig. 15. The poor agreement between calculated and measured gp,2(vG2) for low V,, values in Fig. 15(b) comes from the contribution of the punch-through current, not included in the theoretical model. I n Fig. 15(d) an increase of the transconductance for high gate biases, similar to that discussed with reference to Fig. 14(c), also is visible. In this case it is the second channel which extends slightly under the first gate. A general conclusion with regard to the results of Figs. 14 and 15 is that the transconductances either exhibit a peak and then decrease, or level off beyond some particular gate voltage value. To first order, even the oversimplified analysis given in the Appendix is sufficient for a qualitative description. From this model, as soon as the first channel pinches off gml be- comes roughly proportional to V, l (independent of VG2) and g,2 is zero. Thus gml and gm2 (VG2) show a rise-and- fall behavior (going toward a small value corresponding to the L-S mode, or zero, respectively), whereas gml(VGz) and gm2( V, 1) exhibit (eventually) saturated characteristics. VII. CONCLUDING REMARKS The static characteristics of dual-gate MOS transistors have been investigated, both experimentally and theoretically. The physical model for a pinched-off channel takes into account the inverted channel region, in which the gradual approxima- tion is assumed to be valid, and a drain depletion region, in which Poissons equation has to be solved. A triangular cur- rent flow model is used for the depletion region near the diffused drain, whereas in the inverted-drain space-charge region the carriers are assumed to drift within a layer of uni- form thickness. Mobility reduction due to both the transversal and longitudinal fields is considered. The models correspond- ing to the two channels are coupled by means of the inverted- drain surface potential. An iterative algorithm is used to compute the drain current for a given set of applied voltages. The accuracy of the model has been tested on a variety of structures and was found excellent. Consequently, a reliable investigation of the internal parameters, such as depletion lengths and pinch-off potentials and fields, has been possible. Although short-channel effects have been taken into account in the model, it was found that for the devices which were evaluated (with one channel as short as 3.3 pm) the short- channel threshold effect is negligible (y =0). Short-channel effects can, however, be important in devices with both channels significantly scaled down. In this case, punch- through currents, as well as fringing-field effects in the gap region, also must be considered. The characteristic operational modes of dual-gate MOSFETs BARSAN: DUAL-GATE MOSFETS 533 have been analyzed and used to explain the observed behavior with respect to applied voltages. Emphasis has been placed on the output conductance and transconductances. Several aspects of dual-gate transistor characterization have not been considered in the present work and are subjects for further investigation. These include the frequency response, dynamic parameters, and noise. Regarding dual-gate MOSFETs with both channels shorter than 3 pm, the model developed in this study can be extended to include two-dimensional field effects in the transition region between channels, as well as sub- threshold operation. Although not directly addressing the problem of device design optimization, which is largely depen- dent on the particular application, the present analysis can be very effectively used to investigate the behavior of dual- gate MOSFET devices or circuits with respect to any electrical or geometrical design parameter, APPENDIX Simple Analytical Model for Dual-Gate MOSFETs In order to obtain closed-form expressions for the drain cur- rent in each operating region, (1) is still too complicated to be used. Analytic solutions can only be derived ignoring the body effect. This is a crude approximation, especially for the second channel, but the results are useful for a qualitative first- order description. Using the simplified forms for the drain current of an MOS transistor and below and above pinch off, respectively, the intermediate node voltage V can be calculated by solving the equation ID =ID,. Since the body effect is ignored, the source bias of the dual- gate MOSFET only adds algebraically to all applied voltages and, therefore, can be taken zero without loss of generality. When both channels are operating in the linear region, one finds that - [(v, t mv2) - m(m +1 ) ( 2 ~ 2 VD - I 2 ) (-43) where VI =VG 1 - V,, , V, =V,, - V,, , V,, and V,, being the threshold voltages of the two channels and m =&/ &. The saturation drain voltage for the second channel is b s a t z =VZ (A41 and that corresponding to the saturation of the first channel (VI= Vl ) is For VD >V, and V, <(1 +m-I2) Vl , the second channel is pinched off and V, no longer depends on the applied drain voltage. For V D ~ ~ ~ ~ <V < V, , the first channel is pinched off and v,= V, - [(V, - V,)2 t - V f . m 1 l P (A71 For V >V, >I1 t m-l/*) Vl , both channels operate in the v,= V, - m-12 V, . (A8) Substitution of V, into the proper current expression yields saturation region and the drain current as a function of applied voltages. ACKNOWLEDGMENT The author is very much indebted to C. Bulucea for his sup- port and stimulating suggestions. He also would like to thank A. Delibaltov for invaluable help in device processing, T. Cglin for assistance in the measurements, and A. Rusu, D. Cioacg, and A. Gurau for helpful discussions. REFERENCES T. Okumura, The MOS tetrode, Philips Tech. Rev., vol. 30, pp. 1347141, May 1969. R. J . Nienhuis, A MOS tetrode for the UHF band with a channel 1.5 pm long, Philips Tech. Rev., vol. 31, pp. 259-265, Aug. 1970. F. M. Klaassen, H. J . Wilting, and W. C. J . de Groot, A UHF MOS tetrode with polysilicon gate, Solid-state Electron., vol. 23, pp. 23-30, J an. 1980. R. R. Troutman and H. S. Lee, Inversion charge transistor (ICT) for better threshold control in small dimensions, IEEE J. Solid- State Circuits, vol. SC-13, pp. 490-491, Aug. 1978. N. Weste and J . Mavor, ZOGMOST: An improved m.0.s.t. for c.c.d. peripheral circuits, Electron. Lett., vol. 12, pp. 591-592, Oct. 1976. N. H. Weste, Interactive integrated circuit design: An implemen- tation using a monochrome and colour graphics system, Ph.D. dissertation, Dep. of Electrical Engineering, Univ. of Adelaide, Aug. 1977. N. Weste and J . Mavor, MOST amplifiers for performing periph- eral integrated-circuit functions, IEE J. Electron Circuits Sys- tems, vol. 1, pp. 165-172, Sept. 1977. R. M. Barsan, Dual-gate bucket-brigade devices, IEEE Trans. Electron Devices, vol. ED-27, pp. 1809-1816, Sept. 1980. S. H. Kwan, C. T. Chuang, R. S. Muller, and R. M. White, Dual- gate depletion-mode DMOS transistor for linear gain-control applications, IEEE Trans. Electron Devices, vol. ED-26, pp. 1053-1058, J uly 1979. H. G. Dill, A new insulated gate tetrode with high drain break- down potential and low Miller feedback capacitance, IEEE Trans. Electron Devices, vol. ED-15, pp. 717-728, Oct. 1968. W. P. Noble, J r., Short-channel effects in dual-gate field-effect transistors, presented at IEEE Int. Electron Dev. Meeting, Dig. Tech. Papers, pp. 483-486, Dec. 1978. 5 34 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 5 , MAY 1981 [ 121 V. A. Browne and K. D. Perkins, A non-overlapping gate charge- coupling technology for serial memory and signal processing applications, IEEE J. Solid-state Circuits, vol. SC-11, pp. 203- 207, Feb. 1976. [13] H. G. Dill and T. N. Toombs, A new MNOS charge storage effect,Solid-State Electron., vol. 12, pp. 981-987, 1969. [14] P. Rossel, H. Martinot, and G. Vassilieff, Accurate two sections model for MOS transistor in saturation, Solid-state Electron., [15] G. W. Taylor, The effects of two-dimensional charge sharing on the above-threshold characteristics of short-channel IGFETs, Solid-State Electron., vol. 22, pp. 701-717, 1979. V O~. 19, pp. 51-56,1976. [16] F. M. Klaassen and W. C. J. de Groot, Modeling of scaled-down MOS transistors, Solid-state Electron., vol. 23, pp. 237-242, 1980. [17] G. Merckel, J. Borel, and N. Z. Cupcea, An accuratelarge-signal MOS transistor model for use in computer-aided design, IEEE Trans. Electron Devices, vol. ED-19, pp. 681-690, May 1912. [18] D. Vandorpe, J. Borel, G. Merckel, and P. Saintot, An accurate two-dimensional numerical analysis of the MOS transistor, Solid-state Electron., vol. 15, pp. 547-557,1972. [ 191 P. Rossel, Influence on the characteristics of m.0.s. transistors of the mobility reduction due to a transverse electric field, Elec- tron. Lett., vol. 5, pp. 604-605, Nov. 1969. Two-Dimensional Simulation of a High-Voltage p-i -n Diode wi th Overhanging Metallization Ahtract-A two-dimensional computer simulation of a high-voltage p-i-n diode for a microwave phase shift network mounted in parallel with a microstrip tine has been carried out. The electric field distribution in four different device structures has been analyzed. It is shown that the microstrip line which forms a metal overhang on top of the device can reduce its breakdown voltage due to enhanced total and normal field components at the silicon-dielectric interface. Also, this could lead to avalanche injection of hot carriers into the dielectric which could impair the long-term performance of the device. A structure which should prove less prone to these adverse effects is reported. I I . I NTRODUCTI ON N THIS PAPER we consider a high-voltage p-i-n diode for an F-band phase shifting network mounted in parallel with a microstrip line Fig. l(a)-(d). This leads to the presence of metal overhangs on top of the device. It has been reported that the metal overhangs presumably have an adverse effect on the blocking voltage of a p-i-n diode [l]. However, no de- tailed theoretical treatment of the problem is yet available. We have carried out a detailed two-dimensional computer Manuscript received J uly 10, 1980; revised October 31, 1980. This work was supported in part by research grants from the Natural Sciences and Engineering Research Council, Canada, and Thomson-CSF, France, and also DALSA Inc., Waterloo, Ontario, Canada, for support on the software development. R. Kumar and S. G. Chamberlain are with the Electrical Engineering Department, University of Waterloo, Waterloo, Ontario, Canada N2L 3G1. D. J. Roulston is with the Electrical Engineering Department, Uni- versity of Waterloo, Waterloo, Ontario, Canada N2L 3G1. He is now on a one year sabbatical with the Department of Electronics, The University of Southhampton, Southampton, England. analysis in the presence of a reverse blocking voltage. The following four structures have been analyzed: a) p-i-n diode with a vertical edge, Structure #1, Fig. l(a) b) p-i-n diode with a vertical edge and a molybdenum disk on top of the p+ diffused layer, Structure #2, Fig. l(b) c) p-i-n diode with a negatively beveled edge, Structure #3, Fig. l(c) d) p-i-n diode with a positively beveled edge, Structure #4, Fig. l(d). Information has been obtained on the field and potential distribution in the above device structures. It is shown that a high field region is developed in some cases in silicon close to the silicon-dielectric interface, which could reduce the block- ing voltage of the p-i-n diode in the presence of metal over- hangs. It is further shown that there exists a significant com- ponent of field normal to the interface. This could cause avalanche injection of hot carriers into the dielectric 131-[ 111. As a result, the various trapping sites in the dielectric could get charged up. This in turn could distort the field distribution along the interface and hence adversely affect the blocking voltage of the diode. The bombardment of highly energetic carriers against the interface could also create fast surface states which would give rise to a high leakage current [7], [8]. All of these effects could result in a reduced reliability of the device. 11. THE DEVICE MODEL A two-dimensional computer algorithm has been developed for a p-i-n diode with metal overhangs for the structures shown in Fig. l(a)-(d). The program provides maps of potential and field distribution throughout the device cross section. A 0018-9383/81/0500-0534$00.75 0 1981 IEEE