EEEB273 Electronics Analysis & Design II

Lecturer: Dr Jamaludin Bin Omar 8-1

Gain Stage and
Simple Output
Stage
Reference: Neamen, Chapter 11
(8)
I
Learning Outcome
Able to:
Analyze an example of a gain stage and
output stage of a multistage amplifier.
Z
3
In virtually all operational amplifiers (op-
amps), there are 3 stages:
1) First stage is Input Stage Diff-amp with
active load to amplify difference
between input signals v
1
and v
2
.
2) Second stage is Gain Stage Darlington
pair to provide additional gain.
3) Third stage is Output Stage Emitter
follower to minimize loading effect on
output signal.
8.0) Introduction
4
8.1) Darlington Pair and Simple Emitter-Follower Output
4
Figure 11.46 shows a BJT diff-amp with a
3-transistor active load, a Darlington pair
connected to the diff-amp output, and a
simple emitter-follower output stage.
Diff-pair transistors (Q
1
and Q
2
) are biased
with a Widlar current source at a bias
current I
Q
.
For the diff-amp currents to be balanced:
(11.118)
( ) +
= =
1
5
Q
B O
I
I I
b
8.1) Darlington Pair and Simple Emitter-Follower Output (Cont)
b
Figure 11.46
o
8.1) Darlington Pair and Simple Emitter-Follower Output (Cont)
o
From the figure, can be seen
(11.119)
In order for I
O
= I
B5
, require that I
C7
= I
Q
Means that emitter resistors of Q
10
and Q
11
should have same value (i.e. R
2
= R
3
).
Q
11
also acts as an active load for Darlington pair
gain stage.
Q
8
and R
4
form the simple emitter-follower output
stage minimizes loading effects because its
output resistance is small.
( ) ( ) +
=
+
=
1 1
7 6 C E
O
I I
I
EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 8-2
7
8.1) Darlington Pair and Simple Emitter-Follower Output (Cont)
7
Ideally:
When diff-amp input is a pure common-
mode signal, the output v
o
= 0.
The combination of Q
7
and Q
11
allows dc
level to shift.
By slightly changing bias current I
C7
V
EC7
and V
CE11
can be varied such
that v
o
= 0.
This small variation in I
C7
will not
significantly change the balance between
I
O
and I
B5
.
8
8.2) Darlington Pair: Input Impedance
8
The input resistance of Darlington pair (Q
6
and Q
7
)
determines the loading effect on basic diff-amp.
The gain of Darlington pair affects the overall gain
of the op-amp circuit, and the output resistance of
the emitter follower determines any loading effects
on the output signal.
Figure 11.47(a) is the ac equivalent circuit of the
Darlington pair, where R
L7
is the effective resistance
connected between collector of Q
7
and signal
ground.
Figure 11.47(b) is the simple hybrid- model of
the Darlington pair Q
6
and Q
7
turned upside down.
9
8.2) Darlington Pair: Input Impedance (Cont)
9
Figure 11.47: The Darlington pairs
(a) ac equivalent circuit, and
(b) small-signal equivalent circuit
( )
( )

=
+ =
(

+
=
+ =
=
+ =
6 6
6 7 6
6
7 7
6 6
6
6
7
7
6 6 6
7 6 6
1
1
m
b
m
b
b
g r
I r V
r
r V
V g
r
V
r
V
r I V
V V V
I0
8.2) Darlington Pair: Input Impedance (Cont)
I0
Writing a KVL equation around the B-E loop of Q
6
and Q
7
can obtain
(11.120)
Also (11.121)
The KCL equation at node E
6
is
or (11.122(b))
where
( )
( )
( )
Q
T
C
T
Q
T
C
T
b
b
i
b b b
I
V
I
V
r
I
V
I
V
r
r r
I
V
R
I r r I V

+
= =
= =
+ + = =
+ + =
1
1
1
6
6
7
7
7 6
6
6
6 7 6 6 6
II
8.2) Darlington Pair: Input Impedance (Cont)
II
Substitute (11.122(b)) and (11.121) into (11.120) to
obtain
(11.123)
The input resistance is therefore
(11.124)
Assuming I
C7
= I
Q
, the hybrid- parameters are
(11.125(a))
(11.125(b))
IZ
8.2) Darlington Pair: Input Impedance (Cont)
IZ
Combining (11.125(a)), (11.125(b)), and (11.124)
yields an expression for input resistance, as follows:
(11.126)
( ) ( ) ( )
Q
T
Q
T
Q
T
i
I
V
I
V
I
V
R
+
=
+
+
+
=
1 2 1 1
EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 8-3
( )
( )
( )
( )
7
7
7
6
3
6
6
7 6 7 7 7 7 3
2
1 2
1
1
1 ) (
L
T
Q
Q
T
L
v
i
L
b
o
v
i
b
b
L b L b L c o
R
V
I
I
V
R
A
R
R
v
v
A
R
v
i
R i R i R i v
|
|
.
|

\
|
=
+
+
=
+
= =
=
+ = = =




I3
8.3) Darlington Pair: Voltage Gain
I3
To determine small-signal voltage gain of the
Darlington pair, from Fig 11.47(b) can be obtained
Voltage
Gain:
Thus, (11.130)
I4
8.3) Darlington Pair: Voltage Gain (Cont)
I4
From Figure 11.46, can see that R
L7
is the parallel
combination of the resistance looking into collector
of Q
11
and the resistance looking into base of Q
8
.
Resistance looking into collector of Q
11
is
(11.131)
where
Resistance looking into base of Q
8
is
(11.132)
Since R
c11
and R
b8
are large, then the effective
resistance R
L7
is also large.
( )
3 11
'
'
11 11 11
1
R r R
R g r R
E
E m o c

=
+ =
( )
4 8 8
1 R r R
b

+ + =
Ib
8.3) Darlington Pair: Voltage Gain (Cont)
Ib
Example 11.13
Objective:
Calculate the input resistance and the small-signal
voltage gain of a Darlington pair.
Consider the circuit shown in Figure 11.46, with
parameters I
C7
= I
Q
= 0.2 mA, I
C8
= 1 mA, R
4
= 10
k, and R
3
= 0.2 k. Assume = 100 for all
transistors, and the Early voltage for Q
11
is 100 V.
Io
8.3) Darlington Pair: Voltage Gain (Cont)
Io
Example 11.13 (Cont)
Solution: The input resistance, given by Equation
(11.126), is
The small-signal voltage gain is a function of R
L7
,
which in turn is a function of R
c11
and R
b8
. We can
find that
r
11
= V
T
/ I
Q
= (100)(0.026)/(0.2m) = 13 k
( ) ( )
=
+
= M
I
V
R
Q
T
i
63 . 2
m 2 . 0
) 026 . 0 )( 100 ( 101 2 1 2
I7
8.3) Darlington Pair: Voltage Gain (Cont)
I7
Example 11.13 (Cont)
such that
R
E
= 13k 0.2k = 0.197 k
Also
g
m11
= I
Q
/ V
T
= 0.2m/0.026 = 7.69 mA/V
and
r
o11
= V
A
/ I
Q
= 100/0.2m = 500 k
Therefore,
R
c11
= r
o11
(1 + g
m11
R
E
) = 1.26 M
I8
8.3) Darlington Pair: Voltage Gain (Cont)
I8
Example 11.13 (Cont)
We can determine that
r
8
= V
T
/ I
C8
= (100)(0.026)/(1m) = 2.6 k
Then
R
b8
= r
8
+(1+)R
4
= 2.6k+(101)(10k) = 1.01 M
Consequently, resistance R
L7
is
R
L7
= R
c11
R
b8
= 1.26M1.01M = 0.561 M
Finally, from Equation (11.130), the small-signal
voltage gain is
A
v
= (I
Q
/ 2V
T
) R
L7
= 2158
EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 8-4
I9
8.4) Emitter Follower: Output Resistance
I9
From Figure 11.46, the output resistance of the
emitter follower Q
8
is
(11.133)
where Z is the equivalent impedance, or resistance,
in the base of Q
8
.
In this case, Z = R
c11
|| R
c7
, where R
c7
is resistance
looking into the collector of Q
7
The factor (1+) in the denominator makes output
resistance of the emitter follower normally small.
( )
|
|
.
|

\
|
+
+
=

1
8
4
Z r
R R
o
Z0
8.4) Emitter Follower: Output Resistance (Cont)
Z0
Example 11.14
Objective:
Calculate the output resistance of the circuit in
Figure 11.46.
Consider the same circuit and transistor parameters
described in Example 11.13. Assume the Early
voltage of Q
7
is 100 V.
ZI
8.4) Emitter Follower: Output Resistance (Cont)
ZI
Example 11.14 (Cont)
Solution: From Example 11.13, we have that R
c11
=
1.26 M and r
8
= 2.6 k.
We can determine that
R
c7
= V
A
/ I
Q
= 100/0.2m = 500 k
Then,
Z = R
c11
R
c7
= 1.26M500k = 358 k
Therefore
( ) ( )
k 63 . 2
101
k 358 k 6 . 2
10
1
8
4
=
|
|
.
|

\
| +
=
|
|
.
|

\
|
+
+
= k
Z r
R R
o

ZZ
8.5) Overall Gain of the Op-amp circuit
ZZ
Input stage: Diff-amp with active load A
V1
10
3
Gain stage: Darlington pair A
V2
10
3
Output stage: Emitter-follower A
V3
1
Overall Gain: A
V
= (A
V1
).(A
V2
).(A
V3
) 10
6
10
6
is the typical value for low-frequency,
open-loop gain of the op-amp circuits
Z3
Larger circuits
Z4
8.1) Darlington Pair and Simple Emitter-Follower Output (Cont)
Z4
Figure 11.46
EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 8-5
Zb
8.2) Darlington Pair: Input Impedance and Voltage Gain (Cont)
Zb
Figure 11.47: The Darlington pairs
(a) ac equivalent circuit, and
(b) small-signal equivalent circuit