1

Chapter 1
INTRODUCTION

Power consumption has increased substantially with the increase of
speed and number of transistors per unit chip area. The important design
constraint along with area and speed in modern VLSI design is Power. The
equation which represents Power consumption of a digital CMOS circuits is
shown below:

P= CLVdd
2
f+IscVdd+IleakVdd (1 )

The first term dynamic power consumption is the dominating term ,
which is due to logic switching. Where CL is the load capacitance, is the
switching activity, Vdd is the supply voltage, and f is the switching frequency.
The power dissipated due to the short circuit current, Isc, generated when both
NMOS and PMOS transistors are simultaneously active is shown by the second
term. The term Ileak Vdd is due to leakage current, Ileak, which varies with
processing technology[2].
The best way to reduce power consumption is to lower the supply
voltage level of a circuit. As voltage is quadratically related with dynamic
power, a small reduction in the supply voltage results in a moderate reduction
in the dynamic power consumption. However, that the reduction in the supply
voltage causes an increase in the circuit delay and consequently a reduction in
the throughput. Second method is to reduce the size of the transistor which
reduce the load capacitance results in decrease of dynamic and the leakage
power. The digital and analog circuits can operate at ultra-low voltages
(<0.4V). This region is considered as the sub-threshold voltage region.Sub-
threshold circuits are those whose supply voltage VDD less than the threshold
voltage Vt of the MOS transistor. The power is related quadratically to the
2

supply voltage, reducing the voltage to ultra-low levels results in a dramatic
reduction in both power and energy consumption in digital systems. These
circuits are very useful where battery life is more important than the speed like
in health and environment, where data monitored changes slowly. The
reduction of the supply voltage and transistor size of MOSFET came to an end
since scaling faces serious problem in fabrication and device performance. The
device scaling results in quantum mechanical tunneling of carriers through the
thin gate oxides, quantum mechanical tunneling of carriers from source to
drain and from drain to body, control of the density and location of do pant
atoms in the MOSFET channel and source drain region to provide high on off
current ratio, the finite sub-threshold slope. As scaling towards nm technology,
due to the random nature of manufacturing process, various effects such as
ion implantation, diffusion and thermal annealing have induced significant
fluctuations of electrical characteristics[4]. To overcome these limitations many
solutions are propose. Some include modifications on the existing structures
and technologies with a hope of extending their scalability. Others involve
using new materials and technologies to replace the existing silicon MOSFETs.
Some alternatives which would enable continued improvement in the
performance of electronics systems are high dielectric constant (HighK), metal
gate electrode, double gate FET. Reducing direct tunneling leakage currents
and efficient charge injection are provided by the High-K dielectric materials.
The technologies that could replace the MOSFET as the basic logic device, are
negative differential resistors, nanowire or carbon nano tube FET, quantum
cellular automata, and reconfigurable switches.

1.1 Motivation

The current trend is to reduce the power consumption. Day by day the need to
limit the power consumption has been increasing. Several design
methodologies have been developed to reduce the power consumption. For this
he current reason to introduce a new technology to provide better power
consumption and more drive capability than the current existing technology.
3


1.2 Problem Statement

As the scaling is done the second order effects have been increasing in the
mosfet . The technology of scaling the mosfet has came to an end .For this
purpose a new technology have been investigated to reduce the power
consumption and to increase the speed.
So the CNFET technology has been introduced which provides better
performance than the current existing MOSFET in subthreshold operation.

1.3 Objectives

The thesis objectives are:

To develop a Full Adder circuit which uses CNFETs. The developed full Adder
circuit provides better power consumption and better performance than the
existing CMOS based Full Adder circuit.

A simple DFF was designed using the both CMOS and CNFETs and their
performance is evaluated. The power consumption, delay, PDP has been
calculated for those circuits.

1.4 Main Contribution

A simple DFF using CNFETs has been developed .The developed one provides
the better results when compared to existing CMOS based dff .
To design an energy efficient full adder circuit which is faster than than the
CMOS bridge Full adder circuit. Since the full adder is the fundamental
building block of all the circuits ,a fast and energy efficient full adder increases
the fastness of the total circuit.

1.5 Organization of thesis

4

Chapter 2 deals with the Sub Threshold operation of the different circuits. The
operation of circuits in Sub Threshold regime reduces the power consumption.
Different circuits are in that region and their performance is analysed.

Chapter 3 presents the new technology ie CNFET which reduces the power
consumption when compared to the current MOS technology. Different types of
the CNFET based on geometry and based on the type of the electrode is
presented in this section.

Chapter 4 proposes a DFF and a Full adder made of the MOS and CNFETs and
their performance is analyzed. The CNFETs provide the better power delay
product than the mosfet. Generally all the circuits are build of full adders if
that is fast the circutary is fast. So, a Full adder is proposed which is energy
efficient and provides high performance than CMOS bridge circuit.

Chapter 5 draws the conclusion based on the simulation results of proposed
designs. This chapter also gives the limitations of the CNFET and the future
scope.

















5


Chapter 2

SUBTHRESHOLD OPERATION


2.1 SUBTHRESHOLD OPERATION FOR ULTIMATE LOW POWER LOGIC

The design of medium power and medium performance circuits has given
attention. The well known methods include voltage scaling, switching activity
reduction, architectural techniques of pipelining and parallelism, issues of
device sizing, interconnect and logical optimization. These methods are not
sufficient in many applications such as portable computing gadgets, medical
electronics etc., where low power consumption is the primary requirement. The
design of digital sub-threshold logic is investigated with the devices operated in
sub-threshold region. Fig 2.1 shows the sub-threshold region of interest. In
conventional CMOS the circuits are operated with the voltage greater than
threshold voltage. This region is known as strong inversion or super threshold.
If the supply voltage is less than the threshold voltage the transistor can be
operated in ultra low power consumption. This is called sub-threshold and
current flows is sub-threshold current[10].


Subthreshold moderate strong inversion
Region inversion



Drain
current





Veff(mV)

Fig.2. 1.Region of operation of digital subthreshold logic
-

6


2.2 OPTIMAL LOGIC FAMILIES FOR SUBTHRESHOLD OPERATION

The sub-threshold circuits operate at very low values of supply voltage. The low
supply voltages raises the robustness issues. Design of robust sub-threshold
logic circuits exploring logic families is another area for research. The following
logic families are optimal for sub-threshold operation operation.
Sub-threshold CMOS Logic

It is the conventional CMOS logic operated in the sub- threshold region. The
voltage transfer characteristics (VTC) of the CMOS gates in sub-threshold
region are closer to ideal compared to the VTC in normal strong inversion
region. The ideal VTC yields better noise margins. Drain current ID and gate-
source voltage VGS exhibit exponential relationship in sub-threshold. This
gives rise to an extremely high transconductance.

Sub-threshold Pseudo-NMOS Logic

It is more robust than its strong inversion counter- part. It operates 6 times
faster than conventional CMOS. The PDP of pseudo-NMOS is better and
possess com- parable robustness to static CMOS in sub- threshold region.
Table 2.1 gives a comparison of various performance parameters in sub-
threshold for full-adder using static CMOS and Pseudo-NMOS.

Sub-DTMOS logic

It uses transistors whose gates are tied to their substrate. The substrate
voltage in sub-DTMOS logic changes with the gate input voltage, the threshold
voltage is dynamically changed. The PDP of DTMOS is comparable to the PDP
of regular CMOS. The DTMOS logic can operate the circuit at higher
frequencies while still maintaining the same energy/ switching with enhanced
robustness com- pared to static CMOS.

Sub-threshold Domino Logic

7

It is similar to conventional domino logic except the transistors are operated in
sub-threshold region. Sub- domino outweighs Sub-CMOS by about 32% in
terms of power consumption. The Sub-domino logic is 32% faster than sub-
CMOS logic. Table 2.2 gives a comparison of various performance parameters
using Sub-CMOS and Sub-Domino.
Sub-threshold Dynamic Pass Transistor Logic

The performance characteristics of XOR gates using pass-transistor and
dynamic threshold pass transistor logics in 65nm and 90nm CMOS
technologies for ultra low power applications have been investigated in.
Table 2.1:Comparison of CMOS over Pseudo NMOS inverter

Parameter Sub-Threshold CMOS Sub-Threshold Pseudo
NMOS
Power(nW) 4.691 23.06
Delay(nS) 1377 221.9
PDP(fJ) 6.45 5.117



Table 2.2:Sub CMOS versus Sub Domino Logic

Parameter Sub-CMOS Sub-Domino
Power(nW) 10.64 3.408
Delay(nS) 7.545 2.423
PDP(fJ) 80.28 8.26















8

Chapter 3

LITERATURE SURVEY


3.1 CARBON NANOTUBES:

FUTURE TECHNOLOGY FOR SUB-THRESHOLD REGIME

The sub-threshold circuits are very pro- mising for ultra-low power
applications. However, operating circuits at very low values of supply voltages
raises robustness issues such as sensitivity to process, voltage and
temperature (PVT) variations. High performance carbon nanotube field effect
transistors (CNFETs) with very high on- currents have been reported in
literature and are a promising solution for VLSI requirements.

3.2 OVERVIEW OF THE CNFET STRUCTURE

Carbon Nanotube Field Effect Transistors (CNFETs)
whose conducting channel is made of carbon nanotubes. Nanotubes has
electrical properties that make them attractive as nano-electronics wires and
devices: they can behave as metallic wires or as semiconductors, depending on
their structure. The channel can contain single nano tube(called SWCNFET) or
multiple nano tubes(MWCNFET).





Fig.3.1:Carbon nanotube that can be formed by rolling up graphene

The CNFET is a 1-D structure with a near-ballistic transport capability, can
potentially offer excellent device characteristics and order-of-magnitude better
energy-delay product over standard CMOS devices[7] .The intrinsic delay is
very low, show higher electron mobility compared to bulk silicon. CMOS circuit
9

blocks can be realized using CNFETs since their operation principle is similar.
Single walled carbon nanotubes (SWCNTs) has many in electronics because of
both their metallic and semiconducting properties and their ability to carry
high current. CNTs are capable to carry current density of the order 10
A/nm2, while standard metal wires have a current carrying capability of the
order 10 nA/nm2[14]. SWCNT can be made to act as either conductor or
semiconductor depending on the angle of atom alignment along the tube. This
is known as the chirality vector and is represented by the integer pair(n,m).
Based on them we can determine whether it is metal or semiconductor[8].
When n=m or n-m=3i ( I is an integer ) then the tube is metallic, otherwise it is
semiconducting. The diameter[13] of tube is given by



=

CNFET diameter determines the bandgap energy of the tube. The relationship
between the diameter and bandgap energy is shown below

= 2


CNTFET are broadly classified as shown below:

3.3 Geometry dependent CNTFET
a. Back-gate CNTFET
The CNTs which is semiconducting is made to fall across two metal strips .
One of them is the "source" contact while the other is the "drain" contact. The
gate oxide is nothing but the silicon oxide substrate and adding a metal
contact on the back makes the semiconducting CNT gateable.. The limitations
of this was the metal contact, which actually had very little contact to the
CNT, since the nanotube just lay on top of it and the contact area was
therefore very small and also due to the semiconducting nature of the CNT, a
Schottkey Barrier forms at the metal-semiconductor interface increasing the
contact resistance. The second was due to the back-gate device geometry. Its
10

thickness made it difficult to switch the devices on and off using low voltages,
and the fabrication process led to poor contact between the gate dielectric and
CNT[6].

Fig.3.2.Back Gate CNFET
b. Top gate CNTFET This was proposed by Wind to give better performance
Top gate CNTFET . The figure 3.3 shows the schematic diagram of a top-gated
CNTFET with Ti source, drain, and gate electrodes. The gate oxide used was
15-nm SiO2 film. In this CNFET gate is placed over the CNT. The table below
shows the advantages of top gated CNTFET over back gated CNTFET[9].

Fig 3.3.Top Gate CNFET


Table 3.1: Comparison between Back gate CNTFET and Top gate CNTFET[11].
Parameters Back Gate CNFET Top Gate CNFET
Threshold voltage -12V -0.5V
11


Drain current Of the order of
nanoamperes
Of the order of
microampere

Transconductance

1nS

3.3S

I(on)/I(off)
10
5
10
6




3.4 Based on the type of electrodes CNTFETs are classified into three
categories. (a) Schottky-barrier (SB) CNTFET (b) Partially gated (PG) CNTFET
and (c) doped-S/D CNTFET.

a. Schottky-barrier (SB) CNTFET In this type of CNTFET an intrinsic CNT is
used in the channel region. The intrinsic CNT is connected to metal
Source/Drain and forms Schottky barriers at the junctions. They operate as
unconventional Schottky barrier transistors in which transistor action occurs
primarily by varying the contact resistance rather than the channel
conductance. They require careful alignment of the Schottky barrier and gate
electrode which leads to manufacturing challenge. Due to the presence of
Schottky barrier the on-current is lowered.

b. Partially gated (PG) CNTFET It is a depletion mode CNTFET in which the
nanotube is uniformly doped or uniformly intrinsic with ohmic contacts at their
ends. They can be of n-type or p-type when respectively n-doped or p-doped. In
these devices the gate locally depletes the carriers in the nanotube and turns
off the p-type (n-type) device with an efficiently positive (negative) threshold
voltage that approaches the theoretical limit for room-temperature operation.
The on-current of such devices is given as ID (on) =qvt where is the carrier
density per unit length and vt is the uni-directional thermal velocity .

c. Doped- source or drain (S/D) CNTFET Doped-S/D CNTFETs are composed
of three regions. The region below the gate is intrinsic in nature and the two
12

ungated regions are doped with either p-type or n-type. In this CNFET the ON-
current is limited by the amount of charges that can be induced in the channel
by the gate and not by the doping in the source. They operate in a pure p- or n-
type enhancement-mode or in a depletion-mode, based on the principle of
barrier height modulation when applying a gate potential.
Out of three, doped S/D CNTFETs are promising because (1) they show
unipolar characteristics unlike SB-CNTFETs; (2) the absence of SB reduces the
OFF leakage current; (3) they are more scalable compared to their SB
counterparts; (4) in ON-state, the source-to-channel junction has a
significantly higher ON current[3].





















Fig3.4.(a)SBCNFET(b)CNTFET(c)Tunneling CNFET

Depending on the doping profile doped S/D CNTFETs can again be classified
into two groups.

(a) Conventional CNTFET (C-CNTFET): This comprise of CNTFETs with p/i/p
or n/i/n doping scheme that is both S/D are doped with either p-type or n-type
material.
13


(b) Tunneling CNTFET (T-CNTFET): CNTFETs with n/i/p doping scheme
(source and drain are oppositely doped) comes under this group.
The above CNTFETs discussed are of planer structure. Besides these one more
structure is also developed which is known as vertical CNTFET (V-CNTFET) or
coaxially gated CNTFET. This consists of a SWCNT with a coaxial gate. The
advantage of V-CNTFET is that vertical growth in CNT is easier and aligned
than horizontal growth.































14

Sl.No Title of the
paper
Authors Name of
journal/
conference
with page
numbers
Principle/
procedure
Advantages Dis
advantages

1











2










3










Design and Analysis
of Lowpower Carbon
Nanotube Field Effect
Transistor DFF.








CNFET based Logic
circuits.









Comparing Carbon
Nanotube Transistors-
The Ideal Choice:A
Novel Tunneling
Device Design.






Ovunc Polat,Ali
Manzak










Sanjeet Kumar
Sinha, Saurabh
Choudhury








Joerg
Appenzeller,
Zhihong Chen.








IEEE ,978-1-
61284-840-2/11










IJETAE,ISSN
2250-2459









IEEE, Vol.52










Design a DFF
using CNFET
which consumes
less power than
MOSFETs.







CNTFET based
logic circuits are
discussed .








Three different
carbon nanotube
eld-effect
transistor designs
are compared by
simulation and
experiment.




CNFET DFFs
are faster,
consumes less
power and
operates at
lower supply
voltages
compared the
CMOS DFFs.



A power saving
of 57% can be
achieved with
the ambipolar
CNTFET
library over a
conventional
CMOS library.



Ultra- trathin
body devices as
CNFETs always
show an
increased
probability for
tunneling
processes.



CNFET circuits
show some
imperfections
such as
misalignments,
diameter and
doping
variations.




Unwanted
growth of
metallic tubes
during the
fabrication of
CNTs.





It is required to
transition from
a device that
operates based
on the gate
control of a
thermal
emission
current to a
gate controlled
15



4











5
















6











Comparison of
variations in
MOSFET versus
CNFET in Gigascale
Integration.







Design and Analysis
of High performance
CNFET based
Fulladder.













Design and analysis
of Lowpower
backgated CNFET
SRAM memory cell
operating in
Subthreshhold
Operation.





Ali Arabi M.
Shahi, Payman
Zarkesh-Ha,
Mirza Elahi








Mohammad
Hossein Moaiyeri
, RezaFaghih
Mirzaee , Keivan
Navi
,AmirMomeni











S Namachivayam
and S
Ramasubramanian









IEEE, 978-1-
4673-1036-9



























IJREAT,ISSN
2320-8791










We compared
and presented
overall device
variations in
MOSFET and
CNFET for
gigascale
integrated
systems



CNFET has
higher
performance and
lower power
consumption
compared to the
silicon-based
MOSFET and is
very suitable for
low-voltage and
high-frequency
applications.





Designing
memory cell with
low power
consumption and
high noise
margin.






CNT density
variation with
10 CNTs in the
channel causes
23% Ion, 22%
Ioff, 0.011%
Vth and 23%
gate capacitance
fluctuation



High-speed and
high-
performance
CNFET-based
Full Adder cell
for low-voltage
applications has
been proposed.









We propose
CNTFET
SRAM reduce
the power of
52% and
increase the
voltage noise
margin of nearly
two times.

tunneling
device.
CNFET must
be carefully
designed for
variation to be
able to replace
the MOSFET
technology.





CNFET Design
circuits should
be designed
carefully.













The carbon
nanotube
degrades in a
few days when
exposed to
oxygen.




16



7


















8














9






Emerging research
devices: A study of
CNFET and SET as
replacement for
SiMOSFET.














A new lowpower 9T
SRAM cell based on
CNFET at 32nm
Technology node.











Novel CNFET
SRAM cell design
operating in
Subthreshhold region
using back gate


Mahmoud
Lababidi, Krishna
Natarajan,
Guangyu Sun















Rajendra Prasad
S, Dr. B K
Madhavi, Dr. K
Lal Kishore











Haiqing Nan,
Kyung Ki Kim,
and Ken Choi




IEEE


















IJCSIT,ISSN:
0975-9646













IEEE 978-1-
4244-6875-1/10





Many New
Devices which
have properties
that make them a
candidate to
replace
SiMOSFET are
currently under
study . The
frontrunners
being the
CNTFET and
SET.






This paper
proposes a new
design of highly
stable and low
power SRAM
cell using
CNTFETs at
32nm technology
node.






This paper
proposes a new
design of carbon
nanotube FETs
based SRAM cell


CNFET and
SET has some
properties that
are mandatory
for a logic
device and some
properties that
are absent.











CNTFET based
9T SRAM cell
design achieves
improvements
in stability and
power
consumption,
especially at a
low power
supply.





Noise margin,
delay and power
can be easily
controlled by
using back gate


The challenge
existing in the
development of
molecular
electronics is to
go beyond
single-
molecular
components
and integrate
such devices.








Delay increases
for CNFET
based 9T
SRAM cell.











Challenges
while designing
CNFET SRAM
cell with
different back
17






10
















11









12








biasing.




Subthreshhold Circuit
Design Techniques
for ultra low power
logic.













Simulations of
Carbon Nano tube
Field Effect
Transistor.






CNFET based Basic
Gates and a novel full
adder cell.











Rohit Dhiman,
Rajeevan Chandel
and R.P. Agarwal














Rasmita Sahoo
and R. R. Mishra








Fazel Sharifi ,
Amir Momeni
and keivan Navi




























JEER,ISSN
0975-6450








International
Journal of
VLSI design &
Communication
Systems ,
Vol.3.



operating in
subthreshold
region.


The paper
analyzes
interconnects for
VLSI
applications and
identifies carbon
nano-tube
interconnects as
future technology
for sub-threshold
operation.






A brief
comparison
between the
performance of
Si- MOSFET and
CNTFET is
given.



Design of full
adder circuits
with higher speed
and lower power
consumption.




biasing.




The superiority
of CNFET
based circuits
compared to
MOSFET-based
circuits both for
sub- threshold
and super-
threshold
regimes and
particularly for
sub-threshold
operation.




CNFET has
better
performance
over MOSFET






The proposed
design is
faster,simpler
and smaller.





gate biasing
schemes.



Carbon nano-
tubes have
been identified
as promising
candidate in
deep submicron
ranges
especially
beyond sub-
70nm transistor
era to further
address
robustness
issues.



Some
Challenges in
manufacture of
CNFET.






The
experiments are
still going on.






18

13











14










15











16





Carbon Nanotube
Correlation:Promising
Opportunity for
CNFET Circuit Yield
Enhancement







Assessment of Silicon
MOS and carbon
Nanotube FET
performance limits
using a General
theory of Ballistic
Transistor




Comparitive
performance
Evaluation of Large
FPGA with CNFET
and CMOS based
switches in
Nanoscale.





Design of an energy
efficient CNFET Full
Adder Cell.



Jie Zhang,
Shashikanth
Bobba, Nishant
Patil Albert Lin,
H. -S. Philip
Wong, Giovanni
De Micheli,
Subhasish Mitra




Jing Guo, Supriyo
Datta, and Mark
Lundstrom








Mohammad
Hossein
Moaiyeria,, Ali
Jahaniana,,
Keivan Navia,,







Arezoo Taeb,
Keivan Navi,
MohammadReza
Taheri and Ali
Zakerolhoseini

ACM 978-1-
4503-0002-
5/10/06




















Nano-Micro
letters










International
Journal of
Computer
Science Issues,
Vol. 9, Issue 3.

This paper
introduces a
processing/design
cooptimization
approach to
reduceprobability
of CNFET
failures at the
chip-level.



The device
physics for
operation at
ballistic and
quantum
capacitance
limits will be
explored.



Hybrid CNFET-
CMOS
architecture is
presented for
FPGAs .







Two novel
energy-efficient
Full Adders are
proposed.


CNFETs with
small widths are
vulnerable to
failures due to
CNT specific
imperfections
such as CNT
density
variations



CNTFETs
present the
possibility of
achieving both
the ballistic and
quantum
capacitance
limits.



The average and
leakage power
consumptions
are reduced
more than 6%
and 98% when
the CNFET are
used as
switches.



Improves the
size of adder
and multiplayer
cell in VLSI
design.

Upsizing these
vulnerable
small CNFETs
is an effective
but costly
option.






The contacts
and shorter
channels are to
limited.







Design is
costly











Design should
be carefully
done.


19




17











18



















19








Efficient CNFET
based Rectifier for
Nano electronics.









Review on
Optimization
Methods of Carbon
Nanotube Field Effect
transistor.















Performance Analysis
of CNFET based
Interconnect Drivers
for Subthreshold
circuits.




Mohammad
Hossein Moaiyeri,
Keivan Navi,
Omid
Hashemipour







Changxin Chen
and Yafei Zhang


















S.S. Chopade,
S.D. Pable,
Dinesh V Padole






International
Journal of
Computer
Applications
(0975 8887)
Volume 64
No.2.





The Open
Nanoscience
Jounal, 13-18.

















International
Journal of
Computer
Applications
(0975 8887)
Volume 60



In this paper,
efficient CNFET-
based analog
inverter, half-
wave rectifier
and full-wave
rectifier circuits
are proposed for
nanoelectronics.



CNTFETs have
expe- rienced
great advances at
the device
structure as well
as device
performance.
Various methods
had been
attempted to op-
timize the
devices. These
methods can
mainly be
divided into four
aspects.




This paper
examined use of
CNFET based
interconnect
driver even for
ultra low power



An efficient
CNFET-based
half-wave and
full-wave
rectifiers for on-
chip
nanoelectronics
applications.




The prob- lems
resulting from
increasing
power
dissipation,
leakage
currents, and
variations in
device
parameters
become
insurmountable.








CNFET based
drivers provides
significant
improvement in
EDP and delay
for different



CNFETs
cannot be
generated in
large amounts.








The separation
of
semiconducting
and metallic
CNTs is still
promising.














Interconnects
delay may
cause
functionality
failure of ultra
low power
20






20












21





Performance Analysis
of Interconnect
Drivers for Ultra
lowpower
Applications.








CNTFET-RFB: An
Error Correction
Implementation For
Binary And Multi-
Valued CNTFET
Logic.






S.D.Pable, Mohd.
Hasan











G.Sundararajan,
Chris J. Winstead
No.4




ACEEE Int. J.
on Electrical
and Power
Engineering,
Vol. 02, No.
01.







IEEE
Transactions on
Nanotechnoloy

circuits.




This paper
investigates the
impact of
interconnect
drivers on digital
circuit
performance in
subthreshold
region.




This work
presents two
novel designs of
ternary C-
element in
CNTFETs
exploiting
inherent
CNTFET
properties such as
threshold voltage
tuning and
variable back-
gate biasing.
interconnect
length.



Optimizing the
CNFET
parameters
shows
performance
improvement in
delay and PDP
over the Si-
MOSFET




Energy delay
analysis reveals
that the back-
gate biased
ternary C-
element is
superior to static
complementary
ternary C-
element in terms
of energy
dissipation at a
given delay.
digital systems.




Optimized
CNFET shows
more variation
than
conventional
CNFET.







Design is
difficult.











21

Chapter 4
COMPARISON BETWEEN MOSFET AND CNFET

A a brief comparison between the performance of MOSFET and CNFET has
been described in this section.
4.1 Design of D FlipFlop

CMOS IMPLEMENTATION:
Flip-Flops are major components of digital circuits. Two popular DFFs based on
master-slave latch-pairs have been used for the design and optimized in terms
of power. The first design uses simple and area efficient flip-flop circuit (SDFF)
shown in Fig4.1 BSIM 32nm predictive model has been used for simulation.
Transistor sizes have chosen as small as possible to achieve the lowest power.
In SDFF, because of the loading effect of the feedback path, width to length
ratio is chosen 4 to 1 (W/L=128nm/32nm) for the gates in the forward path
(inv1, inv2, inv3, inv4, tg1 and tg2) and 1 to 2 (W/L=32nm/64nm) for the gates
in the feedback path (inv5, inv6) of both master and slave latches. DFF was able
to operate at 350mV minimum, achieving 27.66ps Clk- Q delay, 2.49 W power
consumption and 68.8aJ PDP in [1].

CNFET IMPLEMENTATION:

Both flip-flop circuits (SDFF, TGFF) are also implemented using CNFETs. The
design requires width to length ratio as 1 for carbon nano-tube PCNFET and
NCNFETs since current driving capacity is the same for both transistors.
Number of tubes are taken as 3 (minimum) and increased for the transistors
requiring larger current driving capability. Similarly, in the first flip-flop circuit
(SDFF) the number of tubes are determined as 12 (4 times the minimum size) in
the forward path (inv1, inv2, inv3, inv4, tg1 and tg2) and 3 (minimum) in the
feedback path (inv5, inv6) because of the loading effect. SDFF was able to
operate at 100mV minimum, achieving Clk-Q delay of 3.38ps, 0.851 W power
consumption and 2.87aJ PDP.
22









Figure.4.1 SDFF, Simple D Flip-Flop[1]



Table 4.1 :COMPARISON OF DFF FOR CMOS AND CNFET IMPLEMENTATIONS


CMOS CNFET
Clk Q Delay 27.66ps 3.38ps
Average Power 2.49 W 0.851W
Power Delay
Product(PDP)
68.87aJ 2.87aJ
Setup Time 10ps 4ps
Hold Time 0 0
Minimum operating
voltage
350mW 100mW
Number of Transistors 16 16
Total Area 0.057m
2
0.057m
2


4.2 Proposed Full Adder Cell

In general, CNFET has higher performance and lower power consumption
compared to the silicon-based MOSFET and is very suitable for low-voltage and
high-frequency applications. Another significant attribute of CNFET is that P-
CNFET and N-CNFET, with the same device geometries, have the same
mobilities and consequently the same current drive capabilities, which is very
important for transistor sizing in the complex circuits. The CMOS-Bridge fully
symmetric Full Adder cell which has 24 transistors, takes advantage of the
high-performance bridge style. It produces the out C (output carry) signal
based on a CMOS style and generates the Sum signal from out C by means of a
bridge circuit. In addition, to generate C out and Sum and for enhancing the
driving capability, two inverters are utilized at the output nodes of this circuit.
23

Despite the low power consumption of this design, its critical path includes six
transistors which leads to long propagation delays. The logic function of a 1-bit
Full Adder cell with A, B, C in (input carry) inputs and Sum and C out (output
carry) outputs is described by the following equations, in which symbol denotes
the XNOR function[5].


Sum= XOR( A,B,Cin ) =A.B.C +A.B.C in+ A.B.C in+ A.B.Cin (2)

Cout= Majority( A,B,Cin )=A.B +A.Cin +B.Cin (3)

According to Equation (2) and Equation (3) the Full Adder cell[12] can be
designed based on two separate circuits, a 3-input XOR and a 3-input Majority
circuit, which generate Sum and C out signals in a parallel manner. The
proposed Full Adder cell, which is shown in Figure 3, is composed of two
separate fully symmetric CNT pass-transistor networks to implement the Sum
and C out functions in a parallel manner. The first network is a 3-input XOR
circuit, which implements the Sum function by means of 10 CNFETs. This
module implements Equation (2), with the shortest possible critical path and
without using any complementary inputs. It is worth mentioning that
shortening the critical path of the designs is the most efficient way to reduce
the delay and power consumption at the same time. In addition, circuits with
complementary inputs need additional inverters to complement the original
inputs and most of them are not efficient. In general, the output of this circuit
has threshold loss in two cases only, when ABC=000 or ABC=111. To
correct the voltage swing of the output node of the Sum generator circuit, some
methods, such as using output buffers or using transmission gate networks
instead of pass-transistor networks, could be utilized. Unfortunately, all of
these solutions lead to lengthening the critical path of the designs and
hardware redundancy, which consequently results in performance degradation.
However, by utilizing CNFET nanotechnology, the intrinsic threshold voltage
drop problem in this circuit can be resolved without any hardware redundancy.
24

The threshold voltage of CNFET is inversely proportional to the diameter of its
carbon nanotube. As a result, threshold voltage can be reduced by increasing
the diameter of the carbon nanotube, which could resolve the threshold loss
problem and leads to better driving capability and higher speed. The diameter
of a CNT can be regulated by adjusting its chiral number (n 1, n 2). As a
result, in this design CNFETs with larger diameters ((n 1,n 2)=(55,0), DCNT
=4.306nm) are only utilized in two paths of the circuit to correct the voltage
swing just when ABC=000 or ABC=111. The second module of the proposed
design is a Majority circuit which generates the Cout signal based on a direct
implementation of Equation (3). The structure of this module is similar to the
first one with its critical path consists of only two CNT pass-transistors and it
has no complementary inputs. The same method as mentioned above can also
be utilized to complete the voltage swing of the Cout generator circuit by using
CNFETs with large diameters ((n 1,n 2)=(55,0), D CNT =4.306nm). The
proposed circuit is simulated using output buffers at 0.65V supply voltage and
250MHz frequency. The input and output signals of the proposed design as
well as the high and low voltage values . It is obvious that the value of
voltage drop is very lower than the value of the threshold voltage in practice,
when CNFETs are used. This is due to the very high-speed operation of
CNFETs with large diameters in subthreshold region. CNTs with larger
diameters have smaller band gaps, due to the fact that the energy band gap of
a CNT is proportional to the inverse of its diameter. A smaller band gap intends
that a CNFET composed of CNTs with larger diameters can exhibit higher on-
currents, which leads to shorter delay times. CNTs with smaller diameters have
higher drain/source resistance, which can be explained by the fact that at
small diameters only the first sub-band is degenerate. In addition, CNFETs
with larger diameters are less sensitive to process variations and leads to better
manufacturability .As described, this solution is based on unique properties of
CNFETs and is not feasible and profitable in CMOS technology. In addition,
according to the results of this experiment, by utilizing CNFETs with the same
device geometries on the critical path of the proposed design at its pull-up and
25

pull- down networks, the high-to-low propagation delay (Tp HL ) and the low-
to-high propagation delay (Tp LH ) are almost the same for both Sum and C out
signals. It is worth mentioning that the Tp HL and Tp LH are 5.9ps and 6.1ps
for the Sum signal and are 5.02ps and 5.08ps for the C out signal, respectively.
This fact is also based on another unique property of the CNFET device
described in the previous sections. In this paper a high-speed and low-PDP
CNFET-based Full Adder with a critical path consisting of only two transistors
is presented for low voltages. The performance of the proposed design is
evaluated in various situations and is compared with the other conventional
and state-of-the-art 32nm-CMOS and 32nm-CNFET Full Adder cells of different
styles which are reviewed briefly in this section[16].



Fig.4.2.CMOS Bridge

Fig.4.3. Input and output signals of the first Design











26















4.3 Simulation Results Analysis and Comparison
In this section, the proposed designs are comprehensively evaluated in various
situations and are compared with the other classical and state-of-the-art
CMOS and CNFET-based Full Adders. All the designs are simulated using
Synopsys HSPICE 2007 simulator tool with 32nm CMOS technology for CMOS
circuits and the Compact SPICE Model for 32nm CNFET-based circuits,
including all nonidealities. This standard model has been designed for
unipolar, MOSFET-like CNFET devices, in which each transistor may have one
or more CNTs. This model also considers Schottky Barrier Effects, Parasitics,
including CNT, Source/Drain, and Gate resistances and capacitances and CNT
Charge Screening Effects.

All of the CMOS circuits are sized for minimizing the PDP, based on the
transistor sizing procedure.Simulations are carried out at room temperature





Figure.4.4. The Proposed CNFET-based Full Adder cell
27

and various supply voltages, frequencies and loads are used for simulation.
Complete input pattern with all the possible transitions from an input
combination to another is applied to the circuits to measure their propagation
delay. The delay of each circuit is calculated from the time that the input signal
reaches V DD to the time that the output signal reaches the same voltage
level. All the transitions from one input to another are checked and the delay is
measured for each transition and the maximum is reported as the delay of
each circuit. The average power consumption during a long period of time is
also considered as the power consumption parameter. In order to make a
compromise between the power consumption and the delay of the circuits, the
performance of the circuits can be evaluated by calculating the power-delay
product (PDP), which is the multiplication of the average power consumption
and the maximum delay. As a result, PDP could be an important parameter for
evaluating and comparing the performance of the circuits.
In the experiment, the circuits are simulated at 0.8V, 0.65V, and 0.5V supply
voltages and at 100MHz frequency with 2.1fF output load capacitors. The
detailed results of this simulation are listed in Table 2. The best results at each
voltage are demonstrated with bold-faced numbers. According to the
experimental results, CNPTL (Proposed) has the shortest delay and the lowest
PDP compared to the other designs at all supply voltages. It has also the lowest
power consumption at 0.8V and 0.65V.

Table. 4.2.Simulation Results
Delay(10
-12
s)
Vdd 0.5 0.65 0.8
CNPTL 26.722 18.733 15.676
CMOS- Bridge 591.62 199.95 130.20
Power(10
-7
)
Vdd 0.5 0.65 0.8
CNPTL 1.2032 1.7241 15.676
CMOS-Bridge 0.8869 1.7560 3.2806
PDP(10
-17
J)
Vdd 0.5 0.65 0.8
CNPTL 0.3215 0.3229 0.4111
CMOS-Bridge 5.2475 3.5113 4.217
28



Another performance parameter of the nanoscale circuits is robustness to the
process variations. Random and systematic process variations are among the
most major challenges regarding the design of nanoscale circuits. As the
feature size of the devices scales down into the nanoranges, the process
variation becomes a critical concern which negatively affects the speed, power
consumption and reliability of the circuits. In this section, the delay, power
consumption and PDP of the CNFET-based Full Adders are measured in the
presence of process variations, i.e. deviations and mismatches in the diameter
of the nanotubes of the carbon nanotube transistors. This variation has the
most significant impact on the energy barrier of the CNFET devices and the
performance of the CNFET-based circuits. For this purpose, Monte Carlo
transient analysis with a reasonable number of 30 iterations for each
simulation is conducted using the HSPICE simulator. The statistical
significance of 30 iterations is quite high. If a circuit operates properly for all
the 30 iterations, there is a 99% probability that over 80% of all the possible
component values operate properly. Distribution of the diameters is assumed
as Gaussian with -sigma distribution; a reasonable supposition for large
numbers of fabricated CNTs.
The maximum variations of the delay, power consumption and
PDP of the CNFET- based Full Adders versus CNT diameter variations, are
demonstrated in Figures 10, 11 and 12, respectively. Considering the
inaccuracy of fabrication techniques, a standard deviation from the mean value
in the range of 0.04nm to 0.2nm is considered for each mean diameter value It
can be concluded from the results that the performance of the proposed Full
Adder is less sensitive to diameter variations, compared to TG-CNFET and
CNFET-Bridge, specifically for the larger deviations.




29


















Fig .4.5.Delay variation of the circuits with respect to CNT diameter variations
































Fig4.6.Power Consumption variation of the circuits with respect to CNT diameter
variations
30




























Fig 4.7 PDP variation of the circuits with respect to CNT diameter variations
31

Chapter 5
CONCLUSION
In this paper, a simple DFF is built using the CMOS and the CNFETs and their
performance is evaluated. The CNFET circuits shows the better performance
than the CMOs circuits . The power saved is more. A high speed and high-
performance CNFET-based Full Adder cell for low-voltage applications has been
proposed. The Sum and C out generator modules of this Full Adder, which are
fully symmetric and have the same hardware configurations, produce the Sum
and C out signals in a parallel manner. Results of the comprehensive
simulations demonstrate considerable improvements in terms of delay, PDP
and sensitivity to process variations in comparison with the other conventional
and state-of-the-art 32-nm CMOS and CNFET-based Full Adder cells, in
various situations.
One of the major challenges faced by the CNFET is the presence of unwanted
metallic tubes that has an unfavourable impact on the delay, power, and
functional yield of carbon nanotube based circuits. The unwanted growth of
metallic tubes during the fabrication of CNTs is a major challenge that will
affect the fabrication of robust CNT-based circuits.
5.2 Future Scope
To built the different circuits which provide the better performance than the
existing CMOS technology for sub-threshold operation.

32

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