T.Adithya St2-861, Centnary Colony, Karimnagar, A.

P 9441472260
CIRICULUM VITAE
AdithyaThorikonda
Contact details: -
Phone:-+919441472260
Email: - adithya.vlsi54@yahoo.com
Objective:
Seek a starting position as a fresher in your organization. I would like to contribute my team
by applying my best efforts for success of the project.
Educational qualification:
B. Tech in ECE from Trinity College of Engineering and Technology in 2012 with 59%.
Intermediate (M.P.C stream) in the year 2008 with an aggregate 55%.
SSC in the year 2006 with an aggregate 78%.
Special Courses:
Diploma in VLSI System Engineering & Verification
Technical Languages:
Experience in Verilog, System-Verilog.
Knowledge in design of Analog, Digital Circuits.
Knowledge SoC Verification Methodology and Physical Design.
Knowledge in FPGA Design Flow (Xilinx tool Flow).
Knowledge on Embedded designing.
Knowledge in C, C++, HTML Languages.
Projects:
Project Name: Design and Implement a slave SPI and verify SPI in testbench.
Role: Team Member.
Tools:
Verilog (Modelsim, Xillinx).
System Verilog(Modelsim ).
Description:
Today, at the low end of the Communication Protocols there are mainly Two
Protocols: Inter- Integrated circuit (I2C) and the Serial Peripheral Interface (SPI) Protocols.
Both the protocols are well suited for communications between Integrated Circuits for
communication with ON-Board Peripherals. SPI is one of the most commonly used serial
protocols for both inter-chip and intra-chip low/medium speed data-stream transfer. In
conformity with design-reuse methodology, this project introduces high-quality SPI IP with
Master & Slave configuration with that of 8-bit data transfer which incorporates all
necessary features required by modern ASIC/SoC applications. The Designed SPI is used for
communication between different peripherals with that of a processor in a SoC application.
The Designed SPI is Implemented and also Verified using a System Verilog in order to show
its code coverage and functional correctness. The whole RTL design code is written in
Verilog for synthesis and its Verification code is written in System Verilog, IEEE (2005).
T.Adithya St2-861, Centnary Colony, Karimnagar, A.P 9441472260


Project Name: Website Design
Role: Project in charge
This Project is under construction
Description:
Presently working on HTML and Dreamweaver for designing a website.
The web site is based on online sales.
The aim of the project is to provide some information to the society.

University Projects:
Project Name: A RFID Based Material Tracking System
Role: Active team member
Due to the lack of time constraints we could able to complete it only up to 80% of
the project and it was appreciated for the work done.
Description:
Radio Frequency Identification (RFID) is the next generation wireless communication
technology applicable to various areas. For the beneficial features of RFID, we integrate
RFID readers into the Material Tracking Information System.

Project Name: Gas leakage detection robot
Role: Team Leader
It was completed successfully and was appreciated for the work done.
Description:
The present invention provides a simple and relatively low cost way of performing a
leakage test on the test system to determine whether or not the system is subject to
leakage. The gas sensor will be fixed in the area where there is a chance of any gas leakages.
If the system leaks, the sensor identifies the change and indicates that leakage exists.
RSTPS:
Worked at NTPC RSTPC in C&I department and it was well received for the work
done by our team
Extracurricular activities:
I have participated in some technical seminars arranged at different colleges.
I have organized a national level event held in our college.
I play cricket and chess.

Declaration:
I hereby declare that above mentioned details are true to my best knowledge

Date: Adithya Thorikonda
T.Adithya St2-861, Centnary Colony, Karimnagar, A.P 9441472260
Place: Hyderabad