IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.
6, JUNE 2011 1733
A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges P. P. Rajeevan, K. Sivakumar, Student Member, IEEE, Chintan Patel, Student Member, IEEE, Rijil Ramchand, Student Member, IEEE, and K. Gopakumar, Senior Member, IEEE AbstractA multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating V dc /2 where V dc is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of V dc /6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two- level inverters, which operate at a higher voltage level of V dc /2, switch less compared to the H-bridges, which operate at a lower voltage level of V dc /6, resulting in switching loss reduction. The experimental vericationof the proposedtopology is carriedout for the entire modulation range, under steady state as well as transient conditions. Index TermsFloating capacitor, H-bridge, induction motor drive, multilevel inverters. I. INTRODUCTION T HE capability of multilevel inverters to generate volt- age waveform with less harmonic distortion, at reduced switching frequency, using switching devices of low-voltage ratings makes them preferred choice for medium- and high- voltage power processing applications [1], [2]. This has led to their increasing applications in the control of medium and high- voltage ac drives [3][5]. Though with increase in number of levels the quality of waveform improves, it also increases the complexity of the circuit due to the increase in the number of Manuscript received June 18, 2010; revised August 4, 2010; accepted October 20, 2010. Date of current version July 22, 2011. This paper was sup- ported by the Defense Institute of Advanced Technology, Pune, India. Recom- mended for publication by Associate Editor P. Barbosa. P. P. Rajeevan, C. Patel, and K. Gopakumar are with the Centre for Elec- tronics Design and Technology, Indian Institute of Science, Bangalore 560012, India (e-mail: prajeev@cedt.iisc.ernet.in; pchintan@cedt.iisc.ernet.in; kgopa@ cedt.iisc.ernet.in). K. Sivakumar is with the National Institute of Technology, Warangal 506004, India (e-mail: siva.eee@gmail.com). R. Ramchand is with the the Department of Electrical Engineering, National Institute of Technology, Calicut 560012, India, and also with the Centre for Elec- tronics Design and Technology, Indian Institute of Science, Bangalore 560012, India (e-mail: rijil@nitc.ac.in). Digital Object Identier 10.1109/TPEL.2010.2090541 devices and associated control circuitry. The other issues of concern in industrial applications are reliability and efciency of the system. Hence, the researchers in this eld are focused mainly on the development of less complex, more reliable and efcient multilevel inverter topologies. A survey of multilevel inverter topologies is presented in [6]. The conventional multi- level converters include the neutral point clamped (NPC), ying capacitor, and cascaded H-bridge topologies. Dual inverter con- guration for an open-end winding induction motor is another interesting multilevel topology for drive applications [7]. The NPC inverter is a well-known topology in the group of conventional multilevel inverters [8]. In this topology, the dc link is split into a number of small voltage levels using series connected capacitor banks. The main issue with this topology is the uctuations in capacitor voltage depending on the load cur- rent drawn fromthe dc link. Hence, special switching strategy is required for balancing the capacitor voltages. A virtual-space- vector-concept-based pulse width modulation (PWM) strategy for balancing of dc-link capacitors of an n-level diode clamped converter, in every switching cycle under any type of load, is proposed in [9]. Another scheme for capacitor voltage balancing of a three-level diode-clamped converter used in a hybrid active lter is discussed in [10]. Various other techniques for capacitor voltage balancing have been reported in [11] and [12]. The num- ber of clamping diodes required in the NPC inverter increases substantially as the number of voltage levels increases. In the ying capacitor topology of multilevel inverter [13], the oating voltages across the capacitors are used for generating different voltage levels. The capacitor voltages have to be maintained at the required levels under all operating conditions. This can be achieved by making use of the redundancy in switching states that exist for generating different voltage levels. An analysis of the voltage-balancing dynamics of a three-phase ying capac- itor converter has been presented in [14]. The ying capacitor topology requires a large number of capacitors to achieve higher number of voltage levels. In the cascaded H-bridge topology, H-bridge cells fed from isolated dc-voltage sources are con- nected in series to realize multilevel inverter structure [15], [16]. The number of H-bridge cells per phase required depends on the number of voltage levels. The control of this topology is relatively simple, as it does not involve any capacitor voltage balancing issues. This topology is considered well suited for high-power applications because of its modular structure that facilitates high-voltage operation using low-voltage switching devices. However, this topology suffers from a disadvantage 0885-8993/$26.00 2011 IEEE 1734 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011 Fig. 1. Power circuit diagram of the proposed seven-level inverter drive topology. that the number of isolated voltage sources required increases considerably as the number of voltage levels increases. Apart from the conventional multilevel topologies cited ear- lier, several other multilevel converters have been proposed in the literature. Most of them are either variants of the conven- tional topologies or their hybrid versions [17]. A hybrid cas- caded multilevel inverter consisting of a standard three-leg in- verter and H-bridges is presented in [18]. A method to increase the number of voltage levels by changing the ratio of the capac- itor voltages in ying capacitor topology is presented in [19]. Another topology called Hexagram converter, composed of six interconnected three-phase converter modules, has been presented in [20]. The multilevel inverter topology proposed in [21] employs series connection of submultilevel converter blocks to achieve reduction in the number of power electronic switches required to synthesize a given number of voltage levels. A single-phase multilevel PWM inverter topology, using a split- wound coupled inductor within each inverter leg, is proposed in [22]. Different pulse width modulated modular multilevel converter topologies are discussed in [23]. In the multilevel in- verter topologies for open-end winding induction motors, each end of the motor phase winding is connected to inverters for achieving multilevel voltage prole in the winding. For exam- ple, a three-level inverter can be realized with two conventional two-level inverters feeding the motor stator windings from both ends [7]. The number of voltage levels in the motor winding can be increased further by cascading two- and three-level invert- ers [24]. A seven-level inverter topology, realized by cascading four two-level and two three-level inverters, is presented in [25]. The seven-level inverter topology proposed in this paper is intended for an induction motor with open-end winding struc- ture. Here, in addition to two two-level inverters feeding the coils from both ends, two H-bridge cells are connected in series with the motor winding in each phase. These H-bridge cells are fed by capacitors whose voltages are maintained at the required level. An important advantage of this topology is the reduction in dc-link voltage requirement by half when compared with the requirement of dc-link voltage in NPC topology. In this topol- ogy, there are multiple ways of generating middle voltage levels and this feature is utilized in balancing the capacitor voltages in the entire modulation range. II. PROPOSED SEVEN-LEVEL INVERTER TOPOLOGY In the proposed circuit, two two-level inverters and six capacitor-fed H-bridges are used to realize a seven-level inverter. The induction motor is fed from both sides of the windings as shown in the power circuit diagram (see Fig. 1). The two-level inverters are powered by two isolated dc-voltage sources of magnitude V dc /2, where V dc is the dc-link voltage requirement of the conventional NPCseven-level inverter. Two capacitor-fed H-bridges are connected in series with the motor winding in each phase. The voltages across the H-bridge capacitors (CA1, CA2, CB1, CB2, CC1, and CC2) are maintained at a level of V dc /6. All switching states available for generation of the seven voltage levels of + V dc /2, +2 V dc /6, + V dc /6, 0, V dc /6, 2V dc /6 in A-phase are given in Table I. Similar methods are used for gen- erating the seven voltage levels in the other two phases. Table I shows that these voltage levels can be realized in multiple ways. One method of generating the seven voltage levels in A-phase winding of the motor is illustrated in Fig. 2. By clamping the H-bridge cells to zero voltage, the two two-level inverters can generate voltage levels of +V dc /2, 0, and V dc /2. The other voltage levels are generated by connecting the two-level invert- ers in series with the H-bridges or by clamping the two-level inverters to zero voltage and using only the H-bridge voltages, as explained in the following paragraphs. The space vector structure of the seven-level inverter is shown in Fig. 3. The seven voltage levels of V dc /2, 2V dc /6, V dc /6, 0, +V dc /6, +2V dc /6, and +V dc /2 are represented by the num- bers 0, 1, 2, 3, 4, 5, and 6, respectively. The triplets of num- bers shown at each space vector location indicate the switching states for generating the corresponding space vector. For exam- ple, the triplet 621 indicates the switching state correspond- ing to the voltage levels of +V dc /2, V dc /6, and 2V dc /6 in A-phase, B-phase, and C-phase windings, respectively. There are six concentric hexagons with zero vector at the centre, in the space vector structure. Redundant switching states are available RAJEEVAN et al.: SEVEN-LEVEL INVERTER TOPOLOGY FOR INDUCTION MOTOR DRIVE 1735 TABLE I SWITCHING STATES FOR THE SEVEN VOLTAGE LEVELS OF A-PHASE for generating all the space vector locations except those on the outermost hexagon. The zero vector can be generated in seven ways. The number of redundant switching states for realizing a space vector location decreases from the center toward the outermost hexagon. It can be seen from Fig. 3 that with the seven voltage levels of V dc /2, 2V dc /6, V dc /6, 0, +V dc /6, +2V dc /6, and +V dc /2, it is possible to attain a maximum mag- nitude of V dc for the voltage space vector. It is pertinent to note that the switching states in which the capacitor voltage is added to the supply voltage (V dc /2) are not required to be used to realize the proposed seven-level structure. The performance of the proposed topology depends greatly on balancing of the H-bridge capacitor voltages. The voltages across the capacitors have to be maintained at V dc /6 with allow- able ripple. The capacitor voltages are not affected while gen- erating the voltage levels of +V dc /2, 0, and V dc /2. As the load current ows through the capacitors while generating the middle voltage levels of +2V dc /6 and +V dc /6, it has to be ensured that the capacitor voltages are balanced. This can be easily achieved by effectively making use of the switching state redundancies that exist for generation of these voltage levels. For example, the voltage level of +2V dc /6 in A-phase can be generated in any of the following methods by selecting the appropriate switch states. 1) By clamping the two-level inverter voltages to zero and adding the two H-bridge capacitor voltages (V CA1 = +V dc /6 and V CA2 = +V dc /6). 2) By subtracting voltage across the H-bridge capacitor CA1 (V CA1 = +V dc /6) from the two-level inverter voltage (+V dc /2) and bypassing the capacitor CA2. 3) By subtracting voltage across the H-bridge capacitor CA2 (V CA2 = +V dc /6) from the two-level inverter voltage (+V dc /2) and bypassing the capacitor CA1. The voltage level of +V dc /6, in A-phase, can be generated in any of the following methods by selecting the appropriate switching states. 1) By using only the voltage across the H-bridge capacitor CA1 (V CA1 = +V dc /6). 2) By using only the voltage across the H-bridge capacitor CA2 (V CA2 = +V dc /6). 3) By subtracting the sumof voltages across H-bridge capac- itors CA1 and CA2 (V CA1 + V CA2 = +2V dc /6) from the two-level inverter voltage (+V dc /2). Similar methods are used for generating the voltage levels of V dc /6 and 2V dc /6. It is evident from the switching logic given in Table I that the redundancies in methods of generation of +2V dc /6, +V dc /6, V dc /6, and 2V dc /6 facilitate charging or discharging of either both H-bridge capacitors (CA1 and CA2) 1736 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011 Fig. 2. Switch states for generating all the seven voltage levels in A-phase. +V dc /2, +2V dc /6, +V dc /6, 0, V dc /6, 2V dc /6, and V dc /2. The current paths are closed through other phases during three-phase switching operations. or any one of them, in any direction of the phase current. The criteria for selection of a switching state for balancing of the capacitor voltages, under a given condition, are also given in Table I. The switching logic is implemented by checking the statuses of the capacitor voltages vis-` a-vis the allowed ripple, in every switching cycle. Hence, the capacitor voltage correction is almost instantaneous when compared to the fundamental period of operation. Thus, the balancing of the capacitors can be done independent of power factor for the entire modulation range including overmodulation. The switching logic of A-phase is followed in B and C phases also. III. COMPARISON OF THE PROPOSED TOPOLOGY WITH CONVENTIONAL MULTILEVEL INVERTER TOPOLOGIES Acomparison of the proposed topology with the conventional seven-level inverter topologies, in terms of the components re- quired, is given in Table II. The magnitude of the dc-voltage source required in the proposed topology is half of the mag- nitude of dc-voltage source required in the conventional NPC or ying capacitor topologies. In the proposed topology, all switches in the H-bridges are rated for a voltage blocking capa- bility of V dc /6, whereas the switches in the two-level inverters are rated for a voltage blocking capability of V dc /2. Unlike the conventional seven-level NPC inverter, the proposed topology does not require any clamping diode. The number of capacitors required in this topology is only 6, which is very less compared to the requirement of capacitors in the conventional seven-level ying capacitor topology. Moreover, balancing of the capaci- tor voltages is much easier in the proposed topology compared to the NPC and ying capacitor topologies. The cascaded H- bridge topology requires nine isolated voltage sources to realize a seven-level inverter. Table I clearly shows that the two-level inverters switch only during a half cycle of the reference volt- age waveform. Even in a half cycle, the two-level inverters do not switch for generating middle voltage levels under certain conditions. Hence switchings in the two-level inverters, which operate at a higher voltage level of V dc /2, are much less compared to the switchings in H-bridge cells, which operate at a lower voltage level of V dc /6. This results in switching loss reduction and im- provement in the overall drive system efciency. The operation of H-bridge cells at a lower voltage level of V dc /6 will also result in conduction loss reduction in H-bridge switches. The proposed topology also prevents circulation of triplen harmonic current through the motor winding since the two two-level inverters are fed from two isolated voltage sources. Reliability of the system is a matter of concern in any industrial application. In the pro- posed topology, if switches in H-bridges fail, the system can be operated as a three-level inverter in the entire modulation range by bypassing the H-bridges. This feature makes the proposed topology more reliable. IV. EXPERIMENTAL VERIFICATION An induction motor rated 5 HP, 415 V, 4-pole, 50 Hz is used as a load for experimental verication of the proposed seven- level inverter topology. The constant V /f control scheme is used for running the motor at different speeds, under no-load condition, spanning two-level to seven-level operation of the inverter. The space vector pulse width modulation technique for multilevel inverters, proposed in [26], is used for generating the inverter gating pulses. The three reference phase voltages are generated from the reference voltage space vector (V
r ), which is determined from the constant V /f ratio and the speed requirement of the motor. In this paper, the modulation index is dened as the ratio of the magnitude of V
r to V dc . The controller is implemented in TMS320F2812 DSP platform. The switching logic given in Table I is implemented in SPARTAN-3 XC3S200 FPGA. The H-bridge capacitors have to be selected properly to re- strict the ripple voltage within acceptable limits. The capac- itance of H-bridge capacitor can be determined by using the formula given as C = I p
T V where C is the capacitance of the H-bridge capacitors (CA1, CA2, CB1, CB2, CC1, and CC2), I p is the peak phase current, T is the inverter switching time period (T s ), and V is the peak-to-peak voltage ripple allowed in the H-bridge capacitor. For a switching frequency of 2 kHz, if the capacitor peak-to-peak RAJEEVAN et al.: SEVEN-LEVEL INVERTER TOPOLOGY FOR INDUCTION MOTOR DRIVE 1737 Fig. 3 Space vector structure of the seven-level inverter with switching state redundancies at each location. The voltage levels of V dc /2, 2V dc /6, V dc /6, 0, +V dc /6, +2V dc /6, and +V dc /2 are represented by the numbers 0, 1, 2, 3, 4, 5, and 6, respectively. TABLE II COMPARISON OF SEVEN-LEVEL INVERTER TOPOLOGIES ripple voltage has to be limited to 5 V, capacitance required is 1150 F. The proposed seven-level inverter is operated at different modulation indices covering the entire linear modulation and overmodulation regions, at a switching frequency of 2 kHz. The corresponding fundamental frequencies of voltages cover the entire range of speed of the motor. The steady state and the transient behaviors under no-load condition are depicted in Figs. 412. Fig. 4 shows the waveforms of 1) phase voltage; 2) current; 3) ripple in H-bridge capacitor voltage V CA1 ; and 4) ripple in H-bridge capacitor voltage V CA2 , for a modulation index of 0.26 corresponding to three-level operation of the in- verter. The motor operates at a frequency of 13 Hz under this condition. It can be seen that the capacitor voltages are well balanced in this mode of operation and the peak-to-peak ripple voltage is less than 2 V. This is well within the limit of 5 V, con- sidered in determining the value of the H-bridge capacitance. Fig. 5 shows pole voltage waveforms of 1) two-level inverter-1; 2) H-bridge cell-CA1; 3) H-bridge cell-CA2; and 4) two-level inverter-2. It is clear from these waveforms that the two-level inverters are switching for much less period compared to the H-bridges. Figs. 6 and 7 show different waveforms when the inverter operates in ve-level mode, with a modulation index of 0.53, corresponding to 26 Hz operation of the motor. The waveforms pertaining to seven-level operation of the inverter (modulation index of 0.8) are shown in Figs. 8 and 9. The motor operates at a frequency of 40 Hz under this condition. The waveforms of Figs. 10 and 11 pertain to the operation of the inverter in over- modulation region with modulation index of 1. The motor op- erates at a frequency of 50 Hz at this value of modulation index. 1738 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011 Fig. 4. Voltage and current waveforms when inverter operates at modulation index M = 0.26. X-axis: 20 ms/div. (1) A-phase voltage (Y-axis: 50 V/div), (2) A-phase current (Y-axis: 2 A/div), (3) ripple in the H-bridge capacitor voltage V CA1 (Y-axis: 5 V/div), and (4) ripple in the H-bridge capacitor voltage V CA2 (Y-axis: 5 V/div). Fig. 5. Pole voltage waveforms when inverter operates at modulation index M = 0.26. X-axis: 100 ms/div, Y-axis: 200 V/div. (1) Two-level inverter-1, (2) H-bridge cell-CA1, (3) H-bridge cell-CA2, and (4) two-level inverter-2. Fig. 6. Voltage and current waveforms when inverter operates at modulation index M = 0.53. X-axis: 10 ms/div. (1) A-phase voltage (Y-axis: 100 V/div), (2) A-phase current (Y-axis: 2 A/div), (3) ripple in H-bridge capacitor voltage V CA1 (Y-axis: 10 V/div), and (4) ripple in H-bridge capacitor voltage V CA2 (Y-axis: 10 V/div). Fig. 7. Pole voltage waveforms when inverter operates at modulation in- dex M = 0.53. X-axis: 10 ms/div, Y-axis: 200 V/div. (1) Two-level inverter-1, (2) H-bridge cell-CA1, (3) H-bridge cell-CA2, and (4) two-level inverter-2. Fig. 8. Voltage and current waveforms when inverter operates at modulation index M = 0.8. X-axis: 10 ms/div. (1) A-phase voltage (Y-axis: 200 V/div), (2) A-phase current (Y-axis: 2 A/div), (3) ripple in the H-bridge capacitor voltage V CA1 (Y-axis: 5 V/div), and (4) ripple in the H-bridge capacitor voltage V CA2 (Y-axis:5 V/div). Fig. 9. Pole voltage waveforms when inverter operates at modulation in- dex M = 0.8. X-axis: 5 ms/div, Y-axis: 200 V/div. (1) Two-level inverter-1, (2) H-bridge cell-CA1, (3) H-bridge cell-CA2, and (4) two-level inverter-2. Fig. 10. Voltage and current waveforms when inverter operates at modulation index M = 1. X-axis: 5 ms/div. (1) A-phase voltage (Y-axis: 200 V/div), (2) A- phase current (Y-axis: 2 A/div), (3) ripple in H-bridge capacitor voltage V CA1 (Y-axis :5 V/div), and (4) ripple in H-bridge capacitor voltage V CA2 (Y-axis: 5 V/div). Fig. 11. Pole voltage waveforms when inverter operates at modulation index M=1. X-axis: 5 ms/div, Y-axis: 200 V/div. (1) Two-level inverter-1, (2) H-bridge cell-CA1, (3) H-bridge cell-CA2, and (4) two-level inverter-2. RAJEEVAN et al.: SEVEN-LEVEL INVERTER TOPOLOGY FOR INDUCTION MOTOR DRIVE 1739 Fig. 12. Voltage and current waveforms under transient condition of acceler- ation of the motor from 6.5 to 40 Hz. (1) A-phase voltage (Y-axis: 100 V/div), (2) A-phase current (Y-axis: 2 A/div), (3) H-bridge capacitor voltage V CA1 (Y-axis: 100 V/div), and (4) H-bridge capacitor voltage V CA2 (Y-axis: 100 V/div). It can be seen from the waveforms given earlier that the H-bridge capacitor voltages are well balanced and the peak-to- peak ripple voltage is only around 2 Vin all modes of operation. This establishes the fact that in the proposed topology of seven- level inverter, it is possible to achieve balancing of the capacitor voltages in the entire modulation range including the overmod- ulation. The pole voltage waveforms of two-level inverter-1 and two-level inverter-2 show that these inverters switch only dur- ing a half cycle of the waveform. As has been explained earlier, this results in switching loss reduction. The distortion in current waveform (see Fig. 10) is due to the introduction of lower order harmonics resulting from operation of the inverter in overmod- ulation region. Fig. 12 depicts the transient performance of the systemduring acceleration of the motor from 6 to 40 Hz. This corresponds to the transition from two-level to seven-level operation of the in- verter. Smooth transition fromtwo-level to seven-level is clearly visible in the waveform of the phase voltage. It is pertinent to note that the capacitor voltages remain balanced during the tran- sient period even though the current drawn by the motor under this condition is much higher than the current drawn during steady-state operation. Thus, the proposed topology is capa- ble of balancing the capacitor voltages in transient as well as steady-state operation of the motor. V. CONCLUSION In this paper, a newtopology of seven-level inverter for induc- tion motor drive, using two two-level inverters and six capacitor- fed H-bridge cells, is presented. The two-level inverters are fed from two isolated dc-voltage sources. An important advantage of this topology is the reduction in dc-link voltage magnitude by half when compared with the requirement of dc-link volt- age in the conventional NPC or ying capacitor topologies. The switching state redundancies are effectively utilized for main- taining the H-bridge capacitor voltages at the required level in the entire linear modulation and overmodulation regions of op- eration. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, in the entire modula- tion range, by bypassing the H-bridges. This feature enhances the reliability of the proposed inverter. It has been shown that the high-voltage two-level inverters switch much less compared to the switching of the low-voltage H-bridge cells for generating the seven-level voltage prole. As a result, the switching loss is reduced thereby improving the efciency of the drive system. This topology is inherently capable of preventing the circulation of triplen harmonic current in the motor winding. The experi- mental verication of the proposed topology is carried out on a 5-HP induction motor, for the entire modulation range, under steady state as well as transient conditions. REFERENCES [1] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, Multilevel converters: An enabling technology for high-power applications, Proc. IEEE, vol. 97, no. 11, pp. 17861817, Nov. 2009. [2] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, The age of multilevel converters arrives, IEEE Ind. Electron. Mag., vol. 2, no. 2, pp. 2839, Jun. 2008. [3] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, Multi- level voltage-source-converter topologies for industrial medium-voltage drives, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 29302945, Dec. 2007. [4] N. Hatti, K. Hasegawa, and H. Akagi, A 6.6-kV transformerless motor drive using a ve-level diode-clamped PWM inverter for energy savings of pumps and blowers, IEEE Trans. Power Electron., vol. 24, no. 3, pp. 796803, Mar. 2009. [5] M. M. Renge and H. M. Suryawanshi, Five-level diode clamped inverter to eliminate common mode voltage and reduced dv/dt in medium voltage rating induction motor drives, IEEE Trans. Power Electron., vol. 23, no. 4, pp. 15981607, Jul. 2008. [6] J. Rodriguez, J.-S. Lai, and F. Z. Peng, Multilevel inverters: A survey of topologies, controls, and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724738, Aug. 2002. [7] V. T. Somasekhar, K. Gopakumar, M. R. Baiju, K. K. Mohapatra, and L. Umanand, A multilevel inverter system for an induction motor with open-end windings, IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 824 836, Jun. 2005. [8] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point clamped PWM inverter, IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523, Sep. 1981. [9] S. Busquets-Monge, S. Alepuz, J. Rocabert, and J. Bordonau, Pulsewidth modulations for the comprehensive capacitor voltage balance of n-level three-leg diode-clamped converters, IEEE Trans. Power Electron., vol. 24, no. 5, pp. 13641375, May 2009. [10] H. Akagi and T. Hatada, Voltage balancing control for a three-level diode- clamped converter in a medium voltage transformerless hybrid active lter, IEEE Trans. Power Electron., vol. 24, no. 3, pp. 571579, Mar. 2009. [11] S. Busquets-Monge, S. Alepuz, J. Bordonau, and J. Peracaula, Voltage balancing control of diode- clamped, multilevel converters with passive front-ends, IEEE Trans. Power Electron., vol. 23, no. 4, pp. 17511758, Jul. 2008. [12] G. P. Adam, S. J. Finney, A. M. Massoud, and B. W. Williams, Capacitor balance issues of the diode clamped multilevel inverter operated in a quasi two-state mode, IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 3088 3099, Aug. 2008. [13] T.A. Meynard and H. Foch, Multilevel choppers for high voltage appli- cations, in Proc. Eur. Conf. Power Electron. Appl., 1992, pp. 4550. [14] B. P. McGrath and D. G. Holmes, Natural capacitor voltage balancing for a ying capacitor converter induction motor drive, IEEE Trans. Power Electron., vol. 24, no. 6, pp. 15541561, Jun. 2009. [15] N. P. Schibli, T. Nguyen, and A. C. Rufer, A three-phase multilevel converter for high-power induction motors, IEEETrans. Power Electron., vol. 13, no. 5, pp. 978986, Sep. 1998. [16] F. Z. Peng, J. S. Lai, J. W. McKeever, and J. VanCoevering, A multilevel voltage-source inverter with separate DC sources for static Var genera- tion, IEEE Trans. Ind. Appl., vol. 32, no. 5, pp. 11301138, Sep./Oct. 1996. [17] D. Zhong, L. M. Tolbert, B. Ozpineci, and J. N. Chiasson, Fundamental frequency switching strategies of a seven-level hybrid cascaded H-bridge multilevel inverter, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 25 33, Jan. 2009. 1740 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 6, JUNE 2011 [18] L. Haiwen, L. M. Tolbert, S. Khomfoi, B. Ozpineci, and D. Zhong, Hybrid cascaded multilevel inverter with PWMcontrol method, Power Electron. Spec. Conf., pp. 162166, 2008. [19] J. Huang and K. A. Corzine, Extended operation of ying capacitor multilevel inverters, IEEETrans. Power Electron., vol. 21, no. 1, pp. 140 147, Jan. 2006. [20] J. Wen and K. M. Smedley, Synthesis of multilevel converters based on single and/or three-phase converter building blocks, IEEE Trans. Power Electron., vol. 23, no. 3, pp. 12471255, May 2008. [21] E. Babaei, Acascade multilevel converter topology with reduced number of switches, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 26572664, Nov. 2008. [22] J. Salmon, A. Knight, and J. M. Ewanchuk, Single-phase multilevel PWM inverter topologies using coupled inductors, IEEE Trans. Power Electron., vol. 24, no. 5, pp. 12591266, May 2009. [23] M. Hagiwara and H. Akagi, Control and experiment of pulsewidth- modulated modular multilevel converters, IEEE Trans. Power Electron., vol. 24, no. 7, pp. 17371746, Jul. 2009. [24] P. N. Tekwani, R. S. Kanchan, and K. Gopakumar, A dual ve level inverter-fed induction motor drive with common mode voltage elimination and dc-link capacitor voltage balancing using only the switching-state redundancy. Part I, IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 2600 2608, Oct. 2007. [25] G. Mondal, K. Sivakumar, R. Ramchand, K. Gopakumar, and E. Levi, A dual seven-level inverter supply for an open-end winding induction motor drive, IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 16651673, May 2009. [26] R. S. Kanchan, M. R. Baiju, K. K. Mohapatra, P. P. Ouseph, and K. Gopakumar, Space vector PWM signal generation for multilevel in- verters using only the sampled amplitudes of reference phase voltages, IEE Proc. Electr. Power Appl., vol. 152, no. 2, pp. 32973309, Apr. 2005. P. P. Rajeevan received the B. Tech. degree in elec- trical engineering from the University of Calicut, Calicut, Kerala, India, and the M.E degree in power electronics from Bangalore University, Bangalore, India. He is currently working toward the Ph.D. de- gree at the Centre for Electronics Design and Tech- nology, Indian Institute of Science, Bangalore, India. His research interests include multilevel power converters, drives, pulse width modulation tech- niques, and power quality. K. Sivakumar (S08) received the B. Tech. de- gree in electrical engineering from S. V. University, Tirupati, India, in 2004, the M. Tech. degree in power electronics from the National Institute of Technol- ogy, Warangal, India, in 2006, and the Ph.D. degree in power electronics from the Centre for Electronics Design and Technology, Indian Institute of Science, Bangalore, India, in 2010. His research interests include power converters, pulse width modulation techniques, and ac drives. Chintan Patel (S08) received the B.E. degree in electrical engineering fromSouth Gujarat University, Surat, India, in 2000, and the M.Tech. degree in elec- trical engineering from the Institute of Technology, Banaras Hindu University, Varanasi, India, in 2003. He is currently working toward the Ph.D. degree at the Centre for Electronics Design and Technology, Indian Institute of Science, Bangalore, India. His research interests include sensorless control of induction motors and hysteresis current controller. Rijil Ramchand (S09) received the B.Tech. de- gree in electrical engineering from Calicut Univer- sity, Thenhipalam, India, in 1996, and the M.E. de- gree from the Indian Institute of Science, Bangalore, India, in 2003, where he is currently working toward the Ph.D. degree at the Centre for Electronics Design and Technology. He is a Faculty Member in the Department of Elec- trical Engineering, National Institute of Technology, Calicut, India. His research interests include power converters, pulse width modulation techniques, and ac drives. K. Gopakumar (M94SM96) received the B.E., M.Sc.(Engg.), and Ph.D. degrees from the Indian In- stitute of Science, Bangalore, India, in 1980, 1984, and 1994, respectively. He was with the Indian Space Research Organiza- tion, Bangalore, from 1984 to 1987. He is currently the Chairman and a Professor at the Center for Elec- tronics Design and Technology, Indian Institute of Science. His research interests include PWM con- verters and high-power drives. Dr. Gopakumar is a Fellow of the Institution of Electrical and Telecommunication Engineers, India, and the Indian National Academy of Engineers. He is currently an Associate Editor of IEEE TRANSAC- TION ON INDUSTRIAL ELECTRONICS.