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Logic Design Lab
Manual 10ESL38 3rd
sem 2013
Ratings: (0)|Views: 15,364 |Likes: 140
Published by vishvakirana
L.D. LAB (10ESL38)
For III Semester B.E. Electronics and Communication Engineering(As per VTU
Syllabus),
Prepared...
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ECE -
10ESL38


Dept.
of Electronics and
Communications
Engg.CITY
ENGINEERING
COLLEGEBANG
ALORE

62.
Manual
Prepared
by:Mr.
Vishvakiran
RC, Asst.
Prof., CEC



Logic Design Lab
2013 10ESL383
rd
Sem, E&C Dept. 1
VK
TABLE OF
CONTENT
SExperime
nts Page No
.

IC Pin Config
urations 21.


Boolean Expr
ession realizat
ion using Logi
c gates 42.


Half/Full Add
er and Subtrac
tor 73.


a. Parallel Ad
der/ Subtracto
r 10 b. BCD
to Excess-3
and Vice-
versa 144.


Binary to Gra
y Conversion
and vice versa
165.


MUX/DEMU
X for arithmet
ic circuits 216
.


Comparators
277.


Decoder Chip
for LED Displ
ay 318.


Priority Encod
er 339.


Flip-
Flop verificati
on 3510.


Counters
3811.


Shift Register
s 5012.


Ring Counter/
Johnson Cou
nter 5513.


Sequence Gen
erator 57

Logic Design
Lab Syllabus



10ESL38

59Possible Vi
va Questions
60


Logic Design Lab
2013 10ESL383
rd
Sem, E&C Dept. 2
VK
IC Pin
configuration
s

Inverter (NOT
Gate) -
7404LS 2-
Input AND Gate
- 7408LS2-
Input OR Gate -
7432LS 2-
Input NAND Ga
te - 7400LS2-
Input NOR Gat
e - 7402LS 2-
Input EX-
OR Gate -
7486LS3-
Input NAND G
ate - 7410LS 4-
bit Binary Full
Adder74LS83

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Logic Design Lab
2013 10ESL383
rd
Sem, E&C Dept. 3
VK
Dual 4-
Input NAND G
ate -
7420LS Dual 4-
input Multiplex
er741534-Bit
Magnitude
Comparator
-
7485 Decoders/
Demultiplexer 7
4139

Shift Register -
7495 Synchron
ous Up/Down C
ounter

74192Decimal
scalar-
7490DualJKFli
p-flop

7476

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