Digital Fundementals

Floyd Floyd
Digital Fundamentals, 9/e Digital Fundamentals, 9/e

Copyright Copyright 2006 by Pearson Education, Inc. 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 Upper Saddle River, New Jersey 07458
All rights reserved. All rights reserved.
Slide 1
Digital Fundamentals
Digital Fundamentals
CHAPTER 7 CHAPTER 7
Latches, Flip Latches, Flip- -Flops and Timers Flops and Timers
Floyd Floyd
Slide 2
Latches
Latches
Floyd Floyd
Slide 3
Latches Latches
S
S
-
-
R (Set
R (Set
-
-
Reset) latch
Reset) latch
Gated S
Gated S
-
-
R latch
R latch
Gated D latch
Gated D latch
Floyd Floyd
Slide 4
Latches Latches
S
S
-
-
R latch
R latch
Floyd Floyd
Slide 5
Latches Latches
S
S
-
-
R latch
R latch
Floyd Floyd
Slide 6
Figure 7 Figure 7 1 1 Two versions of SET Two versions of SET- -RESET (S RESET (S- -R) latches. Open file F07 R) latches. Open file F07- -01 and verify the operation of both latches. 01 and verify the operation of both latches.
Thomas L. Floyd Thomas L. Floyd
Digital Fundamentals, 9e Digital Fundamentals, 9e
Floyd Floyd
Slide 7
Figure 7 Figure 7 2 2 Negative Negative- -OR equivalent of the NAND gate latch in Figure 9 OR equivalent of the NAND gate latch in Figure 9 1(b). 1(b).
Floyd Floyd
Slide 8
Figure 7 Figure 7 3 3 The three modes of basic latch operation (SET, RESE The three modes of basic latch operation (SET, RESET, no T, no- -change) and the invalid condition. change) and the invalid condition.
Figure 73 The three modes of basic latch operation (SET, RESET, no-change) and the invalid condition.
Floyd Floyd
Slide 9
Figure 7 Figure 7 6 6 The latch used to eliminate switch contact bounce. The latch used to eliminate switch contact bounce.
Floyd Floyd
Slide 10
Figure 7 Figure 7 7 7 The 74LS279 quad latch. The 74LS279 quad latch.
Floyd Floyd
Slide 11
Latches Latches
Gated S
Gated S
-
-
R latch
R latch
Floyd Floyd
Slide 12
Latches Latches
Gated D latch
Gated D latch
Floyd Floyd
Slide 13
Figure 7 Figure 7 12 12 The 74LS75 quad gated D latches. The 74LS75 quad gated D latches.
Floyd Floyd
Slide 14
Edge
Edge
-
-
Triggered Flip
Triggered Flip
-
-
Flops
Flops
Floyd Floyd
Slide 15
Edge Edge- -Triggered Flip Triggered Flip- -Flops Flops
Edge
Edge
-
-
triggered S
triggered S
-
-
R flip
R flip
-
-
flop
flop
Edge
Edge
-
-
triggered D flip
triggered D flip
-
-
flop
flop
Edge
Edge
-
-
triggered J
triggered J
-
-
K flip
K flip
-
-
flop
flop
Floyd Floyd
Slide 16
Edge
Edge
-
-
triggered S
triggered S
-
-
R flip
R flip
-
-
flop
flop
Waveforms Waveforms
Floyd Floyd
Slide 17
Edge
Edge
-
-
triggered
triggered
S
S
-
-
R flip
R flip
-
-
flop
flop
Floyd Floyd
Slide 18
Figure 7 Figure 7 13 13 Edge Edge- -triggered flip triggered flip- -flop logic symbols (top: positive edge flop logic symbols (top: positive edge- -triggered; bottom: negative edge triggered; bottom: negative edge- -triggered). triggered).
Floyd Floyd
Slide 19
Figure 7 Figure 7 14 14 Operation of a positive edge Operation of a positive edge- -triggered S triggered S- -R flip R flip- -flop. flop.
Floyd Floyd
Slide 20
Figure 7 Figure 7 17 17 Edge triggering. Edge triggering.
Floyd Floyd
Slide 21
Figure 7 Figure 7 18 18 Flip Flip- -flop making a transition from the RESET state to the SET state o flop making a transition from the RESET state to the SET state on the positive n the positive- -going edge of the clock pulse. going edge of the clock pulse.
Floyd Floyd
Slide 22
Figure 7 Figure 7 19 19 Flip Flip- -flop making a transition from the SET state to the RESET state o flop making a transition from the SET state to the RESET state on the positive n the positive- -going edge of the clock pulse. going edge of the clock pulse.
Floyd Floyd
Slide 23
Edge
Edge
-
-
triggered D flip
triggered D flip
-
-
flop
flop
Waveforms Waveforms
Floyd Floyd
Slide 24
Edge
Edge
-
-
triggered D flip
triggered D flip
-
-
flop
flop
Floyd Floyd
Slide 25
Edge
Edge
-
-
triggered J
triggered J
-
-
K flip
K flip
-
-
flop
flop
Waveforms Waveforms
Floyd Floyd
Slide 26
Edge
Edge
-
-
triggered J
triggered J
-
-
K flip
K flip
-
-
flop
flop
Floyd Floyd
Slide 27
Figure 7 Figure 7 22 22 A simplified logic diagram for a positive edge A simplified logic diagram for a positive edge- -triggered J triggered J- -K flip K flip- -flop. flop.
Floyd Floyd
Slide 28
Figure 7 Figure 7 23 23 Transitions illustrating the toggle operation when Transitions illustrating the toggle operation when J J = 1 and = 1 and K K = 1. = 1.
Floyd Floyd
Slide 29
Figure 7 Figure 7 26 26 Logic symbol for a J Logic symbol for a J- -K flip K flip- -flop with active flop with active- -LOW preset and clear inputs. LOW preset and clear inputs.
Floyd Floyd
Slide 30
Figure 7 Figure 7 27 27 Logic diagram for a basic J Logic diagram for a basic J- -K flip K flip- -flop with active flop with active- -LOW preset and clear inputs. LOW preset and clear inputs.
Floyd Floyd
Slide 31
Flip
Flip
-
-
Flop Operating Characteristics
Flop Operating Characteristics
Floyd Floyd
Slide 32
Flip Flip- -Flop Operating Characteristics Flop Operating Characteristics
Propagation delay times

Propagation delay times
Set
Set
-
-
up time
up time
Hold time
Hold time
Maximum clock frequency

Maximum clock frequency
Pulse widths
Pulse widths
Power dissipation
Power dissipation
Floyd Floyd
Slide 33
Figure 7 Figure 7 32 32 Propagation delays, clock to output. Propagation delays, clock to output.
Floyd Floyd
Slide 34
Figure 7 Figure 7 33 33 Propagation delays, preset input to output and clear input Propagation delays, preset input to output and clear input to output. to output.
Floyd Floyd
Slide 35
Figure 7 Figure 7 34 34 Set Set- -up time ( up time (t t
s s
). The logic level must be present on the ). The logic level must be present on the D D input for a time equal to or greater than input for a time equal to or greater than t t
s s
before the triggering edge of the clock before the triggering edge of the clock pulse for reliable data pulse for reliable data
entry. entry.
Floyd Floyd
Slide 36
Figure 7 Figure 7 35 35 Hold time ( Hold time (t t
h h
). The logic level must remain on the D input for a time equal t ). The logic level must remain on the D input for a time equal to or greater than o or greater than t t
h h
after the triggering edge of the clock pulse after the triggering edge of the clock pulse for reliable data entry. for reliable data entry.
Floyd Floyd
Slide 37
Flip
Flip
-
-
Flop Applications
Flop Applications
Floyd Floyd
Slide 38
Flip Flip- -Flop Applications Flop Applications
Parallel data storage

Frequency division
Frequency division
Counting
Counting
Floyd Floyd
Slide 39

Floyd Floyd
Slide 40
Frequency division
Frequency division
Floyd Floyd
Slide 41
Counting
Counting
Floyd Floyd
Slide 42
One
One
-
-
Shots
Shots
Floyd Floyd
Slide 43
One One- -Shots Shots
Nonretriggerable
Nonretriggerable
one
one
-
-
shot
shot
Regriggerable
Regriggerable
one
one
-
-
shot
shot
Floyd Floyd
Slide 44
Figure 7 Figure 7 44 44 A simple one A simple one- -shot circuit. shot circuit.
Floyd Floyd
Slide 45
Nonretriggerable
Nonretriggerable
one
one
-
-
shot
shot
Floyd Floyd
Slide 46
Nonretriggerable
Nonretriggerable
one
one
-
-
shot
shot
Floyd Floyd
Slide 47
Regriggerable
Regriggerable
one
one
-
-
shot
shot
Floyd Floyd
Slide 48
Regriggerable
Regriggerable
one
one
-
-
shot
shot
Floyd Floyd
Slide 49
The 555 Timer
The 555 Timer
Floyd Floyd
Slide 50
The 555 Timer The 555 Timer
Monostable
Monostable
(one
(one
-
-
shot) operation
shot) operation
Astable
Astable
operation
operation
Floyd Floyd
Slide 51
Monostable
Monostable
(one
(one
-
-
shot) operation
shot) operation
t t
w w
=1.1R =1.1R
1 1
C C
1 1
Floyd Floyd
Slide 52
Figure 7 Figure 7 55 55 One One- -shot operation of the 555 timer. shot operation of the 555 timer.
Floyd Floyd
Slide 53
Astable
Astable
operation
operation
Floyd Floyd
Slide 54
Figure 7 Figure 7 57 57 Operation of the 555 timer in the astable mode. Operation of the 555 timer in the astable mode.
Floyd Floyd
Slide 55
Figure 7 Figure 7 59 59 The addition of diode The addition of diode D D
1 1
allows the duty cycle of the output to be adjusted to less than allows the duty cycle of the output to be adjusted to less than 50 percent by making 50 percent by making R R
1 1
< < R R
2 2
. .

Digital Fundementals

Загружено:

Сведения о документе

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Digital Fundementals

Загружено:

Авторское право:

Доступные форматы

Floyd Floyd

Digital Fundamentals, 9/e Digital Fundamentals, 9/e

Propagation delay times

Maximum clock frequency

Parallel data storage

Parallel data storage

Вам также может понравиться