PSUEDO RANDOM SEQUENCE GENERATOR

AIM: To generate the pseudo random sequence using linear feedback shift register and verify the output
using truth table in bread board and HDL software.
APPARATUS REQUIRED:
DFF(IC 7484)
XOR (IC 7486)

Digital Trainer kit

Connecting wires

Personal Computer with Windows operating system

Xilinx 14.3 software PROCEDURE: Hardware:

Connections are made as per the circuit diagram.


Logic inputs are given as per the circuit diagram.


Observe the output and verify the truth table. Simulation:

Write and draw the Digital logic system and write the Verilog code for above system.


Enter the Verilog code in Xilinx software.


Check the syntax and simulate the above verilog code (using Xilinx) and verify the output waveform as
obtained. THEORY: PRBS generator generates pseudo random binary sequence based on the concept of
linear feedback shift register.It
is pseudo because it is deterministic
and after n elements it starts to repeat itself, unlike real random sequences. Random numbers for
polynomial equations are generated by using the shift register circuit. The random number generator is
nothing but the Linear Feedback Shift Register(LFSR). The shift registers are very helpful and versatile
modules that facilitate the design of many sequential circuits whose design may otherwise appear very
complex. In its simplest form, a shift register consists of a series of flip-flops having identical
interconnection between two adjacent flip-flops. Two such registers are shift right registers and the shift
left registers. In the shift right register, the bits stored in the flip-flops shift to the right when shift pulse is
active. Like that, for a


shift left register, the bits stored in the flip-flops shift left when shift pulse is active. In the shift registers,
specific patterns are shifted through the register. There are applications where instead of specific patterns,
random patterns are more important. For a 4-bit PRBS generator, LFSR consist of 4-registers connected
together as a shift register. Here, we used D flipflop as a register. The input to the first register comes
from the XOR of third and fourth output bits of the register. The inputs fed to the XOR are called the tap
sequence and are often specified with characteristic polynomial. On reset the register must be initialized
to a non zero
value(all 1s).The output seq
uences through all 2^n-1 combinations when clock
signal is given. Obviously, its possible to get a longer m
-sequence using more stages to the shift register. The formula connecting these is: m=2^n-1.Where m is
the length of the m-sequence and n is the number of shift register stages. The pseudo-random sequences
are handy for built-in-test and bit-error-rate testing in communication links. They are also used in many
spread spectrum communications systems such as GPS and CDMA and encoding and decoding the error
control codes. LFSRs used as a generators of pseudorandom sequences have proved externally useful in
the area of testing of VLSI chips.
Logic Diagram:


Verilog Coding: module prbs(q,qb,clk,clr); output [3:0] q,qb; input clk,clr; reg [3:0] tmp, tmpb; always
@(negedge clk or posedge clr) begin if(clr) begin tmp = 4'b1111; tmpb = 4'b0000; end else tmp = {
tmp[3],tmp[2],tmp[1], tmp[3]^tmp[2]}; end assign q=tmp; assign qb=tmpb; endmodule RESULT: Thus the
operation pseudo-random number was verified using hardware and software simulations