VLSI Design

Lecture 2
(MOSFET Structure)
Waqar Ahmad
Department of Electrical Engineering
Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Si Si Si
Si Si Si
Si Si Si
VLSI Design 2
Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts
poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
As Si Si
Si Si Si
Si Si Si
B Si Si
Si Si Si
Si Si Si
-
+
+
-
VLSI Design 3
p-n Junctions
A junction between p-type and n-type
semiconductor forms a diode.
Current flows only in one direction
p-type n-type
anode
cathode
VLSI Design 4
The MOS Transistor
How old is the idea?
The first experimental observation of the surface
and its impact on the electric current was
disclosed in the paper The action of light on
Selenium by W. G. Adams and R. E. Day in the
Proceeding of Royal Society in 1876.
VLSI Design 5
Field effect control device proposed by J. Lilienfield
1928
VLSI Design 6
Physical structure of the enhancement-type
NMOS transistor
VLSI Design 7
3-D perspective
Polysilicon
Aluminum
VLSI Design 8
L = 0.1 to 3 m cross-section.
Typically, W = 0.2 to 100 m, and the
thickness of the oxide layer (tox) is in
the range of 2 to 50 nm.
VLSI Design 9
MOS Transistor
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO
2
(oxide) is a very good insulator
Called metal oxide semiconductor (MOS) capacitor
Even though gate is no longer made of metal
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
VLSI Design 10
MOS Transistors - Types and Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOS
Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS with
Bulk Contact
VLSI Design 11
nMOS operation
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
g=0: When the gate is at a low voltage (V
GS
< V
TN
):
p-type body is at low voltage
source and drain-junctions diodes are OFF
transistor is OFF, no current flows
g=1: When the gate is at a high voltage (V
GS
V
TN
):
negative charge attracted to body
inverts a channel under gate to n-type
transistor ON, current flows, transistor
can be viewed as a resistor
VLSI Design 12
nMOS pass 0 more strongly than 1
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
Why does 1 pass degraded?
VLSI Design 13
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
VLSI Design 14
pMOS operation
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
g=0: When the gate is at a low voltage (V
GS
< V
TP
):
positive charge attracted to body
inverts a channel under gate to p-type
transistor ON, current flows
g=1: When the gate is at a high voltage (V
GS
V
TP
):
negative charge attracted to body
source and drain junctions are OFF
transistor OFF, no current flows
VLSI Design 15
pMOS pass 1 more strongly than 0
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
Why does 0 pass degraded?
VLSI Design 16
Creating a Channel for Current Flow
N-channel MOSFET is formed in a p-type
substrate: Channel created by inverting the
substrate surface from p type to n type.
Hence the induced channel is also called
an inversion layer.
Gate voltage at which a sufficient
number of mobile electrons
accumulate---- Threshold voltage Vt
VLSI Design 17
Applying a Small VDS
VDS causes a current (ld) to flow through source and drain. Conductance of
the channel is proportional to the excess gate voltage VGS above Vt
VLSI Design 18
Channel Formation
VLSI Design 19
Operation as VDS Is Increased
Channel depth depends on this voltage
Channel is no longer of uniform depth;
Channel will take the tapered form shown:
Deepest at the source end and shallowest at the drain end.
As VDS is increased, the channel becomes more tapered and its resistance
increases correspondingly
VLSI Design 20
Cross-section of a CMOS IC
Note that the PMOS transistor is formed in a separate n-type
region, known as an n well. Another arrangement is also
possible in which an n-type body is used and the n device is
formed in a p well. Not shown are the connections made to the
p-type body and to the n well; the latter functions as the body
terminal for the p-channel device.
VLSI Design 21
Transistor in Linear
VLSI Design 22
Transistor in Saturation
VLSI Design 23
The Threshold Voltage
VLSI Design 24
Operating the MOS Transistor in the
Subthreshold Region
It has been found that for values of Vgs smaller than but close to Vt a
small drain current flows. (weak inversion)
In this subthreshold region of operation drain current is exponentially
related to Vgs.
In most digital applications, it is desirable to have faster current drop as
voltage falls below Vt.
The rate of current decline w.r.t. Vgs below Vt is thus a quality measure.
There are special, but a growing number of applications (mostly analog)
that make use of subthreshold operation.
VLSI Design 25
Channel Charge
MOS structure looks like parallel plate capacitor while operating in
inversion (Gate oxide channel)
Q
channel
= CV
C = C
g
=
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
C
ox
=
ox
/ t
ox
VLSI Design 26
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field between source and
drain
v = E called mobility
E = V
ds
/L
Time for carrier to cross channel:
t = L / v
VLSI Design 27
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W
V
C V V V
L
V
V V V

=

=



=


ox
=
W
C
L

VLSI Design 28
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V

=


=
VLSI Design 29
A model for manual analysis
VLSI Design 30
MOS Capacitances
Dynamic Behavior
VLSI Design 31
Dynamic Behavior of MOS Transistor
D
S
G
B
C
GD
C
GS
C
SB
C
DB
C
GB
VLSI Design 32
Capacitance in CMOS
Two conductors separated by an insulator have
capacitance
Overlap Capacitance
Gate to channel capacitance is very important
Creates channel charge necessary for operation
Source and Drain have (Junction) capacitance to
body
Across reverse-biased diodes
Called diffusion capacitance because it is associated with
source/drain diffusion
Interconnect wires also have (distributed) capacitance
VLSI Design 33
Capacitive Device Model
VLSI Design 34
Capacitive Device Model
C
GS
= C
GSO
+ C
GCS
C
GD
= C
GDO
+ C
GCD
C
GB
= C
GCB
C
SB
= C
SDiff
C
DB
= C
DDiff
VLSI Design 35
Overlap Capacitance
Source and Drain diffusion areas tend to extend
below gate oxide (lateral diffusion)
Effective channel length decreases by a factor
d
Creates parasitic capacitance between gate and
source/drain
VLSI Design 36
Overlap Capacitance
C
GSO
= C
GDO
= C
ox
x
d
W
C
ox
=

cx
t
cx
x
d
x
d
L
d
Polysilicon gate
Top view
Gate-bulk
overlap
Source
n
+
Drain
n
+
W
t
ox
n
+
n
+
Cross section
L
Gate oxide
VLSI Design 37
Channel Capacitance
Off region
No channel exists
Only gate to body capacitance
C
G
= C
GCB
= C
ox
WL
S
D
G
C
GC
VLSI Design 38
Channel Capacitance
Linear region
Inversion layer formed
Gate to body capacitance becomes zero
Capacitance equally distributed between drain and
source
C
GCS
= C
GCD
=
1
2
C
ox
WL
C
G
= C
GCS
+ C
GCD
S
D
G
C
GC
VLSI Design 39
Channel Capacitance
Saturated region
Region under the channel is heavily inverted
Drain region of channel is pinched off
C
GCD
reduces to zero
C
G
= C
GCS
=
2
3
C
ox
WL
S
D
G
C
GC
VLSI Design 40
Diffusion (Junction) Capacitance
C
sb
, C
db
Two components
An area component
A sidewall component
Let diffusion capacitance is
Cg for contacted diffusion
Cg for un-contacted
Varies with process
VLSI Design 41
Diffusion (Junction) Capacitance
C
diff
=C
bottom
+C
sw
=C
j
L
s
W+C
sw
x
j
(2L
s
+W)
WhereC
j
=Junctioncapacitanceperunitarea
C
sw
=Sidewallcapacitanceperunitarea
Bottom
Side wall
Side wall
Channel
Source
N
D
Channel-stop implant
N
A
1
Substrate N
A
W
x
j
L
S
Type equation heie.
VLSI Design 42
Parasitic Resistances
W
L
D
Drain
Drain
contact
Polysilicon gate
D
S
G
R
S
R
D
V
GS,eff
VLSI Design 43
Future Perspectives
25 nm FINFET MOS transistor
VLSI Design 44
Review
Polysilicon Gate
SiO2
Insulator
n+ n+
p substrate
channel
Source
Drain
n transistor
G
S
D
SB
L
W
G
S
D
substrate connected
to GND
p+ p+
n substrate
channel
Source
Drain
p transistor
G
S
D
SB
Polysilicon Gate
SiO2
Insulator
L
W
G
substrate connected
to V
DD
VLSI Design 45
References
Contents of this lecture are courtesy of
Jan M. Rabaey
Sherief Reda
Neil H. E. Weste
J. Abraham