Computer Peripherals & Interfacing

CSE-333
Mahmud Hasan
Lecturer
Department of Computer Science & Engineering
Stamford University, Bangladesh
Fall, 2011
Course Overview
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Reference Books
The Intel Microprocessor (4
th
to 7
th
Edition)
Barry B. Brey
IBM PC and Clones (2
nd
Edition)
B. Govindarajalu
Microprocessors and Interfacing (2
nd
Edition)
Douglas V. Hall
Course in Progress
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Lecture One
Microprocessor Basics
Programming Model of Intel x86
Segment and Offset Address
Segment Address defines the beginning of any memory
segment.
Offset Address selects any location within this memory
segment.
address=segment10+offset
Microprocessor Instruction- MOV
Microprocessor Instruction- MOV
Microprocessor Instruction- PUSH
and POP
The PUSH instruction takes data from
a 16-bit register, segment register or
16-bit memory location and places it
into stack.
The POP instruction removes data
from stack and places it into the
target 16-bit register, segment
register or 16-bit memory location.
Microprocessor Instruction- I N and
OUT
Arithmetic Instructions
ADD AL, BL
AL=AL+BL
ADC AL, AH
AL=AL+AH+Carry
SUB CL, BL
CL=CL-BL
SBB AH, AL
AH=AH-AL-Carry
I NC BL
BL=BL+1
DEC BH
BH=BH-1
CMP CL, BL
CL-BL
MUL CL
AX=ALCL
MUL CX
DX-AX=AXCX
DI V CL
AX/CL;
AL contains quotient and AH contains remainder
Logic Instructions
AND, OR, XOR and NOT are the basic logic operations.
AND AL, BL means AL=AL and BL, so do the OR and XOR.
NOT means ones complement.
NEG means twos complement.
TEST instruction performs the AND operation but without
changing the content of the destination operand.
Shift Instruction
Rotate Instruction
JMP, CALL and RET Instructions
JMP Instruction transfers the program control to a memory
location. If the JMP is within the current memory segment,
then the JMP is near; else the JMP is far.
CALL is similar to JMP, except that it has a return address.
RET instruction is usually used at the ending of a procedure
so that the flow of program can be returned to the address
stored in stack.
Hierarchy of Memory
Microprocessor
Cache Memory
Storage
Device
# Data Processing Speed Increases
# Amount of Data Decreases
# Cost of Production Increases
Registers
Questions on Lecture One
1. Find the memory address specified by the following segment and offset.
1. CS=1000H and IP=2000H
2. CS=2000H and IP=1000H
3. CS=2300H and IP=1A00H
4. CS=3456H and IP=ABCDH
2. What happens when we execute the instruction MOV BL, DX?
3. Why do we need to study Computer Peripherals and Interfacing?
4. Differentiate between-
1. PUSH and POP
2. CALL and JMP
3. AND and TEST
4. NOT and NEG
5. Shift and Rotate
6. IN and OUT
5. Why is arithmetic shift is different than logical shift? Whats the difference?
6. What are the responsibilities of Accumulator Register?
Course in Progress
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Lecture Two
BUS Systems
The Universal Serial Bus (USB)
USB has two types of connectors, in either
case, there are four pins on each
connector.
The USB sues NRZI (non-return-to-zero-
inverted) encoding technique for
transmitting packets.
NRZI does not change the signal level for
the transmission of logic-1, but the signal
level is inverted for each change to a logic-
0.
USB Connectors, Pin Configurations and
Interface
NRZI Encoding
PCI Bus System
PCI Stands for Peripheral System Interconnect.
It Has Plug-&-Play Characteristics.
PCI can function with 64 bit data bus and 32 bit address
bus, sometimes, these buses are multiplexed.
It contains a series of registers, located in a small memory
device on the PCI interface, that contain information about
PCI board.
The information allow the computer to automatically
configure the PCI card.
System Structure of PCI Bus
Block Diagram of PCI Interface
Comparison between ISA and PCI
ISA PCI
ISA Stands for Industry
Standard Architecture.
PCI Stands for Peripheral
Component Interconnect.
It doesnt have Plug-&-Play
Characteristics.
It has Plug-&-Play
Characteristics.
ISA functions with 8 or 16 bit
data bus.
PCI functions with 64 bit data
bus.
The clocking speed is lower
than that of PCI.
The clocking speed is greater
than that of ISA.
ISA interfaces modems,
sound cards etc.
PCI interfaces video
controller, disk controller etc.
Questions on Lecture Two
1. Draw the waveform as the result of NRZI encoding
of the digital data 0101010111000100101.
2. Explain the circuit operation of USB interface.
3. What is the purpose of memory on PCI expansion
board?
4. What do you mean by Plug-&-Play Characteristics?
5. Differentiate and relate between PCI and ISA.
Course in Progress
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Lecture Three
The 8237 DMA Controller
Basic Idea behind DMA Technique
Direct Memory Access (DMA) is a technique that allows the
direct data transfer between memory and I/O devices
keeping the microprocessor temporary disabled.
Two control signals are used to request and acknowledge
DMA transfer.
1. HOLD pin is an input that is used to request a DMA
action.
2. HLDA pin is an output that is used to acknowledge a
DMA action.
Timing for HOLD and HLDA
IF HOLD=logic-1, DMA action is requested. Microprocessor responds
to it by suspending its execution and placing its address, data and
control buses at high-impedence state. Then the I/O devices can
access the system buses.
DMA Operation
Pin Configuration of 8237
A0-A7: Address Pins
DB0-DB7: Data Pins
IOR: I/O Read Pin
IOW: I/O Write Pin
MEMR: Memory Read Pin
MEMW: Memory Write Pin
Ready: Ready Signal Pin
HLDA: Hold Acknowledge Pin
CS: Chip Select Pin
CLK: Clock Pin
RESET: Reset Circuit Pin
DACK0-DACK3: DMA Acknowledge Pins
DREQ0-DREQ3: DMA Request Pins
AEN: Address Enable Pin
ADSTB: Address Strobe Pin
HRQ: Hold Request Pin
EOP: End-of-Process Pin
Internal Registers of 8237
8237 has 9 internal registers for different purposes.
Most of the registers are 8-bit long and each bit has its
special operation.
The registers are: CAR, CWCR, BA and BWC, CR, MR,
BR, MRSR, MSR, SR.
As an example of typical 8237 internal register, let us
notice the following bit pattern.
0 0 1 0 0 1 1 0
Registers Descriptions
CAR: CAR stands for Current Address Register. It is
used to hold the 16 bit memory address used
for DMA transfer.
CWCR: CWCR stands for Current Word Count
Register. It holds the number of bytes to be
transferred.
BA-BWC: Base Address and Base Word Count registers
are used when auto initialization is selected
for any channel. They reload CAR and CWCR
after a DMA action is accomplished.
CR: Command Register programs the operation of
8237 DMA controller.
MR: Mode Register programs the mode of
operation for a channel.
BR: Bus Request register is used to request a DMA
transfer via software.
Registers Description (continued)
MRSR: Mask Register Set/Reset sets or clears the
channel masks. If the mask is set, the channel
is disabled.
MSR: Mask Register clears or sets all the masks with
one command instead of individual channels
as with MRSR.
SR: The Status Register shows the status of each
DMA channel.
8237 Command Register
Questions on Lecture Three
1. What are the functions of HLDA and HOLD pins in
case of DMA Transfer?
2. Draw a block diagram and illustrate how a DMA
transfer takes place.
3. Discuss the functions of different pins of 8237.
4. How many registers does 8237 have? Briefly
discuss each of them.
5. Draw the bit pattern of command register and
indicate the functions of each bit.
Course in Progress
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Lecture Four
Memory and I/O Interface
Basic Input Interface:
Three State Buffer
A three-state-buffer is a basic
input device. It fixes up the
voltage level for the binary
data.
Whenever SEL is logic-0, the
contents of the switchers are
passed through the buffer
and sent to microprocessor.
Basic Output Interface: Latch
The peed of microprocessor
is much larger than the speed
of output devices.
To synchronize their speed
a latch is used. The latch
makes a delay of the signal
generated for the output
devices.
This synchronization process
is referred to as Handshaking
or Polling.
Address Decoding
Address Decoding refers to the operation of preparing and
sending different addresses from the microprocessor to the
memory or I/O devices so that various devices can be used in
the system.
Without address decoding only one memory or I/O device
could be connected to a microprocessor which would make it
virtually useless.
Most of memory or I/O devices have different number of
address pins, 8086 microprocessor has 20 address pins. If
microprocessor sends 20 bit address, most of the devices will
not operate.
To resolve this problem, we need a technique that must
convert the 20 bit address to desired-number-of-bit address.
This task is known as address decoding.
Types of Address Decoding
Since a computer system involves simply a
microprocessor, I/O devices and a memory; we
need to interface the microprocessor with either I/O
or memory.
Therefore, we have to decode address only for
either I/O devices or memory.
Thus we have either memory address decoding or
I/O address decoding.
Memory Decoding:
A simple NAND gate Decoder
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1 1 1 1 1 1 1 1 1 X X X X X X X X X X X
1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Therfore, Starting Address FF800 H
Ending Address FFFFF H
Memory Decoding:
3-to-8 Line Decoder (74LS138)
A circuit that uses eight 2764 EPROMs
for a 64Kx8 section of memory in an
8088 microprocessor based system:
Fixed Addressing and Variable
Addressing
Fixed Addressing: The 8-bit form (P8) where the I/O
address of 16 bit is stored is called a fixed address
because it is stored with the instruction.
IN AL, 12H
Variable Addressing: The 16-bit I/O address in DX is
called a variable address because it is stored in DX
and then used to address the I/O device.
MOV DX, 0063H
OUT DX, AL
Isolated I/O and Memory Mapped I/O
Isolated I/O Memory Mapped I/O
Difference between Isolated I/O
and Memory Mapped I/O
Isolated I/O Memory Mapped I/O
The I/O locations are isolated from
memory system in a separated I/O
address space.
I/O locations are mapped within the
memory.
Memory can be expanded to its full
size without using any of memory
space for I/O devices.
Full memory cant be expanded
since a portion is used as I/O map.
Data transfer between
microprocessor and I/O requires IN,
INS, OUT and OUTS instructions.
No such instruction is required for
transferring data.
Expanded amount of memory. Reduced amount of memory.
Separate control signals that indicate
IORC or IOWC operations.
IORC and IOWC have no function
and may reduce the amount of
circuitry.
Questions on Lecture Four
1. Draw the basic input interface and basic output interface
and explain how they operate in a computer system.
2. Define Address Decoding. Briefly explain why address
decoding is necessary.
3. Differentiate between Isolated I/O and Memory Mapped
I/O.
4. With necessary diagram explain the construction and
operation of a simple NAND gate decoder.
5. Design a 64KB EPROM to select the memory for address
range F0000H to FFFFFH.
6. Design a circuit by using 3-8 line decoder to select the
memory for address range D8000H-D8FFFH.
7. Design a circuit that uses eight 2764 EPROMs for a 64KBx8
section of memory in an 8086 microprocessor based
system to select the memory for address range D0000H-
DFFFFH.
Course in Progress
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Lecture Five
Parallel Printer Interface
Signals in Centronic Interface
Printer
Controller
Printer
Data Lines
STROBE (take data)
ACK (give data)
busy
PE (no paper)
ERROR (fault)
SLCT IN (enable interface)
SLCT (selected)
AUTO FEED XT (h/w line feed)
INIT (reset)
ground
Interfacing and Centronic Interface
Interfacing
The process of connecting peripherals with the
microprocessor for transferring instructions and
results is known as interfacing.
Centronic Interface
The interface that shows or provides a handshaking
protocol between a computer and a printer is called
the centronic iterface.
Centronic Interface Timing Diagram
5 s
0.5
s
0.5
s
0.5
s
STROBE
Data
ACK
Busy
The printer controller sends data to the printer.
After a minimum gap of 0.5 s, STROBE is low and kept low
for minimum duration 0.5 s. As soon as STROBE is low, the
Busy pin is high. The controller should retain data on the data
lines for a minimum interval of 0.5 s from the trailing edge of
STROBE.
When the printer is ready to receive next character of data,
It makes ACK line low, thereby removing Busy.
Programming Sequence for
Printer Interface
Start
Establish Logical Connection
Printer
Logically
Connected?
Reset the Printer
Read Device Status
Is
Printer
Busy?
Send Data
Make STROBE Active Make STROBE Inactive Read Status
Is
ACK
Low?
Send Next Data
Is
ACK
High for
Long Time?
Analyze the Reason
Display Error Message
Act as directed by the user
Yes
No
Yes
No
No
No
Yes
Yes
Line Printer (LPT)
LPT stands for Line Printer which is known as the
parallel printer interface. This interface gives the user
access to 8-lines that can be programmed to send or
receive parallel data.
The parallel port LPT
1
operates at I/O addresses
378H, 379H and 37AH. The secondary port LPT
2
, if
present, operates at I/O addresses 278H, 279H and
27AH.
The centronic interface uses two connectors: a 25-pin
D-Connector on the back of the PC and a 36-pin
centronic on the back of the printer.
Data Port and Status Register
of LPT
Port 378H
Bit-0 Bit-7
9 8 7 6 5 4 3 pins
It is the data port that connects
to bits D
0
-D
7
.
Port 379H
x x x
NERROR (1=no error)
ONLINE (1=online)
PAPER (1=out of paper)
ACK (1=acknowledge)
NBUSY(1=not busy)
This is status register which is a
read-only port that returns the
information from the printer
through signals.
Additional Status Port of LPT
x x
Port 37AH
STR (pulse high to print)
ALF (1=line feed by printer)
INI (0=initialize printer)
DSL (1=select printer)
IRQ (1=enabled)
Bidirectional (1=input, 0=output)
Reading or Writing Parallel Port
If the bidirectional bit of port 37AH is set, the port is initialized for reading.
# Initialization:
MOV AL, 20H
MOV DX, 37AH
OUT DX, AL
# Reading:
MOV DX, 378H
IN AL,DX
Again, if the bidirectional bit of port 37AH is reset, the port is initialized for
writing.
# Initialization:
MOV AL, 00H
MOV DX, 37AH
OUT DX, AL
# Writing:
MOV DX, 378H
MOV AL, WRITE-DATA
OUT DX, AL
Questions on Lecture Five
1. Define Interfacing and Centronic Interface.
2. Draw and explain the centronic interface timing diagram.
3. Show the signals that are interacting in a centronic interface. Explain
each of their functions.
4. Draw the flow-chart of the programming sequence that are followed
by software routines for printer interface.
5. What do you mean by LPT? Illustrate the contents of the data port,
status register and additional status port of LPT.
6. With appropriate example show how the parallel port can be read or
written.
7. Explain why we have to send 20H and 00H to port 37AH for initializing
reading and writing respectively.
Course in Progress
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Lecture Six
Programmable Peripheral Interface
(82C55)
Basic Description of 82C55
The 82C55 is a very popular, cost effetive interfacing component for P.
It has 24 pins and three I/O ports.
Group-A consists of Port-A and upper half of Port-C.
Group-B consists of Port-B and lower half of Port-C.
Register selection is done by A1, A0 pins.
It can operate in three distinct modes of operations:
Mode-0 (simple I/O)
Mode-1 (strobed I/O)
Mode-2 (bidirectional I/O)
The I/O port assignment of 82C55
Operating Modes
Mode-0 Operation:
It causes the 82C55 to function as either a buffered input device or
as a latched output device. For example, 82C55 can be interfaced
with LED display (latched output) or with keyboard (buffered
input).
Mode-1 Operation:
It causes Port-A and/or Port-B to function as latching input device.
Port-C is used for control or handshaking signals in this mode.
Mode-2 Operation:
It allows only group-A. Here, Port-A becomes bidirectional,
allowing data to be transmitted and received over the same eight
wires.
Programming 82C55
Command Byte B
Command Byte A
The Command Byte A functions for group-A and
Group-B and Command Byte B sets or resets the bits of
Port-C only if 82C55 is programmed in mode-1 or mode-2.
Group-A can operate in all three modes while Group-B
can operate in only mode-0 and in mode-1.
Control Word and Programming 82C55
Control Word
It is a word stored in a register named control register used to control
the operation of a program of a digital device.
Find the control word for PA=out, PB=in, PC0-PC3=in, PC4-
PC7=out; and write a program to get data from Port-B and
send it to Port-A. In addition, data from PCL is sent out to the
PCU. Use port addresses 300H-303H for 82C55 chip.
1 0 0 0 0 0 1 1
Therefore, Control Word = 83H
The Program (continued)
B82C55 EQU 300H
CNTL EQU 83H
MOV DX, B82C55+3
MOV AL, CNTL
OUT DX, AL
MOV DX, B82C55+1
I N AL, DX
MOV DX, B82C55
OUT DX, AL
MOV DX, B82C55+2
I N AL, DX
AND AL, 0FH
MOV CL, 4
ROL AL, CL
OUT DX, AL
Basic Structure of Delay
Code for Delay
DELAY PROC NEAR
MOV CX, XXXX
D1:
LOOP D1
RET
DELAY ENDP
Finding Value for XXXX
p TimeForLoo
DelayTime
XXXX =
Example:
In pentium-4 system, loop requires 5 clocks.
And the clock rate is 2GHz. Let, T be Time
for Loop.
Since T=1/f sec
or T=1/(2x10
9
) sec
or T=5x10
-10
x10
9
ns
or T=0.5 ns
Therefore, Delay Time= 0.5x5 ns=2.5 ns
8-Digit LED Display Interfaced to
8088 Microprocessor through 82C55
Port-B provides logic-0 to select which LED will operate.
Port-A provides particular values for a selected LED.
Multiplexing 8-Digit LED Display
MOV AL, 80H
MOV DX, 703H
OUT DX, AL
DI SP PROC NEAR
PUSHF
MOV BX, 8
MOV AH, 7FH
MOV SI , OFFSET MEM- 1
MOV DX, 701H
. REPEAT
MOV AL, AH
OUT DX, AL
DEC DX
MOV AL, [ BX+SI ]
OUT DX, AL
CALL DELAY
ROR AH, 1
I NC DX
DEC BX
UNTI L BX==0
POPF
RET
DI SP ENDP
Suppose, 82C55 is interfaced to
microprocessor through PAL16L8
so that it functions at I/O port
0700H-0703H
Operation of a Stepper Motor
A stepper motor is a digital
motor as it moves in discrete
steps.
Figure(a) shows that the rotor
is repelled by the same pole
and moves a step to 45
o
.
Then it is attracted by the
different pole and moves
another step to 135
o
.
Thus it also moves
Upto 225
o
and 315
o
.
Interfacing Stepper Motor
through 82C55
# In order to flow high current through the coils, darlington amplifiers are used in stepper motor interfacing.
# Since a motor is an inductive load, it will produce a back EMF which could damage second transistor.
The single diode prevents the damage by sorting out the back EMF.
Controlling Stepper Motor
in its Full Step Operation
The following procedure controls the stepper motors full step operation
where the motor is interfaced to the port A (40H) of 82C55.
PORT EQU 40H
STEP PROC NEAR
MOV AL, POS
OR CX, CX
I F ! ZERO?
I F ! SI GN?
. REPEAT
ROL AL, 1
OUT PORT, AL
CALL DELAY
. UNTI L CXZ
ELSE
AND CX, 7FFFH
. REPEAT
ROR AL, 1
OUT PORT, AL
CALL DELAY
. UNTI L CXZ
ENDI F
ENDI F
MOV POS, AL
RET
STEP ENDP
Interfacing a 44 Key-Board
Port-A is programmed to read the rows while Port-B is programmed
to select a column. If 1110 is output to Port-B, column-0 has logic-1.
So the four keys of column-0 are selected. Now, if a key is pressed in
column-0, corresponding Port-A line can detect the stroke.
Electrical contacts in mechanical push button
switches often make and break contacts several
times when the button is first pushed. This is called
Debouncing.
A debouncing circuit removes the resulting ripple
signal and provides a clean transition to its output.
Mode-1 and Mode-2 Operation
of 82C55.
Mode-1 Strobed Input
Mode-1 Strobed Output
Mode-2 Bidirectional Input
Mode-1 Strobed Input
Mode-1 Strobed Output
Mode-2 Bidirectional Operation
Questions on Lecture Six
What does PPI stand for? Give a brief description of 82C55 PPI.
What are the operating modes of 82C55? Discuss in short.
Show the I/O port assignment of 82C55.
Show the content of command byte-A and command byte-B of 82C55.
What do you mean by control word? Discuss the basic structure of Delay.
Interface an 8-digit LED display to microprocessor through 82C55.
Write a procedure that multiplexes the 8-digit LED display where this
procedure must be called from a program at whenever possible to display
7-segement coded data from memory.
Explain the Full-Step Operation of a Stepper Motor. How is it interfaced to
Microprocessor?
What are the purposes of using Darlington Amplifiers in Stepper Motor
Interfacing? What does diode do here?
Write an assembly language program that controls the full-step operations
of a Stepper Motor.
Define Debouncing. Illustrate how a 4x4 keyboard can be interfaced
through 82C55 PPI.
Explain Mode-1 and Mode-2 operation of 82C55.
Course up to Mid-Term
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Mid-Term!
Course in Progress
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Lecture Seven
Interrupt
Defining Interrupts
An Interrupt is a hardware initiated procedure that
interrupts whatever program is currently executing by
the microprocessor and requests it to perform some
specific tasks.
Interrupts are particularly useful when interfacing I/O
devices that provide or require data at relatively low
data transfer rates.
Types of Interrupts
The Microprocessor has two types of interrupts-
Hardware Interrupts
Software Interrupts
Hardware Interrupts
Two pins are available for it- I NTR and NMI .
Software Interrupts
It can be caused by the commands like I NT, I NT0, I NT3
and BOUND.
Hardware Interrupts Revised
INTR
The INTR pin is level sensitive which means that it must be held at
logic-1 level until it is recognized. INTR is set by an external event and
cleared inside the interrupt service procedure. INTR is automatically
disabled once it is accepted by the microprocessor and re-enabled by
the IRET instruction at the end of the ISP.
NMI
NMI stands for Non-Maskable-Interrupt which is an edge triggered
input that requests an interrupt on the positive edge. After a positive
edge, the NMI pin must remain at logic-1 until it is recognized by the
microprocessor. Before the positive edge is recognized, the NMI pin
must be a logic-0 for at least two clocking periods.
The NMI is often used for parity errors and other major system faults
such as power failure.
Difference between RET and IRET
Instructions
RET instruction is used for hardware interrupts
but IRET is used for both hardware and
software interrupts.
RET only retrieves the return address from the
stack while IRET also retrieves a copy of flag
register from the stack.
Power Failure Detection by NMI
Converting INTR to Edge-
Triggered Interrupt Request
Questions on Lecture Seven
How will you define Interrupt? When interrupts are
useful?
Give a brief classification of Interrupts. Differentiate
between hardware interrupts and software interrupts.
Write short notes on INTR and NMI. Note down the basic
difference of them.
Differentiate between RET and IRET instructions.
With necessary sketch, briefly describe how NMI detects
power failure.
How can we make the INTR edge-triggered? Draw the
necessary circuit arrangement for this task.
Write down at least two specific interrupt names that are
performed by NMI.
Course in Progress
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Lecture Eight
Programmable Interrupt Controller
(8259)
Introduction and Importance
of 8259A PIC
The 8259A is a PIC. It is called a priority interrupt
controller because it can add eight vectored priority
encoded interrupts to the microprocessor.
The 8086 microprocessor has only two interrupt inputs-
INTR and NMI. As the microprocessor cannot avoid NMI,
only one interrupt (INTR) is left for all other applications.
To have interrupts from multiple sources, we need an
external device that helps to have multiple interrupts.
8259A is such a device that can assign priority to each
interrupt request and inform the microprocessor
accordingly.
Functional Block Diagram
of 8259A
Interfacing 8259A to
Microprocessor
Without any other additional
hardware, 8259A can be
expanded to accept up to 64
interrupt requests. But, for
this expansion, one master
8259A and eight slave 8259A
are required.
Command Words of 8259A
8259A is programmed by two command words called
Initialization Command Words (ICW) and Operation
Command Words (OCW).
ICWs are programmed before the 8259A is able to
function in the system and dictate the basic operations
of 8259A.
OCWs are programmed during the normal course of
operation and control the operations of 8259A.
Initialization order of ICWs
ICW1
ICW2
In Cascade
Mode?
ICW3
ICW4
Is ICW4
needed?
Ready to accept interrupt request
YES (SNGL=0)
NO
(SNGL=1)
YES (IC4=1)
NO
(IC4=0)
ICW1 is selected When A
0
=0
Other ICWs are selected when A
0
=1
For OCW1, A
0
=0.
But for all other OCWs, A
0
=1.
Describing ICW1
ICW1 programs the basic
operations of 8259A.
Describing ICW2
ICW2 selects the vector number used with the interrupt request input.
Describing ICW3
Master Device
Slave Device
ICW3 indicates where the slave
is connected to the master.
Describing ICW4
ICW4 is used with only
8086-Pentium
microprocessors.
Special Fully Nested Mode and
Automatic End of Interrupt
Special Fully Nested Mode
Selecting SFNM allows the highest priority interrupt
request from a slave to be recognized by the master
while processing another interrupt from a slave.
Automatic End of Interrupt
If it is selected, the interrupt automatically resets the
interrupt request bit and does not modify priority. It is
the preferred mode of operation for 8259A and reduces
the length of ISPs. If it is not selected, the EOI command
of OCW2 are used.
Describing OCW1
OCW1 is used to set and read the IMR. When a mask bit is set,
it will turn-off (mask) the corresponding interrupt input.
Describing OCW2
OCW2 selects
the way 859A
responds to
an Interrupt.
Describing OCW3
OCW3 selects the
register to be read,
the operation of the
special mask register
and the poll command.
PIC Terminologies
Non Specific End of Interrupt:
A command sent by the ISP to signal the end of interrupt. The 8259A automatically determines
which interrupt level was active and resets the correct bit of the interrupt status register.
Resetting the status bit allows the interrupt to take action again or a lower priority interrupt to
take effect.
Specific End of Interrupt:
A command that allows a specific interrupt request to be reset. The exact position is
determined with bits L
2
-L
0
of OCW2.
Rotate on Non Specific EOI:
It is similar to NSEOI except that it rotates interrupt priorities after resetting the interrupt
status register bit. If IR4 was first serviced by this command it becomes the lowest priority
interrupt input and IR5 becomes the highest priority.
Rotate on Specific EOI:
It is similar to specific EOI except that it selects rotating priority.
Rotate on Automatic EOI:
Selects automatic EOI with rotating priority. This command must be sent to 8259A once if this
mode is desired. If this mode must be turned off, use the clear command.
Set Priority:
Allows the programmer to set the lowest priority interrupt input using L
2
-L
0
bits.
Questions on Lecture Eight
Mention the importance of Programmable Interrupt
Controller. Why do we call it priority interrupt controller?
Draw the block diagram of 8259A and explain the task of each block.
How many internal registers does 8259A have? Mention their functionalities.
What do you mean by ICW and OCW? State each of their tasks.
How does 8259A handle master-slave interrupt control? Explain with appropriate
figure.
Write down the order of ICWs in which they should be initialized.
Write short notes on-
Automatic End of Interrupt
Special Fully Nested Mode
Non Specific End of Interrupt
Specific End of Interrupt
Rotate on NSEOI
Rotate on SEOI
Rotate on Automatic EOI
Set Priority
Course in Progress
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Lecture Nine
Programmable Interval Timer
(8254)
Purpose of Programmable
Interval Timer
The programmable interval timer is used in
personal computer for controlling real time
events such as real time clocks, events
counter, motor speed control and direction
control. It does the following works in a PC-
Generate a basic timer interrupt that occurs at
approximately 18.2 Hz.
Cause the DRAM memory system to be refreshed.
Provide a timing source to the internal speaker and
other device.
Internal Structure of 8254
Pin Definition of 8254
Gate input controls the operation of
the counter in some mode of operation.
Command Byte of 8254
Mode of Operation of 8254
8254 has three counters. Each counter can operate in any of six
available modes.
Mode-0: In this mode, 8254 counter can work as event counter. The output is zero until
n+count. If count=5, the out=0 for 6 counts beginning with n. G needs to be 1 in this
case.
Mode-1: In this mode, the counter functions as retriggerable monostable multivibrator.
When G triggers the count, the count generates logic-0 for the duration of count. If G is
triggered within a output pulse, the count is reloaded and out continues for the total
length.
Mode-2: In this mode, the counter can generate a series of continuous pulses. The
count determines the separation between pulses. For count=10, the out=1 for 9 clocking
periods and out=0 for 10
th
clock period.
Mode-3: It generates a continuous square wave if G=1. Here, out=1 for half of count
and out=0 for other half of count. But if count=5(odd), out=1 for 3 clock period and
out=0 for 2 clock period.
Mode-4: In this mode, counter produces a single pulse at output. If count=10, out=1 for
10 clocking period and out=0 for 1 clocking period. G must be 1.
Mode-5: It is similar to mode-4 except that G is triggered by hardware instead of
software.
Mode-0, Mode-1, Mode-2
Mode-3, Mode-4, Mode-5
Interfacing 8254 with
Microprocessor
Interface the 8254 so that it functions at I/O locations 0700H, 0702H, 0704H and
0706H. If the clock rate of the microprocessor is 8MHz, then write a procedure that
generates 100KHz square wave at OUT0 and 200KHz continuous pulse at OUT1.
Interfacing 8254 with
Microprocessor (continued)
80
10 100
10 8
100
8
3
6
=

=
KHz
MHz
40
10 200
10 8
200
8
3
6
=

=
KHz
MHz
Wave shaping by 8254
Program COUNTER 1 of 8254 so that it generates a
continuous series of pulses that have high time of
100 s and a low time of 1 s.
MOV AL, 74H
OUT CONTROL, AL
MOV AL, 65H
OUT TI MER1, AL
MOV AL, 0
OUT TI MER1, AL
100+1=101 s
101D=65H
COUNT=65H
DC Motor
Speed & Direction Control
When Q=1, Q
3
=ON, Q
2
=ON
Q
1
=OFF, Q
4
=OFF
When =1, Q
1
=ON, Q
4
=ON
Q
3
=OFF, Q
2
=OFF
If =1, motor rotates in reverse direction
If Q=1, motor rotates in forward direction
Timing for Motor Speed and
Direction Control
DC Motor
Speed & Direction Control
Questions on Lecture Nine
Why is Programmable Interval Timer used in personal computers?
What are its major tasks?
Draw the internal structure of 8254 and briefly mention each of
the blocks function.
Describe the command byte of 8254 with necessary sketch.
With details signals, mention the mode of operations of every
counter of 8254.
Interface an 8254 so that it functions at XX10H, XX12H, XX14H and
XX16H using operating frequency 8 MHz. Write a program that
programs COUNTER 2 to generate an 80 KHz square wave if the
CLK input to COUNTER 2 is 8MHz.
Draw the schematic diagram of DC Motor and its associative driver
circuitry including the correlation with the 8254 timer and Flip-
Flop. Briefly explain the operation of motor driver circuitry.
Explain the timing diagram of forward and reverse direction
rotation of a DC Motor.
Write a program that can control the speed and direction of a DC
Motor.
Course Ends
Microprocessor Basics
Memory Interface
Basic I/O Interface
Interrupts
Direct Memory Access Controller 8237
Programmable Peripheral Interface 82C55
Programmable Interval Timer 8254
Programmable Interrupt Controller 8259A
Parallel Printer Interface
Universal Serial Bus, PCI Bus, ISA Bus
NRZI Encoding Technique
Term Final !!!
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