Вы находитесь на странице: 1из 112

Experiment No: 1 LOGIC GATES

AIM:
To write a VHDL programs for Logic gates and simulate them by using !L!N "#$i %oft
ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity gates is
0ort 1 a : in %TD'L()!*&
b : in %TD'L()!*&
c2d2e2f2g2h2i : out %TD'L()!*3&
end gates&
architecture 4eha5ioral of gates is
begin
process1a2b3
begin
c67a and b&
d67a or b&
e67not a&
f67a nand b&
g67a nor b&
h67a xor b&
i67a xnor b&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
a b c=a.b d=ab !=a" #=(a.b)
"
$=(ab)
"
%=a &'( b )=a*b
+ + + , , , + + ,
+ , + , , , + , +
, + + , + , + , +
, , , + + + , + ,
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL programs for Logic gates are written and simulated by using L!N"#$i 5ersion and the
(utputs are 5erified#
Experiment No: $1a3 HALF ADDER
AIM:
To write a VHDL program for Half adder and simulate them by using !L!N "#$i %oft
ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity half is
0ort 1 a2b : in %TD'L()!*&
s2c : out %TD'L()!*3&
end half&
architecture 4eha5ioral of half is
begin
process1a2b3
begin
s67a xor b&
c67a and b&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:


RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
a b - c
+ + + +
+ , , +
, + , +
, , + ,
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for Half adder is written and simulated by using L!N"#$i 5ersion and the
(utputs are 5erified#
Experiment No: $1b3 FULL ADDER
AIM:
To write a VHDL program for ;ull adder and simulate them by using !L!N "#$i %oft
ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity full is
0ort 1 a2b2cin : in %TD'L()!*&
s2cout : out %TD'L()!*3&
end full&
architecture 4eha5ioral of full is
begin
process1a2b2cin3
begin
if1cin7EDE3 then
s67a xor b&
c67a and b&
else
s67a xnor b&
c67a or b&
end if&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
a b c). - c'/0
+ + + + +
+ + , , +
+ , + , +
+ , , + ,
, + + , +
, + , + ,
, , + + ,
, , , , ,
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for full adder is written and simulated by using L!N"#$i 5ersion and the
(utputs are 5erified#
Experiment No: $1c3 CARR1 LOOK AHEAD ADDER
AIM:
To write a VHDL program for *arry loo8 ahead adder and simulate them by using !L!N
"#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity adder is
0ort 1 a2b : in %TD'L()!*'VE*T(. 1= downto D3&
cin : in %TD'L()!*&
s : out %TD'L()!*'VE*T(. 1= downto D3&
cout : out %TD'L()!*3&
end adder&
architecture 4eha5ioral of adder is
%!)N-L c: %TD'L()!*'VE*T(. 1, D(BNT( D3&
%!)N-L p: %TD'L()!*'VE*T(. 1= D(BNT( D3&
%!)N-L g: %TD'L()!*'VE*T(. 1= D(BNT( D3&
4E)!N
)1: ;(. i !N D T( = )ENE.-TE
p1i3 67 a1i3 (. b1i3&
g1i3 67 a1i3 -ND b1i3&
s1i3 67 p1i3 (. c1i3&
END )ENE.-TE&
c1D3 67 cin&
c113 67 1cin -ND p1D33 (. g1D3&
c1$3 67 1cin -ND p1D3 -ND p1133 (. 1g1D3 -ND p1133 (. g113&
c1=3 67 1cin -ND p1D3 -ND p113 -ND p1$33 (. 1g1D3 -ND p113 -ND p1$33 (. 1g113 -ND p1$33 (.
g1$3&
c1,3 67 1cin -ND p1D3 -ND p113 -ND p1$3 -ND p1=33 (. 1g1D3 -ND p113 -ND p1$3 -ND p1=33 (.
1g113 -ND p1$3 -ND p1=33 (. 1g1$3 -ND p1=33 (. g1=3&
cout 67 c1,3&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for *arry loo8 a head adder is written and simulated by using L!N"#$i
5ersion and the (utputs are 5erified#
Experiment No: $1d3 RIPPLE ADDER
AIM:
To write a VHDL program for .ipple adder and simulate them by using !L!N "#$i %oft
ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity adder is
0ort 1 a2b : in %TD'L()!*'VE*T(. 1= downto D3&
cin : in %TD'L()!*&
s : out %TD'L()!*'VE*T(. 1= downto D3&
cout : out %TD'L()!*3&
end adder&
architecture 4eha5ioral of adder is
%!)N-L c: %TD'L()!*'VE*T(. 1, D(BNT( D3&
begin
process1a2b2cin2c3
begin
c1D367cin&
;(. i !N D T( = loop
s1i367a1i3 xor b1i3 xor c1i3&
c1iF13671a1i3 and b1i33 or 1c1i3 and 1a1i3 xor b1i333&
end loop&
cout 67 c1,3&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for .ipple adder is written and simulated by using L!N"#$i 5ersion and the
(utputs are 5erified#
Experiment No: =1a3 2 TO 3 DECODER
AIM:
To write a VHDL program for $ to , Decoder and simulate it by using !L!N"#$i %oft
ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity dc1 is
0ort 1 en : in %TD'L()!*&
x : in %TD'L()!*'VE*T(. 11 downto D3&
y : out %TD'L()!*'VE*T(. 1= downto D33&
end dc1&
architecture 4eha5ioral of dc1 is
begin
process1en2x3
begin
if en7GDG then y67HDDDDH&
else
case x is
when HDDH7<y67HDDD1H&
when HD1H7<y67HDD1DH&
when H1DH7<y67HD1DDH&
when H11H7<y67H1DDDH&
when others7<null&
end case&
end if&
end process&end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
!. 4, 4+ 15 12 1, 1+
+ & & + + + +
, + + + + + ,
, + , + + , +
, , + + , + +
, , , , + + +
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for $ to , Decoder is written and simulated by using L!N"#$i 5ersion and
the (utputs are 5erified#
Experiment No:=1b3 5 TO 6 DECODER
AIM:
To write a VHDL program for = to C Decoder and simulate it by using !L!N"#$i %oft
ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity dc1 is
0ort 1 en : in %TD'L()!*&
x : in %TD'L()!*'VE*T(. 1$ downto D3&
y : out %TD'L()!*'VE*T(. 1A downto D33&
end dc1&
architecture 4eha5ioral of dc1 is
begin
process1en2x3
begin
if en7GDG then y67HDDDDDDDDH&
else
case x is
when HDDDH7<y67HDDDDDDD1H&
when HDD1H7<y67HDDDDDD1DH&
when HD1DH7<y67HDDDDD1DDH&
when HD11H7<y67HDDDD1DDDH&
when H1DDH7<y67HDDD1DDDDH&
when H1D1H7<y67HDD1DDDDDH&
when H11DH7<y67HD1DDDDDDH&
when H111H7<y67H1DDDDDDDH&
when others7<null&
end case&
end if&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
!. 42 4, 4+ 17 18 19 13 15 12 1, 1+
+ & & & + + + + + + + +
, + + + + + + + + + + ,
, + + , + + + + + + , +
, + , + + + + + + , + +
, + , , + + + + , + + +
, , + + + + + , + + + +
, , + , + + , + + + + +
, , , + + , + + + + + +
, , , , , + + + + + + +
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for = to C Decoder is written and simulated by using L!N"#$i 5ersion and the
(utput is 5erified#
Experiment No: =1c3 7:SEGMENT DECODER
AIM:
To write a VHDL program for AI%egment Decoder and simulate it by using !L!N"#$i %oft
ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
ENT!TJ 4*D$LED !%
0(.T 1D:!N %TD'L()!*'VE*T(.1= D(BNT( D3&
(:(/T %TD'L()!*'VE*T(.1+ D(BNT( D33&
END 4*D$LED&
-.*H!TE*T/.E .TL (; 4*D$LED !%
4E)!N
0.(*E%% 1D3
4E)!N
*-%E D !%
BHEN HDDDDH7<(67H111111DH&
BHEN HDDD1H7<(67HD11DDDDH&
BHEN HDD1DH7<(67H11D11D1H&
BHEN HDD11H7<(67H1111DD1H&
BHEN HD1DDH7<(67HD11DD11H&
BHEN HD1D1H7<(67H1D11D11H&
BHEN HD11DH7<(67HD11111H&
BHEN HD111H7<(67H111DDDDH&
BHEN H1DDDH7<(67H1111111H&
BHEN H1DD1H7<(67H111D11H&
BHEN (THE.%7<(67HH&
END *-%E&
END 0.(*E%%&
END .TL&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
D5 D2 D, D+ O8 O9 O3 O5 O2 O, O+
+ + + + , , , , , , +
+ + + , , , + + + + +
+ + , + , , + , , + ,
+ + , , , , , , + + ,
+ , + + + , , + + , ,
+ , + , , + , , + , ,
+ , , + & + , , , , ,
, , , , , , , + + + +
, + + + , , , , , , ,
, + + , , , , & + , ,
, + , + & & & & & & &
, + , , & & & & & & &
, , + + & & & & & & &
, , + , & & & & & & &
, , , + & & & & & & &
, , , , & & & & & & &
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for AI%egment Decoder is written and simulated by using L!N"#$i 5ersion
and the (utput is 5erified#
Experiment No: ,1b3 64, MULTIPLE4ER
AIM:
To write a VHDL program for C1 Kultiplexer and simulate it by using !L!N"#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity mul1 is
0ort 1 sel : in %TD'L()!*'VE*T(. 1$ downto D3&
x : in %TD'L()!*'VE*T(. 1A downto D3&
y : out %TD'L()!*3&
end mul1&
architecture 4eha5ioral of mul1 is
begin
process1sel2x3
begin
case sel is
when HDDDH7<y67x1D3&
when HDD1H7<y67x113&
when HD1DH7<y67x1$3&
when HD11H7<y67x1=3&
when H1DDH7<y67x1,3&
when H1D1H7<y67x1@3&
when H11DH7<y67x1+3&
when H111H7<y67x1A3&
when others7<null&
end case&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
-!;2 -!;, -!;+ 47 48 49 43 45 42 4, 4+ 1
+ + + + + + + + + + , 4+
+ + , + + + + + + , + 4,
+ , + + + + + + , + + 42
+ , , + + + + , + + + 45
, + + + + + , + + + + 43
, + , + + , + + + + + 49
, , + + , + + + + + + 48
, , , , + + + + + + + 47
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for C1 Kultiplexer is written and simulated by using L!N"#$i 5ersion and
the (utput is 5erified#
Experiment No: ,1a3 34, MULTIPLE4ER
AIM:
To write a VHDL program for ,1 Kultiplexer and simulate it by using !L!N"#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity mul1 is
0ort 1 sel : in %TD'L()!*'VE*T(. 11 downto D3&
x : in %TD'L()!*'VE*T(. 1, downto D3&
y : out %TD'L()!*3&
end mul1&
architecture 4eha5ioral of mul1 is
begin
process1sel2x3
begin
case sel is
when HDDH7<y67x1D3&
when HD1H7<y67x113&
when H1DH7<y67x1$3&
when H11H7<y67x1=3&
when others7<null&
end case&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
-!;, -!;+ 45 42 4, 4+ 1
+ + + + + , 4+
+ , + + , + 4,
, + + , + + 42
, , , + + + 45
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for ,1 Kultiplexer is written and simulated by using L!N"#$i 5ersion and
the (utput is 5erified#
Experiment No: ,1c3 ,84, MULTIPLE4ER
AIM:
To write a VHDL program for 1+1 Kultiplexer and simulate it by using !L!N"#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity mul1 is
0ort 1 sel : in %TD'L()!*'VE*T(. 1= downto D3&
x : in %TD'L()!*'VE*T(. 11@ downto D3&
y : out %TD'L()!*3&
end mul1&
architecture 4eha5ioral of mul1 is
begin
process1sel2x3
begin
case sel is
when HDDDDH7<y67x1D3&
when HDDD1H7<y67x113&
when HDD1DH7<y67x1$3&
when HDD11H7<y67x1=3&
when HD1DDH7<y67x1,3&
when HD1D1H7<y67x1@3&
when HD11DH7<y67x1+3&
when HD111H7<y67x1A3&
when H1DDDH7<y67x1C3&
when H1DD1H7<y67x1"3&
when H1D1DH7<y67x11D3&
when H1D11H7<y67x1113&
when H11DDH7<y67x11$3&
when H11D1H7<y67x11=3&
when H111DH7<y67x11,3&
when H1111H7<y67x11@3&
when others7<null&
end case&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
-!;5 -!;2 -!;, -!;+ <
+ + + + 4+
+ + + , 4,
+ + , + 42
+ + , , 45
+ , + + 43
+ , + , 49
+ , , + 48
, , , , 47
, + + + 46
, + + , 4=
, + , + 4,+
, + , , 4,,
, , + + 4,2
, , + , 4,5
, , , + 4,3
, , , , 4,9
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for 1+1 multiplexer is written and simulated by using L!N"#$i 5ersion and
the (utput is 5erified#
Experiment No: @1c3 ,43 DE:MULTIPLE4ER
AIM:
To write a VHDL program for 1, DeIKultiplexer and simulate it by using !L!N"#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity dem1 is
0ort 1 sel : in %TD'L()!*'VE*T(. 11 downto D3&
x : in %TD'L()!*&
y : out %TD'L()!*'VE*T(. 1= downto D33&
end dem1&
architecture 4eha5ioral of dem1 is
begin
process1x2sel3
begin
y67HDDDDH&
case sel is
when HDDH7<y1D367x&
when HD1H7<y11367x&
when H1DH7<y1$367x&
when H11H7<y1=367x&
when others7<null&
end case&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
-!;, -!;+ 4 15 12 1, 1+
+ + A + + + A
+ , A + + A +
, + A + A + +
, , A A + + +
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL programs for 1, DeImultiplexer is written and simulated by using L!N"#$i 5ersion
and the (utput is 5erified#
Experiment No: @1b3 ,46 DE:MULTIPLE4ER
AIM:
To write a VHDL program for 1C DeIKultiplexer and simulate it by using !L!N"#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity dem1 is
0ort 1 sel : in %TD'L()!*'VE*T(. 1$ downto D3&
x : in %TD'L()!*&
y : out %TD'L()!*'VE*T(. 1A downto D33&
end dem1&
architecture 4eha5ioral of dem1 is
begin
process1x2sel3
begin
y67HDDDDDDDDH&
case sel is
when HDDDH7<y1D367x&
when HDD1H7<y11367x&
when HD1DH7<y1$367x&
when HD11H7<y1=367x&
when H1DDH7<y1,367x&
when H1D1H7<y1@367x&
when H11DH7<y1+367x&
when H111H7<y1A367x&
when others7<null&
end case&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
-!;2 -!;, -!;+ 4 17 18 19 13 15 12 1, 1+
+ + + A + + + + + + + A
+ + , A + + + + + + A +
+ , + A + + + + + A + +
+ , , A + + + + A + + +
, + + A + + + A + + + +
, + , A + + A + + + + +
, , + A + A + + + + + +
, , , A A + + + + + + +
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL programs for 1C DeImultiplexer is written and simulated by using L!N"#$i 5ersion
and the (utput is 5erified#
Experiment No: @1a3 ,4,8 DE:MULTIPLE4ER
AIM:
To write a VHDL program for 11+ DeIKultiplexer and simulate it by using !L!N"#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity dem is
0ort 1 sel : in %TD'L()!*'VE*T(. 1= downto D3&
x : in %TD'L()!*&
y : out %TD'L()!*'VE*T(. 11@ downto D33&
end dem&
architecture 4eha5ioral of dem is
begin
process1x2sel3
begin
y67HDDDDDDDDDDDDDDDDH&
case sel is
when HDDDDH7<y1D367x&
when HDDD1H7<y11367x&
when HDD1DH7<y1$367x&
when HDD11H7<y1=367x&
when HD1DDH7<y1,367x&
when HD1D1H7<y1@367x&
when HD11DH7<y1+367x&
when HD111H7<y1A367x&
when H1DDDH7<y1C367x&
when H1DD1H7<y1"367x&
when H1D1DH7<y11D367x&
when H1D11H7<y111367x&
when H11DDH7<y11$367x&
when H11D1H7<y11=367x&
when H111DH7<y11,367x&
when H1111H7<y11@367x&
when others7<null&
end case&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
-!;
5
-!;
2
-!;
,
-!;
+
4 1
,9
1
,3
1
,5
1
,2
1
,,
1
,+
1
=
1
6
1
7
1
8
1
9
1
3
1
5
1
2
1
,
1+
+ + + + A + + + + + + + + + + + + + + + A
+ + + , A + + + + + + + + + + +
+
+ + A +
+ + , + A + + + + + + + + + + + + + A + +
+ + , , A + + + + + + + + + + + + A + + +
+ , + + A + + + + + + + + + + + A + + + +
+ , + , A + + + + + + + + + + A + + + + +
+ , , + A + + + + + + + + + A + + + + + +
+ , , , A + + + + + + + + A + + + + + + +
, + + + A + + + + + + + A + + + + + + + +
, + + , A + + + + + + A + + + + + + + + +
, + , + A + + + + + A + + + + + + + + + +
, + , , A + + + + A + + + + + + + + + + +
, , + + A + + + A + + + + + + + + + + + +
, , + , A + + A + + + + + + + + + + + + +
, , , + A + A + + + + + + + + + + + + + +
, , , , A A + + + + + + + + + + + + + + +
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL programs for 11+ DeImultiplexer is written and simulated by using L!N"#$i 5ersion
and the (utput is 5erified#
Experiment No: +1a3 D:FLIPFLOP
AIM:
To write a VHDL program for DI;L!0 ;L(0 and simulate it by using !L!N"#$i %oftware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity dff1 is
0ort 1 cl8 : in %TD'L()!*&
d : in %TD'L()!*&
L1 : out %TD'L()!*&
L$ : out %TD'L()!*3&
end dff1&
architecture 4eha5ioral of dff1 is
begin
process1d2cl83
begin
if1d7GDGand cl87G1G3 then
L167GDG&
L$67G1G&
else if1d7G1G and cl87G1G3 then
L167G1G&
L$67GDG&
end if&
end if&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
cl8 d M1 M$
D / /
1 D D 1
1 1 1 D
D M
D
M
D
E
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for DI;L!0;L(0 is written and simulated by using L!N"#$i 5ersion and the
(utput is 5erified#
Experiment No: +1b3 >K:FLIPFLOP
AIM:
To write a VHDL program for NOI;L!0 ;L(0 and simulate it by using !L!N"#$i %oftware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity NO;L!0;L(01 is
0ort 1 N : in std'logic&
O : in std'logic&
*LO : in std'logic&
M : inout std'logic&
MN : inout std'logic3&
end NO;L!0;L(01&
architecture 4eha5ioral of NO;L!0;L(01 is
begin
process1*LO2N2O3
begin
if 1*LO7G1G and *LOGe5ent3 then
if1N7GDG and O7GDG3 then
M 67M&
MN 67MN&
elsif1N7GDG and O7G1G3 then
M 67 G1G&
MN 67 GDG&
elsif1N7G1G and O7GDG3 then
M 67 GDG&
MN 67 G1G&
elsif1N7G1G and O7G1G3 then
M 67 N(T M&
MN 67 N(T MN&
end if&
end if&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
N O M
nF1
D D M
n
D 1 D
1 D 1
1 1 M
n
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for NOI;L!0;L(0 is written and simulated by using L!N"#$i 5ersion and the
(utput is 5erified#
Experiment No: +1c3 T:FLIPFLOP
AIM:
To write a VHDL program for TI;L!0 ;L(0 and simulate it by using !L!N"#$i %oftware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#all&
entity tff is
port1cl8: in std'logic&
reset: in std'logic&
t: in std'logic&
L: out std'logic3&
end tff&
architecture beha5e of tff is
signal L'reg: std'logic&
signal L'next: std'logic&
begin
process1cl83
begin
if 1reset 7 G1G3 then
L'reg 67 GDG&
elsif 1cl8Ge5ent and cl8 7 G1G3 then
L'reg 67 L'next&
end if&
end process&
L'next 67 L'reg when t 7 GDG else
not1L'reg3&
L 67 L'reg&
end beha5e&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
T M ME
D 1 D
1 D 1
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for TI;L!0;L(0 is written and simulated by using L!N"#$i 5ersion and the
(utput is 5erified#
Experiment No: +1d3 RS:FLIPFLOP
AIM:
To write a VHDL program for .%I;L!0 ;L(0 and simulate it by using !L!N"#$i
%oftware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library ieee&
use ieee#std'logic'11+,#all&
entity be:oy'rsff is
port1s2r2cl8:in std'logic&L2L12P:inout std'logic3&
end be:oy'rsff&
architecture arc of be:oy'rsff is
begin
process1cl83
begin
if cl87G1G then
P67s or 11not r3 and L3&
L67P after @ns&
L167not P after @ns&
end if&
end process&
end arc&
BLOCK DIAGRAM:


RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
% . M
nF1
D D M
n
D 1 D
1 D 1
1 1
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for .%I;L!0;L(0 is written and simulated by using L!N"#$i 5ersion and the
(utput is 5erified#
Experiment No: A 3:BIT COMPARATOR
AIM:
To write a VHDL program for ,I4it *omparator and simulate it by using !L!N"#$i
%oftware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity compare is
0ort 1 -24 : in %TD'L()!*'VE*T(. 1= downto D3&
EM2NE2)T2)E2LT2LE : out %TD'L()!*3&
end compare&
architecture 4eha5ioral of compare is
begin
process1-243
begin
EM67GDG&NE67GDG&)T67GDG&)E67GDG&LT67GDG&LE67GDG&
if - 7 4 then EM67G1G&end if&
if - Q7 4 then NE67G1G&end if&
if - < 4 then )T67G1G&end if&
if - <7 4 then )E67G1G&end if&
if - 6 4 then LT67G1G&end if&
if - 67 4 then LE67G1G&end if&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
COMPARING INPUTS OUTPUTS
A5?B5 A2?B2 A,?B, A+?B+ A@B AAB A=B
A5@B5 4 4 4 , + +
A5AB5 4 4 4 + , +
A5=B5 A2@B2 4 4 , + +
A5=B5 A2AB2 4 4 + , +
A5=B5 A2=B2 A,@B, 4 , + +
A5=B5 A2=B2 A,AB, 4 + , +
A5=B5 A2=B2 A,=B, A+@B+ , + +
A5=B5 A2=B2 A,=B, A+AB+ + , +
A5=B5 A2=B2 A,=B, A+=B+ + + ,
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for ,I4it comparator is written and simulated by using L!N"#$i 5ersion and
the (utput is 5erified#
Experiment No: C1a3 DECADE COUNTER
AIM:
To write a VHDL program for Decade *ounter and simulate it by using !L!N"#$i
%oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity *ounter is
port 1cl8: in %TD'L()!*&
reset: in %TD'L()!*&
L: out %TD'L()!* 'VE*T(.1= downto D3 3&
end *ounter&
architecture 4eha5ioural of *ounter is
begin
process1cl82reset3
5ariable Ltemp: std'logic'5ector1= downto D3&
begin
if reset7G1G then
Ltemp:7HDDDDH&
else
if cl87G1G then
if Ltemp6" then
Ltemp:7LtempF1&
else
Ltemp:7HDDDDH&
end if&
end if&
L67Ltemp&
end if&
end process&
end 4eha5ioural&

BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
*(/NT
(/T0/T%
M
D
M
*
M
4
M
-
D D D D D
1 D D D 1
$ D D 1 D
= D D 1 1
, D 1 D D
@ D 1 D 1
+ D 1 1 D
A D 1 1 1
C 1 D D D
" 1 D D 1
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section
below#
,# The next step in creating the new source is to add the beha5ioral description for the
program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the
functionality of the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for Decade *ounter is written and simulated by using L!N"#$i
5ersion and the (utput is 5erified#
Experiment No: C1b3 S1NCHRONOUS COUNTER
AIM:
To write a VHDL program for %ynchronous *ounter and simulate it by using !L!N "#$i
%oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity count1 is
0ort 1 *L(*O : in %TD'L()!*&
D!.E*T!(N : in %TD'L()!*&
*(/NT : out %TD'L()!*'VE*T(. 1= downto D33&
end count1&
architecture 4eha5ioral of count1 is
signal count'int : std'logic'5ector1= downto D3 :7 HDDDDH&
begin
process 1*L(*O3
begin
if *L(*O7G1G and *L(*OGe5ent then
if count'int 6 H1111H then
count'int 67 count'int F 1&
else
count'int67HDDDDH&
end if&
end if&
end process&
*(/NT 67 count'int&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
*(/NT
(/T0/T%
M
D
M
*
M
4
M
-
D D D D D
1 D D D 1
$ D D 1 D
= D D 1 1
, D 1 D D
@ D 1 D 1
+ D 1 1 D
A D 1 1 1
C 1 D D D
" 1 D D 1
1D 1 D 1 D
11 1 D 1 1
1$ 1 1 D D
1= 1 1 D 1
1, 1 1 1 D
1@ 1 1 1 1
D D D D D
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for %ynchronous *ounter is written and simulated by using L!N"#$i 5ersion
and the (utput is 5erified#
Experiment No: "1a3 SHIFT REGISTERS
AIM:
To write a VHDL program for %hift .egister and simulate it by using !L!N "#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity shift is
0ort 1 *2%! : in %TD'L()!*&
%( : out %TD'L()!*3&
end shift&
architecture 4eha5ioral of shift is
signal tmp: std'logic'5ector1A downto D3&
begin
process 1*3
begin
if 1*Ge5ent and *7G1G3 then
for i in D to + loop
tmp1iF13 67 tmp1i3&
end loop&
tmp1D3 67 %!&
end if&
end process&
%( 67 tmp1A3&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for %hift .egister is written and simulated by using L!N"#$i 5ersion and the
(utput is 5erified#
Experiment No: "1b3 UNIVERSAL SHIFT REGISTERS
AIM:
To write a VHDL program for /ni5ersal %hift .egister and simulate it by using !L!N "#$i %oft
ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity uni51 is
0ort 1 D : in %TD'L()!*'VE*T(. 1= downto D3&
*LO2.%T : in %TD'L()!*&
%!.2%!L : in %TD'L()!*&
% : in %TD'L()!*'VE*T(. 11 downto D3&
M : out %TD'L()!*'VE*T(. 1= downto D33&
end uni51&
architecture 4eha5ioral of uni51 is
begin
process1*LO2 .%T3 is
5ariable .E) : std'logic'5ector1= downto D3&
begin
if 1.%T 7 GDG3 then
.E) :7 1others 7< GDG3&
elsif rising'edge1cl83 then
case % is
when H11H 7<
.E) :7 D&
when HD1H 7<
.E) :7 %!. R .E)1= downto 13&
when H1DH 7<
.E) :7 .E)1$ downto D3 R %!L&
when others 7<null&
end case&
end if&
M 67 .E)&
end process&
end 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORMS (AFTER SIMULATION):
TRUTH TABLE:
RESET S, S+ CLOCK SIL SIR da0a B
A
B
B
B
C
B
D
A B C D
D D D D D
1 D M
-D
M
4D
M
*D
M
DD
1 1 1 1 a b c d a b c d
1 D 1 1 a a M
-N
M
4N
M
*N
1 1 D 1 a M
4N
M
*N
M
DN
a
1 D D M
-D
M
4D
M
*D
M
DD
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for /ni5ersal %hift .egister is written and simulated by using L!N"#$i
5ersion and the (utput is 5erified#
Experiment No: "
3:BIT COUNTER
AIM:
To write a VHDL program for ,I4it *ounter and simulate it by using !L!N "#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#%TD'L()!*'-.!TH#-LL&
use !EEE#%TD'L()!*'/N%!)NED#-LL&
entity count1 is
0ort 1 *L(*O : in %TD'L()!*&
D!.E*T!(N : in %TD'L()!*&
*(/NT : out %TD'L()!*'VE*T(. 1= downto D33&
end count1&
architecture 4eha5ioral of count1 is
signal count'int : std'logic'5ector1= downto D3 :7 HDDDDH&
begin
process 1*L(*O3
begin
if *L(*O7G1G and *L(*OGe5ent then
if count'int 6 H1111H then
count'int 67 count'int F 1&
else
count'int67HDDDDH&
end if&
end if&
end process&
*(/NT 67 count'int&
end 4eha5ioral&
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for ,I4it *ounter is written and simulated by using L!N"#$i 5ersion and the
(utput is 5erified#
Experiment No: 1D ALU DESIGN
AIM:
To write a VHDL program for -rithmetic and Logic /nit and simulate it by using !L!N
"#$i %oft ware#
SOFTWARE:
1#!L!N "#$i
$#!%E %imulator
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
use !EEE#N/KE.!*'%TD#-LL&
entity alu is
port
1
!nput12 !nput$ : in std'logic'5ector1= downto D3&
(peration : in std'logic'5ector1$ downto D3&
;lag : out std'logic&
.esult : out std'logic'5ector1= downto D3
3&
end entity alu&
architecture 4eha5ioral of alu is
signal Temp: std'logic'5ector1, downto D3&
begin
process1!nput12 !nput$2 (peration2 temp3 is
begin
;lag 67 GDG&
case (peration is
when HDDDH 7< II res 7 in1 F in$2 flag 7 carry 7 o5erflow
Temp 67 1unsigned1HDH R !nput13 F unsigned1!nput$33&
.esult 67 temp1= downto D3&
;lag 67 temp1,3&
when HDD1H 7< II res 7 Sin1 I in$S2 flag 7 1 if in$ < in1
if 1!nput1 <7 !nput$3 then
.esult 67 1unsigned1!nput13 I unsigned1!nput$33&
;lag 67 GDG&
else
.esult 67 1unsigned1!nput$3 I unsigned1!nput133&
;lag 67 G1G&
end if&
when HD1DH 7<
.esult 67 !nput1 and !nput$&
when HD11H 7<
.esult 67 !nput1 or !nput$&
when H1DDH 7<
.esult 67 !nput1 xor !nput$&
when H1D1H 7<
.esult 67 not !nput1&
when H11DH 7<
.esult 67 not !nput$&
when others 7< II res 7 in1 F in$ F 12 flag 7 D
Temp 67 1unsigned1HDH R !nput133 F 1unsigned1not !nput$3 F 13&
.esult 67 temp1= downto D3&
;lag 67 temp1,3&
end case&
end process&
end architecture 4eha5ioral&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for -rithmetic and Logic /nit is written and simulated by using L!N"#$i
5ersion and the (utput is 5erified#
Experiment No: 11 MEAL1 MACHINE
AIM:
To write a VHDL program for Kealy machine and simulate it by using !L!N "#$i %oft
ware#
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
entity mealy is
0ort 1 rst2cl82w : in %TD'L()!*&
P : out %TD'L()!*3&
end mealy&
architecture beha5ioral of Kealy is type state'type is 1a2b2c3&
signal y'present2y'next:state'type&
begin
process1w2y'present3
begin
case y'present is
when a7<
if w7GDG then
y'next67a&
else
y'next67b&
end if&
when b7<
if w7GDG then
y'next67a&
else
y'next67c&
end if&
when c7<
if w7GDG then
y'next67a&
else

y'next67c&
end if&
end case&
end process&
process1cl82rst3
begin
if rst7GDG then y'present67a&
elsif1cl8Ge5ent and cl87G1G3then y'present67 y'next&
end if&
end process&
P67G1G when y'present 7c else GDG&
end 4eha5ioral&
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
11#(pen !mplement design tool to physical layouts for our modified design#
RESULT:
The VHDL program for Kealy machine is written and simulated by using L!N"#$i 5ersion and the
(utput is 5erified#
Experiment No: 1$ MOORE MACHINE
AIM:
To write a VHDL program for Koore machine and simulate it by using !L!N "#$i %oft
ware#
PROGRAM:
library !EEE&
use !EEE#%TD'L()!*'11+,#-LL&
entity moore is
0ort 1 cloc82reset2w : in %TD'L()!*&
P : out %TD'L()!*3&
end moore&
architecture 4eha5ioral of moore is type state'type is 1a2b2c3&
signal y:state'type&
begin
process1reset2cloc83
begin
if reset7GDG then y67a&
elsif 1cloc8Ge5ent and cloc87G1G3 then
case y is
when a7<
if w7GDG then y67a&
else y67b&
end if&
when b7<
if w7GDG then y67a&
else y67c&
end if&
when c7<
if w7GDG then y67a&
else y67c&
end if&
end case&
end if&
end process&
P67G1G when y 7 c else GDG&
end 4eha5ioral&
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for Koore machine is written and simulated by using L!N"#$i 5ersion and
the (utput is 5erified#
Experiment No: 1= SUBTRACTOR
AIM:
To write a VHDL program for %ubtractor and simulate it by using !L!N "#$i %oft ware#
PROGRAM:
library ieee&
use ieee#std'logic'11+,#all&
II entity
entity fullsub is
port 1 a2b2c: in std'logic&
diff2borrow : out std'logic3&
end fullsub&
architecture ob: of fullsub is
begin
diff67 a xor b xor c&
borrow 67 1c and 1not1a xor b333or 11not a3 and b3&
end ob:&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for %ubtractor is written and simulated by using L!N"#$i 5ersion and the
(utput is 5erified#
Experiment No: 1, PRIORIT1 ENCODER
AIM:
To write a VHDL program for 0riority encoder and simulate it by using !L!N "#$i %oft
ware#
PROGRAM:
L!4.-.J ieee&
/%E ieee#std'logic'11+,#all&
/%E ieee#std'logic'arith#all&
ENT!TJ pri'enc !%
port1a2b2c2d:in std'logic&
s:out std'logic'5ector11 downto D33&
END ENT!TJ pri'enc&
architecture pr'en of pri'enc is
begin
process1a2b2c3
begin
if a7G1G then
s67HDDH&
elsif b7G1G then
s67HD1H&
elsif c7G1G then
s67H1DH&
else s67H11H&
end if&
end process&
end pr'en&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for 0riority encoder is written and simulated by using L!N"#$i 5ersion and
the (utput is 5erified#
Experiment No: 1@ READ ONL1 MEMOR1
AIM:
To write a VHDL program for .(K and simulate it by using !L!N "#$i %oft ware#
PROGRAM:
L!4.-.J !EEE&
/%E !EEE#%TD'L()!*'11+,#-LL&
/%E !EEE#%TD'L()!*'-.!TH#-LL&
/%E !EEE#%TD'L()!*'/N%!)NED#-LL&
Entity rom'using'constant is
port1read'en:in std'L()!*&
address:in %TD'L()!*1= downto D3&
data:out %TD'L()!*'VE*T(.1A downto D3&
end entity &
architecture beha5iour of rom'using'constant is
subtype .(K'word is std'logic'5ector1A downto D3&
subtype .(K'addr is integer range D to 1@&
type .(K is array1.(K'addr3of .(K'word&
constant .(K'table:
.(K:71con5'std'logic'5ector11D2C32
con5'std'logic'5ector1@@2C32
con5'std'logic'5ector1$,,2C32
HDDDDDDDDH2
con5'std'logic'5ector112C3
xHffH2
xH11H2
xHD1H2
xH1DH2
xHDDH2
xH1DH2
xH1@H2
xH+DH2
xHADH2
xH"DH2
xHDDH32
begin
process1read'en2adress3 begin
if1read'en 7G1G3then
data67.(K'table1con5Iinteger1address33&
end if&
end process&
end architecture&
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1#%tart the ilinx !%E software by Double clic8ing on the !con or
%tart 9 -ll 0rograms 9 ilinx !%E "#$i 9 0ro:ect Na5igator
$#*reate a new pro:ect by %electing ;ile < New 0ro:ect###
=# *reate a VHDL source file2 then2 continue either to the >*reating a VHDL %ource? section below#
,# The next step in creating the new source is to add the beha5ioral description for the program#
@#0lace the cursor :ust below the begin statement within the program architecture#
+# %a5e the file by selecting ;ile 9 %a5e#
A#Bhen the source files are complete2 chec8 the syntax of the design to find errors and types#
C#Verify the ;unctionality using 4eha5ioral %imulation#
"#*reate a test bench wa5eform containing input stimulus you can use to 5erify the functionality of
the program module#
1D# %a5e the wa5eform#
RESULT:
The VHDL program for .(K is written and simulated by using L!N"#$i 5ersion and the (utput is
5erified#
Experiment No: 1+ VERILOG PROGRAMS
AIM:
To write a Verilog code for all programs and 5erify them by using !L!N "#$i %oft ware#
,. LOGIC GATES:
module logic1a2b2 c2d2e2f2g2h2i3&
input a2b&
output c2d2e2f2g2h2i&
assign c7 a R b&
assign d7 a S b&
assign e7 Ta&
assign f7 T1a R b3&
assign g7 T1a S b3&
assign h7 a U b&
assign i7 T1a U b3&
endmodule
2(a).HALF ADDER:
module half1a2b2 s2cout3&
input a2b&
output s2cout&
xor x11s2a2b3&
and x$1cout2a2b3&
endmodule
2(b).FULL ADDER:
module full1x2y2cin2 s2cout3&
input x2y2cin&
output s2cout&
wire P12P$2P=2P,2P@&
xor x11P12x2y3&

xor x$1s2P12cin3&
and x=1P$2x2y3&
and x,1P=2y2cin3&
and x@1P,2cin2x3&
or x+1P@2P$2P=3&
or xA1cout2P@2P,3&
endmodule
2(c).RIPPLE ADDER:
module rip1a2b2 co2 sum2 cout13&
input V=:DW a2b&
input co&
output V=:DW sum&
output cout1&
wire c12c$2c=2c,&
full x11aVDW2bVDW2co2sumVDW2c13&
full x$1aV1W2bV1W2c12sumV1W2c$3&
full x=1aV$W2bV$W2c$2sumV$W2c=3&
full x,1aV=W2bV=W2c=2sumV=W2c,3&
assign cout17c,&
endmodule
module full1x2y2cin2 s2cout3&
input x2y2cin&
output s2cout&
wire P12P$2P=2P,2P@&
xor x11P12x2y3&
xor x$1s2P12cin3&
and x=1P$2x2y3&
and x,1P=2y2cin3&
and x@1P,2cin2x3&
or x+1P@2P$2P=3&
or xA1cout2P@2P,3&
endmodule
5(a).2 TO 3 DECODER:
module decoder$1i2 en2 y3&
input V1:DW i&
input en&
output VD:=W y&
reg VD:,W y&
always X1en or i or y3
begin
if1en3
case1i3
D:y7,Gb1DDD&
1:y7,GbD1DD&
$:y7,GbDD1D&
=:y7,GbDDD1&
default:y7,GbDDDD&
endcase
else
y7,GbDDDD&
end
endmodule
5(b).5 TO 6 DECODER:
module decoder$1i2 en2 y3&
input V$:DW i&
input en&
output VD:AW y&
reg VD:AW y&
always X1en or i or y3
begin
if1en3
case1i3
D:y7CGb1DDDDDDD&
1:y7CGbD1DDDDDD&
$:y7CGbDD1DDDDD&
=:y7CGbDDD1DDDD&
,:y7CGbDDDD1DDD&
@:y7CGbDDDDD1DD&
+:y7CGbDDDDDD1D&
A:y7CGbDDDDDDD1&
default:y7CGbDDDDDDDD&
endcase
else
y7CGbDDDDDDDD&
end
endmodule
5(c).SEVEN SEGMENT DECODER:
module se5en'segment1a2b2c2d2en2 y3&
input a2b2c2d2en&
output V+:DW y&

reg V+:DW y&
always X1a or b or c or d or en or y3
begin
if1en3
case1Yd2c2b2aZ3
D:y7AGb111111D&
1:y7AGbD11DDDD&
$:y7AGb11D11D1&
=:y7AGb1111DD1&
,:y7AGbD11DD11&
@:y7AGb1D11D11&
+:y7AGbDD11111&
A:y7AGb111DDDD&
C:y7AGb1111111&
":y7AGb111DD11&
default y7AGbx&
endcase
else
y7AGbD&
end
endmodule
3(a).34, MULTIPLE4ER:
module mux1a2b2c2d2 s2 J3&
input a2b2c2d&
input V1:DW s&
output J&
reg J&
always X 1a or b or c or d or s or J3
begin
case1s3
$GbDD: J7a&
$GbD1: J7b&
$Gb1D: J7c&
$Gb11: J7d&
default:J7$Gbx&
endcase
end
endmodule
3(b).64, MULTIPLE4ER:
module muxC1a2b2c2d2e2f2g2h2 s2 y3&
input a2b2c2d2e2f2g2h&
input V$:DW s&
output y&
reg y&
always X 1a or b or c or d or e or f or g or h or s or y3
begin
case1s3
=GbDDD: y7a&
=GbDD1: y7b&
=GbD1D: y7c&
=GbD11: y7d&
=Gb1DD: y7e&
=Gb1D1: y7f&
=Gb11D: y7g&
=Gb111: y7h&
default:y7=Gbx&
endcase
end
endmodule
3(c).,84, MULTIPLE4ER:
module muxC1a2b2c2d2e2f2g2h2i2:282l2m2n2o2p2 s2 y3&
input a2b2c2d2e2f2g2h2i2:282l2m2n2o2p&
input V=:DW s&
output y&
reg y&
always X 1a or b or c or d or e or f or g or h or i or : or 8 or l or m or n or o or p or s or y3
begin
case1s3
,GbDDDD: y7a&
,GbDDD1: y7b&
,GbDD1D: y7c&
,GbDD11: y7d&
,GbD1DD: y7e&
,GbD1D1: y7f&
,GbD11D: y7g&
,GbD111: y7h&
,Gb1DDD: y7i&
,Gb1DD1: y7:&
,Gb1D1D: y78&
,Gb1D11: y7l&
,Gb11DD: y7m&
,Gb11D1: y7n&
,Gb111D: y7o&
,Gb1111: y7p&
default:y7,Gbx&
endcase
end
endmodule
9(a).,43 DE: MULTIPLE4ER:
module demux1x2 sel2 y3&
input x&
input VD:1Wsel&
output VD:=W y&
regVD:=W y&
always X1x or sel or y3
begin
y7,GbD&
case1sel3
D:yVDW7x&
1:yV1W7x&
$:yV$W7x&
=:yV=W7x&
default :y7,GbD&
endcase
end
endmodule
9(b).,46 DE: MULTIPLE4ER:
module demux1x2 sel2 y3&
input x&
input VD:$Wsel&
output VD:AW y&
regVD:AW y&
always X1x or sel or y3
begin
y7CGbD&
case1sel3
D:yVDW7x&
1:yV1W7x&
$:yV$W7x&
=:yV=W7x&
,:yV,W7x&
@:yV@W7x&
+:yV+W7x&
A:yVAW7x&
default :y7CGbD&
endcase
end
endmodule
9(c).,4,8 DE: MULTIPLE4ER:
module demux1x2 sel2 y3&
input x&
input VD:=Wsel&
output VD:1@W y&
regVD:1@W y&
always X1x or sel or y3
begin
y71@GbD&
case1sel3
D:yVDW7x&
1:yV1W7x&
$:yV$W7x&
=:yV=W7x&
,:yV,W7x&
@:yV@W7x&
+:yV+W7x&
A:yVAW7x&
C:yVCW7x&
":yV"W7x&
1D:yV1DW7x&

11:yV11W7x&
1$:yV1$W7x&
1=:yV1=W7x&
1,:yV1,W7x&
1@:yV1@W7x&
default :y71@GbD&
endcase
end
endmodule
8.3:BIT COMPARATOR:
module compare1-242-)42-L42-E43&
input VD:=W-24&
output -)42-L42-E4&
reg -)42-L42-E4&
always X1- or 4 or -)4 or -L4 or -E43
begin
-)471GbD&-L471GbD&-E471GbD&
if1-7743
begin -)471GbD&-L471GbD&-E471Gb1&end
else if 1-<43
begin -)471Gb1&-L471GbD&-E471GbD&end
else
begin -)471GbD&-L471Gb1&-E471GbD&end
end
endmodule
7.PRIORIT1 ENCODER:
module encoder1E!'L2!'L2-'L2E('L2)%'L3&
input E!'L&
input VA:DW!'L&
output V$:DW-'L&
output E('L2)%'L&
reg VA:DW!&
reg V$:DW-2-'L&
reg E!2E('L2E(2)%'L2)%&
integer :&
always X1E!'L or E! or !'L or ! or - or E( or )%3
begin
E!7TE!'L&!7T!'L&
E('L7TE(&)%'L7T)%&-7T-&
E(71&)%7D&-7D&
begin
if 1E!77D3 E(7D&
else for 1:7D&:67A&:7:F13
if 1!V:W7713
begin )%71&E(7D&-7:&end
end
end
endmodule
D:FLIPFLOP:
module d'flipflop1cl82d2 L2Ln3&
input cl82d&
output L2Ln&
reg L2Ln&
always X1posedge cl83
begin
L 67 d&
Ln 67 [d&
end
endmodule
>K FLIPFLOP:
module :8'flipflop1cl82:282 L2Ln3&
input cl82:28&
output L2Ln&
reg L2Ln&
always X1posedge cl83
begin
if1 : 77 D R 8 77 D3
begin
L 67 L&
Ln 67 Ln&
end
else if1: 77 D R 8 77 13
begin
L 67 1GbD&
Ln 67 1Gb1&
end
else if1: 77 1 R 8 77 D3
begin
L 67 1Gb1&
Ln 67 1GbD&
end
else if1: 77 1 R 8 77 13
begin
L 67 [L&
Ln 67 [Ln&
end
else
begin
L 671Gbx&
Ln 671Gbx&
end
end
endmodule
RS:FLIPFLOP:
module rsflipflop1s2r2cl82 L2Ln3&
input s2r2cl8&
output L2Ln&
reg L2Ln&
always X1posedge cl83
begin
if1s77D R r 77 D3
begin
L 67 L&
Ln 67 Ln&
end
else if1s771 R r77D3
begin
L 671Gb1&
Ln 671GbD&
end
else if1s77D R r7713
begin
L 671GbD&
Ln 671Gb1&
end
else if1s771 R r7713
begin
L 671Gbx&
Ln 671Gbx&
end
else
begin
L 671GbD&
Ln 671GbD&
end
end
endmodule
T :FLIPFLOP:
module t'flipflop1cl82t2reset2 L3&
input cl82t2reset&
output L&
reg L&
always X1posedge cl83
begin
if1reset3
L 671GbD&
else
L67[t&
end
endmodule

Вам также может понравиться