US007030570B2

( 1 2) United Sta tes Pa tent ( 1 0) Pa tent N 0. : US 7, 030, 570 B2

Alexa ndrov ( 4 5) D a te of Pa tent: * Ap r. 1 8 , 2006
( 54 ) RESON AN T IN VERTER IN CLUD IN G FEED 5, 24 5, 253 A 9 / 1 9 9 3 Qua zi . . . . . . . . . . . . . . . . . . . . . . . . . 31 5/ 224
BACK CIRCUIT WITH SOURCE OF 5, 71 9 , 4 72 A 2/ 1 9 9 8 Ka chma rik et a 1 . . . . . . . . . . 31 5/ 224
VARIABLE BIAS CURREN T 5, 723, 9 53 A 3/ 1 9 9 8 N erone et a 1 . . . . . . . . . . . . . . . 31 5/ 307
6 , 008 , 59 3 A 1 2/ 1 9 9 9 Riba rich . . . . . . . . 31 5/ 307
75 _ . - 6 , 24 6 , 1 8 3 B1 6 / 2001 Buona vita . . . . . . . . . . . . . . . . . . . 31 5/ 24 8
( ) Inventor. I. AleX a ndr0v, Burlmg ton, MA 2003/ 0 1 4 726 3 Al 8 / 2003 Riba rich
OTHER PUBLICATION S
( 73) As s ig nee: Os ra m Sylva nia Inc. , D a nvers , MA _ _ _ _
( Us ) 1 R Ap p l1 ca t1 on N otes AN - 9 9 9 5A Electronic Ba lla s t Us ing
the Cos t- Sa ving 1 R21 55X D rivers , p p . C- 59 - C6 8 , ( a p p rox.
( * ) N otice: Subj ect to a ny dis cla imer, the term of this 1 9 9 9 )
p a tem is extended or a dj us ted under 3 5 Melvinb C. Cos by a nd R. M. N elms , IEEE Tra ns a ctions On
U_ S_ C_ 1 54 ( 1 ) ) by 0 da ys _ Indus tria l Electronics , vol. 4 1 , N o. 4 , Aug . 1 9 9 4 .
IR D es ig n Tip D T9 8 - 1 , Va ria ble Freq uency D rive us ing
This p a tent is s ubj ect to a termina l dis - IR21 5X Self Os cilla ting IC S , PP~ 1 ' 7, 1 9 9 9 ~
Cla lmer' Prima ry Exa mineriD a vid Vu
( 21 ) Ap p l N O _ 1 0/ 8 8 6 4 4 6 ( 74 ) Attorney, Ag ent, or FirmiCa rlo S. Bes s one
. . . ,
( 22) Filed: J ul. 7, 2004 ( 57) ABSTRACT
( 6 5) Prior Publica tion D a ta A res ona nt inverter With a s elf - os cilla ting driver 1 C f or
Us 2006 / 0006 8 1 2 A1 J a n 1 2 2006 p owering AC loa ds , s uch a s g a s dis cha rg e la mp s or reg u
la ted D C/ D C converters , includes a timing circuit tha t
( 51 ) Int CL g enera tes control s trobe p uls es tha t a re inj ected into the
H053 37/ 00 ( 2006 01 ) timing circuit. The timing circuit is coup led to a n inverter
( 52) us . Cl. . . . . . . . . . . . . . . . . . . 31 5/ 224 - 31 5/ 307- 31 5/ D IG. 5 res ona nt ta nk throug h a f eed ba ck Circuit Providing Pha s e
( 58 ) Fi 6 1 d of Cla s s i? ca tion s ea m}; N O n e lock f or the res ona nt inverter. The f eed ba ck circuit includes
See a p p lica tion ? le f or COmPIetQS' ' r' e' H' j ii' Sg rY a s ource of va ria ble bia s current connected to a n inp ut
' termina l of a Zero s ig na l detector to s hif t a n a ng le a t Which
( 56 ) Ref erences Cited p ola rity cha ng es to control a f req uency f or the res ona nt
inverter.
U. S. PATEN T D OCUMEN TS
4 , 9 9 8 , 06 4 A 3/ 1 9 9 1 Fuderer et a 1 . . . . . . . . . . . . . . 324 / 309 6 Cla ims , 1 0 D ra wing Sheets
+ VBUS
H
+ T Vcc CB ( 1 5 ( 1 6
. VB 1 1
H0 J VY \ I _ j : r/
24 R 1 3
1 7 T 1 0 V RESON AN T Vout
5 ~ LOAD
v TAN K ~
CT 1 2
CT L0
1 8 * COM 1 4 J ] j
1 9 +
23- > | 20
26 \ 27
0y 22 31 \ _ =
5M1 28
21 V, N 33 : J
In
25 : l 50 1 c 29
U. S. Pa tent Ap r. 1 8 , 2006 Sheet 1 0f 1 0 US 7, 030, 570 B2
+ VBUS
| |
IICB
HO " VY S
24 RT V
t
if 1 7 E vs REig mN T z LOAD
VcT 1 2
1 9 J , l]
231 % 2k
2s
21 N 33 % _
Vin "
. 29 '
25; i] % ~ 30 IC 4
32
FIG. 1 A
~ 0
~ VCT
Vim W o > < L
WM
FIG. 1 8
U. S. Pa tent Ap r. 1 8 , 2006 Sheet 2 0f 1 0 US 7, 030, 570 B2
+ VBUS
ll
+ < [ V " 0B ( 1 5 ( 1 s
VB 1 1
Voux H0 J VY V- {I/
36 RT 1 3 v
1 7 1 0 VS RESON AN T out LOAD
TAN K #
VCT 1 2
CT LO W
1 8 - \ COM 1 4 $ L
35 9 20 {7 v
kl i0 2s \
22 W
2s
21 Vin + 33 1 ;)
. 29 '
34 j i % 30 ' c
32
FIG. 2A
SY N C 1 c = 0
V01
Vin
FIG. 2B
U. S. Pa tent Ap r. 1 8 , 2006 Sheet 5 0f 1 0 US 7, 030, 570 B2
Vout
0
FIG. 4 C
a ce/ coo
( H/ we wz/ wo
FIG . 4 D
U. S. Pa tent Ap r. 1 8 , 2006 Sheet 6 0f 1 0 US 7, 030, 570 B2
, + VBUS
1 3
1 4
FIG. 4 E
C56
6
2
\
S
c
w m, w
V 3 4 S
B 1 1 V
+ LIC -
O S
BH V m
V M w
0_ OIV Va
1 c _ 7
5
T T 2
R C 0 2
2
m V
ol. 7 U
+ 4 V \
2 8
1 WI. Y m
0
FIG. 4 F
U. S. Pa tent Ap r. 1 8 , 2006 Sheet 9 0f 1 0 US 7, 030, 570 B2
27/ :
5 .
2s
29
1 3
1 4
23
> 1
21
FIG. 7A
PHASE
SHIFT
FIG. 7B
U. S. Pa tent Ap r. 1 8 , 2006 Sheet 1 0 0f 1 0 US 7, 030, 570 B2
50
4 O \ /
30
P0 ( W)
20
PN P N PN
1 o {
0
0. 3 0. 2 0. 1 O 0. 1 0. 2 0. 3
1 0 ( mA)
FIG. 8
US 7, 030, 570 B2
1
RESON AN T IN VERTER IN CLUD IN G FEED
BACK CIRCUIT WITH SOURCE OF
VARIABLE BIAS CURREN T
BACKGROUN D OF THE IN VEN TION
The p res ent invention rela tes to res ona nt inverters f or
p owering AC loa ds , p ref era bly g a s dis cha rg e la mp s , a nd f or
dimming s uch la mp s . The invention a ls o rela tes to reg ula ted
D C/ D C converter circuits .
The f olloWing ref erences a re incorp ora ted by ref erence:
US. Pa t. N os . 5, 24 5, 253; 4 , 9 9 8 , 04 6 ; 6 , 24 6 , 1 8 3; 5, 723, 9 53;
a nd 5, 71 9 , 4 72; US. Pa tent Ap p lica tion US2003/ 01 4 726 3
A1 ; IR Ap p lica tion N otes AN - 9 9 5A Electronic Ba lla s t
Us ing the Cos t- Sa ving lR2l55X D rivers ; IR D es ig n Tip
D T9 8 - 1 , Va ria ble f req uency D rive Us ing IR2l5X s elf
os cilla ting IC s ; a nd A Res ona nt Inverter f or Electronic
Ba lla s t Ap p lica tion, Melvin C. Cos by a nd R. M. N elms ,
IEEE Tra ns a ctions On Indus tria l Electronics , vol. 4 1 , no. 4 ,
Aug us t 1 9 9 4 .
A g a s dis cha rg e la mp typ ica lly utilizes electronic ba lla s t
f or converting AC line volta g e to hig h f req uency current f or
p oWering the la mp . Conventiona l electronic ba lla s ts include
a n AC to D C converter a nd a res ona nt inverter converting
D C volta g e to la mp hig h f req uency current. The res ona nt
inverter includes s Witching tra ns is tors g enera ting a hig h
f req uency recta ng ula r AC volta g e tha t is a p p lied to a volta g e
res ona nt circuit ha ving a n inductor a nd a ca p a citor in s eries .
The g a s dis cha rg e la mp is coup led in p a ra llel to the ca p a ci
tor. For hig h f req uency electronic ba lla s ts , a s elf - os cilla ting
res ona nt inverter is a common p a rt tha t g enera tes AC
volta g e f or s ta rting a nd AC current f or p owering the la mp .
Self - os cilla ting res ona nt inverters utilize a f eed ba ck tra ns
f ormer coup led betWeen a res ona nt ta nk circuit a nd g a tes of
the s Witching tra ns is tors to p rovide a s inus oida l volta g e to
the g a tes f or s us ta ining the os cilla tions . Res ona nt inverters
a re a ls o us ed in D C/ D C converters .
The ma in a dva nta g e of res ona nt inverters is zero volta g e
s Witching tha t p ermits op era tion a t hig her s Witching f re
q uencies . A typ ica l res ona nt inverter comp ris es a ha lf ( or
f ull) bridg e With p oWer MOSFETs g enera ting hig h f re
q uency AC to p oWer a res ona nt loa d. Three typ es of res ona nt
loa ds a re common tha t dif f er by rea l loa d coup ling to LC
comp onents : s eries , p a ra llel a nd s eries - p a ra llel circuit con
? g ura tions . In a ny combina tion of res ona nt loa d comp o
nents , the control circuit p rovides MOSFET s Witching
a bove res ona nt f req uency f or ef ? cient a nd relia ble MOSFET
op era tion. When s Witching a bove res ona nt, the inp ut of the
res ona nt loa d is inductive. When s Witching beloW res ona nt,
this inp ut is ca p a citive a nd s hould be a voided. Self - os cil
la ting inverter circuits built a s os cilla tors With a p os itive
f eed ba ck a utoma tica lly p rovide a s ta ble inductive mode of
op era tion. In s uch os cilla tors , s Witching f req uency a dva nces
the res ona nt f req uency of the res ona nt loa d a nd tra cks a ny
cha ng es in res ona nt loa d.
Ba lla s ts With hig h f req uency os cilla ting inverter s ta nda rd
indus tria l controllers a nd s elf - os cilla ting ha lf bridg es , s uch
a s the IR2l5X a nd IR53H( D ) s eries f rom Interna tiona l
Recti? er or the L6 579 s eries f rom ST Microelectronics a nd
others , do not ha ve the dra Wba cks of s elf - os cilla ting res o
na nt inverter circuits . HoWever, the p re- a dj us ted s Witching
f req uency is not s ens itive to res ona nt f req uency cha ng es of
the res ona nt loa d, a nd is s us cep tible to nois e a nd va ria tions
of integ ra ted circuit ( IC) s up p ly volta g e Vcc. In vieW of this ,
a direct a p p lica tion of thes e controllers is not likely. Without
correction of s Witching f req uency, the MOSFETs could
cros s conduct a nd f a il When op era ting beloW res ona nt f re
20
25
30
35
4 0
4 5
50
55
6 0
6 5
2
q uency in s ome s tea dy- s ta te conditions , dimming mode or,
a t la mp s ta rting . Als o, p oWer control With the a bove ICs is
not p rovided.
One s olution f or a voiding this p roblem is des cribed in
Ap p lica tion N otes AN 9 9 5A Electronic Ba lla s ts Us ing the
Cos t- Sa ving IR2l5X D rivers is s ued by Interna tiona l Rec
ti? er. This ref erence recommends a f eed ba ck circuit With
tWo a nti- p a ra llel p oWer diodes connected in s eries With the
res ona nt loa d a s zero current detectors . The diodes g enera te
a recta ng ula r AC p uls e s ig na l tha t f orces the timing circuit
in the IC to s Witch s ynchronous ly With this s ig na l. A f eed
ba ck s ig na l indica tes p ha s ing of current in the res ona nt loa d.
HoWever, zero current s ens ing in a ny p ortion of the res ona nt
loa d does not p rovide the neces s a ry 36 00 p os itive f eed ba ck
a ng le f or p ha s e locked op era tion a bove res ona nt f req uency.
In a ddition, When us ed a s a s ource of s ynchroniza tion
s ig na ls , the p oWer diodes a dd s ig ni? ca nt p oWer los s es to the
ba lla s t.
Other p rior a rt IC driven res ona nt inverters a re dis clos ed
in US. Pa t. N os . 5, 723, 9 53 a nd 5, 71 9 , 4 72. Both p a tents
tea ch ha lf bridg e IC f eed ba ck control by cha ng ing s inus oi
da l control s ig na l a mp litude. With this a p p roa ch, p ha s e
s hif ting is f orced to dep end on the a mp litude of the f eed
ba ck s ig na l a nd thus the s ta bility of the os cilla ting s ys tem
ca n be p ure, es p ecia lly during tra ns ients .
US. Pa tent Ap p lica tion 2003/ 01 4 726 3 A1 dis clos es a
p ha s e dela y control tha t controls the inverter. This control
ha s a s ta tic f eed ba ck circuit ha ving a n inp ut s ig na l rep re
s enting the p ha s e of the inductor current Which is comp a red
With a s ig na l rep res enting a ref erence p ha s e. The dif f erence,
or error s ig na l, is s up p lied to a volta g e controlled os cilla tor
( V CO) to control inverter f req uency a nd p oWer. This control
techniq ue utilizes a ctive comp onents incorp ora ted in a con
troller f or p roces s ing p uls e s ig na ls .
The p res ent a p p lica nt s p rior a p p lica tion ( Ser. N o. 1 0/ 6 4 9 ,
8 9 8 ) dis clos es a method f or controlling a res ona nt inverter
by s ynchroniza tion of a s elf - os cilla ting driver IC. The
method utilizes a volta g e a ttenua ted a nd p ha s e s hif ted f eed
ba ck s inus oida l s ig na l f or loop lock up . Even s o, there is s till
a need f or circuitry With a Wider ra ng e of control a nd better
robus tnes s a nd p ha s e s hif t control.
One of the p roblems of the p rior a rt circuits f or interna l
s ynchroniza tion of IC driven res ona nt ha lf bridg e inverters
is tha t they req uire s ig ni? ca nt p ha s e rota tion to g et 36 00 tota l
p ha s e s hif t of the f eed ba ck s ig na l. It is very des ira ble, f or
relia ble p ha s e lock up a nd bef ore clos ing the loop , tha t the
inj ected f eed ba ck s ig na l is g enera ted With a minimum p ha s e
dif f erence rela tive to the externa l s ynchroniza tion s ig na l. It
is a ls o very des ira ble f or relia ble s ynchroniza tion tha t the
inj ected s ig na l be s uf ? ciently a bove the ra mp s ig na l in Wide
ra ng e of op era ting f req uencies . It is a ls o very dis a ble to ha ve
inverter outp ut p oWer control by a s ma ll externa l D C s ig na l
( a s When dimming ) .
SUMMARY OF THE IN VEN TION
It is a n obj ect of the p res ent invention to p rovide a method
a nd circuit f or Wide ra ng e relia ble s ynchroniza tion of s elf
os cilla ting ICs f rom a s ma ll s inus oida l s ig na l.
It is a nother obj ect of the p res ent invention to p rovide f eed
ba ck p ha s e lock up circuit f or the res ona nt inverter via the
s ynchroniza tion circuit.
It is s till a nother obj ect of the invention to p rovide a
volta g e p ha s e lock loop circuit With minimum req uired
p ha s e s hif ting built With inexp ens ive p a s s ive comp onents .
It is yet a nother obj ect of the invention to p rovide a
volta g e f eed ba ck circuit With va ria ble p ha s e s hif t f or
US 7, 030, 570 B2
3
g enera ting a s inus oida l p ha s e s ig na l a nd increa s ing inverter
f req uency during la mp s ta rting .
It is a f urther obj ect of the invention to p rovide a com
bined volta g e/ la mp current p ha s e control f eed ba ck circuit
f or op timiza tion of s ta rting a nd s tea dy s ta te op era tion
modes .
It is s till a f urther other obj ect of the invention to p rovide
a f eed ba ck circuit With va ria ble s tructure f or g enera ting
p ha s e s ig na ls a nd increa s ing inverter f req uency during la mp
s ta rting .
It is yet a f urther obj ect of the invention to p rovide
p rog ra mmed inverter f req uencies during inverter op en cir
cuit a nd during s tea dy- s ta te la mp op era tion.
It is a n a dditiona l obj ect of the invention to p rovide
inverter p oWer control ( dimming ) With a s ma ll D C s ig na l.
It is s till a n a dditiona l obj ect of the invention to p rovide
p oWer converter reg ula ted outp ut volta g e or current.
Unlike p rior res ona nt inverters With p ha s e control, the
p res ent invention includes a control s ys tem tha t utilizes
s inus oida l s ig na ls in its p ha s e control s o p a s s ive comp onents
ca n be us ed f or p ha s e s hif ting . By contra s t, p rior a rt s ys tems
ma nip ula te With p uls e s ig na ls utilizing a ctive comp onents
f or p ha s e s hif ting . The p res ent invention p rovides a n ef f i
cient a nd cos t ef f ective s ys tem f or controlling a res ona nt
inverter throug h a cos t ef f ective IC. With only a f eW externa l
comp onents , ef f ective s ynchroniza tion a nd dimming a re
obta ined. With the a ddition of volta g e a nd current f eed ba cks
coup led to thes e inp uts , ba lla s t inverter circuits f or p oWering
g a s dis cha rg e la mp ca n be obta ined.
BRIEF D ESCRIPTION OF THE D RAWIN GS
The a bove a nd other f ea tures a nd a dva nta g es of the
invention Will be better unders tood throug h the f olloWing
illus tra tive.
FIG. 1 A is a circuit dia g ra m of a res ona nt inverter driven
by a s elf - os cilla ting IC With volta g e loop lock up a nd
externa l control in a ? rs t embodiment of the p res ent inven
tion.
FIG. 1 B s hoWs Wa vef orms of s ig na ls f orming s ynchro
nizing s trobe p uls es in the timing circuit of FIG. 1 A.
FIG. 2A is a circuit dia g ra m of a f urther embodiment in
Which the res ona nt inverter is driven by a s elf - os cilla ting IC
s imila r to FIG. 1 A, but ha ving inverted control s ig na ls .
FIG. 2B s hoWs Wa vef orms of s ig na ls f orming s ynchro
nizing s trobe p uls es in the timing circuit of FIG. 2A.
FIG. 3A is a circuit dia g ra m of yet a f urther embodiment
in Which the res ona nt inverter us es control ba s ed on a n n- p - n
tra ns is tor in the f eed ba ck loop .
FIG. 3B s hoWs Wa vef orms of s ig na ls f orming s ynchro
nizing s trobe p uls es in the control circuit of FIG. 3A.
FIG. 4 A s hoWs a circuit dia g ra m of a volta g e res ona nt
inverter f or a ba lla s t p rovided With va ria ble p ha s e s hif t in the
loop lock up circuit.
FIG. 4 B s hoWs Wa vef orms of s ig na ls f orming s trobe
p uls es in the circuit of FIG. 4 A in a s tea dy- s ta te mode.
FIG. 4 C s hoWs the s a me Wa vef orms a s in FIG. 4 B, but in
a n inverter op en circuit mode or in the beg inning of la mp
s ta rting interva l.
FIG. 4 D illus tra tes f req uency cha ra cteris tics of the res o
na nt inverter of FIG. 4 A during la mp s ta rting .
FIG. 4 E s hoWs a n imp lementa tion of the control s ys tem
in a s ymmetrica l ha lf bridg e res ona nt inverter.
FIG. 4 F s hoWs a n embodiment of the invention With a
p ha s e dela y comp ens a tor in a volta g e lock up loop .
20
25
30
35
4 0
4 5
50
55
6 0
6 5
4
FIG. 5A s hoWs a circuit dia g ra m of the res ona nt inverter
With combined volta g e a nd current lock loop s f or op timized
s ta rting a nd s tea dy- s ta te modes .
FIG. 5B s hoWs Wa vef orms in the circuit dia g ra m of FIG.
5A a f ter la mp s ta rting .
FIG. 6 A is a circuit dia g ra m of a ba lla s t res ona nt inverter
of the p res ent invention With a dimming f ea ture.
FIG. 6 B s hoWs Wa vef orms of s ig na ls f orming s ynchro
nizing s trobe p uls e in the circuit dia g ra m of FIG. 6 A When
a D C dimming control s ig na l is p os itive.
FIG. 7A s hoWs a circuit dia g ra m of a ba lla s t res ona nce
inverter of the p res ent invention With s ynchronizing control
ba s ed on a p - n- p tra ns is tor a nd With a dimming f ea ture.
FIG. 7B s hoWs Wa vef orms of s ig na ls f orming s ynchro
nizing control s trobe p uls es in the circuit dia g ra m of FIG. 7A
When D C dimming control s ig na l is neg a tive.
FIG. 8 illus tra tes dimming cha ra cteris tics ( outp ut p oWer
vers us D C control s ig na l) of a ba lla s t inverter With control
circuits of FIG. 6 A ( n- p - n) a nd FIG. 7A ( p - n- p ) When
p oWering the s a me g a s dis cha rg e la mp .
D ESCRIPTION OF PREFERRED
EMBOD IMEN TS
FIG. 1 A is a ba lla s t res ona nt inverter block- circuit dia
g ra m With a s ta nda rd s elf - os cilla ting driver integ ra ted circuit
( IC) 1 0 tha t illus tra tes a s ynchronizing control a rra ng ement
of the p res ent invention. HO a nd LO outp uts of IC 1 0 drive
a ha lf bridg e p oWer s ta g e tha t includes MOSFETs 1 1 a nd 1 2
a nd g a te res is tors 1 3 a nd 1 4 . IC 1 0 is p rovided With a
boots tra p ca p a citor CB connected to the p in VB of IC 1 0
coup led to a boots tra p diode ( not s hown) . MOSFETs 1 1 a nd
1 2 a re connected to hig h volta g e ( + V bus ) D C f or g enera ting
AC volta g e a cros s the inp ut of a res ona nt ta nk 1 5. A loa d 1 6 ,
s uch a s a g a s dis cha rg e la mp or a tra ns f ormer With a recti? er
With a ? lter, is coup led to res ona nt ta nk 1 5. The controller
IC 1 0 ha s a built- in os cilla tor tha t is s imila r to the indus try
s ta nda rd CMOS 555 timer. Initia l os cilla tor f req uency ca n
be p rog ra mmed With a timing circuit tha t includes externa l
timing res is tor 1 7 a nd timing ca p a citor 1 8 coup led to p ins CT
a nd RT of IC 1 0. In the circuit of FIG. 1 A a nd other s imila r
circuits dis clos ed beloW, loW s ide outp ut LO of IC 1 0 is in
p ha s e With the RT p in volta g e s ig na l. Since the RT p in
volta g e p otentia l cha ng es betWeen loW ( 0) a nd hig h ( + Vcc)
rela tive to the common termina l ( COM) , CT p in volta g e VCT
ha s a ra mp s ha p e s up erp os ed on D C volta g e. IC 1 0 os cilla tor
s Witches a t hig h ( 2/ 3 Vcc) a nd loW ( 1 / 3 Vcc) p redetermined
CT p in volta g e levels .
In one a s p ect of the p res ent invention, the timing circuit
is imp roved by ins erting betWeen the COM termina l a nd the
timing ca p a citor 1 8 a netWork With tWo a nti- p a ra llel diodes
1 9 a nd 20 a nd s eries res is tors 21 a nd 22 tha t a re both coup led
to the COM termina l. A s ma ll ca p a citor 23 ( e. g . , l00i200 p f )
is connected to a node betWeen diode 1 9 a nd res is tor 21 a nd
to + Vcc termina l throug h a res is tor 24 . The node betWeen
ca p a citor 23 a nd res is tor 24 is connected to the outp ut of a
zero s ig na l detector ( ZSD ) 25 tha t s Witches When a n inp ut
s ig na l V1 1 1 a t a ? rs t inp ut termina l cha ng es p ola rity. ZSD 25
ma y be a hig h f req uency a mp li? er, a volta g e comp a ra tor, or
a s ing le tra ns is tor. The circuit of FIG. 1 A us es a n inverting
typ e ZSD . The ZSD 25 Will initia te a n ins ta nt dis cha rg e of
ca p a citor 23 to the res is tor 21 When ZSD 25 s inus oida l inp ut
s ig na l cha ng es f rom neg a tive to p os itive. N eg a tive s trobe
p uls es g enera ted a cros s res is tor 21 Will be s up erp os ed on the
CT p in ra mp volta g e VCT. This s trobe p uls e control ca n be
us ed in control ICs utilizing dif f erent typ es of os cilla tors
With timing ca p a citor CT tied to g round ( common) .
US 7, 030, 570 B2
5
FIG. 1 B demons tra tes Wa vef orms in the circuit of FIG.
1 A, including neg a tive s trobe p uls es g enera ted by ZSD 25
When its s inus oida l inp ut s ig na l Vin cha ng es f rom neg a tive
to p os itive. N eg a tive s trobe p uls es tha t a re s up erp os ed on the
ra mp volta g e VCT f orce IC 1 0 s Witching bef ore ra mp volta g e
VCT a chieves the loWer 1 / 3 Vcc limit.
The control s ys tem ca n be built With a ny typ e of f ull Wa ve
res ona nt inverter ( s eries , p a ra llel or s eries - p a ra llel) a nd a ny
typ e of loa d ( g a s dis cha rg e la mp s , induction hea ters , tra ns
f ormers With recti? ers With ? lters a nd D C loa ds , etc. )
According to a f urther a s p ect of the p res ent invention, a
volta g e lock up loop circuit is p rovided f rom a n outp ut of
res ona nt ta nk 1 5 to the inp ut of ZSD 25 via a p ha s e
comp ens a tor 26 . Pha s e comp ens a tor 26 p rovides a p ha s e
a dva nce ( or dela y) f or a f eed ba ck s ig na l tha t s ynchroniZes
the controller a t a des ira ble f req uency by p roviding a p ha s e
s hif t of up to 36 0 in the f eed ba ck loop . The outp ut volta g e
Vout f rom the res ona nt ta nk 1 5 is a ttenua ted a nd p ha s e
s hif ted by the p ha s e comp ens a tor 26 . In FIG. 1 A, a n
economica l vers ion of p ha s e comp ens a tor 26 is s hoWn
ha ving s eries ca p a citors 27 a nd 28 a nd a res is tor 29 con
nected in p a ra llel to the ca p a citor 28 . Other embodiments of
p ha s e comp ens a tor 26 a ls o built With p a s s ive comp onents
a re dis clos ed beloW.
The s ys tem des cribed a bove ca n be p rovided With a
controller f or a dditiona l inverter f req uency/ p oWer control.
The s ys tem os cilla ting f req uency is controlled by cha ng ing
s trobe p uls e p ha s e. As s hoWn in FIG. 1 A, the controller ma y
include a s ource 32 of a va ria ble D C bia s current ic tha t is
coup led to ZSD 25 inp ut Vin via res is tor 33 f or externa l
s trobe p uls e p ha s e control. A res is tive divider With res is tors
30 a nd 31 ma y be us ed a s a ma tching network f or ZSD 25
inp ut. A node N ma y be connected to ( a ) the p ha s e com
p ens a tor 26 throug h res is tor 31 , ( b) the s ource 32 of D C bia s
current IC throug h res is tor 33, ( c) res is tor 30 tha t is con
nected to g round, a nd ( d) the ? rs t inp ut termina l of the ZSD
25.
FIG. 2A illus tra tes a nother embodiment tha t includes a
non- inverting ZSD 34 Whos e outp ut is coup led to the
res is tor 22 via f urther ca p a citor 35. A p os itive s trobe p uls e
is g enera ted a cros s the s eries res is tor 22 by dis cha rg ing the
f urther ca p a citor 35 to the res is tor 22 via ZSD 34 . This
embodiment is s imila r to the ? rs t embodiment excep t tha t
f urther ca p a citor 35 is connection to the node betWeen diode
20 a nd res is tor 22 a nd the other inp ut termina l of ZSD 34
receives Vin. With this connection, cha rg e interva ls of the
timing ca p a citor 1 8 ca n be controlled. The f urther ca p a citor
35 is cha rg ed f rom a neg a tive a uxilia ry volta g e s ource Va ux
throug h a limiting res is tor 36 . When inp ut s ig na l Vin of ZSD
34 cha ng es f rom p os itive to neg a tive, a p os itive s trobe p uls e
is g enera ted a cros s the res is tor 22 by dis cha rg ing the ca p a ci
tor 35 to the res is tor 22 via ZSD 34 .
As ca n be s een f rom FIG. 2B, p os itive s trobe p uls es a re
s up erp os ed on the VCT ra mp volta g e. As a res ult, s trobe
p uls es f orce os cilla tor to s Witch bef ore the p oint When ra mp
volta g e VCT a chieves the hig her 2/ 3 Vcc limit.
Both neg a tive a nd p os itive s trobe p uls es of thes e tWo
embodiments p rovide a Wide ra ng e of relia ble f req uency
control a s the a mp litude of the s trobe p uls e is comp a ra ble to
p ea k- to- p ea k ra mp volta g e a nd ma y be hig her tha n this
volta g e.
The circuits of FIGS. 1 A a nd 2A ha ve identica l op en loop
control cha ra cteris tics a nd ma y us e identica l f eed ba ck
s ig na l s hif ting f or p ha s e lock up . Tha t is , the D C control
s ig na l IC ma y be a p p lied to the s inus oida l volta g e f eed ba ck
inp ut to ZSD 25 or 34 to s hif t a s Witching a ng le of ZSD 25
or 34 . With a clos ed lock up loop , p ha s e s hif ting in the f eed
20
25
30
35
4 0
4 5
50
55
6 0
6 5
6
ba ck loop by mea ns of the s ource of bia s current 32 p rovides
f req uency control of the res ona nt inverter.
The f urther embodiments des cribed beloW a re va ria tions
of the ? rs t a nd s econd embodiments tha t p rovide yet f urther
imp rovements a nd f a cilita te a n unders ta nding of the p res ent
invention.
FIGS. 3AiB illus tra te a n embodiment With a n n- p - n
tra ns is tor 36 a s a Zero s ig na l detector. To p rovide s ymmetri
ca l s Witching f rom a n AC current s ource, a n a nti- p a ra llel
diode 37 is connected to the ba s e- emitter j unction of the
tra ns is tor 36 . The inp ut of tra ns is tor 36 is coup led to the
outp ut of the p ha s e comp ens a tor 26 via res is tor 38 , s o
tra ns is tor 36 could be cons idered a volta g e driven device.
When tra ns is tor 36 is OFF, the ca p a citor 23 is cha rg ed via
res is tors 24 a nd 21 by the s ma ll current derived f rom + Vcc
volta g e. When the tra ns is tor 36 turns ON , the ca p a citor 23
ins ta ntly dis cha rg es to res is tor 21 , g enera ting neg a tive
s trobe p uls es . The s trobe p uls es s ynchroniZe the os cilla tor of
IC 1 0 With s inus oida l volta g e Vs ync. The p ha s e a ng le
betWeen outp ut inverter volta g e Vout a nd externa l s ynchro
niZing s inus oida l volta g e Vs ync ( a s s uming op en loop a t
res is tor 38 ) corres p onds to the p ha s e s hif ting a ng le f rom
p ha s e comp ens a tor 26 f or p ha s e lock up a t inverter op era ting
f req uency. For mos t AC loa ds , including g a s dis cha rg e
la mp s , a p ha s e a dva nce p ha s e comp ens a tor 26 is us ed ( a
p ha s e a dva nce s chema tic is s hoWn in a ll dra Wing s ) . If a
s ma ll p ha s e dela y is needed, a p ha s e dela y comp ens a tor ma y
be us ed. For ins ta nce, f or a p ha s e dela y or a Zero p ha s e s hif t,
a n a dditiona l res is tor ( not s hoWn) ca n be connected in
p a ra llel to the ca p a citor 27 in the p ha s e comp ens a tor 26 .
Control current IC f rom s ource 32 p rovides D C bia s to the
ba s e of tra ns is tor 36 via res is tor 33 f or inverter f req uency/
p oWer control.
FIG. 4 A s hoWs a f urther embodiment of the invention in
a ba lla s t res ona nce p a ra llel inverter ha ving a g a s dis cha rg e
la mp 39 a s a loa d. The res ona nt ta nk of the inverter ma y
include a res ona nt inductor 4 0 a nd a res ona nt ca p a citor 4 1
coup led in p a ra llel to the la mp 39 . A D C blocking ca p a citor
4 3 is connected in s eries With the inductor 4 0. The inverter
p ha s e lock up f eed ba ck netWork ma y include a n imp roved
p ha s e comp ens a tor 4 4 ha ving a non- linea r s eries netWork
With ba ck- to- ba ck connected Zener diodes 4 5 a nd 4 6 a nd
res is tor 4 7. This s eries netWork is connected in p a ra llel to the
loWer ca p a citor 28 of the p ha s e comp ens a tor 4 4 . Zener
diodes 4 5 a nd 4 6 ha ve a thres hold volta g e tha t is a little bit
hig her tha n the p ea k of Vs ync outp ut volta g e of the p ha s e
comp ens a tor in s tea dy- s ta te mode. Theref ore, the res is tor 4 7
Would not conduct a ny current during this mode. In this
mode, the op era tion of p ha s e comp ens a tor 4 4 is s imila r to
op era tion of p ha s e comp ens a tor 26 in FIG. 3A.
Wa vef orms in s tea dy- s ta te mode a re s hoWn in FIG. 4 B,
Where it ma y be s een tha t p ha s e a dva nce a ng le 1 P1 is
g enera ted by p ha s e comp ens a tor 4 4 to p rovide nomina l la mp
p oWer. D uring la mp s ta rting , or op en circuit mode, the
res ona nt f req uency of res ona nt loa d g oes hig her a nd ma y
ca us e volta g e a nd current s tres s in inverter comp onents .
Indeed, a ca p a citive mode tha t is s tres s f ul f or MOSFETs is
likely. This s itua tion is p revented in the inverter of FIG. 4 A
during la mp s ta rting . Since outp ut volta g e Vout of the
inverter is much hig her a t s ta rting tha t in s tea dy- s ta te mode,
Vs ync volta g e a cros s ca p a citor 28 of the p ha s e comp ens a tor
4 4 is a ls o hig her a nd Zener diodes 4 5 a nd 4 6 s ta rt conduct
ing . By introduction of res is tor 4 7, the tota l res is ta nce
coup led to the ca p a citor 28 is decrea s ed a nd the a dva nce
a ng le of p ha s e comp ens a tor 4 4 is even hig her tha n in
s tea dy- s ta te mode. This res ults in hig her s Witching f re
q uency a nd outp ut volta g e reduction in the s ta rting a nd op en
US 7, 030, 570 B2
7
circuit modes . The ba lla s t inverter op era tes a bove res ona nt
f req uency. Wa vef orms in the op en circuit or la mp s ta rting
mode a re s hoWn in the FIG. 4 C. Even if a s inus oida l inp ut
current to ZSD 36 is s lig htly dis torted, the a dva nce a ng le of
this q ua s i- s inus oida l current is increa s ed comp a red With a
s tea dy- s ta te mode ( 1 P2> 1 P1 ) .
FIG. 4 D s hoWs tra ns f er f unctions ( rea l volta g e g a in
lVout/ Vinl vers us rela tive f req uency 00/ 000, Where ( no is a
res ona nt f req uency of a n unloa ded res ona nt ta nk) . Plot 1
corres p onds to a n op en circuit res ona nt ta nk tra ns f er f unc
tion a s s uming s ome p oWer los s es . Plot 2 illus tra tes a tra ns f er
f unction of the s a me res ona nt ta nk loa ded by a n op era ting
la mp . FIG. 4 D a ls o illus tra tes ba lla s t/ la mp s ta rting tra j ectory
f or the embodiment in FIG. 4 A. Bef ore ig nition of the la mp
its res is ta nce is very hig h ( p lot 1 ) a nd the inverter g enera tes
hig h volta g e Vout. The p ha s e comp ens a tor 4 4 p rovides
hig her p ha s e a dva nce a ng le 1 P2 in the lock up loop of the
res ona nt inverter. Theref ore, the inverter op era tes in the
inductive mode a t the hig her s Witching f req uency 002, Which
is a n initia l f req uency of ig nition ( IGN in FIG. 4 D ) . When
the la mp is s ta rted a nd the res ona nt ta nk is loa ded With a rea l
res is ta nce, res ona nt f req uency decrea s es . Simulta neous ly,
the p ha s e a ng le of the p ha s e comp ens a tor 4 4 decrea s es to
1 P1 , a nd s Witching f req uency a ls o decrea s es to 001 . The
s ys tem op era ting p oint ( s ee FIG. 4 D ) tra ns f ers f rom IGN to
RUN tha t corres p onds to nomina l outp ut p oWer of the
inverter. D uring la mp s ta rting the inverter a lWa ys op era tes
a bove its va ria ble res ona nt f req uency.
FIG. 4 E illus tra tes a n embodiment of a s ymmetrica l ha lf
bridg e p a ra llel loa ded res ona nt inverter. The loa d, f or
ins ta nce, g a s dis cha rg e la mp 39 , is connected in p a ra llel to
the res ona nt ca p a citor 4 8 a nd in s eries With a res ona nt
inductor 4 0. Firs t common termina ls of the res ona nt ca p a ci
tor 4 0 a nd the la mp 4 0 a re connected to a j unction of s eries
s tora g e ca p a citors 4 9 a nd 50. The inp ut of the volta g e f eed
ba ck loop a t ca p a citor 27 is connected to the s econd com
mon termina ls of the la mp 39 a nd res ona nt ca p a citor 4 0. The
ca p a citor 27 blocks D C volta g e f rom the s tora g e ca p a citor
50 into the lock up loop .
FIG. 4 F s hoWs a nother embodiment ha ving a n enha nced
p ha s e comp ens a tor 51 p roviding a s ig na l dela y in the lock up
loop . The p ha s e comp ens a tor 51 inp ut is connected to a
volta g e s ource tha t g enera tes a volta g e s ig na l p rop ortiona l to
outp ut volta g e Vout. The p ha s e comp ens a tor 51 is connected
to the j unction of s eries res ona nt ca p a citors 52 a nd 53, Which
both rep res ent the p a ra llel res ona nt ca p a cita nce of the
inverter. The p ha s e comp ens a tor 51 ma y include a ? rs t p ha s e
dela y RC- netWork ha ving a res is tor 54 a nd ca p a citor 55, a nd
a ls o a s econd RC s ig na l p ha s e a dva nce netWork comp ris ing
a ca p a citor 56 a nd res is tor 38 . It a ls o includes a non- linea r
netWork s imila r to the one in FIG. 4 B ha ving Zener diodes
4 5, 4 6 a nd res is tor 4 7.
In a s tea dy- s ta te mode, there is no current in the res is tor
4 7. The dela y a ng le of the ? rs t RC- netWork is s elected to
overcomp ens a te f or the p ha s e a dva nce of the s econd RC
netWork. By ha ving a p ha s e dela y in the lock up loop , hig her
outp ut p oWer ca n be a chieved. Tha t p oWer ca n be f urther
increa s ed With a neg a tive D C bia s f rom neg a tive a uxilia ry
volta g e Va ux via a res is tor 57 to the ba s e of tra ns is tor 36 .
The embodiment in FIG. 4 F a dds a neg a tive bia s to the inp ut
of tra ns is tor 36 to p rovide deep la mp dimming .
When s ta rting the la mp , or in a n op en circuit mode, the
inverter in FIG. 4 F is p rotected f rom overvolta g e a nd
ca p a citive mode op era tion by increa s ing its s Witching f re
q uency. At hig h volta g e, Zener diodes 4 5 a nd 4 6 s ta rt
conducting a nd the s tructure of lock loop is cha ng ed by
introducing a n a dditiona l s eries p ha s e a dva nce RC- netWork
5
20
25
30
35
4 0
4 5
50
55
6 0
6 5
8
With ca p a citor 56 a nd res is tor 4 7 p roviding a s ig ni? ca nt
p ha s e a dva nce a nd s ys tem f req uency boos t.
FIG. 5A s hoWs a n embodiment combining tWo f eed ba ck
lock up loop s : a volta g e loop a ccording to the p res ent
invention des cribed a bove ( e. g . , FIG. 1 A) a nd a la mp current
loop . A ca p a citor 58 connected in s eries to the la mp 39 is
us ed a s a la mp current s ens or. Res is tor 59 ( op tiona l) s p eeds
up the ca p a citor 58 dis cha rg e When the la mp turns of f . The
ca p a citor 58 is coup led to the ba s e of tra ns is tor 36 via
res is tor 6 0.
FIG. 5B illus tra tes Wa vef orms of s ig na ls in the control
netWork of the inverter in FIG. 5A a f ter la mp s ta rting .
D uring la mp s ta rting , the s ig na l f rom the la mp current
s ens or ( ca p a citor 58 ) is neg lig ibly loW. The s ys tem is locked
up via volta g e f eed ba ck tha t is p roviding a current iv to the
ZSD 36 in s uch a p ha s e tha t the s ys tem g enera tes a hig her
f req uency a t loW p oWer needed to p rovide s p eci? ed s ta rting
volta g e f or the la mp 39 .
Typ ica lly volta g e loop s p rovide p ha s e a dva nce reg a rding
outp ut volta g e Vout during s ta rting . Then, la mp current is
built up a nd a limited current s ig na l io a p p ea rs in the current
loop . Volta g e a cros s ca p a citor 58 a nd current i0 both dela y
a bout 9 0 vers us inverter outp ut volta g e Vout. N oW the
g eometrica l s um of a bove currents iv+ io: iin, a p p lied to the
inp ut of ZSD 36 , f ea tures a p ha s e dela y s hif t ( s ee a s hif t
a ng le 1 P3 in FIG. 5B) . This ca us es a corres p onding p ha s e
s hif t of the s trobe p uls e s up erp os ed on ra mp s ig na l VCT. As
a res ult, inverter f req uency is reduced a nd p oWer is
increa s ed, s o nomina l la mp p oWer is g enera ted by the
inverter a f ter la mp s ta rting .
FIG. 6 A illus tra tes a circuit dia g ra m of a dimma ble la mp
ba lla s t inverter, a nd is a vers ion of the inverter circuit s hoWn
in FIG. 4 A. The dimming control current 1 0 p rovides a D C
s hif t f or s inus oida l s ig na l current iin ( s ee the Wa vef orms in
FIG. 6 B) . If the dimming s ig na l is p os itive ( ic> 0) , then
tra ns is tor 36 turns on ea rlier, s trobe p uls e p ha s e is a dva nced
a nd s Witching f req uency is increa s ed. When the dimming
s ig na l is neg a tive, s Witching f req uency is decrea s ed ( not
s hoWn) .
FIGS. 7A a nd 7B illus tra te dimming control f or a dim
ma ble la mp ba lla s t inverter ha ving a circuit dia g ra m derived
f rom the inverter circuit dia g ra m in FIG. 2A. This embodi
ment us es a p - n- p tra ns is tor 36 a s the Zero s ig na l detector.
FIG. 8 p res ents dimming control cha ra cteris tics f or res o
na nt inverters of FIGS. 6 A a nd 7A. Both inverters Were
a lmos t identica l a nd p oWer s ta nda rd T8 la mp s f rom
1 55VD C Bus .
While embodiments of the p res ent invention ha ve been
des cribed in the f oreg oing s p eci? ca tion a nd dra Wing s , it is
to be unders tood tha t the p res ent invention is de? ned by the
f olloWing cla ims When rea d in lig ht of the s p eci? ca tion a nd
dra Wing s . Both inverters utiliZe a n IR21 531 controller op er
a ting a t 1 25 kHZ a t nomina l la mp p oWer. By a p p lying a D C
bia s ( 1 0) , p ha s e a dva nce ( dela y) a ng les in the volta g e f eed
ba ck circuit ca n be cha ng es f rom 4 50 to 4 50 tha t p rovide a
Wide ra ng e of f req uency a nd p oWer reg ula tion ca p a bility.
I cla im:
1 . A res ona nt inverter comp ris ing :
a s elf - os cilla ting driver circuit;
a timing circuit connected to a n inp ut of s a id driver
circuit;
a Zero s ig na l detector tha t cha ng es a n outp ut s ig na l When
a n inp ut s ig na l received a t a ? rs t inp ut termina l cha ng es
p ola rity, a n outp ut of s a id Zero s ig na l detector being
connected to s a id timing circuit;
US 7, 030, 570 B2
9
a res ona nt ta nk connected to a n outp ut of s a id driver
circuit; a nd
a f eed ba ck circuit tha t connects a n outp ut of s a id res ona nt
ta nk to s a id ? rs t inp ut termina l of s a id Zero s ig na l
detector, s a id f eed ba ck circuit comp ris ing a s ource of 5
a va ria ble bia s current tha t is connected to s a id ? rs t
inp ut termina l of s a id Zero s ig na l detector to s hif t a n
a ng le a t Which p ola rity cha ng es to control a f req uency
f or the res ona nt inverter.
2. The res ona nt inverter of cla im 1 , Wherein s a id f eed
ba ck circuit f urther comp ris es a p ha s e comp ens a tor tha t is
connected to a controller tha t includes s a id s ource of bia s
current.
3. The res ona nt inverter of cla im 2, f urther comp ris ing a
p a ir of s Witching tra ns is tors op era ted by s a id driver circuit 1 5
a nd g enera ting a volta g e a cros s a n inp ut of s a id res ona nt
1 0
ta nk, Wherein s a id outp ut of s a id res ona nt ta nk is connected
to s a id p ha s e comp ens a tor.
4 . The res ona nt inverter of cla im 2, Wherein s a id p ha s e
comp ens a tor comp ris es tWo ca p a citors connected in s eries
betWeen s a id outp ut of s a id res ona nt ta nk a nd a common
termina l a nd a f urther res is tor in p a ra llel With one of s a id
tWo ca p a citors tha t is clos es t to s a id common termina l.
5. The res ona nt inverter of cla im 4 , Wherein s a id p ha s e
comp ens a tor f urther comp ris es , in p a ra llel With s a id f urther
res is tor, a p a ir of Zener diodes connected ba ck- to- ba ck.
6 . The res ona nt inverter of cla im 2, Wherein s a id control
ler comp ris es a s econd node tha t is connected to s a id ? rs t
inp ut termina l of s a id Zero s ig na l detector, s a id p ha s e
comp ens a tor, a nd s a id s ource of bia s current.
* * * * *