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The main objective of this project is to design and simulate the One-Bit Full-Adder Using
VHDL (hardware description language); which helps us to get familiar with the
designing, coding and simulation process using VHDL.
2. Discussion

2.1 One-Bit-Full-Adder
One Bit Full Adder is an important/essential component of design for all types of
processor including digital processor, Arm processor, micro processer, etc. A one-bit
full adder, used in this simulation process is a device that uses three binary inputs A, B,
C-in and two binary outputs sum(s) and c-out. The simulation process was achieved
using the VHDL (hardware description language). There are several ways to
implement a 1 bit full header. This simulation uses the following implementation to
achieve the expected specification for sum(s) and c-out.


( ) (

( ). (2)
The design will use the Boolean function from equation 1 and 2 and produces the final
truth table that will similar to the following table:-

Figure 1. 1 Bit Full Adder Truth Table
Where A, B and

are input and S (sum) and

are output and carry out

representation respectively. The summation is symbolically listed below along with
the block diagram in figure 2. To meet the specification, the design must use Boolean
operation described in the equation 1 and 2. The visual representation for inputs and
outputs are represented in block diagram in figure-2

+ B

3. Schematics:

Figure 2.Symbolic addition of a column of
three bits and Block diagram

4. Waveform:
Following figure:-3 is a waveform for One-Bit Full-Adder, generated using VHDL program.
The waveform is zoomed to 100ns, showing both inputs and outputs.

Figure:-3 , Simulated waveform
The testing results was tested by moving the yellow line into time axis, the results is shown
in Table 1
(ns) A B Cin Cout S(Sum)
5 0 0 0 0 0
15 1 0 0 0 1
25 0 1 0 0 1
35 1 1 0 1 0
45 0 0 1 0 1
55 1 0 1 1 0
65 0 1 1 1 0
75 1 1 1 1 1
Table 1. Testing Result
The testing result was compared with truth table of the 1bit full adder. The result has been
verified that the testing results are same as the results from the original truth table from
figure 1.

5. Project Summery
Slice =
IO utilization in percentage=

6. Self-Evaluation:
Overall project was very informative and fun to complete. We were somewhat familiar with
the VHDL software from project-1, but then also we faced difficulties to write the VHDL
code. We watched some tutorial video on VHDL, deed some research, and review the note
from class, about conversion of project one code to solve our problems. At the end, we end
up figuring out the procedure and modify the code from project one and make it functional.

7. Code
Following figure:-4, is a VHDL source code for this exercise and figure:-5 , is a code for test

Figure 4.Source File Code

Figure 5.Simulation testbench Code