Lecture 13 ECE 425

Lecture 13 -- Memories
Lecture 13 ECE 425
Outline
Types of memory in semiconductor systems
Basic array layout
ROM design
SRAM cell design
Multi-port SRAMs
Content-addressable memories
DRAMs
Decoders
Lecture 13 ECE 425
Storage Systems
Many types of storage devices in electronic systems -- disk,
tape, memory chips, etc.
Two high-level differentiating features:
Volatility -- does data go away if you remove power?
Does time to access a datum depend on the
address/location of the datum? (random-access)
Most semiconductor memories are described as random-
access, although this description is becoming increasingly
untrue.
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Memory Terminology
ROM -- Read-Only Memory. Once fabricated, you cant
change the contents of the memory
PROM -- Programmable Read-Only Memory. Writes
take orders of magnitude longer than reads (often
milliseconds)
FLASH memory is an example of this technology
RAM -- Random-Access Memory. Reads and writes take
approximately the same amount of time. Access time is
independent of which address youre referencing.
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Basic Memory Layout
Organization is similar for all types of semiconductor
memory, difference is in the cells that hold bits
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Chip-Level Organization
Memory chips may contain multiple arrays, or modules, to
improve performance
Also allows idle modules to be powered down
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Memory Cells
Memory arrays are grids of bit cells, each of which holds
one bit of data
Typically the high bits of the address select a row of the
memory, the signal that selects the row is called a word
line
Each cell in the selected row drives its output and/or
reads its input on a bit line or lines
Low bits of the address select which of the bit lines are
sent to the output or written
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ROMs
Simplest ROM cell is a single transistor
Precharge all bit lines high, assert word line. Transistors
pull bits whose output = 0 low.
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Example Layout
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Programming ROMs
Done at fabrication time
Multiple options
Put transistors in the array where you want 0s in the
output
Place transistors in every possible position, only
connect up the ones that correspond to 0s
If you care about speed, you only want to include
necessary transistors (reduce load on wordlines)
For general-purpose ROM chips, often use the connection
method, as that allows chip to be customized by changing
only 1-2 layers/masks
In some technologies, can program by burning
connections with a laser/electron beam
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Random-Access Memories
Two major types:
1. Static RAM (SRAM): relies on active transistor drive to
hold state
Retains data indefinitely
Fast
Relatively large bit cells
2. Dynamic RAM (DRAM): stores data on capacitors
Small bit cells
Slower than SRAM
Needs to be refreshed, or will lose data over time
Destructive read
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Basic SRAM Cell
Cross-coupled inverters hold state
To write, drive data strongly on bit lines, such that you
overwhelm the stored value
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Circuit Implementation
Generally precharge bit lines to Vdd/2 while decoder is
determining which word line to drive
Reduces read time
Allows use of differential sense-amplifier
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Example Layout
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Multi-Ported SRAM Cell
Often want to be able to access multiple locations within
an array simultaneously
Example: Processor register file typically wants to
handle two reads, one write per cycle
Add additional pass-transistors, bit lines to each cell to
allow this
Need to be careful about simultaneous reads/writes and
not writing multiple times to the same bit
Area grows quadratically with number of ports
If you need many ports, often better to make multiple
copies of the memory with fewer ports/copy
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Three-Port SRAM Cell
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Variant -- Content-Addressable Memory
Can do parallel comparison of all words in an array to see
if their data matches a given value
Drive data on !bit line, !data on bit, do not assert any
word lines
Match signals of all bits in a word act as wired-AND
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SRAM Cell Design Issues
N-FET pass-transistors limit voltage on bit lines to V
dd
-V
t
Count on sense amplifiers to generate rail-rail outputs
with these inputs
Older designs precharged both bitlines to V
dd
, let cell
discharge one of them to ground.
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Design Issues -- Reads
Strong size/speed trade-off
Small transistors will take a long time to
charge/discharge the bit lines
Big transistors take more space, require stronger drive
to write
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Design Issues -- Writes
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Dynamic RAMs
Use single-transistor cell to store charge on a capacitor
Output voltage depends on relative capacitances of C
d
and bit line
Destructive read, requires sense amplifier
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DRAM Cell Layout
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DRAM Layout
Bit cell capacitor is effectively a dummy transistor that
we only use for its gate capacitance
Can bias polysilicon line to create a depletion region and
increase cell capacitance
Modern designs use more sophisticated structures, such
as trench capacitors, to reduce area
Tradeoff:
High cell capacitance increases cell area and write
time, but increases output voltage swing and time
before data is lost
Low cell capacitance reduces area, but increases
demands on the sense amplifier
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Decoders
Reminder of basic array layout
Decoders job is to generate a one-hot output
Word line corresponding to input value is high, all
others low
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Example
If there are only two address inputs, decoder truth table is
We can implement decoders using static or dynamic
circuits
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Static Row Decoder
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Static Row Decoder
If there are many address inputs, may be better to use
multi-level structure
Limits number of inputs to each gate
Allows staging of transistor sizes to get enough drive
on word line without too much load on address lines
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Example Using Two-Input Predecoders
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Dynamic Row Decoders
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Dynamic Row Decoders
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Column Decoders
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Column Decoders
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Column Decoders
An alternative design is to use a structure similar to the
row decoder to generate a one-hot drive signal based on
the address bits
Put full pass-gate at the output of each bit line, control
signal to pass-gates are the outputs of the decoder
Gives full output swings
Fewer transistors in series --> faster
May take more area, especially when you consider the
number of control wires
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Putting it All Together
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Readings
Sections 11.1-11.4, 11.6 in your book