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Subhash Patel

ID - 4045
Electronics & Communication
1
Term Paper
2
Contents
1 MOS Switch 4
2 MOS Diode 5
3 Current Sink and Source 5
4 Current Mirror 6
5 Current and Voltage References 7
6 CMOS Inverters 8
7 Dierential Amplier 10
8 Cascode Amplier 11
9 Current Amplier 11
10 Two Stage Op-Amp 13
11 Cascode Op-Amp 16
12 Comparators 16
13 Digital-Analog Converter 18
14 Analog-Digital Converter 20
15 References 23
3
1 MOS Switch
A B
C
(a) MOSFET as a switch (b) I-V characteristic of MOSFET operating as a
switch
Figure 1: MOSFET as a switch
The MOS technology provides a very good switch. In gure 1a, MOS transistor that may be used
as a switch is illustrated. Terminals A and B can be considered as the two terminals of the switch,
while terminal C is the control terminal to turn on and o the switch. The MOS switch is a voltage
controlled switch. The voltage at terminal C controls the switch. Here, MOS device is assumed to be in
non-saturation, thus in on stage, the voltage across the switch V
DS
is smaller than V
GS
V
TH
. The on
state resistance of switch consists of series combination of r
d
and r
s
. The drain current in non-saturation
is given by,
I
d
=
K

W
L
_
(V
GS
V
T
)V
DS

V
2
DS
2
_
(1)
r
ON
=
1
i
d
/V
DS
|
Q
=
L
K

W [V
GS
V
T
V
DS
]
(2)
Where, Q is quiescent point of the transistor. In gure 1b the channel current as a function of the V
DS
voltage is plotted. When the V
GS
is less than V
T
, the switch is OFF. The OFF state resistance of the
switch is very high. The performance of the OFF stage is limited by the leakage currents. The leakage
currents are source-drain leakage current, source to bulk and drain to bulk leakage current. The application
of the MOS switch can be found in many circuits such as modulator, multiplexers, ltering circuits and
to simulate the resistor.
B A

Figure 2: CMOS switch


The dynamic range limitations of the MOS device switch can be overcome by CMOS switch illustrated
in gure 2. When is high, both transistors are ON providing low impedance path.
4
Vds
I
+

(a) MOSFET as
a diode
-5e-05
0
5e-05
0.0001
0.00015
0.0002
0.00025
0.0003
0.00035
0 0.5 1 1.5 2 2.5 3 3.5
I
d
Vds
(b) I-V characteristic of MOSFET operating as a
diode
Figure 3: MOSFET as a diode
2 MOS Diode
When the gate of the MOS device is tied together with the drain, the device operates in saturation region
and V
DS
becomes same as the V
GS
. The drain current is given by,
I
d
=
K

W
L
(V
GS
V
T
)
2
=

2
(V
GS
V
T
)
2
(3)
V = V
GS
= V
DS
=
_
2I
d
+V
T
(4)
The IV characteristic of this conguration is plotted in gure 3b, which is similar to that of diode. From
Equ. 4, if V and I is known then device size() can be adjusted. The output resistance of MOS diode
excluding parasitic capacitors can be given by,
r
out
=
1
g
m
+g
mbs
+g
ds

1
g
m
(5)
3 Current Sink and Source
VGG
Iout
Vout
Iout
Vout
VGG V
TH
+

(a) Current sink


VGG
Vout
Iout
VDD
Vout VGG
+|V |
TH
Iout
+

(b) Current source


Figure 4: Current Sink and Source
The current sink and sources are two terminal devices whose current at any instance of time is in-
dependent of the voltage across their terminals. In gure 4a current sink is illustrated along with its
characteristic. When the gate voltage is greater than threshold voltage and the device is in saturation it
acts like a current sink. Thus when V
out
V
GG
V
T
> 0, transistor draws almost constant current. The
with constant gate voltage output resistance is given by,
r
out
=
1 +V
DS
I
d

1
I
d
(6)
In gure 4b current source implemented with the PMOS transistor is illustrated. The condition for the
proper operation region is V
out
V
GG
+ |V
T0
| The advantage of current source and sink shown in gure
4a, 4b is their simplicity. However, there are two areas in which improvements may be needed for certain
5
VGG
Iout
Vout
+

r
(a)
Iout
Vout
VGG
VGC
+

M2
M1
(b)
Figure 5: Current Sink with improved output resistance
applications. One is to increase the output resistance resulting in more constant current over range of the
V
out
. The second improvement is to decrease the value of V
MIN
. In gure 5a, technique is illustrated to
increase the value of the output resistance. The output resistance in this case is given by, r
out
= g
m2
r
ds2
r.
The similar technique using MOS transistor instead of the resistor is illustrated in gure 5b. The output
resistance is given by, r
out
= g
m2
r
ds2
r
ds1
. Here, we get improvement in the output resistance, however
the value of the V
MIN
is also increased which is unwanted and worse eect.
2VON T +2V
+V
ON
VT
+V
ON
VT
IOUT
IREF
M2
M1 M3
M4
+
_
+
_
+
_
V
OUT
(a) Cascode Current sink
IOUT
IREF
IREF
V
OUT
V
ON
V
ON
M3
_
+
_
M4
+
_
+
_
M2
M1
(b) Improved Cascode current sink
Figure 6: Cascode Current sink
In Figure 6a standard cascode is illustrated. The V
MIN
voltage is in this case is the voltage to keep
transistors M1 and M2 in saturation that is equal to V
T
+ 2V
ON
. In gure 6b improved version of the
standard cascode current source with its characteristic is shown. Here, V
MIN
is reduced further to the
value 2V
ON
4 Current Mirror
Current mirror is extension of the current sink and source which can be used to mirror the current and as a
current amplier. In gure 7a simple current mirror is illustrated. As the gates of the both transistors are
tied together, as long as both transistors are in saturation, current of M1 is mirrored in M2, assuming that
both transistors are identical and eect of channel length modulation is absent. The output resistance of
this current mirror is r
out
1/I
d
. The rst non-linear eect that ditoriates the performance of illustrated
current mirror is channel length modulation. The second non-linear eect is oset in threshold voltage
of transistors because of process variations. The third non-linear eect is error in the aspect ratio of two
transistors that arises due to error in manufacturing process.
In gure 7b, standard cascode current mirror is illustrated that reduces ratio errors due to the dierence
in input and output voltage and improves the output resistance. The output resistance is given by,
r
out
= r
ds2
+r
ds4
+g
m4
r
ds2
r
ds4
(1 +
4
)
Another current mirror named Wilson current mirror is illustrated in gure 7c that increases the
output resistance through the negative feedback. If I
0
increases, mirror action causes current through M1
to increase. If I
I
is constant and if we assume that there is some resistance form drain of M1 (gate of M3)
6
i
I
i
O
M1 M2
(a) Simple current mirror
i
I
i
O
M1 M2
M3 M4
(b) Cascode current mirror
i
I
i
O
M1 M2
M2
(c) Wilson current mirror
Figure 7: Current mirrors
to ground, then gate voltage of M3 decreases. The output resistance for Wilson current source is given by,
r
out
= r
ds3
+r
ds2
_
1 +r
ds3
(1 +
3
) +g
m1
r
ds1
g
m3
r
ds33
1 +g
m2
r
ds2
_
(7)
5 Current and Voltage References
An ideal voltage or current reference is independent of the power supply and temperature variations.
Such voltage or current references provides stable current and voltages to CMOS circuit building blocks.
Simplest voltage reference can be built with the help of the voltage divider circuit, however the output
of such reference is directly proportional to the power supply variations. The performance of the voltage
reference can be measured in terms of sensitivity S.
S
V
REF
V
DD
=
V
REF
/V
REF
V
DD
/V
DD
=
V
DD
V
REF
_
V
REF
V
DD
_
(8)
Vref
+
VDD
R
I
Figure 8: Simple voltage reference using MOSFET
A simple way of obtaining a better voltage reference is to use active device as shown in gure 8. The
reference voltage has less dependence on the supply voltage. If eect of the channel length modulation is
ignored then reference voltage and sensitivity are given by,
V
REF
= V
T

1
R
+

2(V
DD
V
T
)
R
+
1

2
R
2
(9)
7
S
V
REF
V
DD
=
_
1
1 +(V
REF
V
T
)R
__
V
REF
V
DD
_
(10)
Here, it can be noted that the sensitivity is less than unity.
Startup
M8
M7
M3
M4
M2
M5
M6
R
M1
I1 I2
I5
I6
VDD
Figure 9: Bootstrap reference circuit
If the voltage across the active device is used to create a current and this current is somehow used
to provide original current through the device, then the current or voltage is for all practical purpose
independent of supply voltage. This technique of generating reference is called bootstrap reference. In
gure 9, realization of such circuit is shown. M3 and M4 causes currents I
1
and I
2
to be equal. Current
I
2
ows through R creating voltage I
2
R and I
1
ows through M1 causing V
gs1
voltage. Since these two
voltages are connected together equilibrium is established. If channel length modulation is neglected then
the equilibrium point can be described by,
I
Q
= I
2
=
V
T1
R
+
1

2
R
2
+
1
R

2V
T1

1
R
+
1

2
1
R
2
(11)
Here, I
2
and I
Q
are independent of V
DD
in rst order analysis. We can get I
5
and I
6
through I
2
which
can be used further. However to get desired equilibrium point, startup circuit as shown in gure 9 is
required.
6 CMOS Inverters
Active load inverter
VDD
M2
M1
Out
In
(a) Active PMOS load in-
verter
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5 3
V
O
U
T
VIN
(b) Voltage transfer characteristic curve
Figure 10: CMOS active PMOS load inverter circuit and VTC
8
In gure 10, PMOS active load inverter is illustrated. The PMOS device is connected in diode fashion
and thus it operates in the saturation region. The voltage transfer characteristic of this inverter is shown
in gure 10. From this characteristic it can been observed that, this inverter has limited gain and limited
output voltage swing. The maximum output voltage V
OUT
(max) and minimum output voltage V
OUT
(min)
can be given by,
V
out
(max) = V
DD
| V
TP
| (12)
V
out
(min) = V
DD
V
T

V
DD
V
T
_
1 +
2
/
1
(13)
The minimum output voltage V
OUT
(min) is not at lower limit (ground) because M2 is in saturation
and thus continuously current ows through it and that must ow through M1. For any MOSFET, there
is zero voltage across it only its drain-source current is zero that is not case here. Thus minimum voltage
is corresponding to the minimum value of current that passes through M1. The small signal voltage gain
and output resistance are given by,
V
out
V
in
=
g
m1
g
m2
=

N
W
1
L
2
K

P
W
2
L
1
(14)
R
out
=
1
g
ds1
+g
ds2
+g
m2

1
g
m2
(15)
Current source inverter
VDD = 3.3V
VGG
1.65V
M2
M1
Vin
Vout
(a) Current source inverter
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5 3
V
O
U
T
VIN
(b) Voltage transfer characteristic curve
Figure 11: CMOS current source inverter circuit and VTC
In gure 11a current source inverter is illustrated that has higher gain than active load inverter. Instead
of connecting the PMOS in diode fashion as a load, current source is used. The current source implemented
using common gate PMOS conguration with gate is connected to x bias voltage. The gure 11b shows
the voltage transfer characteristic of this inverter. The maximum output voltage V
out
(max) is V
DD
since
when M1 is o, the voltage across the M2 can go to zero, allowing output voltage to reach V
DD
. The
lower limit of the output voltage V
out
(min) can be found assuming M1 in non-saturation region.
V
out
(min) = (V
DD
V
T1
)
_
_
_
1
_
1
_

1
__
V
SG2
| V
T2
|
V
DD
V
T1
_
2
_1
2
_
_
_
(16)
The small signal gain and the output resistance is given by
V
out
V
in
=
g
m1
g
ds1
+g
ds2
=
_
2K

N
W
1
L
1
I
D
_1
2
_
1

1
+
2
_

I
D
(17)
r
out
=
1
g
ds1
+g
ds2
=
1
I
D
(
1
+
2
)
(18)
9
VDD
M2
M1
Vout Vin
(a) Push Pull inverter
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5 3
V
O
U
T
VIN
(b) Voltage transfer characteristic curve
Figure 12: CMOS current source inverter circuit and VTC
i
D3
i
D1
i
SS
i
D2
i
D4
VDD
M1
M2
M3
M4
Vout
Vg
M5
Vin
Figure 13: CMOS dierential amplier
Push pull inverter
In gure 12a, push pull CMOS inverter is illustrated. From the voltage transfer characteristic it can be
interpreted that this amplier has higher gain and output voltage swing is rail to rail. The largest voltage
gain can be achieved in region when both transistors M1 and M2 are in saturation. The voltage gain under
this condition is given by,
v
out
v
in
=
g
m1
+g
m2
g
ds1
+g
ds2
=
_
2/I
D
_
_
K

N
W
1
/L
1
+
_
K

P
W
2
/L
2

1
+
2
_
(19)
7 Dierential Amplier
In gure 13, CMOS dierential amplier using a PMOS current mirror load is illustrated. Under quiescent
conditions two currents in M1 and M2 are equal and summed to I
SS
, the current in current sink M5. The
current of M1 will determine the current in M3. Ideally this current is mirrored in M4. If V
GS1
= V
GS2
and M1 and M2 are matched, then currents in M1 and M2 are equal. Thus current that M4 sources to M2
should equal to the current that M2 requires, causing i
OUT
to be zero provided that load is negligible. If
V
GS1
> V
GS2
, then I
D1
increases with respect to I
D2
. Since I
SS
= i
D1
+i
D2
, this increase in i
D1
implies
an increase in i
D3
and i
D4
.However i
D2
decreases as V
GS1
is greater than V
GS2
. Therefore only way to
establish circuit current equilibrium is for i
out
to become positive and v
out
increases. If V
GS1
< V
GS2
, then
i
out
becomes negative and v
out
decreases. If the currents in current mirror are assumed to be identical,
then i
OUT
can be found by subtracting I
D2
from I
D1
. The unloaded dierential voltage gain can be found
out by nding the small signal output resistance of the dierential amplier.
r
out
=
1
g
ds2
+g
ds4
(20)
A
v
=
v
out
v
id
=
g
md
g
ds2
+g
ds4
=
g
m2
g
ds2
+g
ds4
(21)
10
The slew rate performance of the dierential amplier depends upon the value of I
SS
and the capaci-
tance connected from output node to ac ground. The slew rate is given by I
SS
/C
8 Cascode Amplier
The cascode amplier has two distinct advantages over inverting amplier. First the output impedance
provided by cascode amplier is high and second it reduces the eect of the Miller capacitance on the
input of amplier. In gure 14, simple cascode amplier is illustrated. The primary function of M2 is to
M3
M2
M1
Vin
Vout
1.52V
2.25V
VDD = 3.3V
(a) Simple cascode ampli-
er
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5 3
V
O
U
T
VIN
(b) Voltage transfer characteristic curve
Figure 14: CMOS cascode amplier circuit and VTC
keep the small signal resistance at drain of M1 low. The small signal resistance into the drain of M2 is
approximately r
ds1
r
ds2
g
m2
while resistance looking into drain of M3 is r
ds3
. The output resistance is the
parallel combination of r
ds1
r
ds2
g
m2
and r
ds3
that is approximately r
ds3
. Compared to inverter amplier
the output resistance is improved by factor of 2 and thus the gain of amplier is also improved by factor
of 2. From the voltage transfer characteristic of the amplier it can be seen that the output voltage swing
is not rail to rail. The maximum and minimum values of the output voltages are given by,
v
out
(max) = V
DD
V
SD3
(sat) (22)
v
out
(min) = V
DS1
(sat) +V
DS2
(sat) (23)
The small signal voltage gain of cascode amplier is given by,
v
out
v
in
=
g
m1
g
ds3
(24)
When the CMOS inverter is driven by the high resistance source, the miller eect essentially places the
capacitance C
2
, a capacitance between the input and output node, by the gain form eective input voltage
point to output and put in parallel to input impedance resulting dominant pole. The miller capacitance
can have negative eects on the circuit in several viewpoints. It creates dominant pole and also provides
large capacitive load to driver circuits. In case of cascode amplier the eect of the Miller capacitance
is reduced by keeping the low frequency voltage gain across M1 low, so that the C
2
is not multiplied by
the large factor. The eect of the dominant pole is removed in cascode amplier and this is very useful in
controlling the frequency response of the amplier.
The small signal gain of the cascode amplier shown in gure 14 can be increased by increasing the
DC current through M1 without changing current in M2 and M3. This can be done by connecting the DC
current source between V
DD
and drain of M1.
9 Current Amplier
The current ampliers nd many applications in analog signal processing circuits at low supply voltage
and in discrete time circuits. The input impedance of the current amplier is very low while the output
11
i
out
i
in
i
1
i
2
VDD
M1 M2
(a) Simple
i
in i
out
i
2
i
1
M1 M2
VDD
M4 M3
R
(b) Self-bias
i
out
i
in
i
1
i
2
i
VDD
M3
M2 M1
3
(c) Negative shunt feedback
Figure 15: Current mirror implementation of current amplier
resistance is very high. The current ampliers are driven by source with very high impedance and loaded
with very low resistance. There are several advantages of current ampliers over the voltage ampliers.
The rst is that, the current is not restricted by the power supply voltages and thus wider signal dynamic
range may be possible at lower supply voltage. The second advantage is that, -3dB bandwidth of a current
amplier using negative feedback amplier is independent of the closed-loop gain.
In gure 15a, simple current mirror implementation of the current amplier is illustrated that performs
reasonably good. The input resistance, output resistance and current gain are given by,
R
in
=
1
g
m1
, R
out
=
1

1
I
2
, A
i
=
W
2
/L
2
W
1
/L
1
(25)
In gure 15b, current amplier implemented with the help of self biased cascode current mirror is shown.
The cascoding increases the output resistance. However in this case the input resistance is also increased
because of presence of the self-biased resistor and that is unwanted eect. Figure 15c shows the current
amplier implemented using negative shunt feedback. This negative feedback reduces the input impedance
below the value 1/g
m
. One of the disadvantages of using negative shunt feedback to achieve low input
impedance is that at higher frequencies the loop gain will decrease and input impedance increases.
In gure 16a, the symbolic representation of the dierential current amplier is illustrated. The
dierential input current amplier input-output relationship is given by,
i
o
= A
ID
i
ID
A
IC
i
IC
= A
ID
(i
1
i
2
) A
IC
_
i
1
+i
2
2
_
(26)
i
1
i
2
i
ic
i
i
i
+

id
ic
2
2
o
(a) Dierential input Current Amplier
i
1
i
2
i
o
i
1
i
2
i
2
I 2I
I

M1 M2 M3
M4
VDD
(b) Circuit of dierential input current amplier
Figure 16: Dierential input current amplier
were A
ID
is dierential current gain and A
IC
is common mode current gain. In gure 16b, the
implementation of dierential input current amplier is shown. The minimum value of the current source
12
should be at least twice the maximum value of the i
1
and i
2
or higher. The size of the M3 and M4 decides
the current current gain of the amplier. If the higher current gain is required then output resistance has
to be modied accordingly.
10 Two Stage Op-Amp
Differential
Transconductance
stage
Compensation
Circuitry
High
Gain
Stage
Bias
Circuitry
Output
Stage
v
1
v
2
v
out
v
out
Figure 17: Block diagram of a general Two-stage op amp
In gure 17, block diagram of two stage op amp is illustrated. The rst stage is dierential transcon-
ductance stage which is followed by the high gain stage and output buer. The output buer is essential
only when op amp has to drive a very low impedance load. Ideally the op amp has innite input resistance,
innite dierential gain and zero output impedance. The practical op amp only approaches these values.
In gure 18 model of the non-ideal op amp is illustrated. The nite dierential input impedance is modeled
by R
id
and C
id
. The output resistance is modeled by the R
out
. The common mode input resistance is
modeled by R
icm
that is connected from each input terminal to ground. V
os
is the input oset voltage
necessary to make the output voltage zero. The I
os
, input oset current, is dened as the dierence of the
two bias currents I
B1
and I
B2
. Since the CMOS op amp has very high input impedance the bias currents
are approaching zero and thus oset current is almost zero. The common mode rejection ratio (CMRR)
is modeled by the voltage controlled voltage source indicated by V
1
/CMRR. This source approximates
the eect of the common mode input signal on the op amp. Two sources designated as e
2
n
and i
2
n
are used
to modeled op amp noise. These rms voltage and current noise sources with unit of mean square voltage
and mean square ampere have no polarity and are always assumed to add. The output voltage of the op
amp is given by,
*
Ideal
op amp
R
icm
R
icm
V
os
V
1
V
2
R
out
R
icm
e
n
2
i
n
2
I
B2
I
B2
I
B2
R
id
C
id
V
1
CMRR

+
+

+
V
out
Figure 18: A model of non ideal op amp
V
out
(s) = A
v
(s) [v
1
(s) v
2
(s)] A
c
(s)
_
v
1
(s) +v
2
(s)
2
_
(27)
13
where, the rst term on the right is the dierential portion of the V
out
and the second term is the common
mode portion of the output. The dierential frequency response of the op amp is typically given by,
A
v
(s) =
A
v0
_
s
p
1
1
__
s
p
2
1
__
s
p
3
1
_

(28)

2
3

|Av| dB
0dB
Figure 19: Frequency response of uncompensated op amp
where p
1
, p
2
, p
3
ect are the poles of the open loop transfer function. In general a pole designated as
p
i
can be expressed as p
i
= w
i
, where w
i
is the break frequency of pole p
i
. A
v0
is the gain of op amp
when frequency approaches to zero. In gure 19, typical frequency response of the op amp is illustrated.
The frequency
1
is much lower than the rest break away frequencies making
1
dominant inuence in
the frequency response. Another characteristic of the non-ideal op amp is the power supply rejection
ratio which is dened as the product of the ratio of the change in supply voltage to change in the output
voltage of the op amp caused by the change in power supply and open loop gain of the op amp. For
the ideal op amp PSRR is innite. The input common mode range is the range over which the input
common mode signal can vary. The output of the op amp has several limitations. First limitation is
current sink and source. Another limitation is characterized by the slew rate that is rate of change of the
output voltage with respect to time. The time taken by th output of the op amp to reach its nal value
is called the settling time. There are two major architectures of op amp. One is classical two stage op
amp and second is folded cascode op amp. Before doing the actual design of op amp, one should know
the boundary conditions and requirements of op amp. The boundary conditions are process specication,
supply voltage and range, supply current and its range, operating temperature and range. The design
requirements are gain, gain bandwidth, settling time, slew rate, phase margin, ICMR, CMRR, PSRR,
output resistance, oset voltage, noise and layout area. For the frequency compensation of the op amp
feedback and feed-forward methods are developed.
VBias
C C
L C
Vin
VDD
M4
M3
M5
M1 M2
_
+
+
_
M6
M7
VSS
R
Figure 20: Classical Two stage opamp
Op amps are generally used in negative feedback conguration. In this way, the relatively high,
inaccurate forward gain can be used with feedback to achieve a very accurate transfer function that is
function of only feedback elements only. In gure 21 the general negative feedback conguration of op amp
is shown. A(s) is the open loop gain of op amp and F(s) is the feedback path gain. The loop gain of the
14
F(s)
A(s)
_
+

V (s) in
V (s)
out
Figure 21: Negative feedback conguration of op amp
system is given by L(s) = -A(s)F(s). In order to system be stable following conditions must be satised.
|A(j
0
)F(j
0
)| < 1 (29)
Arg [A(j
0dB
)F(j
0dB
)] > 0 (30)
where,
0
is called the phase crossover frequency and it is a frequency when phase becomes 0 .
0dB
is
called the gain crossover frequency, the frequency at which the magnitude of the system becomes unity.
Larger phase margin results in less ringing of the output signal. Too much ringing can be undesirable,
so it is important to have adequeate phase margin that keeps the ringing of the output signal under
desired level. It is desired to have phase margin of at least 45 while 60 phase margin is preferred in many
applications. In gure 22a equivalent small signal model of the uncompensated op amp is illustrated. The
g
mI
v
in
CI I R
g
mII
v
1
RII
CII
vin vout
v
1
+

(a) Small signal model of uncompensated op amp


g
mI
v
in
CI I R
g
mII
v
1
RII
CII
vin vout
v
1
R z Cc
+

(b) Small signal model of compensated op amp


Figure 22: Dierential input current amplier
poles of this system are given by p
1
= 1/R
I
C
I
and p
2
= 1/R
II
C
II
.
The feedback compensation technique is also known as the miller compensation technique. In this tech-
nique the compensation capacitor C
C
is connected between the output and input of the second transcon-
ductance stage. The resultant location of the poles are given by the
p

1
=
1
g
mII
R
I
R
II
C
C
(31)
p

2
=
g
mII
C
C
C
I
C
II
+C
II
C
C
+C
I
C
C

g
mII
C
I
I
(32)
Here, it is assumed that C
I
I is much greater than C
I
and C
C
is greater than C
I
. The location of the zero
is given by,
z
1
=
g
mII
C
C
(33)
This zero is located on the right hand side of s-plane. The task of the op amp compensation includes
moving poles and zeros other than dominant pole(p
1
) away from the origin of s-plane that results in
desired eect of phase shift as shown in gure. The dominant pole is also called the Miller pole. The unity
gain bandwidth of the compensated op amp is given by GB g
m2
/C
C
. It can be shown that if the zero
is placed at least ten times higher than GB, then in order to achieve 60 phase margin, the second pole p
2
must be placed at least 2.22 times higher than GB. The right hand zero resulting from the feed-forward
path through the compensation capacitor tends to limit the GB that might otherwise be achieved if the
zero was not present. There are several ways to eliminate the eect of this zero. The simplest way is to
insert nulling resistor in series with C
C
. The small signal model of the resulting circuit is illustrated in
gure 22b. The location of the new zero is given by,
z
1
=
1
C
C
(1/g
mII
Rz)
(34)
This shows that the value of R
Z
can control the location of the zero. If the z
1
is placed exactly on the
p
2
, then the eect of the both z
1
and p
2
can be eliminated. The eect of the remaining poles remains
present.This compensation concept is used widely in design of two sate op amp.
15
11 Cascode Op-Amp
VBias
VBias
Vin
2
Vin
2
VO1
VDD
M3 M4
MC3 MC4
MC1 MC2
M1 M2
M5
R
+
_
_
+
(a) Cascode in rst stage
VBias
C C
L C
Vin
VDD
M4
M3
M5
M1 M2
_
+
+
_
M6
MC7
M7
VSS
VBN
VBP
R
MC6
(b) Cascode in second stage
Figure 23: Two stage cascode op amp
The two stage op amp mentioned in previous section is used widely. However its performance does not
meet the requirements of certain applications. The performance limitations of two stage op amp op amp
includes insucient gain and bandwidth. The gain of the two stage op amp can be increased by (1) adding
additional gain stages, (2) increasing transconductance of rst or second stage (3) increasing the output
resistance of rst or second stage. Since the rst stage suggests to increase the number of gain stage, it
does not seem attractive. The third approach is more attractive because increasing output resistance is
more power ecient than increasing the transconductance. The cascode ampliers utilize third approach
to increase gain. The increase in gain is possible by increasing output resistance of rst or second stage.
In gure 23a shows cascode op amp in which the gain is improved by improving the output resistance of
rst stage. The transistors MC3 and MC4 increases the output resistance of the rst stage. The output
resistance of the rst stage is given by,
R
I
= (g
mC2
r
dsC2
r
ds2
) || (g
mC4
r
dsC4
r
ds4
) (35)
As the output resistance is improved by the factor of two, the gain will also improve by the factor of
two. In gure 23b cascode amplier with cacoding in second stage is illustrated. The output resistance of
the second stage in this case is given by,
R
I
I = (g
mC6
r
dsC6
r
ds6
) || (g
mC7
r
dsC7
r
ds7
) (36)
With compared to standard two stage op amp, it is possible to improve the gain by up to factor of 100.
However the it decreases the stability of the system and increase the output resistance of the op amp.
These both are undesired eects, thus trade o between the stability and gain has to be considered.
12 Comparators
A comparator is a circuit with binary output which depends upon the comparison of two analog input
signals. In gure 24b, transfer curve of ideal comparator is illustrated. Mathematically, the comparator
can be modeled as the voltage controlled voltage source. The output of the comparator is high (V
OH
) when
the dierence of the analog input signal is positive, otherwise the output is low(V
OL
). The ideal comparator
has innitely high gain. In gure 24c, the transfer curve of comparator with nite gain is illustrated. V
IH
and V
IL
represents the input voltage dierence V
P
V
N
needed to saturate the output comparator at its
upper and lower limit respectively. Another non-ideal eect in comparator is oset voltage. If the output
did not change until the input dierence reached a value V
OS
then the dierence would be dened as oset
voltage. If the oset voltage is constant then it is not a problem, but it varies randomly from circuit to
circuit and thus dicult to predict exact value of the oset voltage. The delay is present between the input
16
o v
p v
vn
(a) Comparator Symbol
VOH
VO
VP VN
VOL
(b) Transfer characteristic of Ideal com-
parator
VOH
VO
VP VN
VOL
VIL
VIH
(c) Transfer characteristic of compara-
tor with nite gain
VOL
VOH
Vout
VIN
VTRP
VTRP
+
(d) Transfer characteristic of compara-
tor with hysteresis
Figure 24
voltage excitation and output response. This delay is called the propagation delay. The ideal comparator
has zero propagation delay. The propagation delay aect the speed of operation or response adversely.
VBias
Vin
Vin
Vout
+
+
VDD
VSS
M1 M2
M3 M4
M5 M6
M7
M8
M9
(a) Clamped Push-pull output comparator
Vin
Vin

1
Vos
Vout
CAZ
+
+
(b) Oset auto zero technique
Figure 25
Simple two stage op amp operating in open loop conguration can be used as a comparator. However
such simple comparator suers from the problems of propagation delay due to transition of the output of
rst stage and second stage. To overcome this problem clamped comparator as shown in gure 25a can be
used instead of simple two stage op amp. In clamped comparator, diode connected transistor is used in
place of mirror connected load. This reduces the gain, but it makes push pull output stage and increasing
current sink and source capacity of the output. The lower gain of this comparator can be compensated
by providing cascoding in output.
For precision applications such as high resolution ADC, large input oset voltage cannot be tolerated
and design of the comparator becomes very dicult task. In order to overcome the problem of input oset
voltage, auto-zeroing technique as illustrated in gure 25b can be used. The task of the comparison is
done in two phases. During the rst stage switch
1
is close while switch
2
is opened. In second stage,
switch
2
is closed and
1
is opened. In rst phase, the capacitor C
AZ
is charged to value same as the
input oset voltage with polarity as shown in gure 25b. In second phase the input voltages are applied
to the comparator. The polarity of the voltage across capacitor C
AZ
is in such a way that it cancels the
input oset voltage. The switches in CMOS technology can be implemented either with the help of single
17
mos transistor or transmission gate.
in v
o v
1 R
2 R
(a) Hysteresis using external positive
feedback
Ibias
Vin1
Vout
Vin2
M1
M2
M3
M9
M11
M4
M6
M7
M5
M8
M10
M12
(b) Hysteresis using internal positive feedback
Figure 26
If high speed comparator is placed in noisy environment to detect the signal around its threshold, then
due to large noise, the output becomes very. In such situation, the hysteresis is needed in the characteristic
of the comparator. The transfer characteristic of comparator with the hysteresis is illustrated in gure
24d. In gure 26a, the comparator with hysteresis is shown. In this circuit external positive feedback is
used to implement the hysteresis. In gure 26b, the comparator with output stage is illustrated that uses
internal positive feedback.
13 Digital-Analog Converter
Voltage
Reference
Scaling
Network
Output
Amplifier
Binary Switches
b0 b2 b1 bN1
VREF DV REF
VOUT
(a) General Block Diagram of DAC
Serial Parallel
Charge Current Voltage
Voltage and Charge
DigitalAnalog Converters
Charge
Slow Fast
(b) Classication of DAC
Figure 27
Digital-Analog converter converts the digital data into equivalent analog signal. In gure 27a, block
diagram of the DAC is illustrated. The output voltage of the DAC is given by,
V
OUT
= KV
REF
_
b
0
2
1
+b
1
2
2
+ +b
N1
2
N

(37)
The number of bits that can be applied at the input of the DAC is called resolution and it is expressed
in terms of the bits. For each input word, there is an unique output. The output levels are separated
by LSB. Thus LSB can be given by as V
REF
/2
N
. When the input word is increased by one, the output
of DAC is increased by LSB. The full scale value of DAC is dened as th dierence between the analog
output for the largest word and analog output for smallest digital word. The dynamic range of DAC is
the ratio of full scale range to LSB. In decibels dynamic range is given by 6.02N, where N is resolution of
DAC. Integral nonlinearity (INL) for DAC is the maximum dierence between the actual nite resolution
characteristic and ideal nite resolution characteristic measured vertically. Integral Nonlinearity can be
expressed as a percentage of full scale range or in terms of the least signicant bit. Dierential non-linearity
is the measure of separation between adjacent levels measured at each vertical jump.
In gure 27b, broad classication is illustrated. This classication is based on the mode of digital input
and the methods utilize for the conversion. In gure 28, general block diagram of the current scaling DAC
18
I0
I1
I2
N1 I
REF V
Current
Scaling
Network
OUT V
F R
Digital Input Word
Figure 28: Block diagram of current scaling DAC
is shown. Here, V
REF
is converted into the set of the binary weighed currents. These binary weighed
currents are summed up to generate the output voltage. The general equation of output voltage for such
DAC is given by,
V
OUT
= R
F
i
out
= R
F
(I
0
+I
1
+I
2
+ +I
N1
) (38)
out V
Iout
REF V
I0 I1
I2 IN1
2
N1
R
KR
R
2R 4R
Figure 29: Binary weighed resistor DAC implementation
The current scaling network can be implemented in dierent ways. The simplest way is to use network of
binary weighed resistors as shown in gure 29.The advantage of binary weighed network is the insensitivity
to parasitic capacitance and thus very fast. However the values of resistor required are spread over wide
span. For N bit DAC the ratio of largest value resistor to smallest value resistor is 2
N1
. If the value of
MSB resistors are not accurate then the performance of DAC is very poor.
out V
REF V
0 S 1 S 2 S N1 S
I0
I1 I2
Iout
KR
R R R
2R 2R 2R 2R
Figure 30: R-2R resistor DAC implementation
The requirements of the large value resistors can be overcome by using R-2R ladder network as shown
in gure 30. This network uses the resistor of only two values R and 2R. These resistor values can be
implemented easily with the help of three equal valued resistors. The value of currents shown in gure 30
is given by,
I
0
=
V
REF
2R
, I
1
=
V
REF
4R
, , I
N1
=
V
REF
2
N
R
(39)
The DAC implemented with R-2R ladder is also as fast as binary weighed DAC structure.
The third way of implementing the current scaling structure is to use binary weighed current sinks.
The binary weighed current sinks can be implemented with the help of MOSFETs. If the width and
length of the MOSFETs are adjusted properly then proper ratio in the value of the current sinks can
be obtained. However the matching requirements of the transistors must be satised in order to have
19
better performance. To increase conversion speed current sinks can be implemented with the help of BJT
transistors instead of MOSFETs.
V
1
V
2
V
3
2
N
V
Scaling
Voltage
Network
Decoder
Logic
V
REF
V
OUT
Digital Input Word
Figure 31: Block diagram of Voltage Scaling DAC
In gure 31, general block diagram of the voltage scaling DAC is illustrated. The voltage scaling
network converts the V
REF
into binary weighed voltages and decoder connects one of these voltages to
output. Since structure of voltage scaling DAC is very regular, it is used widely in MOS technology. The
area requirements of such DAC is more if the number of bits are 8 or more. This structure suers from
the parasitic capacitance present at each voltage tapping.
0 S 1 S 2 S N1 S
out V
REF V

2

2

2

2
1
c
2
c
2
c
2
N1 c
Figure 32: Charge Scaling DAC implementation
In gure 32, the implementation of the charge scaling DAC is shown. The conversion is done in two
phases and non-overlapping clocks are used. During
1
, the top and bottom pates of DAC are grounded
and in phase
2
, the capacitors are either connected to ground and V
REF
depending upon the input bits.
Since the capacitors are binary weighed, the output is given by,
V
OUT
= V
REF
_
b
0
2
1
+b
1
2
2
+ +b
N1
2
N

(40)
The performance of this DAC is limited by the accuracy of the capacitors and their values. In MOS
technology, since the capacitance ratio with accuracy of 0.1% can be provided, the DAC of 10-bits are
possible with this structure.
14 Analog-Digital Converter
Prefilter Sample/Hold Quantizer Encoder y(kT) x(t)
Figure 33: General block diagram of ADC
In gure 33, general block diagram of ADC is illustrated. The pre-lter is also known as the anti-aliasing
lter, which is a low pass lter and removes the higher frequency components from the input signal. The
presence of this lter avoids aliasing of higher frequency components back to base band. The anti-aliasing
lter is followed by the sample and hold circuit. The sample-hold circuit samples and maintains the level
of the input analog signal for the certain period of time generally known as the conversion time. The
conversion is accomplished by quantizer. Generally quantizer has 2
N
subranges, where N is the number
of bits of output. The quantizer is followed is followed by the encoder, that encodes the output of the
quantizer. Within conversion time analog input is converted in digital word.
20
According to Nyquist rate, to avoid anti-aliasing, the sampling rate f
S
must be twice the bandwidth f
B
of the signal. To increase the bandwidth of the ADC, 0.5f
S
should be very close to f
B
. But this requires the
pre-lter with very sharp response. The ADCs those work this principle are known as Nyquist ADC. The
ADCs which sample the input signal at much higher rate than Nyquist rate are called over sampled ADCs.
The resolution of ADC is the smallest analog range that can be distinguished by the ADC. Resolution may
be expressed with respect to full scale but it is typically given in the numbers of bits N, where converted
signal has 2
N
possible output stages.
ref V
in V int V
th V
Positive
Integrator
Digital
Control
Counter
output
carry
Binary output
Figure 34: General block diagram of dual-slope adc
The serial ADC performs the operation until the conversion is completed. In gure 34, dual slope ADC
is shown. First the input charges the integrator for xed amount of time. So depending upon the value
of the input signal, integrator is charged. Then V
REF
discharges the integrator. Since V
REF
is constant,
discharge rate of integrator is constant for all value of input, so discharge time depends upon the value of
the input signal. The digital control block allows counter to run for the discharging time. So depending
upon the value of input, output of counter is set. Such ADCs are slow, but provides very high resolution.
Typical values for such serial ADCs are conversion frequencies less than 100Hz and resolution greater than
12bits.
Output
Register
SAR
Logic
V
Ref
V
in
DAC Clock
Output
Figure 35: Block diagram of SAR adc
In gure 35, general block diagram of the successive approximation ADC is illustrated. In this ADC,
the conversion is done in N discrete steps, where N is the resolution of the ADC. In each step one bit is
changed, the resultant digital word is converted to analog signal with help of the DAC for comparing it
with input signal. Depending upon the output of comparator, during next successive step, another bit is
changed. Such ADCs are medium speed and used very widely. As the resolution of such ADC increases,
the conversion time also increases.
The ash or parallel ADCs are the fastest ADC. In ash ADC, input signal is directly compared with
dierent voltage level parallel. The dierent voltage levels are generated from the V
REF
voltage and
resistive network. In such ADCs, for parallel comparison, 2
N
comparators are needed, where N is the
resolution of the ADC. So as the resolution of ADC increases, design of ash ADC becomes challenging.
Another challenge is to generate accurate set of dierent voltage using resistive network. With ash ADC
of 8-bit sampling rate of 1G and even more can be achieved.
The problems encountered in designing ash ADC with higher resolutions can be overcome in folding
ADC. The folding ADC is one type of pipelined ADC in which the input is split into two parallel path. One
path consists of course quantizer which converts input into 2
N1
values and generates N1 bits. In second
path input is folded into single subrange and converted into 2
N2
stages using ne quantizer that produces
21
Analog
Input
Folding
Processor
Fine
Quantizer
Coarse
Quantizer
Encoding
Logic
Digital
Output
Processor
Figure 36: Block diagram of folded ADC
DeltaSigma
Modulator
Decimation
Filter
I/P O/P
Figure 37: Block diagram of delta-sigma ADC
N2 bits. The en-coder combines these two output into single digital word of N1+N2 bits. For 6 bit ash
ADC 63 comparators are needed but for folded ADC if N1=2 and N2=4, then only 18 comparators are
needed. The advantage of the folding ADC is that the power consumption and area requirements are less
compared to ash ADC with almost same conversion speed.
The Delta-Sigma ADC is example of oversampled ADC. In this case sampling rate is much higher than
the nyquist sampling rate. Such ADC is also known as the noise shaping ADC. Depending upon the oder
of the delta-sigma modulator used in ADC, quantization noise is shifted toward higher frequencies which
is ltered latter by the low pass lter providing better conversion. In gure 38, rst order delta-sigma
modulator is illustrated. Usually rst and second order delta-sigma modulators are used in ADCs. The
output of Delta-sigma modulator is bit stream which is converted in to digital word with the help of the
decimation lter. The decimation lter has comb lter like response.
Integrator
1bit DAC
1bit ADC Input O/p
+
Figure 38: Delta-Sigma Modulator
22
15 References
1. Book : CMOS Analog Circuit Design, Second Edition, Philip Allen, Douglas Holberg, Oxford Uni-
versity Press, ISBN-10: 0-19-806440-3
2. Book : Design of Analog CMOS Integrated Circuits, Behzad Razavi, Tata McGraw-Hill
23