1
Power Semiconductor
Devices
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Lesson
1
Power Electronics
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Introduction
This lesson provides the reader the following:
(i) Create an awareness of the general nature of Power electronic equipment;
(ii) Brief idea about topics of study involved,
(iii) The key features of the principal Power Electronic Devices;
(iv) An idea about which device to choose for a particular application.
(v) A few issues like base drive and protection of PE devices and equipment common to
most varieties.
Power Electronics is the art of converting electrical energy from one form to another in an
efficient, clean, compact, and robust manner for convenient utilisation.
A passenger lift in a modern building equipped with a VariableVoltageVariableSpeed
inductionmachine drive offers a comfortable ride and stops exactly at the floor level. Behind the
scene it consumes less power with reduced stresses on the motor and corruption of the utility
mains.
Fig. 1.1 The block diagram of a typical Power Electronic converter
Power Electronics involves the study of
Power semiconductor devices  their physics, characteristics, drive requirements and their
protection for optimum utilisation of their capacities,
Power converter topologies involving them,
Control strategies of the converters,
Digital, analogue and microelectronics involved,
Capacitive and magnetic energy storage elements,
Rotating and static electrical devices,
Quality of waveforms generated,
Electro Magnetic and Radio Frequency Interference,
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Thermal Management
The typical converter in Fig. 1.1 illustrates the multidisciplinary nature of this subject.
How is Power electronics distinct from linear electronics?
It is not primarily in their power handling capacities.
While power management IC's in mobile sets working on Power Electronic principles are
meant to handle only a few milliwatts, large linear audio amplifiers are rated at a few thousand
watts.
The utilisation of the Bipolar junction transistor, Fig. 1.2 in the two types of amplifiers best
symbolises the difference. In Power Electronics all devices are operated in the switching mode 
either 'FULLYON' or 'FULLYOFF' states. The linear amplifier concentrates on fidelity in
signal amplification, requiring transistors to operate strictly in the linear (active) zone, Fig 1.3.
Saturation and cutoff zones in the V
CE
 I
C
plane are avoided. In a Power electronic switching
amplifier, only those areas in the V
CE
 I
C
plane which have been skirted above, are suitable. On
state dissipation is minimum if the device is in saturation (or quasisaturation for optimising
other losses). In the offstate also, losses are minimum if the BJ T is reverse biased. A BJ T switch
will try to traverse the active zone as fast as possible to minimise switching losses.
Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage)
amplifier stage and (b) switching (power) amplifier
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Fig 1.3 Operating zones for operating a Bipolar Junction Transistor as a linear and a
switching amplifier
Linear operation Linear operation Switching operation Switching operation
Active zone selected:
Good linearity between input/output
Active zone avoided :
High losses, encountered only during
transients
Saturation & cutoff zones avoided: poor
linearity
Saturation & cutoff (negative bias) zones
selected: low losses
Transistor biased to operate around
quiescent point
No concept of quiescent point
Common emitter, Common collector,
common base modes
Transistor driven directly at base  emitter
and load either on collector or emitter
Output transistor barely protected SwitchingAidNetwork (SAN) and other
protection to main transistor
Utilisation of transistor rating of secondary
importance
Utilisation of transistor rating optimised
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An example illustrating the linear and switching solutions to a power supply specification will
emphasise the difference.
230 V
Series regulator 
high losses
Line freq transformer:
heavy, lossy
(a)
230 V
Highfreq Dutyratio
(ON/OFF) control
 low losses
Ferrite core HF transfr:
Light, efficient
(b)
Spec: Input : 230 V, 50 Hz, Output: 12 V regulated DC, 20 W
Fig. 1.4 (a) A Linear regulator and (b) a switching regulator solution of the specification
above
The linear solution, Fig. 1.4 (a), to this quite common specification would first step down the
supply voltage to 12012 V through a power frequency transformer. The output would be
rectified using Power frequency diodes, electrolytic capacitor filter and then series regulated
using a chip or a audio power transistor. The tantalum capacitor filter would follow. The balance
of the voltage between the output of the rectifier and the output drops across the regulator device
which also carries the full load current. The power loss is therefore considerable. Also, the step
down ironcore transformer is both heavy, and lossy. However, only twicelinefrequency ripples
appear at the output and material cost and technical knowhow required is low.
In the switching solution Fig. 1.4 (b) using a MOSFET driven flyback converter, first the line
voltage is rectified and then isolated, steppeddown and regulated. A ferritecore highfrequency
(HF) transformer is used. Losses are negligible compared to the first solution and the converter is
extremely light. However significant high frequency (related to the switching frequency) noise
appear at the output which can only be minimised through the use of costly 'grass' capacitors.
Power Semiconductor device  history
Power electronics and converters utilizing them made a head start when the first device the
Silicon Controlled Rectifier was proposed by Bell Labs and commercially produced by General
Electric in the earlier fifties. The Mercury Arc Rectifiers were well in use by that time and the
robust and compact SCR first started replacing it in the rectifiers and cycloconverters. The
necessity arose of extending the application of the SCR beyond the linecommutated mode of
action, which called for external measures to circumvent its turnoff incapability via its control
terminals. Various turnoff schemes were proposed and their classification was suggested but it
became increasingly obvious that a device with turnoff capability was desirable, which would
permit it a wider application. The turnoff networks and aids were impractical at higher powers.
The Bipolar transistor, which had by the sixties been developed to handle a few tens of
amperes and block a few hundred volts, arrived as the first competitor to the SCR. It is superior
to the SCR in its turnoff capability, which could be exercised via its control terminals. This
permitted the replacement of the SCR in all forcedcommutated inverters and choppers.
However, the gain (power) of the SCR is a few decades superior to that of the Bipolar transistor
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and the high base currents required to switch the Bipolar spawned the Darlington. Three or more
stage Darlingtons are available as a single chip complete with accessories for its convenient
drive. Higher operating frequencies were obtainable with a discrete Bipolars compared to the
'fast' invertergrade SCRs permitting reduction of filter components. But the Darlington's
operating frequency had to be reduced to permit a sequential turnoff of the drivers and the main
transistor. Further, the incapability of the Bipolar to block reverse voltages restricted its use.
The Power MOSFET burst into the scene commercially near the end seventies. This device
also represents the first successful marriage between modern integrated circuit and discrete
power semiconductor manufacturing technologies. Its voltage drive capability giving it again a
higher gain, the ease of its paralleling and most importantly the much higher operating
frequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub10 KW range
mainly for SMPS type of applications. Extension of VLSI manufacturing facilities for the
MOSFET reduced its price visvis the Bipolar also. However, being a majority carrier device
its onstate voltage is dictated by the R
DS(ON)
of the device, which in turn is proportional to about
V
2.3
DSS
rating of the MOSFET. Consequently, highvoltage MOSFETS are not commercially
viable.
Improvements were being tried out on the SCR regarding its turnoff capability mostly by
reducing the turnon gain. Different versions of the Gateturnoff device, the Gate turnoff
Thyristor (GTO), were proposed by various manufacturers  each advocating their own symbol
for the device. The requirement for an extremely high turnoff control current via the gate and
the comparatively higher cost of the device restricted its application only to inverters rated above
a few hundred KVA.
The lookout for a more efficient, cheap, fast and robust turnoffable device proceeded in
different directions with MOS drives for both the basic thysistor and the Bipolar. The Insulated
Gate Bipolar Transistor (IGBT) basically a MOSFET driven Bipolar from its terminal
characteristics has been a successful proposition with devices being made available at about 4
KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive saw
it totally removing the Bipolar from practically all applications. Industrially, only the MOSFET
has been able to continue in the sub 10 KVA range primarily because of its high switching
frequency. The IGBT has also pushed up the GTO to applications above 25 MVA.
Subsequent developments in converter topologies especially the threelevel inverter
permitted use of the IGBT in converters of 5 MVA range. However at ratings above that the
GTO (6KV/6KA device of Mitsubishi) based converters had some space. Only SCR based
converters are possible at the highest range where linecommutated or loadcommutated
converters were the only solution. The surge current, the peak repetition voltage and I
2
t ratings
are applicable only to the thyristors making them more robust, specially thermally, than the
transistors of all varieties.
1200V Version 3 ASIPM
Presently there are few hybrid devices and Intelligent Power Modules (IPM) are marketed by
some manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A
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IEGT (injectionenhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (Integrated
Gate Commutated Thyristors) of ABB which are promising at the higher power ranges.
However these new devices must prove themselves before they are accepted by the industry at
large.
Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about
2 eV that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbide
is the only wide band gap semiconductor among gallium nitride (GaN, E
G
=3.4 eV), aluminum
nitride (AlN, E
G
=6.2 eV), and silicon carbide that possesses a highquality native oxide suitable
for use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 times
higher than in silicon. This is important for highvoltage power switching transistors. For
example, a device of a given size in SiC will have a blocking voltage 8 times higher than the
same device in silicon. More importantly, the onresistance of the SiC device will be about two
decades lower than the silicon device. Consequently, the efficiency of the power converter is
higher. In addition, SiCbased semiconductor switches can operate at high temperatures
(~600 C) without much change in their electrical properties. Thus the converter has a higher
reliability. Reduced losses and allowable higher operating temperatures result in smaller heatsink
size. Moreover, the high frequency operating capability of SiC converters lowers the filtering
requirement and the filter size. As a result, they are compact, light, reliable, and efficient and
have a high power density. These qualities satisfy the requirements of power converters for most
applications and they are expected to be the devices of the future.
Ratings have been progressively increasing for all devices while the newer devices offer
substantially better performance. With the SCR and the pindiodes, so called because of the
sandwiched intrinsic ilayer between the p and n layers, having mostly linecommutated
converter applications, emphasis was mostly on their static characteristics  forward and reverse
voltage blocking, current carrying and overcurrent ratings, onstate forward voltage etc and also
on issues like paralleling and series operation of the devices. As the operating speeds of the
devices increased, the dynamic (switching) characteristics of the devices assumed greater
importance as most of the dissipation was during these transients. Attention turned to the
development of efficient drive networks and protection techniques which were found to enhance
the performance of the devices and their peak power handling capacities. Issues related to
paralleling were resolved by the system designer within the device itself like in MOSFETS,
while the converter topology was required to take care of their series operation as in multilevel
converters.
The range of power devices thus developed over the last few decades can be represented as a
tree, Fig. 1.5, on the basis of their controllability and other dominant features.
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Fig. 1.5 Power semiconductor device variety
Power Diodes
Silicon Power diodes are the successors of Selenium rectifiers having significantly improved
forward characteristics and voltage ratings. They are classified mainly by their turnoff
(dynamic) characteristics Fig. 1.6. The minority carriers in the diodes require finite time  t
rr
(reverse recovery time) to recombine with opposite charges and neutralise. Large values of Q
rr
(=
Q
1
+Q
2
)  the charge to be dissipated as a negative current when the and diode turns off and t
rr
(=t
2
 t
0
)  the time it takes to regain its blocking features, impose strong current stresses on the
controlled device in series. Also a 'snappy' type of recovery of the diode effects high di/dt
voltages on all associated power device in the converter because of load or stray inductances
present in the network. There are broadly three types of diodes used in Power electronic
applications:
Linefrequency diodes: These PIN diodes with generalpurpose rectifier type applications, are
available at the highest voltage (~5kV) and current ratings (~5kA) and have excellent over
current (surge rating about six times average current rating) and surgevoltage withstand
capability. They have relatively large Q
rr
and t
rr
specifications.
SCR
GTO
TRIAC
POWER SILICON
DIODES
FREDS
SCHOTTKY
RECTIFIERS
ACCESSORIES
DIAC
Zenner
MOV
POWER SEMICONDUCTOR
DEVICES
UNCONTROLLED CONTROLLED
NONREGENERATIVE REGENERATIVE
BJT
MOSFET
IGBT
INTEGRATED
IGCT
PIC
INTELLIGENT
POWER MODULES
Q1 Q2
SNAPPY
SOFT
di
F
/dt
I
RM
V
RM
t
o
t
0
t
1
t
2
Fig. 1.6 Typical turnoff dynamics of a soft and a 'snappy' diode'
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Fast recovery diodes: Fast recovery diffused diodes and fast recovery epitaxial diodes, FRED's,
have significantly lower Q and t
rr rr
(~1.0 sec). They are available at high powers and are
mainly used in association with fast controlleddevices as freewheeling or DCDC choppers and
rectifier applications. Fast recovery diodes also find application in induction heating, UPS and
traction.
Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without any
Q
rr..
However, they are available with voltage ratings up to a hundred volts only though current
ratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedom
from minority carrier recovery permits reduced snubber requirements. Schottky diodes face no
competition in low voltage SPMS applications and in instrumentation.
Silicon Controlled Rectifier (SCR)
The Silicon Controlled Rectifier is the most popular of the thyristor family of four layer
regenerative devices. It is normally turned on by the application of a gate pulse when a forward
bias voltage is present at the main terminals. However, being regenerative or 'latching', it cannot
be turned off via the gate terminals specially at the extremely high amplification factor of the
gate. There are two main types of SCR's.
Converter grade or Phase Control thyristors These devices are the work horses of the
Power Electronics. They are turned off by natural (line) commutation and are reverse biased at
least for a few milliseconds subsequent to a conduction period. No fast switching feature is
desired of these devices. They are available at voltage ratings in excess of 5 KV starting from
about 50 V and current ratings of about 5 KA. The largest converters for HVDC transmission are
built with seriesparallel combination of these devices. Conduction voltages are device voltage
rating dependent and range between 1.5 V (600V) to about 3.0 V (+5 KV). These devices are
unsuitable for any 'forcedcommutated' circuit requiring unwieldy large commutation
components.
The dynamic di/dt and dv/dt capabilities of the SCR have vastly improved over the years
borrowing emitter shorting and other techniques adopted for the faster variety. The requirement
for hard gate drives and di/dt limting inductors have been eliminated in the process.
Inverter grade thyristors: Turnoff times of these thyristors range from about 5 to 50 secs
when hard switched. They are thus called fast or 'inverter grade' SCR's. The SCR's are mainly
used in circuits that are operated on DC supplies and no alternating voltage is available to turn
them off. Commutation networks have to be added to the basic converter only to turnoff the
SCR's. The efficiency, size and weight of these networks are directly related to the turnoff time,
t
q
of the SCR. The commutation circuits utilised resonant networks or charged capacitors. Quite
a few commutation networks were designed and some like the McMurrayBedford became
widely accepted.
Asymmetrical, lightactivated, reverse conducting SCR's Quite a few varieties of the
basic SCR have been proposed for specific applications. The Asymmetrical thyristor is
convenient when reactive powers are involved and the light activated SCR assists in paralleling
or series operation.
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MOSFET
The Power MOSFET technology has mostly reached maturity and is the most popular device
for SMPS, lighting ballast type of application where high switching frequencies are desired but
operating voltages are low. Being a voltage fed, majority carrier device (resistive behaviour)
with a typically rectangular Safe Operating Area, it can be conveniently utilized. Utilising shared
manufacturing processes, comparative costs of MOSFETs are attractive. For low frequency
applications, where the currents drawn by the equivalent capacitances across its terminals are
small, it can also be driven directly by integrated circuits. These capacitances are the main
hindrance to operating the MOSFETS at speeds of several MHz. The resistive characteristics of
its main terminals permit easy paralleling externally also. At high current low voltage
applications the MOSFET offers best conduction voltage specifications as the R
DS(ON)
specification is current rating dependent. However, the inferior features of the inherent anti
parallel diode and its higher conduction losses at power frequencies and voltage levels restrict its
wider application.
The IGBT
It is a voltage controlled fourlayer device with the advantages of the MOSFET driver
and the Bipolar Main terminal. IGBTs can be classified as punchthrough (PT) and nonpunch
through (NPT) structures. In the punchthrough IGBT, a better tradeoff between the forward
voltage drop and turnoff time can be achieved. Punchthrough IGBTs are available up to about
1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are more
robust than PT IGBTs particularly under short circuit conditions. However they have a higher
forward voltage drop than the PT IGBTs. Its switching times can be controlled by suitably
shaping the drive signal. This gives the IGBT a number of advantages: it does not require
protective circuits, it can be connected in parallel without difficulty, and series connection is
possible without dv/dt snubbers. The IGBT is presently one of the most popular device in view
of its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square Safe
Operating Area devoid of a Second Breakdown region.
The GTO
The GTO is a power switching device that can be turned on by a short pulse of gate current and
turned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anode
current to be turned off. Hence there is no need for an external commutation circuit to turn it off.
Because turnoff is provided by bypassing carriers directly to the gate circuit, its turnoff time is
short, thus giving it more capability for highfrequency operation than thyristors. The GTO
symbol and turnoff characteristics are shown in Fig. 30.3. GTOs have the I
2
t withstand
capability and hence can be protected by semiconductor fuses. For reliable operation of GTOs,
the critical aspects are proper design of the gate turnoff circuit and the snubber circuit.
Power Converter Topologies
A Power Electronic Converter processes the available form to another having a different
frequency and/or voltage magnitude. There can be four basic types of converters depending upon
the function performed:
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CONVERSION
FROM/TO
NAME FUNCTION SYMBOL
DC to DC Chopper Constant to variable DC or
variable to constant DC
DC to AC Inverter DC to AC of desired voltage and
frequency
~
AC to DC Rectifier AC to unipolar (DC) current
~
Cycloconverter,
ACPAC,
Matrix
converter
AC to AC AC of desired frequency and/or
magnitude from generally line
AC
~
~
Base / gate drive circuit
All discrete controlled devices, regenerative or otherwise have three terminals. Two of these are
the Main Terminals. One of the Main Terminals and the third form the Control Terminal. The
amplification factor of all the devices (barring the now practically obsolete BJ T) are quite high,
though turnon gain is not equal to turnoff gain. The drive circuit is required to satisfy the
control terminal characteristics to efficiently tunon each of the devices of the converter, turn
them off, if possible, again optimally and also to protect the device against faults, mostly over
currents. Being driven by a common controller, the drives must also be isolated from each other
as the potentials of the Main Terminal which doubles as a Control terminal are different at
various locations of the converter. Gateturnoffable devices require precise gate drive
waveform for optimal switching. This necessitates a waveshaping amplifier. This amplifier is
located after the isolation stage.
Thus separate isolated power supplies are also required for each Power device in the
converter (the ones having a common Control Terminal  say the Emitter in an IGBT  may
require a few less). There are functionally two types of isolators: the pulse transformer which
can transmit after isolation, in a multidevice converter, both the unshaped signal and power and
optical isolators which transmit only the signal. The former is sufficient for a SCR without
isolated power supplies at the secondary. The latter is a must for practically all other devices.
Fig. 1.7 illustrates to typical drive circuits for an IGBT and an SCR.
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IGBT
V
ref
TIMER
COMPARATOR
Fig. 1.7 Simple gatedrive and protection circuit for a standalone IGBT and a SCR
Protection of Power devices and converters
Power electronic converters often operate from the utility mains and are exposed to the
disturbances associated with it. Even otherwise, the transients associated with switching circuits
and faults that occur at the load point stress converters and devices. Consequently, several
protection schemes must be incorporated in a converter. It is necessary to protect both the Main
Terminals and the control terminals. Some of these techniques are common for all devices and
converters. However, differences in essential features of devices call for special protection
schemes particular for those devices. The IGBT must be protected against latching, and similarly
the GTO's turnoff drive is to be disabled if the Anode current exceeds the maximum permissible
turnoffable current specification. Power semiconductor devices are commonly protected
against:
1. Overcurrent;
2. di/dt;
3. Voltage spike or overvoltage;
4. dv/dt ;
5. Gateunder voltage;
6. Over voltage at gate;
7. Excessive temperature rise;
8. Electrostatic discharge;
Semiconductor devices of all types exhibit similar responses to most of the stresses, however
there are marked differences. The SCR is the most robust device on practically all counts. That it
has an I
2
t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitably
selected, and in coordination with fast circuit breakers would mostly protect it. This sometimes
becomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJ T
and the IGBT is actively protected (without any operating cost!) by sensing the Main Terminal
voltage, as shown in Fig. 1.7. This voltage is related to the current carried by the device. Further,
the transistors permit designed gate current waveforms to minimise voltage spikes as a
consequence of sharply rising Main terminal currents. Gate resistances have significant effect on
turnon and turnoff times of these devices  permitting optimisation of switching times for the
reduction of switching losses and voltage spikes.
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Protection schemes for overvoltages  the prolonged ones and those of short duration  are
guided by the energy content of the surges. Metal Oxide Varistors (MOV's), capacitive dynamic
voltageclamps and crowbar circuits are some of the strategies commonly used. For high dv/dt
stresses, which again have similar effect on all devices, RC or RCD clamps are used
depending on the speed of the device. These 'snubbers' or 'switchingaidnetworks', additionally
minimise switching losses of the device  thus reducing its temperature rise.
Gates of all devices are required to be protected against overvoltages (typically +20 V)
specially for the voltage driven ones. This is achieved with the help of Zener clamps  the zener
being also a very fastacting device.
Protection against issues like excessive case temperatures and ESD follow wellset practices.
Forcedcooling techniques are very important for the higher rated converters and whole
environments are aircooled to lower the ambient.
Objective type questions
Qs#1 Which is the Power semiconductor device having
a) Highest switching speed;
b) Highest voltage / current ratings;
c) Easy drive features;
d) Can be most effectively paralleled;
e) Can be protected against overcurrents with a fuse;
f) Gateturn off capability with regenerative features;
g) Easy drive and High power handling capability
Ans: a) MOSFET; b) SCR; c) MOSFET; d) MOSFET; e) SCR ; (f) GTO; (g) IGBT
Qs#2 An SCR requires 50 mA gate current to switch it on. It has a resistive load and is supplied
from a 100 V DC supply. Specify the Pulse transformer details and the circuit following it, if the
driver circuit supply voltage is 10 V and the gatecathode drop is about 1 V.
Ans: The most important ratings of the Pulse transformer are its voltsecs rating, the isolation
voltage and the turns ratio.
The voltsecs is decided by the product of the primary pulsevoltage multiplied by the period for
which the pulse is applied to the winding
If the primary pulse voltage =(Supply voltage drive transistor drop)
The turnon time of he SCR may be in the range 50 secs for an SCR of this rating.
Consequently the volt secs may be in the range of 9 x 50 =450 voltsecs
=2.5 KV, I The Pulse transformer may be chosen as: 1:1, 450 Vs, V
isol M
=150 mA
The circuit shown in Fig. 1.7 may be used. Diodes 1N4002
Series resistance
=(Supply voltage drive transistor drop gatecathode drop)/100mA
=(10 1 1) / 100 E3
=80 Ohm
=49 or 57 Ohm (nearest available lower value)
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Module
1
Power Semiconductor
Devices
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Lesson
2
Constructional Features,
Operating Principle,
Characteristics and
Specification of Power
Semiconductor Diode
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Instructional Objective
On Completion the student will be able to
1. Draw the spatial distribution of charge density, electric field and electric potential in a
step junction pn diode.
2. Calculate the voltage drop across a forward biased diode for a given forward current and
viceverse.
3. Identify the constructional features that distinguish a power diode from a signal level
diode.
4. Differentiate between different reverse voltage ratings found in a Power Diode speciation
sheet.
5. Identify the difference between the forward characteristic of a power diode and a signal
level diode and explain it.
6. Evaluate the forward current specifications of a diode for a given application.
7. Draw the Turn On and Turn Off characteristics of a power diode.
8. Define Forward recovery voltage, Reverse recovery current Reverse Recovery
charge as applicable to a power diode.
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Power Semiconductor Diodes
2.1 Introduction
Power semiconductor diode is the power level counter part of the low power signal diodes
with which most of us have some degree of familiarity. These power devices, however, are
required to carry up to several KA of current under forward bias condition and block up to
several KV under reverse biased condition. These extreme requirements call for important
structural changes in a power diode which significantly affect their operating characteristics.
These structural modifications are generic in the sense that the same basic modifications are
applied to all other low power semiconductor devices (all of which have one or more pn
junctions) to scale up their power capabilities. It is, therefore, important to understand the nature
and implication of these modifications in relation to the simplest of the power devices, i.e., a
power semiconductor diode.
2.2 Review of Basic pn Diode Characteristics
A pn junction diode is formed by placing p and n type semiconductor materials in intimate
contact on an atomic scale. This may be achieved by diffusing acceptor impurities in to an n type
silicon crystal or by the opposite sequence.
In an open circuit pn junction diode, majority carriers from either side will defuse across the
junction to the opposite side where they are in minority. These diffusing carriers will leave
behind a region of ionized atoms at the immediate vicinity of the metallurgical junction. This
region of immobile ionized atoms is called the space charge region. This process continues till
the resultant electric field (created by the space charge density) and the potential barrier at the
junction builds up to sufficient level to prevent any further migration of carriers. At this point the
pn junction is said to be in thermal equilibrium condition. Variation of the space charge density,
the electric field and the potential along the device is shown in Fig 2.1 (a).
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(a) (b) (c)
Fig 2.1: Space change density the electric field and the electric potential in side a pn
junction under (a) thermal equilibrium condition, (b) reverse biased condition,
(c) forward biased condition.
When an external voltage is applied with p side move negative then the n side the junction is
said to be under reverse bias condition. This reverse bias adds to the height of the potential
barrier. The electric field strength at the junction and the width of the space change region (also
called the depletion region because of the absence of free carriers) also increases. On the other
hand, free minority carrier densities (n
p
in the p side and p
n
in the n side) will be zero at the edge
of the depletion region on either side (Fig 2.1 (b)). This gradient in minority carrier density
causes a small flux of minority carriers to defuse towards the deletion layer where they are swept
immediately by the large electric field into the electrical neutral region of the opposite side. This
will constitute a small leakage current across the junction from the n side to the p side. There
will also be a contribution to the leakage current by the electron hole pairs generated in the space
change layer by the thermal ionization process. These two components of current together is
called the reverse saturation current I
s
of the diode. Value of I
s
is independent of the reverse
voltage magnitude (up to a certain level) but extremely sensitive to temperature variation.
When the applied reverse voltage exceeds some threshold value (for a given diode) the reverse
current increases rapidly. The diode is said to have undergone reverse break down.
Reverse break down is caused by "impact ionization" as explained below. Electrons accelerated
by the large depletion layer electric field due to the applied reverse voltage may attain sufficient
knick energy to liberate another electron from the covalent bonds when it strikes a silicon atom.
The liberated electron in turn may repeat the process. This cascading effect (avalanche) may
produce a large number of free electrons very quickly resulting in a large reverse current. The
power dissipated in the device increases manifold and may cause its destruction. Therefore,
operation of a diode in the reverse breakdown region must be avoided.
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When the diode is forward biased (i.e., p side more positive than n side) the potential barrier is
lowered and a very large number of minority carriers are injected to both sides of the junction.
The injected minority carriers eventually recombines with the majority carries as they defuse
further into the electrically neutral drift region. The excess free carrier density in both p and n
side follows exponential decay characteristics. The characteristic decay length is called the
"minority carrier diffusion length"
Carrier density gradients on either side of the junction are supported by a forward current I
F
(flowing from p side to n side) which can be expressed as
( ) (
IF = IS exp qv/kT 1
)
(2.1)
Where I
s
= Reverse saturation current ( Amps)
v = Applied forward voltage across the device (volts)
q = Change of an electron
k = Boltzmans constant
T = Temperature in Kelvin
From the foregoing discussion the iv characteristics of a pn junction diode can be drawn as
shown in Fig 2.2. While drawing this characteristics the ohmic drop in the bulk of the
semiconductor body has been neglected.
Fig 2.2: VoltAmpere ( iv ) characteristics of a pn junction diode
Exercise 2.1
(1) Fill in the blanks with the appropriate word(s).
(i) The width of the space charge region increases as the applied ______________ voltage
increases.
(ii) The maximum electric field strength at the center of the depletion layer increases
with _______________ in the reverse voltage.
(iii) Reverse saturation current in a power diode is extremely sensitive to ___________
variation.
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(iv) Donor atoms are _____________________ carrier providers in the p type and
_________________ carrier providers in the n type semiconductor materials.
(v) Forward current density in a diode is __________________________ proportional to the
life time of carriers.
Answer: (i) Reverse, (ii) increase, (iii) temperature, (iv) Minority Majority, (v) inversely
(2) A pn junction diode has a reverse saturation current rating of 50 nA at 32C. What
should be the value of the forward current for a forward voltage drop of 0.5V. Assume V
T
=
KT/q at 32C = 26 mv.
Answer
T
V
V
F s
I = I e  1 ,
8 3
s T
I = 510 A, V = 2610 V V = 0.5V
F
I = 11.24 Amps.
(3) For the diode of Problem2 calculate the dynamic ac resistance
F
ac
F
di
dv
r =
at 32C and a
forward voltage drop of 0.5V.
Answer:
F
T
V
V
F s
i = I e  1
F
T
V
V s F
F T
I d i
= e
d V V
8
s F
Now I = 5 10 A, V = 0.5V,
 3 o
T
V = 2 6 1 0 V a t 3 2 C
F
T
V

V
F T
ac
F s
dV V
= r = e = 2 .3 1 3 m
di I
2.3 Construction and Characteristics of Power Diodes
As mention in the introduction Power Diodes of largest power rating are required to conduct
several kilo amps of current in the forward direction with very little power loss while blocking
several kilo volts in the reverse direction. Large blocking voltage requires wide depletion layer in
order to restrict the maximum electric field strength below the impact ionization level. Space
charge density in the depletion layer should also be low in order to yield a wide depletion layer
for a given maximum Electric fields strength. These two requirements will be satisfied in a
lightly doped pn junction diode of sufficient width to accommodate the required depletion layer.
Such a construction, however, will result in a device with high resistively in the forward
direction. Consequently, the power loss at the required rated current will be unacceptably high.
On the other hand if forward resistance (and hence power loss) is reduced by increasing the
doping level, reverse break down voltage will reduce. This apparent contradiction in the
requirements of a power diode is resolved by introducing a lightly doped drift layer of required
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thickness between two heavily doped p and n layers as shown in Fig 2.3(c). Fig 2.3 (a) and (b)
shows the circuit symbol and the photograph of a typical power diode respectively.
(b)
Fig. 2.3: Diagram of a power; (a) circuit symbol (b) photograph; (c) schematic cross
section.
To arrive at the structure shown in Fig 2.3 (c) a lightly doped n

epitaxial layer of specified width
(depending on the required break down voltage) and donor atom density (N
dD
) is grown on a
heavily doped n
+
substrate (N
dK
donor atoms.Cm
3
) which acts as the cathode. Finally the pn
junction is formed by defusing a heavily doped (N
aA
acceptor atoms.Cm
3
) p
+
region into the
epitaxial layer. This p type region acts as the anode.
Impurity atom densities in the heavily doped cathode (N
dk
.Cm
3
) and anode (N
aA
.Cm
3
) are
approximately of the same order of magnitude (10
19
Cm
3
) while that of the epitaxial layer (also
called the drift region) is lower by several orders of magnitude (N
dD
10
14
Cm
3
). In a low
power diode this drift region is absent. The Implication of introducing this drift region in a power
diode is explained next.
2.3.1 Power Diode under Reverse Bias Conditions Back
As in the case of a low power diode the applied reverse voltage is supported by the depletion
layer formed at the p
+
n

metallurgical junction. Overall neutrality of the space change region
dictates that the number of ionized atoms in the p
+
region should be same as that in the n

region.
However, since N
dD
<< N
aA
, the space charge region almost exclusively extends into the n

drift
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region. Now the physical width of the drift region (W
D
) can be either larger or smaller than the
depletion layer width at the break down voltage. Consequently two type of diodes exist, (i) non
punch through type, (ii) punch through type. In nonpunch through diodes the depletion layer
boundary doesnt reach the end of the drift layer. On the other hand in punch through diodes
the depletion layer spans the entire drift region and is in contact with the n
+
cathode. However,
due to very large doping density of the cathode, penetration of drift region inside cathode is
negligible. Electric field strength inside the drift region of both these type of diodes at break
down voltage is shown in Fig 2.4.
Fig 2.4: Electric field strength in reverse biased power Diodes; (a) Nonpunch through
type; (b) punch through type.
In nonpunch through type diodes the electric field strength is maximum at the p
+
n

junction and
decrease to zero at the end of the depletion region. Where as, in the punch through construction
the field strength is more uniform. In fact, by choosing a very lightly doped n

drift region,
Electric field strength in this region can be mode almost constant. Under the assumption of
uniform electric field strength it can be shown that for the same break down voltage, the punch
through construction will require approximately half the drift region width of a comparable
non  punch through construction.
Lower drift region doping in a punch through diode does not carry the penalty of higher
conduction lasses due to conductivity modulation to be discussed shortly. In fact, reduced
width of the drift region in these diodes lowers the onstate voltage drop for the same forward
current density compared to a nonpunch through diode.
Under reverse bias condition only a small leakage current (less than 100mA for a rated forward
current in excess of 1000A) flows in the reverse direction (i.e from cathode to anode). This
reverse current is independent of the applied reverse voltage but highly sensitive to junction
temperature variation. When the applied reverse voltage reaches the break down voltage, reverse
current increases very rapidly due to impact ionization and consequent avalanche multiplication
process. Voltage across the device dose not increase any further while the reverse current is
limited by the external circuit. Excessive power loss and consequent increase in the junction
temperature due to continued operation in the reverse brake down region quickly destroies the
diode. Therefore, continued operation in the reverse break down region should be avoided. A
typical IV characteristic of a power diode under reverse bias condition is shown in Fig 2.5.
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Fig 2.5: Reverse bias iv characteristics of a power Diode.
A few other important specifications of a power Diode under reverse bias condition usually
found in manufacturers data sheet are explained below.
DC Blocking Voltage (V
RDC
): Maximum direct voltage that can be applied in the reverse
direction (i.e cathode positive with respect to anode) across the device for indefinite period of
time. It is useful for selecting freewheeling diodes in DCDC Choppers and DCAC voltage
source inverter circuits.
RMS Reverse Voltage (V
RMS
): It is the RMS value of the power frequency (50/60 HZ) since
wave voltage that can be directly applied across the device. Useful for selecting diodes for
controlled / uncontrolled power frequency line commutated AC to DC rectifiers. It is given by
the manufacturer under the assumption that the supply voltage may rise by 10% at the most. This
rating is different for resistive and capacitive loads.
Peak Repetitive Reverse Voltage (V
RRM
): This is the maximum permissible value of the
instantiations reverse voltage appearing periodically across the device. The time period between
two consecutive appearances is assumed to be equal to half the power cycle (i.e 10ms for 50 HZ
supply). This type of period reverse voltage may appear due to commutation in a converter.
Peak NonRepetitive Reverse Voltage (V
RSM
): It is the maximum allowable value of the
instantaneous reverse voltage across the device that must not recur. Such transient reverse
voltage can be generated by power line switching (i.e circuit Breaker opening / closing) or
lightning surges.
Fig. 2.6 shows the relationship among these different reverse voltage specifications.
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Fig. 2.6: Reverse Voltage ratings of a power diode; (a) Supply voltage wave form; (b)
Reverse iv characteristics
2.3.2 Power Diode under Forward Bias Condition
In the previous section it was shown how the introduction of a lightly doped drift region in the p
n structure of a diode boosts its blocking voltage capacity. It may appear that this lightly doped
drift region will offer high resistance during forward conduction. However, the effective
resistance of this region in the ON state is much less than the apparent ohmic resistance
calculated on the basis of the geometric size and the thermal equilibrium carrier densities. This is
due to substantial injection of excess carriers from both the p
+
and the n
+
regions in the drift
region as explained next.
As the metallurgical p
+
n

junction becomes forward biased there will be injection of excess p
type carrier into the n

side. At low level of injections (i.e
p
<< n
no
) all excess p type carriers
recombine with n type carriers in the n

drift region. However at high level of injection (i.e large
forward current density) the excess p type carrier density distribution reaches the n

n
+
junction
and attracts electron from the n
+
cathode. This leads to electron injection into the drift region
across the n

n
+
junction with carrier densities
n
=
p
. This mechanism is called double
injection
Excess p and n type carriers defuse and recombine inside the drift region. If the width of the drift
region is less than the diffusion length of carries the spatial distribution of excess carrier density
in the drift region will be fairly flat and several orders of magnitude higher than the thermal
equilibrium carrier density of this region. Conductivity of the drift region will be greatly
enhanced as a consequence (also called conductivity modulation).
The voltage dropt across a forward conducting power diode has two components i.e
V
ak
= V
j
+ V
RD
(2.2)
Where V
j
is the drop across the p
+
n

junction and can be calculated from equation (2.1) for a
given forward current j
F
. The component V
RD
is due to ohmic drop mostly in the drift region.
Detailed calculation shows
V
RD
J
F
W
D
(2.3)
Where J
F
is the forword current density in the diode and W
D
is the width of the drift region.
Therefore
V
ak
= V
j
+ R
ON
I
F
(2.3)
The ohmic drop makes the forward iv characteristic of a power diode more linear.
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Fig 2.7: Characteristics of a forward biased power Diode; (a) Excess free carrier density
distribution; (b) iv characteristics.
Both V
j
and V
AK
have negative temperature coefficient as shown in the figure.
Few other important specifications related to forward bias operation of power diode as found in
manufacturers data sheet are explained next.
Maximum RMS Forward current (I
FRMS
): Due to predominantly resistive nature of the
forward voltage drop across a forward biased power diode, RMS value of the forward current
determines the conduction power loss. The specification gives the maximum allowable RMS
value of the forward current of a given wave shape (usually a half cycle sine wave of power
frequency) and at a specified case temperature. However, this specification can be used as a
guideline for almost all wave shapes of the forward current.
Maximum Average Forward Current (I
FAVM
): Diodes are often used in rectifier circuits
supplying a DC (average) current to be load. In such cases the average load current and the diode
forward current usually have a simple relationship. Therefore, it will be of interest to know the
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maximum average current a diode can conduct in the forward direction. This specification gives
the maximum average value of power frequency half cycle sine wave current allowed to flow
through the diode in the forward direction. Average current rating of a diode decreases with
reduction in conduction angle due to increase in current form factor.
Both I
FRMS
and I
FAVM
ratings are given at a specified case temperature. If the case temperature
increases beyond this limit these ratings has to be reduced correspondingly. Derating curves
provide by the manufacturers give the relationship between I
FAVM
(I
FRMS
) with allowable case
temperature as shown in Fig. 2.8.
Fig 2.8: Derating curves for the forward current of a Power Diode.
Average Forward Power loss (P
AVF
): Almost all power loss in a diode occurs during forward
conduction state. The forward power loss is therefore an important parameter in designing the
cooling arrangement. Average forward power loss over a full cycle is specified by the
manufacturers as a function of the average forward current (I
AVF
) for different conduction angles
as shown in Fig 2.9.
Fig 2.9: Average forward power loss vs. average forward current of a power Diode.
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Surge and Fault Current: In some rectifier applications a diode may be required to conduct
forward currents far in excess of its RMS or average forward current rating for some duration
(several cycles of the power frequency). This is called the repetitive surge forward current of a
diode. A diode is expected to operate normally after the surge duration is over.
On the other hand, fault current arising due to some abnormality in the power circuit may have a
higher peak valve but exists for shorter duration (usually less than an half cycle of the power
frequency). A diode circuit is expected to be disconnected from the power line following a fault.
Therefore, a fault current is a non repetitive surge current. Power diodes are capable of
withstanding both types of surge currents and this capability is expressed in terms of two surge
current ratings as discussed next.
Peak Repetitive surge current rating (I
FRM
): This is the peak valve of the repetitive surge
current that can be allowed to flow through the diode for a specific duration and for specified
conditions before and after the surge. The surge current waveform is assumed to be half
sinusoidal of power frequency with current pulses separated by OFF periods of equal duration.
The case temperature is usually specified at its maximum allowable valve before the surge. The
diode should be capable of withstanding maximum repetitive peak reverse voltage (V
RRM
) and
Maximum allowable average forward current (I
FAVM
) following the surge. The surge current
specification is usually given as a function of the surge duration in number of cycles of the
power frequency as shown in figure 2.10
Fig 2.10: Peak Repetitive surge current VS time curve of a power diode.
In case the surge current is specified only for a fixed number of cycles m
then the surge current specification applicable to some other cycle number n can be found from
the approximate formula.
FRM n FRM m
m
I \ = I \
n
(2.4)
Peak NonRepetitive surge current (I
FRM
): This specification is similar to the previous one
except that the current pulse duration is assumed to be within one half cycle of the power
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frequency. This specification is given as a function of the current pulse duration as shown in Fig
2.11.
Maximum surge current Integral (i
2
dt): This is a surge current related specification and gives
a measure of the heat energy generated inside the device during a nonrepetitive surge. It is
useful for selecting the protective fuse to be connected in series with the diode. This specification
is also given as a function of the current pulse duration as shown Fig 2.11
Fig. 2.11: Nonrepetitive surge current and surge current integral vs. current pulse width
characteristics of a power Diode.
Exercise 2.2
(1) Fill in the blanks with the appropriate word(s).
i. The ____________ region in a power diode increases its reverse voltage blocking
capacity.
ii. The maximum DC voltage rating (V
RDC
) of a power diode is useful for selecting
________________ diodes in a DCDC chopper.
iii. The reverse breakdown voltage of a Power Diode must be greater than
________________ .
iv. The iv characteristics of a power diode for large forward current is __________ .
v. The average current rating of a power diode _______________ with reduction in the
conduction angle due to increase in the current ___________________ .
vi. The derating curves of a Power diode provides relationship between the ______________
and the _________________ .
vii. rating of a power diode is useful for selecting the ________________ .
2
i dt
Answer: (i) drift, (ii) free wheeling, (iii) V
RSM
, (iv) linear, (v) decrease, form factor, (vi)
I
FAVM
/I
FRM
, case temperature, (vii) protective fuse.
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(2). (a) For the single phase half wove rectifier shown find out the V
RRM
rating of D.
(b) Will the required V
RRM
rating change if a inductor is placed between the diode and
n capacitor.
(c) What will be the required V
RRM
rating if the capacitor is removed. Assume a resistive
load.
(d) The source of the single phase rectifier circuit has an internal resistance of 2 . Find
out the required Non repetitive peak surge current rating of the diode. Also find the i
2
t
rating of the protective fuse to be connected in series with the diode.
Answer: (a) During every positive half cycle of the supply the capacitor charges to the peak
value of the supply voltage. If the load disconnected the capacitor voltage will not change when
the supply goes through its negative peak as shown in the associated waveform. Therefore the
diode will be subjected to a reverse voltage equal to the peak to peak supply voltage in each
cycle. Hence, the required V
RRM
rating will be
RRM
V = 2 2 230V = 650V
(b) When an inductor is connected between the diode and the capacitor the inductor current
will have some positive value at t = t
1
. If the load is disconnected the stored energy in the
inductor will charge the capacitor beyond the peak supply voltage. Since there is no discharge
path for the capacitor this voltage across the capacitor will be maintained when the supply
voltage goes through negative peak. Therefore, the diode will be subjected to a reverse voltage
greater than the peak to peak supply voltage. The required V
RRM
rating will increase.
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(c) If the capacitor is removed and the load is resistive the voltage V
KN
during negative half
cycle of the supply will be zero since the load current will be zero. Therefore the reverse voltage
across the diode will be equal to the peak supply voltage. So the required V
RRM
rating will be
RRM
V = 2 230V = 325 Volts
(d) Peak surge current will flow through the circuit when the load is accidentally short circuited.
The peak surge current rating will be
FSM
2 230
I = A = 162.64 A
2
The peak non repetitive surge current should not recur. Therefore, the protective fuse (to
be connected in series with the diode) must blow during the negative half cycle following the
fault. Therefore the maximum i
2
t rating of the fuse is
2 2 2 2 3
M ax FS M FS m
o
i d t = I S i n w t d w t = I = 4 1 . 5 5 1 0 A s e c
2
2
2.3.3 Switching Characteristics of Power Diodes
Power Diodes take finite time to make transition from reverse bias to forward bias condition
(switch ON) and vice versa (switch OFF).
Behavior of the diode current and voltage during these switching periods are important due to the
following reasons.
Severe over voltage / over current may be caused by a diode switching at different points
in the circuit using the diode.
Voltage and current exist simultaneously during switching operation of a diode.
Therefore, every switching of the diode is associated with some energy loss. At high
switching frequency this may contribute significantly to the overall power loss in the
diode.
Observed Turn ON behavior of a power Diode: Diodes are often used in circuits with di/dt
limiting inductors. The rate of rise of the forward current through the diode during Turn ON has
significant effect on the forward voltage drop characteristics. A typical turn on transient is shown
in Fig. 2.12.
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Fig. 2.12: Forward current and voltage waveforms of a power diode during Turn On
operation.
It is observed that the forward diode voltage during turn ON may transiently reach a significantly
higher value V
fr
compared to the steady slate voltage drop at the steady current I
F
.
In some power converter circuits (e.g voltage source inverter) where a free wheeling diode is
used across an asymmetrical blocking power switch (i.e GTO) this transient over voltage may be
high enough to destroy the main power switch.
V
fr
(called forward recovery voltage) is given as a function of the forward di/dt in the
manufacturers data sheet. Typical values lie within the range of 1030V. Forward recovery time
(t
fr
) is typically within 10 us.
Observed Turn OFF behavior of a Power Diode: Figure 2.13 shows a typical turn off
behavior of a power diode assuming controlled rate of decrease of the forward current.
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Fig. 2.13: Reverse Recovery characteristics of a power diode
Salient features of this characteristics are:
The diode current does not stop at zero, instead it grows in the negative direction to I
rr
called peak reverse recovery current which can be comparable to I
F
. In many power
electronic circuits (e.g. choppers, inverters) this reverse current flows through the main
power switch in addition to the load current. Therefore, this reverse recovery current has
to be accounted for while selecting the main switch.
Voltage drop across the diode does not change appreciably from its steady state value till
the diode current reaches reverse recovery level. In many power electric circuits
(choppers, inverters) this may create an effective short circuit across the supply, current
being limited only by the stray wiring inductance. Also in high frequency switching
circuits (e.g, SMPS) if the time period t
4
is comparable to switching cycle qualitative
modification to the circuit behavior is possible.
Towards the end of the reverse recovery period if the reverse current falls too sharply,
(low value of S), stray circuit inductance may cause dangerous over voltage (V
rr
) across
the device. It may be required to protect the diode using an RC snubber.
During the period t
5
large current and voltage exist simultaneously in the device. At high
switching frequency this may result in considerable increase in the total power loss.
Important parameters defining the turn off characteristics are, peak reverse recovery current (I
rr
),
reverse recovery time (t
rr
), reverse recovery charge (Q
rr
) and the snappiness factor S.
Of these parameters, the snappiness factor S depends mainly on the construction of the diode
(e.g. drift region width, doping lever, carrier life time etc.). Other parameters are interrelated and
also depend on S. Manufacturers usually specify these parameters as functions of di
F
/dt for
different values of I
F
. Both I
rr
and Q
rr
increases with I
F
and di
F
/dt while t
rr
increases with I
F
and
decreases with di
F
/dt.
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The reverse recovery characteristics shown in Fig. 2.13 is typical of a particular type of diodes
called normal recovery or soft recovery diode (S>1). The total recovery time (t
rr
) in this case
is a few tens of microseconds. While this is acceptable for line frequency rectifiers (these diodes
are also called rectifier grade diodes) high frequency circuits (e.g PWM inverters, SMPS)
demand faster diode recovery. Diode reverse recovery time can be reduce by increasing the rate
of decrease of the forward current (i.e, by reducing stray circuit inductance) and by using
snappy recovery (S<<1) diode. The problems with this approach are:
i) Increase of di
F
/dt also increases the magnitude of I
rr
ii) Large recovery current coupled with snappy recovery may give rise to current and
voltage oscillation in the diode due to the resonant circuit formed by the stray circuit
inductance and the diode depletion layer capacitance. A typical recovery characteristics
of a snappy recovery diode is shown in Fig 2.14 (a).
Fig. 2.14: Diode overvoltage protection circuit; (a) Snappy recovery characteristics; (b)
Capacitive snubber circuit; (c) snubber characteristics.
Large reverse recovery current may lead to reverse voltage peak (V
rr
) in excess of V
RSM
and
destroy the device. A capacitive protection circuit (also called a snubber circuit) as shown in
Fig. 2.14 (b) may to used to restrict V
rr
. Here the current flowing through L
l
at the time of diode
current snapping is bypassed to C
s
. L
l
,R
s
& C
s
forms a damped resonance circuit and the initial
energy stored in L
l
is partially dissipated in R
s
, thereby, restricting V
rr
. Normalized values of V
rr
as a function of the damping factor with normalized I
rr
as a parameter is shown in Fig. 2.14(c).
However, it is difficult to correctly estimate the value of L
l
and hence design a proper snubber
circuit. Also snubber circuits increase the overall power loss in the circuit since the energy stored
in the snubber capacitor is dissipated in the snubber resistance during turning ON of the diode.
Therefore, in high frequency circuits other types of fast recovery diodes (Inverter grade) are
preferred. Fast recovery diodes offer significant reduction in both I
rr
and t
rr
(10%  20% of a
rectifier grade diode of comparable rating). This improvement in turn OFF performance,
however, comes at the expense of the steady state performance. It can be shown that the forward
voltage drop in a diode is directly proportion to the width of the drift region and inversely
proportional to the carrier life time in the drift region. On the other hand both I
rr
and t
rr
increases
with increase in carrier life time and drift region width. Therefore if I
rr
and t
rr
are reduced by
reducing the carrier life time, forward voltage drop increases. On the other hand, if the drift
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region width is reduced the reverse break down voltage of the diode reduces. The performance of
a fast recovery diode is therefore, a compromise between the steady state performance and the
switching performance. In high voltage high frequency circuits switching loss is the dominant
component of the overall power loss. Therefore, some increase in the forward voltage drop in the
diode (and hence conduction power lass) can be tolerated since the Turn OFF loss associated
with reverse recovery is greatly reduced.
In some very high frequency applications (f
sw
>100KHZ), improvement in the reverse recovery
performance offered by normal fast recovery diode is not sufficient. If the required reverse
blocking voltage is less (<100v) schottky diodes are preferred over fast recovery diodes.
Compared to pn junction diodes schottky diodes have very little Turn OFF transient and almost
no Turn ON transient. On state voltage drop is also less compared to a pn junction diode for
equal forward current densities. However, reverse breakdown voltage of these diodes are less
(below 200V) Power schottky diodes with forward current rating in excess of 100A are
available.
Exerciser 2.3
1. Fill in the blanks with appropriate word(s)
i. Forward recovery voltage appears due to higher ohmic drop in the ______________ region
of a power diode in the beginning of the Turn On process.
ii. The magnitude of the forward recovery voltage is typically of the order of few
______________ of volts.
iii. The magnitude of the forward recovery voltage also depends on the _______________ of
the diode forward current.
iv. The reverse recovery charge of a power diode increases with the _______________ of the
diode forward current.
v. For a given forward current the reverse recovery current of a Power Diode ______________
with the rate of decrease of the forward current.
vi. For a given forward current the reverse recovery time of a Power diode ______________
with the rate of decrease of the forward current.
vii. A snappy recovery diode is subjected to _________________ voltage over shoot on
recovery.
viii. A fast recovery diode has _______________________ reverse recovery current and time
compared to a __________________ recovery diode.
ix. A Schottky diode has _______________ forward voltage drop and ______________ reverse
voltage blocking capacity.
x. Schottky diodes have no __________________ transient and very little
_________________ transient.
Answer: (i) drift, (ii) tens, (iii) rate of rise, (iv) magnitude, (v) increases, (vi) decreases, (vii)
large, (viii) lower, (ix) low, law, (x) Turn On, Turn Off.
2. In the buck converter shown the diode D has a lead inductance of 0.2H and a reverse
recovery change of 10C at i
F
=10A. Find peak current through Q.
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Answer: Assuming i
L
=10A (constant) the above waveforms can be drawn
As soon as Q is turned ON. a reverse voltage is applied across D and its lead inductance.
7
F
6
d i 2 0
= A S e c = 1 0 A S e c
d t . 2 1 0
Assuming a snappy recovery diode
( ) s o
2
F
rr rr rr rr
6
di 1
1
Q = I t = t
2
2 dt
= 10 10 C
r r
F
r r r r
t = 1 . 4 1 4 s
d i
I = t = 1 4 . 1 4 A
d t
i = I + I = 24.14 A
Q peak L rr
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References
1. Ned Mohan, Tore M. Undeland, William P. Robbins, Power Electronics, Converters,
Application and Design John Wiley & Sons(Asia), Publishers. Third Edition 2003.
2. P. C. Sen, Power Electronics Tata McGraw Hill Publishing Company Limited, New
Delhi, 1987.
3. Jacob Millman, Christos C. Halkias, Integrated Electronics, Analog and Digital Circuits
and Systems, Tata McGrawHill Publishing Company Limited, New Delhi, 1991.
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Module Summary
A pn junction diode is a minority carrier, unidirectional, uncontrolled switching device.
A power diode incorporates a lightly doped drift region between two heavily doped p
type and n type regions.
Maximum reverse voltage withstanding capability of a power diode depends on the width
and the doping level of the drift region.
A power diode should never be subjected to a reverse voltage greater than the reverse
break down voltage.
The iv characteristics of a forward biased power diode is comparatively more linear due
to the voltage drop in the drift region.
The forward voltage drop across a conducting power diode depends on the width of the
drift region but not affected significantly by its doping density.
For continuous forward biased operation the RMS value of the diode forward current
should always be less than its rated RMS current at a given case temperature.
Surge forward current through a diode should be less than the applicable surge current
rating.
During Turn On the instantaneous forward voltage drop across a diode may reach a
level considerably higher than its steady state voltage drop for the given forward current.
This is called forward recovery voltage.
During Turn Off the diode current goes negative first before reducing to zero. This is
called reverse recovery of a diode.
The peak negative current flowing through a diode during Turn Off is called the reverse
recovery current of the diode.
The total time for which the diode current remains negative during Turn Off is called the
reverse recovery time of the diode.
A diode can not block reverse voltage till the reverse current through the diode reaches its
peak value.
Both the reverse recovery current and the reverse recovery time of a diode depends
on the forward current during Turn Off, rate of decrease of the forward current and the
type of the diode.
Normal or slow recovery diodes have smaller reverse recovery current but longer reverse
recovery time. They are suitable for line frequency rectifier operation.
Fast recovery diodes have faster switching times but comparatively lower break down
voltages. They are suitable for high frequency rectifier or inverter free wheeling
operation.
Fast recovery diodes need to be protected against voltage transients during Turn Off
using RC snubber circuit.
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Schottky diodes have lower forward voltage drop and faster switching times but
comparatively lower break down voltage. They are suitable for low voltage very high
frequency switching power supply applications.
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Practice Problems and Answers
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Practice Problems (Module2)
1. If a number of pn junction diodes with identical iv characteristics are connected in
parallel will they share current equally? Justify your answer.
2. A power diode have a reverse saturation current of 15A at 32C which doubles for
every 10 rise in temperature. The dc resistance of the diode is 2.5 m. Find the forward
voltage drop and power loss for a forward current of 200 Amps. Assume that the
maximum junction temperature is restricted to 102C.
o
T
T
V = k = 2 6 m v a t 3 2 C
q
3. In the voltage commutated chopper T & TA are turned ON alternately at 400 HZ. C is
initially charged to 200 V with polarity as shown. Find the I
FRMS
and V
RRM
ratings of D
I
& D
F
.
4. In the voltage commutated chopper of Problem 5 the voltage on C reduces by 1% due to
reverse recovery of D
I
. Find out I
rr
& t
rr
for D
I
. (Assume S = 1 for D
I
).
5. What precaution must be taken regarding the forward recovery voltage of the free
wheeling diodes in a PWM voltage source inverter employing Bipolar Junction
Transistors of the npn type?
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Answers to Practice Problems
1. The reverse saturation current of a pn junction diode increases rapidly with temperature. If
follows then (from Eqn. 2.1) the voltage drop across a diode for a given forward current
decreases with increase in temperature. In other words if the volt ampere characteristics of a
diode is modeled as a non linear (current dependent) resistant it will have a negative
temperature coefficient.
Let us now consider the situation where a number of diodes are connected in parallel. If due
to some transient disturbance the current in a diode increases momentarily the junction
temperature of that diode will increase due increased power dissipation. The voltage drop
across that particular diode will decrease as a result and more current will be diverted
towards that diode. This positive feedback mechanism will continue to increase its current
share till parasitic lead resistance drop becomes large enough to prevent farther voltage drop
across that diode. Therefore, it can be concluded that a number of pn junction diodes conned
in parallel will not, in general, share current equally even if it is assumed that they have
identical iv characteristics.
However, equal current sharing can be forced by connecting suitable resistances in series
with the diodes so that the total resistance of each branch has positive temperature
coefficient.
2. Since the reverse saturation current double with every 10C rise in junction temperature.
o o
10232
10
s s
102 C 32 C
I = 2 I = 1.92 mA
o o
t t
KT
V = = 26mv at 32 C V at 102 = 31.97mv
q
j F
V f o r i = 2 0 0 A i s
o
o
F
j t
1 0 2 C
s
1 0 2 C
i
V = V ln = 0 . 3 7 V
I
Voltage drop across drift region V
R
= i
F
R
D
= 0.5V
Therefore, the total voltage drop across the diode is
D R j
V = V + V = 0.87V
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3. Important wave forms of the system are shown in the figure.
As soon as T is turned ON the capacitor voltage starts reversing due to the LC resenant
circuit formed by CTL & D
I
. Neglecting all the capacitor voltage reaches a 200V.
The current i
di
is given by
D I D IP n n
i = I S i n 0 7
DIP
C
where I = 200 = 89.44 A
L
3
n
1
& = = 22.3610
LC
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n
n n
Capacitor voltage reversal time
T 1
= = = = 140s.
2 2 f
Capacitor voltage remains at 200 V till TA is turned ON when it is charged linearly towards
+200 V. Time taken for charging is
C
L
2 200 C
T = = 400s
I
At the end of charging DF turns ON and remains on till T is turned on again.
DIP
FRMS I
FRMS F
I 140
I For D is = 10.58 Amps
5000
2
2100
I For D is 20 = 12.96 Amps
5000
RRM I
RRM F
From figure V for D is 200 V
V for D is 400 V
4. Since the Capacitor voltage reduces by 1%
rr
Q = 0.01C200 = 40c
2
dI
rr rr rr rr
di
with S = 1 Q = I t = t
dt
I DIP n
Now id = I Sin t
dI
n DIP n
di
= I Cos t
dt
dI
n n DIP
di 1 C
A
at t = , = I = , 200 = 2
s
dt L
LC
2 12 2
rr rr
t = 2010 sec or t = 4.472 s
rr
I = 8.94 Amps
5. Figure shows one leg of a PWM VSI using npn transistor and freewheeling diode.
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Consider turning off operation of Q
1
. As the current through Q
1
reduces
1
D turns On. The
forward recovery voltage of
1
D
appears as a reverse voltage across the npn transistor whose
base emitter junction must with stand this reverse voltage. Therefore, the forward recovery
voltage of the free wheel diodes must be less them the reverse break down voltage of the base
emitter junction of the npn transistors for safe operation of the inverter.
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Module
1
Power Semiconductor
Devices
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Lesson
3
Power Bipolar Junction
Transistor (BJT)
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Constructional Features, Operating Principles, Characteristics and specifications of Power
Bipolar Junction transistors.
Objective: On completion the student will be able to
1. Distinguish between, cut off, active, and saturation region operation of a Bipolar Junction
Transistor.
2. Draw the input and output characteristics of a junction transistor and explain their nature.
3. List the salient constructional features of a power BJT and explain their importance.
4. Draw the output characteristics of a Power BJT and explain the applicable operating
limits under Forward and Reverse bias conditions.
5. Interpret manufacturers data sheet ratings for a Power BJT.
6. Differentiate between the characteristics of an ideal switch and a BJT.
7. Draw and explain the Turn On characteristics of a BJT.
8. Draw and explain the Turn Off characteristics of a BJT.
9. Calculate switching and conduction losses of a Power BJT.
10. Design a BJT base drive circuit.
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3.1 Introduction
Power Bipolar Junction Transistor (BJT) is the first semiconductor device to allow full control
over its Turn on and Turn off operations. It simplified the design of a large number of Power
Electronic circuits that used forced commutated thyristors at that time and also helped realize a
number of new circuits. Subsequently, many other devices that can broadly be classified as
Transistors have been developed. Many of them have superior performance compared to the
BJT in some respects. They have, by now, almost completely replaced BJTs. However, it should
be emphasized that the BJT was the first semiconductor device to closely approximate an ideal
fully controlled Power switch. Other transistors have characteristics that are qualitatively
similar to those of the BJT (although the physics of operation may differ). Hence, it will be
worthwhile studying the characteristics and operation a BJT in some depth. From the point of
view of construction and operation BJT is a bipolar (i.e. minority carrier) current controlled
device. It has been used at signal level power for a long time. However, the construction and
operating characteristics of a Power BJT differs significantly from its signal level counterpart
due to the requirement for a large blocking voltage in the OFF state and a high current carrying
capacity in the ON state. In this module, the construction, operating principle and
characteristics of a Power BJT will be explored.
3.2 Basic Operating Principle of a Bipolar J unction Transistor
A junction transistor consists of a semiconductor crystal in which a p type region is sandwiched
between two n type regions. This is called an npn transistor. Alternatively an n type region
may be placed in between two p type regions to give a pnp transistor. Fig 3.1 shows the circuit
symbols and schematic representations of an npn and a pnp transistor. The terminals of a
transistor are called Emitter (E), Base (B) & Collector (C) as shown in the figure.
V
BB
V
CC
R
C
R
B
V
BE
V
CE
i
B
B (p)
i
C
i
E
E (n)
C (n)
+

V
BB
V
CC
R
C
V
BE
V
CE
i
B
B (n)
i
C
i
E
E (p)
C (p)
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Fig. 3.1: Bipolar junction transistor under different biasing condition.
(a) n p n transistor ; (b) p n p transistor.
(Emitter) (Base) (Collector)
n
n p
(E)
(B) (C)
J
CB
J
BE J
CB
0
BE
If no external biasing voltages are applied (i.e.; V
BB
and V
CC
are open circuited) all transistor
currents must be zero. The transistor will be in thermal equilibrium condition with potential
barriers and at the base emitter and the base collector functions respectively.
Corresponding depletion layer widths will be and . It is clear from the diagram that p
type carriers in the base region of an npn transistor are trapped in a potential well and cannot
escape. Similarly, in a pnp transistor p type carriers in the emitter and collector regions are
separated by a potential hill.
o
CB
O
BE
W
O
CB
W
When biasing voltages are applied as shown in the figure, the base emitter junction (J
BE
)
becomes forward biased where as the base collector junction is reverse biased. Potential barrier
and depletion layer width at J
BE
reduces to
A
CB
A
CB
W
0
BE
W
A
BE
W
0
CB
W
S
BE
S
BE
W
S
CB
0
CB
S
CB
W
(Emitter) (Base) (Collector)
n
n p
(E)
(B) (C)
x
A
pE
n
(b)
S
nB
p
noB
p
A
nB
p
S
pE
n
poE
n
S
pC
n
poC
n
A
pC
n
x x
A
nE
p
(a)
S
pB
n
poB
n
A
pB
n
S
nE
p
noE
p
S
nC
p
noC
p
A
nC
p
J
BE
0
BE
A
BE
A
CB
A
CB
W
0
BE
W
A
BE
W
S
BE
S
BE
W
S
CB
0
CB
W
0
CB
S
CB
W
x
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transistor and
A A
pE nB
n , p for pnp transistor). A portion of the minority carriers reaching the base
recombines with majority carriers. The rest, defuse to the edge of the depletion region at J
CB
where they are swept away to the collector region by the large electric field. Under this condition
the transistor is said to be in the Active region.
As V
BE
is increased injected minority charge into the base region increases and so does the base
current and the collector current. For a fixed collector bias voltage V
CC
, the voltage V
CB
reduces
with increase in collector current due to increasing drop in the external resistance R
C
. Therefore,
the potential barrier at J
CB
starts reducing. At one point J
CB
becomes forward biased. The
potential barriers and depletion layer widths under this condition are indicated in Fig. 3.1 by
variables with a super script s. Due to forward biasing of J
CB
there will be minority carrier
injection into the base from this junction also as shown in Fig. 3.1. The total voltage drop
between collector and emitter will be the difference between the forward bias voltage drops at
J
BE
and J
CB
. Under this condition the transistor is said to be in the saturation region.
From the operating principle described above one can form a qualitative idea about the input (i
B
vs V
B
BE
) and output (i
C
Vs V
CE
) characteristics of a transistor. In the following section these
characteristics of an npn transistor will be discussed qualitatively. Similar explanation applies
to a pnp transistor.
When a biasing voltage V
BB
of appropriate polarity is applied across the junction J
BE
the
potential barrier at this junction reduces and at one point the junction becomes forward biased.
The current crossing this junction is governed by the forward biased pn junction equation for
a given collector emitter voltage. The base current i
B
is related to the recombination of minority
carriers injected into the base from the emitter. The rate of recombination is directly proportional
to the amount of excess minority carrier stored in the base. Since, in a normal transistor the
emitter is much more heavily doped compared to the base the current crossing J
B
BE
is almost
entirely determined by the excess minority carrier distribution in the base. Thus, it can be
concluded that the relationship between i
B
B and V
BE
will be similar to the iv characteristics of a
pn junction diode. V
CE
, however have some effect on this characteristic. As V
CE
increases
reverse bias of J
CB
increases and the depletion region at J
CB
moves deeper into the base. The
effective base width thus reduces, reducing the rate of recombination in the base region and
hence the base current. Therefore i
B
for a given V B
BE
reduces with increasing V
CE
as shown in
Fig. 3.2(a).
It has been mentioned before that only a fraction (denoted by the letter ) of the total minority
carriers injected into the base reaches junction J
CB
where they are swept in to the collector region
by the large electric field at J
CB
. These minority carriers constitute the major component of the
total collector current. The other component of the collector current consists of the small reverse
saturation current of the reverse biased junction J
CB
.
Therefore I
C
= I
E
+ I
cs
(3.1)
Where I
cs
is the reverse saturation current of junction J
CB
But I
E
= I
B
+ I B
C
(3.2)
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CS
C
I
I = + I
1 1
B
(3.3)
By defining
1
I
C
=
IB
+ (+1) I
cs
(3.4)
is called the large signal common emitter current gain of the transistor and remains fairly
constant for a large range of I
C
, as shown in Fig. 3.2 (c). Fig: 3 (b) shows the complete out put
characteristics (i
c
vs V
CE
) of an npn transistor.
With V
BB
= 0 or negative there is little injected minority carrier into the base from the
emitter side. Therefore, i
B
= 0 and i B
C
is negligibly small. The transistor is said to be in the cut
off region under this condition.
As V
BB
is increased from zero, base current starts flowing. From equation (3.4) it will be
expected that the collector current should increase proportionately independent of V
CE
. However
Fig 3.2 (b) does indicate a slight increase in i
C
with V
CE
for a given i
B
. This is expected because
with increasing V
B
CE
a larger value of V
BE
will be required to maintain a given i
B
B (Fig. 3.2 (a)).
Therefore, the component I
E
of collector current will increase. I
CS
is ,for all practical
purpose, independent of V
CE
. This is the active or amplifier mode of operation of a transistor.
In the active region as i
B
increases i B
C
also increases. For a given value of V
CC
, V
CE
reduces with
increasing i
C
due to increased drop in an external load (i.e., Rc in Fig 3.1). At one point the
junction J
CB
becomes forward biased. V
CE
, now is just the difference between the voltages across
two forward biased junction J
BE
and J
CB
(a few handed milli volts). This is when the transistor
enters the saturation mode of operation. The ratio i
C
/i
B
B at the onset of saturation is called
Min
and
is an important parameter for a power transistor. In saturation i
C
is almost entirely determined by
the external load and further increase in i
B
changes i
C
or V
CE
very little.
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v
CE
increasing
(a)
i
B
v
BE
(c)
Fig. 3.2: Input and output characteristics of an n p n transistor.
(a) Input characteristics; (b) Output characteristics; (c) Current
gain[] characteristics
S
a
t
u
r
a
t
i
o
n
Cut off
(b)
i
B
increasing
v
CE
i
B
= 0
i
B1
i
B6
i
B5
i
B4
i
B3
Active
i
B2
i
C
Exercise 3.1
Fill in the blank(s) with the appropriate word(s)
a) Under forward bias condition a large number of ___________________ carriers are
introduced in the base region.
b) Some minority charge carriers reaching base __________________ with majority
carriers there and the rest of them ___________________ to the collector.
c) When the baseemitter junction of a BJT is forward biased while the basecollector
junction is reverse biased the BJT is said to be in the _______________ region.
d) When both BE & CB junction of a BJT are reverse biased it is said to be in the
_________________ region.
e) When both BE & CB junction of a BJT are forward biased it is said to be in the
_______________ region.
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Answer: (a) minority; (b) recombine, diffuse; (c) active; (d) cutoff; (e) saturation.
Exercise 3.2
Why does the collector current of a BJT in the active region increases with increasing collector
voltage for a given base current.
Answer: In the active region as the V
CE
voltage is increased the depletion layer width at the CB
junction increases and the effective base width reduces. Therefore, for a given V
BE
recombination of minority carriers in the base region reduces and base current also
reduces. In order to main constant base current with increasing V
CE
, V
BE
must
increased. Therefore, for a constant base current the number of minority carriers in the
base region will increase and consequently, collector current will increase.
Exercise 3.3
A power BJT has I
C
= 20 A at I
B
= 2.5 A. I B
cs
= 15 mA. Find out & .
Answer: I
c
= I
B
+ ( + 1) I B
cs
= ( I
B
B + I
cs
) + I
cs
.
= 7.95,
3.3 Constructional Features of a Power BJ T
Power transistors face the same conflicting design requirements (i.e. large off state blocking
voltage and large on state current density) as that of a power diode. Therefore, it is only natural
to extend some of the constructional features of power diodes to power BJT. Following Section
summarizes some of the constructional features of a Power BJT. Since Power Transistors are
predominantly of the npn type, in this section and subsequently only this type of transistor will
be discussed.
A power BJT has a vertically oriented alternating layers of n type and p type
semiconductor materials as shown in Fig 3.3(a). The vertical structure is preferred for
power transistors because it maximizes the cross sectional area through which the on
state current flows. Thus, on state resistance and power lass is minimized.
In order to maintain a large current gain (and hence reduce base drive current) the
emitter doping density is made several orders of magnitude higher than the base region.
The thickness of the base region is also made as small as possible.
In order to block large voltage during OFF state a lightly doped collector drift region
is introduced between the moderately doped base region and the heavily doped collector
region. The function of this drift region is similar to that in a Power Diode. However, the
doping density donation of the base region being moderate the depletion region does
penetrate considerably into the base. Therefore, the width of the base region in a power
transistor can not be made as small as that in a signal level transistor. This comparatively
larger base width has adverse effect on the current gain () of a Power transistor which
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typically varies within 520. As will be discusses later the collector drift region has
significant effect on the out put characteristics of a Power BJT.
Practical Power transistors have their emitters and bases interleaved as narrow fingers.
This is necessary to prevent current crowding and consequent second break down.
In addition multiple emitter structure also reduces parasitic ohmic resistance in the base
current path.
These constructional features of a Power BJT are shown schematically in Fig 3.3(a). Fig.3.3 (b)
shows the photograph of some community available Power transistors in different packages.
Emitter contact
Collector contact
Base
contact
n
+
(emitter) n
+
n
+
p (Base)
n

(Collector Drift)
n
+
(Collector)
(a)
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(b)
Fig. 3.3: Constructional Features of a Power Bipolar Junction Transistor
(a) Schematic of Construction,
(b) Photograph of commercial packages.
Exercise 3.4
Fill in the blank(s) with the appropriate word(s)
a) Doping density of the emitter of a Power BJT is several orders of magnitude
______________ than the base doping density.
b) Collector drift region is introduced in a Power BJT to block _______________ voltage.
c) Doping density of the base region in a power BJT is ________________.
d) Power BJT has ________________ DC current gain compared to signal level transistors.
e) In a Power BJT multiple, narrow finger like distributed emitter structure is used to avoid
emitter ___________________.
Answer: (a) higher; (b) high reverse; (c) moderate; (d) low; (e) current crowding.
Exercise 3.5
What are the constructional features of a power transistor that affect the dc current gain?
Large doping density of the emitter increases dc current gain.
Moderately doped base regain of relatively larger width tend to reduce the dc current
gain. The base width in a power transistor cannot be reduced below a certain level in
order to avoid reach through of the base region under large applied voltage.
Multiple, narrow emitter regions distributed uniformly over the entire device cross
section also tends to improve dc current gain by minimizing current crowding.
3.4 Output iv characteristics of a Power Transistor
A typical output (i
C
vs V
CE
) characteristics of an npn type power transistor is shown in
Fig 3.4 A power transistor exhibits Cut off, Active and Saturation regions of operation in
its output characteristics similar to a signal level transistor. In fact output characteristics of a
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Power Transistor in the Cut off and Active regions are qualitatively identical to a signal
level transistor. Certain quantitative restrictions apply, however, which are discussed next.
Active
Total Power dissipation limit
Primary break down voltage
Cut off
V
SUS
V
CE0
(i
B
= 0)
V
CB0
(i
B
< 0)
Second break down limit
Quasi Saturation
Hard Saturation
Increasing i
B
i
C
CE
i
B9
i
B8
i
B7
i
B6
i
B5
i
B4
i
B3
i
B2
i
B1
i
B
0
Fig. 3.4 Output ( i
c
v
CE
) characteristics of an n p n type Power Transistor
i
B10
In the cut off region (i
B
0) the collector current is almost zero. The maximum voltage between
collector and emitter under this condition is termed Maximum forward blocking voltage with
base terminal open (i
B
B
B = 0) and is denoted by V
CEO
. For all practical purpose this is the
maximum voltage that can be applied in the forward direction (C positive with respect to E)
across a power transistor since a power transistor is expected to see any significant forward
voltage only with i
B
= 0. This blocking voltage can however be increased to a value V B
CBO
by
keeping the emitter terminal open. In this case i
B
< o. Actually V
CBO
is the breakdown voltage of
the collector base junction. However, since the open base configuration is more common the
value of V
CEO
is used by the manufacturers as the maximum voltage rating of a power transistor.
Power transistors have poor reverse voltage withstanding capability due to low break down
voltage of the baseemitter junction. Therefore, reverse voltage (C negative with respect to E)
should not appear across a power transistor.
In the active region the ratio of collector current to base current (DC current Gain ()) remains
fairly constant upto certain value of the collector current after which it falls off rapidly.
Manufacturers usually provide a graph showing the variation of as a function of the collector
current for different junction temperatures and collector emitter voltages. This graph is useful for
designing the base drive of a Power transistor. Typically, the value of the dc current gain of a
Power transistor is much smaller compared to their signal level counterpart.
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The maximum collectoremitter voltage that a power transistor can withstand in active region is
determined by the Base collector avalanche break down voltage. This voltage, denoted by V
SUS
in Fig, 3.4 is usually smaller than V
CEO
. The voltage V
SUS
can be attained only for relatively
lower values of collector current. At higher collector current the limit on the total power
dissipation defines the boundary of the allowable active region as shown in Fig 3.4.
At still higher levels of collector currents the allowable active region is further restricted by a
potential failure mode called the Second Break down. It appears on the output characteristics
of the BJT as a precipitous drop in the collectoremitter voltage at large collector currents. The
collector voltage drop is often accompanied by significant rise in the collector current and a
substantial increase in the power dissipation. Most importantly this dissipation is not uniformly
spread over the entire volume of the device but is concentrated in highly localized regions. This
localized heating is a combined effect of the intrinsic non uniformity of the collector current
density distribution across the cross section of the device and the negative temperature
coefficient of resistively of minority carrier devices which leads to the formation of current
filamements (localized areas of very high current density) by a positive feedback mechanism.
Once current filaments are formed localized thermal runaway quickly takes the junction
temperature beyond the safe limit and the device is destroyed.
It is in the saturation region that the output characteristics of a Power transistor differs
significantly from its signal level counterpart. In fact the saturation region of a Power transistor
can be further subdivided into a quasi saturation region and a hard saturation region.
Appearance of the quasi saturation region in the output characteristics of a power transistor is a
direct consequence of introducing the drift region into the structure of a power transistor. In the
quasi saturation region the basecollector junction is forward biased but the lightly doped drift
region is not completely shorted out by excess minority carrier injection from the base. The
resistivity of this region depends to some extent on the base current. Therefore, in the quasi
saturation region, the base current still retains some control over the collector current although
the value of decreases significantly. Also, since the resistivity of the drift region is still
significant the total voltage drop across the device in this mode of operation is higher for a given
collector current compared to what it will be in the hard saturation region.
In the hard saturation region base current looses control over the collector current which is
determined entirely by the collector load and the biasing voltage V
CC
. This behavior is similar to
what happens in a signal transistor except that the drift region of a power transistor continues to
offer a small resistance even when it is completely shorted out (by excess carrier injection from
the base). Therefore, for larger collector currents the collectoremitter voltage drop is almost
proportional to the collector current. Manufacturers usually provide the plots of the variation of
V
CE
(sat) vs. i
C
for different values of base current and junction temperature. Curves showing
the variation of V
CE
(sat) with i
B
for different values of i B
C
and junction temperature are also
provided by certain manufacturers.
Applicable operating limits on a power transistors are compactly represented in two diagrams
called the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe Operating
Area. (RBSOA) applicable to i
B
> 0 and i B
B
B 0 conditions respectively. Typical safe operating
areas of power transistors are shown in Fig 3.5.
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i
C
I
CM
DC
10
2
sec
10
3
sec
10
4
sec
10
5
sec
i
C
V
CB0
CE
(V
BE
< 0)
V
CE0
(V
BE
= 0)
I
CM
Log
CE
V
SUS
(a)
(b)
Fig. 3.5: Safe operating areas of a Power Transistor.
(a) FBSOA; (b) RBSOA.
The horizontal upper limit of the FBSOA is determined by the maximum allowable collector
current (I
CM
) that should not be exceeded even as a pulse. Exceeding this current limit may cause
bonding wire or metallization of the wafer to vaporize or otherwise fail. Since a power transistor
does not have any appreciable reverse voltage blocking capacity they are usually not used in ac
circuits. However, if the collector current, for some reason is not dc or a pulse, the rms value of
the collector current waveform should not exceed this limit.
The next applicable limit in the FBSOA (green lines) corresponds to the restriction on the
maximum allowable power dissipation and maximum junction temperature. Since FBSOA is
shown on a loglog scale constant Power dissipation (P
d
= V
CE
i
C
) limits appear as straight lines.
This limit is different for dc and pulsed operation due to the thermal time constant of the device.
The DC limit is applicable to the average power loss if the transistor remains continuously in
the conduction state (active, quasi saturation or saturation). On the other hand the pulsed power
dissipation limits are applicable to conduction duration up to the value marked on them (the
figures on the right of Fig 3.5 (a)). Pulsed power dissipation limits are specified for a low value
(1%2%) of duty cycle and are useful for shaping the switching trajectory of the transistor as will
be seen later.
The third limit of the FBSOA (red line) arises due to the second break down failure mode of
a Power transistor. It shows the limiting combinations of collector voltage and current so that
second break down does not occur. On the log log scale of the FBSOA this limit also appears as
a straight limit. Like the maximum power dissipation limit, the second break down limit is also
different for DC and Pulsed operation of different pulse durations. The interpretation of the
pulse duration (marked on the right side of Fig 3.5 (a)) corresponding to a particular limit is also
same.
The final limit of the FBSOA corresponds to the forward biased avalanche break down voltage
(V
SUS
) of the transistor and appear as a vertical line in the FBSOA at V
CE
= V
SuS
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The FBSOA of a Power transistor is given at a specified case temperature. Both the maximum
power dissipation limit and the second break down limits are to be derated as per the derating
characteristics provided by the manufacturers when the case temperature exceeds the specified
value.
In contrast to the FBSOA, the RBSOA (Fig 3.5 (b)) is plotted on a linear scale and has a more
rectangular shape. RBSOA is a switching SOA since a transistor can not conduct current for any
appreciable duration under reverse biased condition. It essentially shows the limiting permissible
combinations of V
CE
& i
C
with base emitter junction reverse biased. The upper horizontal limit
corresponds to the maximum allowable collector current (I
CM
) and is same as that in the FBSOA.
The right hand side vertical limit corresponds the avalanche break down voltage of the transistor
with reverse bias. If the base terminal is open (i,e, i
B
= 0) then this voltage is V B
CEO
. If a negative
voltage is applied across the BE junction the right hand side limit of the RBSOA increases
somewhat to the value V
CBO
at low value of the collector current.
In addition to the applicable limits on the output characteristics as represented in the FBSOA and
the RBSOA, limiting specification with respect to the base emitter junction is also provided by
the manufacturer. Typical specifications that are provided are
V
EBO
: This is maximum allowable reverse bias voltage across the BE junction
I
B
: Maximum allowable average base current at a given case temperature. B
I
BM
: Maximum allowable peak base current at a given case temperature and of
specified pulse duration.
The input characteristics (i
B
Vs V B
BE
) at a given case temperature is also provided.
Exercise 3.6
Fill in the blank(s) with the appropriate word(s)
a) In the Cut off region collector current of a Power Transistor is _____________.
b) In the __________________ region of a Power Transistor the dc current gain remains
fairly constant.
c) Saturation region of a Power Transistor can be divided into _______________ region and
______________________ region.
d) Active region operation of a Power BJT is limited mostly by _______________
consideration.
e) Second breakdown in a Power BJT occurs due to ________________ of the collector
current distribution.
Answer: (a) negligible; (b) active; (c) Quasi saturation, hard saturation; (d) Power
dissipation; (e) non uniformity.
3.5 Switching characteristics of a Power Transistor
In a power electronic circuit the power transistor is usually employed as a switch i.e. it operates
in either cut off (switch OFF) or saturation (switch ON) regions. However, the operating
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characteristics of a power transistor differs significantly from an ideal controlled switch in the
following respects.
It can conduct only finite amount of current in one direction when ON
It can block only a finite voltage in one direction.
It has a voltage drop during ON condition
It carries a small leakage current during OFF condition
Switching operation is not instantaneous
It requires non zero control power for switching
Of these the exact nature and implication of the first two has been discussed in some depth in the
previous section. The third and fourth non idealities give rise to power loss termed the
conduction power loss. In this section the nature and implications of the last two non idealities
will be discussed in detail.
Exercise 3.7
Fill in the blank(s) with the appropriate word(s)
a) An ideal switch can conduct current in ______________ directions. While a power
transistor conducts current in _______________ direction.
b) In power transistor there will be power loss due to ON state ________________ and OFF
state _________________.
c) Unlike an ideal switch the switching of a power transistor is not ____________.
Answer: (a) two, one; (b) voltage drop, leakage current; (c) instantaneous.
3.5.1 Turn On characteristics of a Power Transistor
From the description of the basic operating principle of a power transistor presented in the
previous sections it is clear that minority carriers must be moved across different regions of a
power transistor in order to make it switch between cut off and saturation regions of operation.
The time delay in the switching operation of a power transistor is due to the time taken by the
minority carriers to reach appropriate density levels in different regions. The exact level of
minority carrier densities (and depletion region widths) required for proper switching is
determined by the collector current and biasing collector voltage during switching, both of which
are determined by external circuits. The rate at which these densities are attained is determined
by the base current waveform. Therefore, the switching characteristics of a power transistor is
always specified in relation to the external load circuit and the base current waveform as shown
in Fig 3.6 which shows a clamped inductive switching circuit with a flat base drive.
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V
BB
V
CC
i
D
D
I
L
R
B
i
B
Q V
CE
V
BE
i
C
+

(a)
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Fig 3.6 Turn ON characteristics of a power transistor;
(a) Switching circuit, (b) Switching wave forms
v
CE
(sat) I
L
V
CC
I
L
V
CE
(sat)
V
CC
P
e
v
CE
I
L
I
L
i
c
i
d
i
B
BB BE(sat)
B
V  V
R
V
BE sat
V
BB
V
BE
0
t
t
t
t
t
(b)
t
d t
ri
t
fv1
t
fv2
The switching wave forms shown in Fig 3.6 (b) are the expanded and to some extent idealized
version of the actual waveforms that will be observed in a clamped inductive switching circuit as
shown in Fig.3.6 (a). Some simplifying assumptions have been made to draw these waveforms.
These are
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The load inductor has been assumed to be large enough so that the load current does not
change during Turn ON period.
Reverse recovery characteristics of D has been ignored.
All parasitic elements have been ignored.
Before t = 0, the transistor (Q) was in the OFF state. In order to utilize the increased break
down voltage (V
CBO
) the baseemitter junction of a Power Transistor is usually reverse biased
during OFF state. Under this condition only negligible leakage current flows through the
transistor. Power loss due to this leakage current is negligible compared to other components of
power loss in a transistor. Therefore, it is not shown in Fig 3.6 (b). The entire load current flows
through the diode and V
CE
is clamped to V
CC
(approximately).
To turn the transistor ON at t = 0, the base biasing voltage V
BB
changes to a suitable positive
value. This starts the process of charge redistribution at the baseemitter junction. The process is
akin to charging of a capacitor. Indeed, the reverse biased base emitter junction is often
represented by a voltage dependent capacitor, the value of which is given by the manufacturer as
a function of the baseemitter reverse bias voltage. The rising base current that flows during this
period can be thought of as this capacitor charging current. Finally at t = t
d
the BE junction is
forward biased. The junction voltage and the base current settles down to their steady state
values. During this period, called the Turn ON delay time no appreciable collector current
flows. The values of i
O
and V
CE
remains essentially at their OFF state levels.
At the end of the delay time (t
d ON
) the minority carrier density at the base region quickly
approaches its steady state distribution and the collector current starts rising while the diode
current (i
d
) starts falling. At t = t
dON
+ t
ri
the collector current becomes equal to the load current
(and i
d
becomes zero) I
L
. At this point D starts blocking reverse voltage and V
CE
becomes
unclamped. t
ri
is called the current rise time of the transistor.
At the end of the current rise time the diode D regains reverse blocking capacity. The collector
voltage V
CE
which has so far been clamped to V
CC
because of the conducting diode D starts
falling towards its saturation voltage V
CE
(sat). The initial fall of V
CE
is rapid. During this period
the switching trajectory traverses through the active region of the output characteristics of the
transistor. At the end of this rapid fall (t
fv1
) the transistor enters quasi saturation region. The
fall of V
CE
in the quasi saturation region is considerably slower. At the end of this slow fall (t
fv2
)
the transistor enters hard saturation region and the collector voltage settles down to the
saturation voltage level V
CE
(sat) corresponding to the load current I
L
. Turn ON process ends
here. The total turn on time is thus, T
SW
(ON) = t
d
(ON)
+ t
ri
+ t
fv1
+ t
fv2
.
Power loss occurs at all time during the operation of a power transistor. However, the collector
leakage current is usually negligibly small and power loss due it can be safely neglected in
comparison to the power loss during ON condition. Power loss occurs during Turning ON a
Power transistor due to simultaneous existence of nonzero V
CE
and i
c
during t
ri
, t
fv1
, and t
fv2
. The
energy lost during these periods is called the Turn ON loss and given by the area under the P
l
curve in Fig 3.6 (b). The average Turn ON loss is obtained by dividing this area by (t
ri
+ t
fv1
+
t
fv2
). For safe Turn ON this average power loss must be less than the limit set on the maximum
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power dissipation in the FBSOA corresponding to a pulse width greater than t
ri
+ t
fv1
+ t
fv2
.
Similar restriction with respect to second break down should also be observed.
Turn ON time can be reduced by increasing the base current. However large base current
increases the quantity of excess carrier in the base and collector drift region which has to be
removed during Turn Off. As will be seen later this increases the Turn OFF time. The Turn ON
delay time can however be reduced by boosting the base current at the beginning of the Turn ON
process. This can be achieved by connecting a small capacitance across R
B
. This increases the
rate of rise of V
B
BE
& i
B
B. Therefore, Turn ON delay time decreases. However, in steady state i
B
settle downs to a value determined by R
B
B
B & V
BB
and no adverse effect on the Turn OFF time is
observed.
In figure 3.6 (b) the reverse recovery current of D has been neglected. If this current is not
negligible then for safe Turn ON operation the sum of the load current and the diode reverse
recovery current must be less than the I
CM
rating of the transistor. Thermal and second break
down limits must also be observed.
It should be noted that there is some power loss at the BE junction as well. This power loss
depends on the current gain of the transistor during hard saturation. Since current gain reduces
during saturation (typically between 5 to 10) this power loss may become significant.
Manufacturers usually provide the values of t
d
(ON), t
ri
, t
fv
as functions of i
c
for a given base
current and case temperature.
Exercise 3.8
Fill in the blank(s) with the appropriate word(s)
a) For faster switching of a BJT _______________ carriers are to be swept quickly from the
________________ region.
b) The reverse biased base emitter junction can be represented as a ______________
dependent __________________.
c) In the quasi saturation region collectoremitter voltage falls at a ______________ rate.
d) Turn ON delay can be reduced by __________________ the rate of rise of the base
current.
Answer: (a) minority, base; (b) voltage, capacitor; (c) slow; (d) increasing.
3.5.2 Turn Off Characteristics of a Power Transistor
During Turn OFF a power transistor makes transition from saturation to cut off region of
operation. Just as in the case of Turn ON, substantial redistribution of minority charge carriers
are involved in the Turn OFF process. Idealized waveforms of several important variables in the
clamped inductive switching circuit of Fig. 3.6 (a) during the Turn OFF process of Q are shown
in Fig 3.7 (a)
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V
BE(sat) V
BB
V
BE
V
BB
i
B
i
C
t
I
L
I
L
V
CC
t
t
i
d
V
CE
P
e
t
t
t
s
V
CE(Sat)
t
rv1
t
rv2
t
fi
(a)
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Reverse recovery current of D
Forward recovery
Voltage of D
Fig. 3.7: Turn off, characteristics of a BJT.
(a) Switching wave forms
(b) Switching trajectory
FBSOA
The Turn OFF process starts with the base drive voltage going negative to a value V
BB
.
The baseemitter voltage however does not change from its forward bias value of V
BE
(sat)
immediately, due to the excess, minority carriers stored in the base region. A negative base
current starts removing this excess carrier at a rate determined by the negative base drive voltage
and the base drive resistance. After a time t
s
called the storage time of the transistor, the
remaining stored charge in the base becomes insufficient to support the transistor in the hard
saturation region. At this point the transistor enters quasi saturation region and the collector
voltage starts rising with a small slope. After a further time interval t
rv1
the transistor completes
traversing through the quasi saturation region and enters the active region. The stored charge in
the base region at this point is insufficient to support the full negative base current. V
BE
starts
falling forward V
BB
and the negative base current starts reducing. In the active region, V
CE
increases rapidly towards V
CC
and at the end of the time interval t
rv2
exceeds it to turn on D.
V
CE
remains clamped at V
CC
, thereafter by the conducting diode D. At the end of t
rv2
the stored
base charge can no longer support the full load current through the collector and the collector
current starts falling. At the end of the current fall time t
fi
the collector current becomes zero and
the load current freewheels through the diode D. Turn OFF process of the transistor ends at this
point. The total Turn OFF time is given by Ts
(OFF)
= t
s
+ t
rv1
+ t
rv2
+ t
fi
As in the case of Turn ON considerable power loss takes place during Turn OFF due to
simultaneous existence of i
c
and V
CE
in the intervals t
rv1
, t
rv2
and t
fi
. The last trace of Fig 3.7 (a)
shows the instantaneous power loss profile during these intervals. The total energy last per turn
off operation is given by the area under this curve. For safe turn off the average power
dissipation during t
rv1
+ t
rv2
+ t
fi
should be less than the power dissipation limit set by the FBSOA
corresponding to a pulse width greater than t
rv1
+ t
rv2
+ t
fi
.
Turn off
Trajectory
Turn on
Trajectory
RBSOA
V
(sus) V
CEO
V
CBO
log i
C
I
CM
log v
CE
P
P
(b)
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Turn OFF time intervals of a power transistor are strongly influenced by the operating conditions
and the base drive design. Manufacturers usually specify these values as functions of collector
current for given positive and negative base current and case temperatures. Variations of these
time intervals as function of the ratio of positive to negative base currents for different collector
currents are also specified.
In this section and the precious one inductive load switching have been considered. However, if
the load is resistive. The freewheeling diode D will not be used. In that case the collector voltage
(V
CE
) and collector current (i
c
) will fall and rise respectively together during Turn ON and rise
and fall respectively together during Turn OFF. Other characteristics of the switching process
will remain same. The switching Power loss in this case will also be substantially lower.
Exercise 3.9
Fill in the blank(s) with the appropriate word(s)
a) Turn OFF process in a BJT is associated with transition from the _______________
region to the ______________ region.
b) Negative _______________ current is required to remove excess charge carriers from the
______________ region of a BJT during Turn OFF process.
c) V
CE
increases rapidly in the ________________ region.
Answer: (a) Saturation, Cutoff; (b) base, base; (c) active.
3.5.3 Switching Trajectory and Switching Losses in a Power
Transistor
It has been mentioned in the earlier sections that energy loss takes place in a power transistor
during each switching operation. Instantaneous power loss during switching can be calculated
and plotted as shown in Fig 3.6 (b) and 3.7 (a). The areas under these curves indicate the energy
loss during each switching operation (Turn ON and Turn OFF). Indicating these areas as E
ON
and
E
OFF
during Turn ON and Turn OFF operations respectively one can write.
( )
( )
( )
( )
ON CC L ri CC CEf1 L fv1 CEf1 L fv2 CE sat
1
E = V I t + V + V I t + V + V I t 3.5
2
Where V
CEf1
is the value of V
CE
at the end of the interval t
fv1
Similarly
( ) ( ) ( )
OFF CE CEr1 L rv1 CEr1 CC L rv2 CC L fi
1
E = V sat + V I t + V + V I t + V I t 3.6
2
( )
If the switching frequency of the transistor is f
SW
, then the average switching power loss is given
by
( ) ( )
SW ON OFF SW
P = E + E f 3.7
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On the other hand the conduction energy loss is given by the area hatched black in Fig 3.6 (b)
and 3.7(a). From these figures the conduction power loss is given by
( ) ( ) ( ) ( )
C CE L ON d ri fv1 fv2 s SW
P = V sat I T  t ON  t  t  t + t f 3.8
Where T
ON
is the time period for which the base drive voltage remain positive. Usually t
s
T
SW
(ON) << T
ON
, Therefore
( ) ( ) ( )
C CE L ON SW CE L
P = V sat I T f = V sat I D 3.9
Where D is the switching duly cycle.
For a given V
CC
and I
L
and base drive design, E
ON
and E
OFF
are constant. Therefore, the
switching power loss is proportional to the switching frequency. Being a minority carrier device
a BJT has comparatively larger switching times (compared to some other devices broadly
categorized as transistors) and hence larger switching power loss for a given frequency. On the
other hand a BJT has the lowest ON state voltage drop V
CE
(sat) among all fully controlled
switches. Therefore, a BJT is suitable for switching large current at moderate (around a few
KHZ) switching frequency. At high frequency BJT based circuits tend to become inefficient due
to increased switching power loss.
Even without any restriction on the switching power loss the maximum switching frequency of a
BJT is limited by its Turn ON and Turn OFF times. The value of the maximum switching
frequency is given by
( )
( ) ( )
( )
SW
SW SW
1
F Max = 3.10
T ON +T OFF
For a given collector current and base drive design.
For safe switching operation, however it is not sufficient to merely restrict the switching power
loss. It will be necessary to restrict the switching trajectory (an instantaneous plot of i
c
vs V
CE
during switching with time as a parameter) within the FBSOA /RBSOA region corresponding to
a pulse width greater than T
SW
(ON) or T
SW
(OFF). Fig 3.7 (b) shows these switching trajectories
superimposed on the FBSOA /RBSOA. In this diagram the green line corresponds to the Turn
ON trajectory while the blue line corresponds to the Turn OFF trajectory. These trajectories are
rectangular in nature. Clearly full voltage (V
CEO
) or current rating (I
CM
) of the transistor can not
be utilized in such a trajectory. The situation becomes worse a when the reverse recovery current
and forward recovery voltage of D is considered. Switching aid circuits or snubbers (as they
are popularly known) are used to enhance the switching performance of a power transistor. They
serve two specific purpose.
Shape the switching trajectory such that the voltage and current rating of a transistor can
be fully utilized.
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Reduce the switching power loss inside the device.
Fig. 3.8 shows a typical snubber circuit for a power transistor and the corresponding switching
trajectories.
V
BB
I
L
R
B
i
B
Q V
CE
i
C
+

(a)
V
CC
D
+
C
S
R
S
D
S
L
S
Turn
on
Turn off
RBSO
FBSO
A
V
CBO
V
CC
log
ic
I
CM
I
L
V
CE
(sus) V
CEO
log v
CE
(b)
Fig. 3.8: Switching characteristics of a BJT with Snubber
(a) Clamped inductive switching circuit with snubber
(b) Switching trajectory.
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Fig 3.8 (a) shows the same clamped inductive switching circuit of Fig 3.6 (a) but with the
snubber elements. The inductor L
S
connected between the load and the collector is the Turn ON
snubber. In decouples the collector from the supply voltage during Turn ON. Therefore, as the
junction V
BE
becomes forward biased V
CE
starts falling. At the same time i
c
also starts rising
towards I
L
. The resultant switching trajectory is shown by the solid green line in Fig 3.8 (b). This
should be compared with the unsnubbed Turn ON trajectory (broken green line). In the
unsnubbed case, the collector current rises to the maximum value before V
CE
starts falling from
V
CC
. V
CC,
therefore, must necessarily be smaller than V
CE
(SUS). In the snubber assisted
trajectory V
CE
falls substantially before i
c
rises to any appreciable value. Therefore, V
CC
can be
made larger than V
CE
(sat) and can be chosen closer to V
CEO
. Maximum collector current that can
be handled is also considerably higher ( )
( )
CM rr L Max
I = I  I D
. In the unsnubbed case
maximum I
L
is restricted essentially by the maximum power dissipation consideration and not by
I
CM
. L
S
also helps to reduce I
rr
(D) by restricting the rate of decrease of current through D. This
also helps to increase
L Max
I
RsCsDs constitute the Turn OFF snubber. This is popularly known as the RCD snubber.
During Turn OFF as the base drive of Q is removed i
c
starts falling and the remaining load
current is bypassed to Cs through D
s
. Therefore, the collector voltage rises simultaneously giving
rise to the Turn OFF trajectory shown by the solid blue line in Fig 3.8 (b). At the end of the Turn
OFF process V
CE
shoots over V
CC
due to L
s
C
s
oscillation. However, by proper design
CE Max
V
can be restricted well below V
CBO
. Therefore, the turn OFF snubber circuit can effectively utilize
the enhanced voltage withstanding capability of a power transistor with base reverse biased.
Comparison of the switching trajectories with and with out snubber circuit makes it evident that
the snubber circuit can considerably enhance the voltage and current capacity utilization of a
Power transistor.
The area enclosed under the switching trajectories is a measure of the switching loss occurring in
the device at each switching. Therefore, it is evident from Fig 3.8 (b) that the snubber circuit
reduces the switching power loss inside the device considerably. However, it should be
emphasized that the total switching loss (device + snubber resistance) may not reduce. It is also
necessary to place the snubber components very close to the transistor since any stray inductance
in the Rs Cs Ds loop may give rise to an unacceptably large voltage spike across Q.
Components should also be chosen very carefully. Rs must be non inductive and the lead
inductances of Ds and Cs must be kept to a minimum Power loss in Rs can be considerably large
and its wattage should selected accordingly. To avoid excessive power loss in Rs, lossless
(regenerate) snubber circuits have been proposed.
Exercise 3.10
Fill in the blank(s) with the appropriate word(s)
a) BJT has large switching times, since it is a _________________ carrier device.
b) BJT has _______________ ON state voltage drop.
c) BJT is inefficient at ______________ switching frequencies.
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d) Turn OFF snubber circuit is used to improve _______________ withstand capacity of a
BJT.
Answer: (a) minority; (b) low; (c) high; (d) voltage.
Exercise 3.11
What are the effects of introducing a drift region in the output iv characteristics of a power
transistor?
Answer: The drift region in a power transistor is introduced in order to block large forward
voltage. However, one effect of introducing the drift region is the appearance of a
quasi saturation region in the output iv characteristics of a power transistor. In the
quasi saturation state the drift region is not completely shorted out by conductivity
modulation by excess carriers from the base region. In offers a resistance which is a
function of the base current. Although the base current retain some control over
collector current in this state the value of dc current gain reduces substantially due to
increased effective base width.
Another effect of introducing the drift region is to make the V
CE
saturation voltage
depend linearly on the collector current in the hard saturation region due to the ohmic
resistance of the conductivity modulated drift region.
Exercise 3.12
Explain the importance of the following manufacturers specifications
(a) FBSOA, (b) vs i
c
characteristics, (c) i
B
vs V B
BE
characteristics
Answer: (a) FBOSOA compactly represents the safe operating limits of a power transistor in
terms of maximum forward current, maximum forward voltage, maximum average &
instantaneous power dissipation and second break down limits. It is most useful in
designing the switching trajectory of a power transistor.
(b) This characteristics gives the amount of base current required so that the transistor
can operate in the saturation mode for a given collector current.
(c) After the base current is determined, this characteristics is used to design the base
drive circuit for a given base power source.
3.5.4 Base Drive Design and Power Darlington
The performance of a Power transistor depends largely on the base drive design.
The rate of rise of base current in the beginning of the turn on process determines the turn on
delay time.
The magnitude of the base current during turn on decides the values of the voltage fall time,
current rise time and V
CE
(sat) for a given collector current.
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The negative base current during turn off determines the storage time, voltage rise time and
current fall time.
A negative bias at the base also enhances the voltage withstanding capacity of a power
transistor.
From the discussion of the switching characteristics of a BJT it is evident that the base drive
voltage source should be bipolar and the base drive resistance should be different during turn
on and turn off. The following step by step procedure can be followed to arrive at the values.
From the load current value (to be switched) and desired conduction power loss the desired
value of V
CE
(sat) is determined.
Using the desired value of V
CE
(sat) for the given load current, the required value of forward
base current (i
BP
) and the corresponding V
BE
(sat) is obtained from the manufacturers data
sheet.
The forward and reverse base drive voltages (V
BB
+ & V
BB
) are decided on the basis of the
availability of control power supply. These should be kept as low as possible in order to
reduce base drive power requirement.
The forward base drive resistance R
BP
is given by
( )
( )
BB+ BE
BP
BP
V  V sat
R = 3.11
i
It has been mentioned earlier that the turn on delay time can be reduced by increasing the rate
of rise of i
BP
at the beginning of the turn ON process. This is achieved by connecting a small
capacitor across R
BP
.
Once i
BP
is known the turn on loss is fixed. The allowable turn off loss is determined by
subtracting the turn on loss for the desired total switching loss. The required current fall and
voltage rise times for the calculated turn off loss is determined for the given load current and
V
CC
.
A suitable negative base current (i
BN
) to give the desired voltage rise time is determined from
the manufacturers data sheet.
R
BN
is given
( )
( )
BB BE
BN
BN
V + V sat
R = 3.12
i
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Once i
BN
is fixed the storage time (ts) can be determined from the manufacturers data sheet.
The storage time can be reduced by connecting a small capacitor across R
BN
.
The resulting base drive circuit can be realized as shown in Fig 3.9
From
Control
circuit
Electrical
Isolation
Optocoupler
V
BB

V
BB
+
R
3
R
1
R
2
R
BP
R
BN
Q
Fig 3.9: Typical base drive circuit of a power transistor
Power transistors have low values of dc current gain () compared to their signal level
counterpart. Particularly, if a low value of V
CE
(sat) is desired at full load current, can be as
low as 5. With such low gain large current switching becomes difficult since the base drive
circuit is required to handle about 20% of the full load current, Monolithic, Darlington connected
transistors can solve this problem. Fig 3.10 shows the circuit connection and the vertical cross
section of a Monolithic Darlington pair. The effective current gain of a Darlington pair is given
by
( )
M D M D
= + + 3.13
So that even when individual s are small effective can still be quite large.
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(a)
B
D
I
BD
i
CD
Q
D
i
ED
i
BM
E
Q
M
i
CM
C
I
L
i
ED
n+ n+
C
n+
n
n+
n i
CM
B E
i
BM
i
BD
sio
2
p
p
i
CD
Fig 3.10: Monolithic Darlington connected power transistor.
(a) circuit diagram, (b) schematic cross section.
(b)
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In the Darlington configuration the base drive current for the main transistor is derived from the
collector biasing power supply through a drive transistor. This drive transistor should have the
same voltage rating as the main transistor but lower current rating. In a monolithic design both
are fabricated from the same crystal. The silicon protrusion through the p layer (the base region
for both transistors) isolates the two bases from each other. A discrete diode D is added (Fig 3.10
(a)) to speed up the turn off time of the main transistor.
The major quantitative difference in the operating characteristics of a Power Darlington is due to
the fact that the main transistor can not go into hard saturation. The ON state voltage drop of the
drive transistor prevents forward biasing of the CB junction of the main transistor. Therefore,
the ON state power dissipation of the main transistor will be larger than that of an otherwise
comparable single BJT. The switching times will also be somewhat larger for the Darlington
transistor.
Exercise 3.13
A Power BJT is used to switch an inductive load carrying 20 A. The supply voltage is 200V,
switching frequency and duty cycle are 1 KHZ and 0.5 respectively. Switching times are as
follows. t
d
= 1s, t
ri
= t
fv1
= 8 s, t
fv2
= 0, t
s
= 12 s, t
fi
= t
rv2
= 8 s, t
rv1
= 0.
CE sat c
V = 1.0V at i = 20 A
Calculate switching and conduction losses in the transistor.
Answer: Turn on energy loss is given by.
( )
ON CC L ri fv1
1
E = V I t + t = 32 mJ
2
Turn off energy loss is given by
( )
off CC L fi rv2
1
E = V I t + t = 32mJ
2
So total energy loss per switching = E
ON
+ E
0ff
= 64 mJ.
Switching power loss = f
sw
(E
ON
+ E
off
) = 64 watts.
Conducting loss per switching is given by
( ) COND L CE sat d ri fv s
D
E = I V  t  t  t + t = 9.9 m
fsw
J
Conduction power loss = 9.9 watts.
Exercise 3.14
With reference to Fig. 3.9 determine the values of the base resistors R
BP
& R
BN
for the following
data
V
BB+
= 10 volts, V
BB
= 10 V, I
BP
= 2.5 A, I
BN
= 1.5 A,
BE sat
V = 0.7 V,
CE sat
V (of
drive transistors) = 0.3 V
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Answer:
BB BE sat CE sat
BP
BP
V +  V  V
R = = 3.6 ohms.
I
BE sat CE sat BB
BN
BN
V  V  V
R = = 6.93 ohms
I
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References
1) Jacob Millman, Christos C. Halkis, Integrated Electronics, Analog and Digital circuit
and systems, Tata McGrowHill publishing Company Limited, New Delhi, 1991.
2) Ned Mohan, Tore M. Undeland, William P. Robbins, Power Electronics, Converters,
Application and Design. John Willey & Sons (Asia) Publishers, Third Edition, 2003.
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Lesson Summary
A Bipolar Junction Transistor is a minority carrier, current controlled unidirectional
device.
A BJT can be of npn or pnp type with three terminals called the collector, the base
and the emitter.
A BJT can operate in cutoff, active or saturation regions.
In the cutoff region the base emitter junction is reverse biased and the collector current is
almost zero.
In the active region the ratio of collector current to base current is fairly constant. This
ratio is called the dc current gain ().
A transistor can be driven into saturation by increasing the base current for a given
collector current. In saturation the V
CE
voltage drop of a transistor is very low.
For power application normally, npn type transistor in the common emitter
configuration with the base as the control terminal is used. They operate either in the cut
off, or saturation mode.
For safe operation power transistors must observe maximum current, maximum voltage,
maximum power dissipation and second break down limits.
Operating restrictions applicable to a power transistor under forward and reverse bias
conditions are represented compactly in FBSOA & RBSOA diagrams respectively.
Power transistor output iv characteristics exhibits a quasi saturation region not found in
their signal level counterpart. It is the direct consequence of introducing a lightly doped
n

drift region in the structure of a power transistor which enhances its forward voltage
blocking capacity.
Switching of Power transistors from ON (saturation) to OFF (cutoff) state involves
considerable redistribution of minority carriers. Therefore, switching operation is not
instantaneous.
Switching characteristics of a power transistor is greatly influenced by the external load
circuit and the base drive circuit.
Energy loss takes place during each switching operation of a power transistor due to
simultaneous existence of collector current and voltage. This is called switching loss.
Energy loss taking place during ON condition of the transistor is called the conduction
loss. Conduction loss during the OFF state of a Power transistor is negligibly small.
Switching power loss is proportional to the switching frequency while the conduction
power loss is proportional to the duly cycle.
BJT being a minority carrier device have low on state voltage drop and longer switching
delay times compared to some majority carrier transistors. Consequently, BJT has
higher switching loss and lower conduction loss.
A Power transistor is suitable for large current switching at low to moderate (a few kHZ)
frequency.
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Switching aid circuits (snubbers) are used for enhancing the capacity utilization of a
power transistor. They also reduce switching loss internal to the device.
Ordinary LRCD snubber circuits may not reduce total switching loss. For that purpose
lossless (regenerative) snubber circuits are used.
Proper design of the base drive circuit helps to reduce both conduction and switching
losses. For optimal operation, base drive voltage should be bipolar and have different
output resistance for Turn ON and Turn OFF operations.
Power transistors have relatively small current gain () and hence require large base drive
current.
Monolithic Power Darlingtons can solve the problem of low current gain. But they have
larger ON state voltage drop and longer switching times.
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Practice Problems and Answers
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V
BB
= 12V
R
B
V
CC
= 200V
R
L
= 20
+

1. In the transistor switching circuit
BE sat CE sat
V = 0.75 V, V = 0.2 V 10 40 .
Find out the value of R
B
and Power requirement of the base source. B
V
BB
= 12V
R
B
V
CC
= 200V
R
L
= 20
+

D
3
D
2
D
1
2. In the transistor switching circuit shown
BE sat D1 D2 D3
V = 0.75 v, V = V = V = 0.7 v, 10 40
Find maximum allowable value of R
B
and power output of the base source. Also compare
conduction power loss with the circuit shown in Problem 1.
B
3. The transistor of Problem 1 has the following switching time specifications.
t
d
= 1s, t
ri
= t
fv
= 2.5 s, t
s
= 5 s, t
fi
= t
rv
= 2.5 s. The transistor is switched at a frequency
of 10 KHZ with duty ratio d = 0.5. Find out, (i) conduction power loss, (ii) switching power
loss.
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200v 200v
V
BB
50s
50s
t
t
t
t
i
C
V
CE
P
loss
10 A
t
d
t
ri
t
s t
fi
t
fv
t
rv
P
COND
P
SW
(on) P
SW
(off)
4. Figure shows practical implementation of a power transistor base drive circuit. The
comparator has an output voltage swing of 12 V.
Also
For Q
P
BE sat CE sat
V = 0.7V, V = 0.2V,
For Q
N
BE sat CE sat
V =  0.7V, V =  0.2V,
For Q
BE sat Min
V = 0.75 V. = 10. Also it is desired that negative base current should be at least
equal to positive base current.
Min
of Q
P
& Q
N
are same. Find the values of R
BP
, R
BN
and
R
1
5. Explain why the dc current gain of a Power BJT is considerably lower compared to its Signal
level counterpart. What adverse effect does it have on the switching performance of a BJT?
Suggest one solution to this problem.
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6. Differentiate between the voltage ratings V
SUS
, V
CEO
& V
CBO
of a Power BJT. How can these
three voltage ratings of a BJT be utilized in an inductive switching circuit.
7. The pulsed FBSOA of a Power BJT is usually specified for a very low duty cycle. Then now
does it help to extend the usable voltage and current rating of a BJT?
Answer to Test Problems
1. The load current
CE sat
L c
200 V
I = i = 10 Amps
20
CE sat
V = 0.2V, which indicates that the transistor is in hard saturation. Therefore =
min
= 10.
So required base current
c
i
= = 1 amps
10
BE sat B BB BE sat
V = 0.75 volts R = V  V = 11.25
Power drawn from base source is 12 1 = 12 watts.
2. In this case
CE BE sat D2 D1 D3
V = V + V + V  V = 1.45 volts . The transistor is not in saturation
since V
CB
is positive. So =
max
= 40
L c
c
B
2001.45
I = i = = 9.93 Amps.
20
i
i = = 0.25 Amps.
For maximum value of R
B
current through D B
3
will be zero
So
BB D1 D2 BE sat
B
B
V  V  V  V
R = = 39.4
i
Power Drawn from base source is 12 0.25 = 3 watts.
Conduction power lass in 1
st
problem was 10 0.2 = 2 watts
Conduction power lass in this case is 9.93 1.45 = 14.4 watts
Note: This circuit is known as the antisaturation clamp or the Bakers clamp.
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TTL
Pulse
10 K
+ 12v
 12v
1.5v
comp
0
Rl
 15v
i
B2
i
B1
i
C2
i
E2
i
E1
i
C1
A
Q
N
Q
P
Q
P
B
E
i
B
R
BP
+ 15v
V
CC
I
L
= 50 A
R
BN
3. Figure shows switching waveforms of the transistor. Major difference with clamped inductive
switching waveform is that in this case rise and fall of i
c
& V
CE
are simultaneous. In the
interval ( )
ri fv
t or t
( )
6
c
ri
5
CE
fv
CE sat
t
i = 10 = 410 t
t
t
V 200 1 = 200 4 10 t .
t
where V has been neglected.
In the interval ( )
fi rv
t or t
( )
5
c
fi
6
CE
rv
t
i = 10 1 = 10 1  4 10 t
t
t
V = 200 = 80 10 t
t
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( )
( )
( ) ( )
ri
6
6
fi
t
SW CE c
o
2.510
8 5
o
t 2.510
8 5
SW CE c
o o
E ON = V i dt
= 810 t 1 410 t dt
= 0.83 mJ
E OFF = V i dt = 810 t 1 410 t dt
= 0.83 mJ
( ) ( )
SW SW SW
3 3
SW SW SW
E = E ON + E OFF = 1.66 mJ
P = E f = 1.6610 10 10 = 16.6 watts.
Conduction loss occurs in the interval from the end of t
ri
to the beginning of t
fi
( )
COND CE sat L ON ri s
3 3
COND COND SW
E = V I T  td  t + t
= 0.103 mJ
P = E f = 0.103 10 10 10 = 1.03 watts.
4. For the transistor Q,
Min
=10, & i
c
= 50 A.
required positive
BP
50
i = = 5 Amps
10
Now
BP E1 c1 B1
i = i = i + i
AB BE
B1
1 1
CE sat BE
C1
BP BP
12  V  V 10.55
Now i = =
R R
15  V  V 14.1
i = =
R R
So
1 BP
10.55 14.1
+ = 5
R R
Now i
BN
i
BP
= 5A
BN E2 B2 C2
BE BA
B2
1 1
BE EC2
C2
BN BN
i = i = i + i
V  V + 12 12.05
i = =
R R
V  V + 15 15.55
i = =
R R
So
1 BN
12.05 15.55
+ 5
R R
Now
min
of Q
P
& Q
N
are same.
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So
C1 C2
B1 B2
i i
=
i i
or
1 1
BP BN
14.1 R 15.55 R
=
10.55 R 12.05 R
1 1
BP
1 1
BN
14.1 R 5R
Now 1 + =
10.55 R 10.55
10.55 R 5R
1 +
12.05 R 12.05
1
1 1
0 5R 
12.05 10.55
1
or R > 0
1
BP
BN
choose R = 100
R = 2.88
R = 2.78
5. The main reason for comparatively lower dc current gain in a power transistor is a relatively
thicker base region (a few tens of m compared to a fraction of a m incase of a signal
transistor). The thicker base region is required to withstand the large blocking voltage.
Unlike a power diode the doping density of the base region cannot be made very much large
compared to the lightly doped collector drift region since it will reduce by increasing
minority carrier injection into the emitter. As a result the depletion layer at the CB junction
penetrates considerably in to the base region. The base width has to be larger than this
penetration depth. A thicker base leads to larger rate of recombination of minority carriers
injected by the emitter. Therefore, for a given collector current the required base current is
relatively high and the dc current gain is low.
A second reason for lowering of arises from the emitter crowding effect where by the
collector current tends to crowd near specific regions of the emitter. In these localized high
current density regions tends to fall off very sharply reducing the effective dc current gain.
Due to lower dc current gain the base current requirement of a power transistor switching
circuit increases. This requires a large base drive power supply and increased base drive
power loss.
This problem can be solved to some extent by using two power transistors connected in the
Darlington configuration as shown.
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i
L
i
CM
i
BD
i
CD
i
ED
D
Q
M
Q
D
For this configuration.
( )
L CD CM
CD D BD
CM M ED M BD CD
i = i + i
But i = i
i = i = i + i
( )
L D BD M BD M D BD
M D M D BD eqv B
i = i + i + i
= + + i = i
D
equivalent (
eqv
) can be increased considerably due to multiplication of
M
&
D
.
Power Darlington has one problem, however. The main transistor (Q
M
) does not go into hard
saturation due to V
CE
drop of Q
D
. Therefore, the conduction loss is higher.
6. The voltage rating V
SUS
is the maximum allowable voltage across C & E when the transistor
is in active region with i
B
> 0 and collector current above a minimum value. B
With both i
B
and i B
C
greater than zero, there is considerable supply of minority carriers which
are accelerated by the large CB junction electric field to start avalanche breakdown at a
relatively lower voltage. Therefore, the voltage rating V
SUS
is the lowest of the three.
The rating V
CEO
is the maximum allowable voltage between C & E terminals when the
transistor is in cut off region with i
B
= 0 or i B
C
is less than a specified value. Under this
condition the supply of minority carriers at the CB junction is much less compared to the
previous case. Therefore, avalanche breakdown of the CB junction occurs at a higher voltage.
Thus V
CEO
> V
SUS
.
The rating V
CBO
is the maximum allowable voltage between C & E terminals when the
transistor is in cut off with i
B
< 0 and i B
C
less than a specified value. With i
B
B = 0 the EB
junction is still forward biased and there is small injection of minority carriers from the
emitter to the CB junction. However, with i
B
< 0 base emitter junction is reverse biased and
there is no supply of minority carriers to the CB junction from the emitter. Thus avalanche
B
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break down of this junction occurs at a relatively higher voltage making the rating V
CBO
largest of the three. Therefore, in general for a power transistor.
CBO CEO SUS
V > V > V
In an inductive switching circuit using snubber the collector voltage falls considerably before
i
C
builds up to any significant level. This can be utilized to increase the usable steady state
blocking voltage of the transistor up to V
CEO
. Since V
CE
will go below V
SUS
before i
C
can
build up to the level where the rating V
SUS
becomes applicable.
Similarly during turn off, the overshoot in the V
CE
voltage can be accommodated in the
difference between V
CBO
and V
CEO
. Since during turn off i
B
< 0 and the voltage. overshoot
occurs with i
B
C
= 0 the applicable voltage limit will be V
CBO
and not V
CEO
. However,
precaution must be taken such that the voltage over shoot decays before i
B
B becomes equal to
zero.
However, if a snubber circuit is not used the applicable voltage limit will always be V
SUS
since in this case V
CE
does not fall till i
C
rises to its full value during turn ON. Similarly
during turn off i
C
does not fall till V
CE
rises to steady state blocking voltage level.
Pulsed
log i
C
I
CM
B
P
D
C
B
D
A
D
A
P
C
D
C
P
O
log v
CE
7. The main difference between the DC and pulsed FBOSA is in the boundary corresponding to
maximum power dissipation and second break down. With only DC FBSOA the switching
trajectory has to be restricted to something similar to A
D
B
D
C
D
. However, with pulsed
FBSOA applicable limits of power dissipation and second break down increases
considerably. Both these limits require simultaneous existence of nonzero V
CE
& i
C
which for
a power transistor occurs only during switching. Therefore, the increases FBSOA can be
utilized and the switching trajectory improved to A
P
B
P
C
P
provided total switching time is
less than the pulse period for which the increased FBSOA is applicable.
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In addition pulsed FBSOA s are usually specified for a very low duty ratio. This condition
can be easily satisfied provided total turn on and turn off times of the transistor expressed as
a percentage of total ON and OFF periods of the transistor is less than this duty ratio
since during ON or OFF period the transistor remain well within DC FBSOA. In practice this
condition is satisfied by specifying a minimum ON and OFF period of the transistor.
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Module
1
Power Semiconductor
Devices
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Lesson
4
Thyristors and Triacs
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Instructional objects
On completion the student will be able to
Explain the operating principle of a thyristor in terms of the two transistor analogy.
Draw and explain the iv characteristics of a thyristor.
Draw and explain the gate characteristics of a thyristor.
Interpret data sheet rating of a thyristor.
Draw and explain the switching characteristics of a thyristor.
Explain the operating principle of a Triac.
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4.1 Introduction
Although the large semiconductor diode was a predecessor to thyristors, the modern power
electronics area truly began with advent of thyristors. One of the first developments was the
publication of the PNPN transistor switch concept in 1956 by J.L. Moll and others at Bell
Laboratories, probably for use in Bells Signal application. However, engineers at General
Electric quickly recognized its significance to power conversion and control and within nine
months announced the first commercial Silicon Controlled Rectifier in 1957. This had a
continuous current carrying capacity of 25A and a blocking voltage of 300V. Thyristors (also
known as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modest
beginning and now high power light triggered thyristors with blocking voltage in excess of 6kv
and continuous current rating in excess of 4kA are available. They have reigned supreme for two
entire decades in the history of power electronics. Along the way a large number of other devices
with broad similarity with the basic thyristor (invented originally as a phase control type device)
have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch
(SCS), light activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse Conducting
Thyristor (RCT), Diac, Triac and the Gate turn off thyristor (GTO).
From the construction and operational point of view a thyristor is a four layer, three terminal,
minority carrier semicontrolled device. It can be turned on by a current signal but can not be
turned off without interrupting the main current. It can block voltage in both directions but can
conduct current only in one direction. During conduction it offers very low forward voltage drop
due to an internal latchup mechanism. Thyristors have longer switching times (measured in tens
of s) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using
a control input, have all but eliminated thyristors in high frequency switching applications
involving a DC input (i.e, choppers, inverters). However in power frequency ac applications
where the current naturally goes through zero, thyristor remain popular due to its low conduction
loss its reverse voltage blocking capability and very low control power requirement. In fact, in
very high power (in excess of 50 MW) AC DC (phase controlled converters) or AC AC
(cycloconverters) converters, thyristors still remain the device of choice.
4.2 Constructional Features of a Thyristor
Fig 4.1 shows the circuit symbol, schematic construction and the photograph of a typical
thyristor.
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A
G
K
(a)
(c)
A
p
n

p
n
+
n
+
K
G
(b)
Fig. 4.1: Constructional features of a thysistor
(a) Circuit Symbol, (b) Schematic Construction, (c) Photograph
As shown in Fig 4.1 (b) the primary crystal is of lightly doped n

type on either side of
which two p type layers with doping levels higher by two orders of magnitude are grown. As in
the case of power diodes and transistors depletion layer spreads mainly into the lightly doped n

region. The thickness of this layer is therefore determined by the required blocking voltage of the
device. However, due to conductivity modulation by carriers from the heavily doped p regions
on both side during ON condition the ON state voltage drop is less. The outer n
+
layers are
formed with doping levels higher then both the p type layers. The top p layer acls as the Anode
terminal while the bottom n
+
layers acts as the Cathode. The Gate terminal connections are
made to the bottom p layer.
As it will be shown later, that for better switching performance it is required to maximize
the peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are
finely distributed between gate contacts of the p type layer. An Involute structure for both the
gate and the cathode regions is a preferred design structure.
4.3 Basic operating principle of a thyristor
The underlying operating principle of a thyristor is best understood in terms of the two
transistor analogy as explained below.
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A
p
n

p
n
+
n
+
K
G
(a)
K
p
p
p
n

n

G
A
J
1
J
2
J
3
J
2
J
3
(b)
n
+
Fig. 4.2: Two transistor analogy of a thyristor construction.
(a) Schematic Construction, (b) Schematic division in component
transistor
(c) Equivalent circuit in terms of two transistors.
A
(
2
) Q
2
(c)
G
K
Q
1
(
1
)
I
K
I
G
I
A
i
C2
i
C1
a) Schematic construction,
b) Schematic division in component transistor
c) Equivalent circuit in terms of two transistors.
Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode
positive with respect to the cathode and the gate terminal open. With this voltage polarity J
1
& J
3
are forward biased while J
2
reverse biased.
Under this condition.
( )
( )
1 1 A co1
2 2 K co2
ic = I +I 4.1
ic = I +I 4.2
Where
1
&
2
are current gains of Q
1
& Q
2
respectively while I
co1
& I
co2
are reverse
saturation currents of the CB junctions of Q
1
& Q
2
respectively.
Now from Fig 4.2 (c).
( )
( ) (
c1 c2 A
A K G
i +i = I 4.3
& I = I 4.4 I = 0 )
Combining Eq 4.1 & 4.4
( ) ( )
( )
co1 co2 co
A
1 2 1 2
I + I I
I = = 4.5
1 + 1 +
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Where is the total reverse leakage current of J
co co1 co2
I I +I
2
Now as long as V
AK
is small I
co
is very low and both
1
&
2
are much lower than unity.
Therefore, total anode current I
A
is only slightly greater than I
co
. However, as V
AK
is increased
up to the avalanche break down voltage of J
2,
I
co
starts increasing rapidly due to avalanche
multiplication process. As I
co
increases both
1
&
2
increase and
1
+
2
approaches unity.
Under this condition large anode current starts flowing, restricted only by the external load
resistance. However, voltage drop in the external resistance causes a collapse of voltage across
the thyristor. The CB junctions of both Q
1
& Q
2
become forward biased and the total voltage
drop across the device settles down to approximately equivalent to a diode drop. The thyristor is
said to be in ON state.
Just after turn ON if I
a
is larger than a specified current called the Latching Current I
L
,
1
and
2
remain high enough to keep the thyristor in ON state. The only way the thyristor can be
turned OFF is by bringing I
A
below a specified current called the holding current (I
H
) where
upon
1
&
2
starts reducing. The thyristor can regain forward blocking capacity once excess
stored charge at J
2
is removed by application of a reverse voltage across A & K (ie, K positive
with respect A).
It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to
cathode) without increasing the forward voltage across the device up to the forward breakover
level. With a positive gate current equation 4.4 can be written as
( )
K A G
I = I +I 4.6
Combining with Eqns. 4.1 to 4.3
( )
( )
2 G co
A
1 2
I + I
I = 4.7
1 +
Obviously with sufficiently large I
G
the thyristor can be turned on for any value of I
co
(and hence
V
AK
). This is called gate assisted turn on of a Thyristor. This is the usual method by which a
thyristor is turned ON.
When a reverse voltage is applied across a thyristor (i.e, cathode positive with respect to anose.)
junctions J
1
and J
3
are reverse biased while J
2
is forward biased. Of these, the junction J
3
has a
very low reverse break down voltage since both the n
+
and p regions on either side of this
junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported by
junction J
1
. The maximum value of the reverse voltage is restricted by
a) The maximum field strength at junction J
1
(avalanche break down)
b) Punch through of the lightly doped n

layer.
Since the p layers on either side of the n

region have almost equal doping levels the avalanche
break down voltage of J
1
& J
2
are almost same. Therefore, the forward and the reverse break
down voltage of a thyristor are almost equal.Up to the break down voltage of J
1
the reverse
current of the thyristor remains practically constant and increases sharply after this voltage.
Thus, the reverse characteristics of a thyristor is similar to that of a single diode.
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If a positive gate current is applied during reverse bias condition, the junction J
3
becomes
forward biased. In fact, the transistors Q
1
& Q
2
now work in the reverse direction with the roles
of their respective emitters and collectors interchanged. However, the reverse
1
&
2
being
significantly smaller than their forward counterparts latching of the thyristor does not occur.
However, reverse leakage current of the thyristor increases considerably increasing the OFF state
power loss of the device.
If a forward voltage is suddenly applied across a reverse biased thyristor, there will be
considerable redistribution of charges across all three junctions. The resulting current can
become large enough to satisfy the condition
1
+
2
= 1 and consequently turn on the thyristor.
This is called
dv
dt
turn on of a thyristor and should be avoided.
Exercise 4.1
1) Fill in the blank(s) with the appropriate word(s)
i. A thyristor is a ________________ carrier semi controlled device.
ii. A thyristor can conduct current in ________________ direction and block voltage in
________________ direction.
iii. A thyristor can be turned ON by applying a forward voltage greater than forward
________________ voltage or by injecting a positive ________________ current pulse
under forward bias condition.
iv. To turn OFF a thyristor the anode current must be brought below ________________
current and a reverse voltage must be applied for a time larger than ________________
time of the device.
v. A thyristor may turn ON due to large forward ________________.
Answers: (i) minority; (ii) one, both; (iii) break over, gate; (iv) holding, turn off;
(v)
dv
dt
2. Do you expect a thyristor to turn ON if a positive gate pulse is applied under reverse bias
condition (i. e cathode positive with respect to anode)?
Answer: The two transistor analogy of thyristor shown in Fig 4.2 (c) indicates that when a
reverse voltage is applied across the device the roles of the emitters and collectors of the
constituent transistors will reverse. With a positive gate pulse applied it may appear that the
device should turn ON as in the forward direction. However, the constituent transistors have very
low current gain in the reverse direction. Therefore no reasonable value of the gate current will
satisfy the turn ON condition (i.e.
1
+
2
= 1). Hence the device will not turn ON.
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4.4 Steady State Characteristics of a Thyristor
4.4.1 Static output iv characteristics of a thyristor
V
AK
i
g
I
A
A
K
+ 
Fig. 4.3: Static output characteristics of a Thyristor
V
BRF
V
BRF V
BRR
I
g
I
A
i
g4
> i
g3
> i
g2
> i
g1
> i
g
= 0
i
g4
> i
g3
> i
g2
> i
g1
> i
g
= 0
I
s
V
AK
i
g1
i
g2
i
g3
i
g4
I
H
I
L
V
H
The circuit symbol in the left hand side inset defines the polarity conventions of the variables
used in this figure.
With ig = 0, V
AK
has to increase up to forward break over voltage V
BRF
before significant anode
current starts flowing. However, at V
BRF
forward break over takes place and the voltage across
the thyristor drops to V
H
(holding voltage). Beyond this point voltage across the thyristor (V
AK
)
remains almost constant at V
H
(11.5v) while the anode current is determined by the external
load.
The magnitude of gate current has a very strong effect on the value of the break over voltage as
shown in the figure. The right hand side figure in the inset shows a typical plot of the forward
break over voltage (V
BRF
) as a function of the gate current (I
g
)
After Turn ON the thyristor is no more affected by the gate current. Hence, any current pulse
(of required magnitude) which is longer than the minimum needed for Turn ON is sufficient to
effect control. The minimum gate pulse width is decided by the external circuit and should be
long enough to allow the anode current to rise above the latching current (I
L
) level.
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The left hand side of Fig 4.3 shows the reverse iv characteristics of the thyristor. Once the
thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding
current (I
H
). The gate terminal has no control over the turn OFF process. In ac circuits with
resistive load this happens automatically during negative zero crossing of the supply voltage.
This is called natural commutation or line commutation. However, in dc circuits some
arrangement has to be made to ensure this condition. This process is called forced
commutation.
During reverse blocking if i
g
= 0 then only reverse saturation current (I
s
) flows until the reverse
voltage reaches reverse break down voltage (V
BRR
). At this point current starts rising sharply.
Large reverse voltage and current generates excessive heat and destroys the device. If i
g
> 0
during reverse bias condition the reverse saturation current rises as explained in the previous
section. This can be avoided by removing the gate current while the thyristor is reverse biased.
The static output iv characteristics of a thyristor depends strongly on the junction temperature as
shown in Fig 4.4.
25 75 125 150 T
j
T
j
=
I
A
V
BRF
V
AK
150 135 25 75 125
T
j
= 125 75 25 135 150
Fig. 4.4: Effect of junction temperature (T
j
) on the output
i v characteristics of a thyristor.
4.4.2 Thyristor Gate Characteristics
The gate circuit of a thyristor behaves like a poor quality diode with high on state voltage drop
and low reverse break down voltage. This characteristic usually is not unique even within the
same family of devices and shows considerable variation from device to device. Therefore,
manufacturers data sheet provides the upper and lower limit of this characteristic as shown in
Fig 4.5.
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Load line
V
ng
V
g min
V
g
E
h
g
b
f
e
d
c
V
g max
I
g max
I
g min
I
g
S
2
S
1
P
gav
Max
Fig. 4.5: Gate characteristics of a thyristor.
P
gm
E
K
A
R
g
i
g
V
g
Each thyristor has maximum gate voltage limit (V
gmax
), gate current limit (I
gmax
) and maximum
average gate power dissipation limit
( )
gav Max
P . These limits should not be exceeded in order to
avoid permanent damage to the gate cathode junction. There are also minimum limits of V
g
(V
gmin
) and Ig (I
gmin
) for reliable turn on of the thyristor. A gate non triggering voltage (V
ng
) is
also specified by the manufacturers of thyristors. All spurious noise signals should be less than
this voltage V
ng
in order to prevent unwanted turn on of the thyristor. The useful gate drive area
of a thyristor is then b c d e f g h.
Referring to the gate drive circuit in the inset the equation of the load line is given by
V
g
= E  R
g
i
g
A typical load line is shown in Fig 4.5 by the line S
1
S
2
.
The actual operating point will be some where between S
1
& S
2
depending on the particular
device.
For optimum utilization of the gate ratings the load line should be shifted forwards the
gav Max
P
curve without violating
g Max
V or I
gMax
ratings. Therefore, for a dc source E c f represents the
optimum load line from which optimum values of E & R
g
can be determined.
It is however customary to trigger a thyristor using pulsed voltage & current. Maximum power
dissipation curves for pulsed operation (P
gm
) allows higher gate current to flow which in turn
reduces the turn on time of the thyristor. The value of P
gm
depends on the pulse width (T
ON
) of
the gate current pulse. T
ON
should be larger than the turn on time of the thyristor. For T
ON
larger
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than 100 s, average power dissipation curve should be used. For T
ON
less than 100 s the
following relationship should be maintained.
( )
gm gav Max
ON p p
P P 4.9
Where = T f , f = pulse frequency.
The magnitude of the gate voltage and current required for triggering a thyristor is inversely
proportional to the junction temperature.
The gate cathode junction also has a maximum reverse (i.e, gate negative with respect to the
cathode) voltage specification. If there is a possibility of the reverse gate cathode voltage
exceeding this limit a reverse voltage protection using diode as shown in Fig 4.6 should be used.
Fig. 4.6: Gate Cathode reverse voltage protection circuit.
E
R
g
G
K
A
(a)
E
K
A
(b)
Exercise 4.2
1) Fill in the blank(s) with the appropriate word(s)
i. Forward break over voltage of a thyristor decreases with increase in the
________________ current.
ii. Reverse ________________ voltage of a thyristor is ________________ of the gate
current.
iii. Reverse saturation current of a thyristor ________________ with gate current.
iv. In the pulsed gate current triggering of a thyristor the gate current pulse width should be
larger than the ________________ time of the device.
v. To prevent unwanted turn ON of a thyristor all spurious noise signals between the gate
and the cathode must be less than the gate ________________ voltage.
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Answer: (i) gate; (ii) break down, independent; (iii) increases; (iv) Turn ON; (v) non
trigger.
2) A thyristor has a maximum average gate power dissipation limit of 0.2 watts. It is triggered
with pulsed gate current at a pulse frequency of 10 KHZ and duly ratio of 0.4. Assuming the gate
cathode voltage drop to be 1 volt. Find out the allowable peak gate current magnitude.
Answer: On period of the gate current pulse is
4 ON S
0.4
But P
gm
= I
g
V
g
; V
g
= 1V
g Max
.5
I = = 0.5Amps.
1
4.5 Thyristor ratings
Some useful specifications of a thyristor related to its steady state characteristics as found in a
typical manufacturers data sheet will be discussed in this section.
4.5.1 Voltage ratings
Peak Working Forward OFF state voltage (V
DWM
): It specifics the maximum forward (i.e,
anode positive with respect to the cathode) blocking state voltage that a thyristor can withstand
during working. It is useful for calculating the maximum RMS voltage of the ac network in
which the thyristor can be used. A margin for 10% increase in the ac network voltage should be
considered during calculation.
Peak repetitive off state forward voltage (V
DRM
): It refers to the peak forward transient
voltage that a thyristor can block repeatedly in the OFF state. This rating is specified at a
maximum allowable junction temperature with gate circuit open or with a specified biasing
resistance between gate and cathode. This type of repetitive transient voltage may appear across
a thyristor due to commutation of other thyristors or diodes in a converter circuit.
Peak nonrepetitive off state forward voltage (V
DSM
): It refers to the allowable peak value of
the forward transient voltage that does not repeat. This type of over voltage may be caused due to
switching operation (i.e, circuit breaker opening or closing or lightning surge) in a supply
network. Its value is about 130% of V
DRM
. However, V
DSM
is less than the forward break over
voltage V
BRF
.
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Peak working reverse voltage (V
DWM
): It is the maximum reverse voltage (i.e, anode negative
with respect to cathode) that a thyristor can with stand continuously. Normally, it is equal to the
peak negative value of the ac supply voltage.
Peak repetitive reverse voltage (V
RRM
): It specifies the peak reverse transient voltage that may
occur repeatedly during reverse bias condition of the thyristor at the maximum junction
temperature.
Peak nonrepetitive reverse voltage (V
RSM
): It represents the peak value of the reverse
transient voltage that does not repeat. Its value is about 130% of V
RRM
. However, V
RSM
is less
than reverse break down voltage V
BRR
.
Fig 4.7 shows different thyristor voltage ratings on a comparative scale.
V
BRR V
RSM
V
RRM
V
RWM
V
DWM V
DRM
V
DSM
V
BRF
V
AK
I
A
Fig. 4.7: Voltage ratings of a thyristor.
4.5.2 Current ratings
Maximum RMS current (I
rms
): Heating of the resistive elements of a thyristor such as metallic
joints, leads and interfaces depends on the forward RMS current I
rms
. RMS current rating is used
as an upper limit for dc as well as pulsed current waveforms. This limit should not be exceeded
on a continuous basis.
Maximum average current (I
av
): It is the maximum allowable average value of the forward
current such that
i. Peak junction temperature is not exceeded
ii. RMS current limit is not exceeded
Manufacturers usually provide the forward average current derating characteristics which
shows I
av
as a function of the case temperature (T
c
) with the current conduction angle as a
parameter. The current wave form is assumed to be formed from a half cycle sine wave of power
frequency as shown in Fig 4.8.
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= 180
= 120
= 30
= 60
T
C
(C)
Fig. 4.8: Average forward current derating characteristics
I
av
Amps
120
100
0
20
40
60
80
60 80 100 120 140
Maximum Surge current (I
SM
): It specifies the maximum allowable non repetitive current the
device can withstand. The device is assumed to be operating under rated blocking voltage,
forward current and junction temperation before the surge current occurs. Following the surge
the device should be disconnected from the circuit and allowed to cool down. Surge currents are
assumed to be sine waves of power frequency with a minimum duration of cycles.
Manufacturers provide at least three different surge current ratings for different durations.
For example
sM
sM
sM
1
I = 3000 A for cycle
2
I = 2100 A for 3 cycles
I =1800 A for 5 cycles
Alternatively a plot of I
sM
vs. applicable cycle numbers may also be provided.
Maximum Squared Current integral (i
2
dt): This rating in terms of A
2
S is a measure of the
energy the device can absorb for a short time (less than one half cycle of power frequency). This
rating is used in the choice of the protective fuse connected in series with the device.
Latching Current (I
L
): After Turn ON the gate pulse must be maintained until the anode
current reaches this level. Otherwise, upon removal of gate pulse, the device will turn off.
Holding Current (I
H
): The anode current must be reduced below this value to turn off the
thyristor.
Maximum Forward voltage drop (V
F
): Usually specified as a function of the instantaneous
forward current at a given junction temperature.
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Average power dissipation P
av
): Specified as a function of the average forward current (I
av
) for
different conduction angles as shown in the figure 4.9. The current wave form is assumed to be
half cycle sine wave (or square wave) for power frequency.
30
60
90
= 180
P
av
I
av
i
F
t
Fig. 4.9: Average power dissipation vs average forward current in a thyristor.
In the above diagram
( )
( )
av F
o
av F F
o
1
I = i d 4.10
2
1
P = v i d 4.11
2
4.5.3 Gate Specifications
Gate current to trigger (I
GT
): Minimum value of the gate current below which reliable turn on
of the thyristor can not be guaranteed. Usually specified at a given forward break over voltage.
Gate voltage to trigger (V
GT
): Minimum value of the gate cathode forward voltage below
which reliable turn on of the thyristor can not be guaranteed. It is specified at the same break
over voltage as I
GT
.
Non triggering gate voltage (V
GNT
): Maximum value of the gatecathode voltage below which
the thyristor can be guaranteed to remain OFF. All spurious noise voltage in the gate drive circuit
must be below this level.
Peak reverse gate voltage (V
GRM
): Maximum reverse voltage that can appear between the gate
and the cathode terminals without damaging the junction.
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Average Gate Power dissipation (P
GAR
): Average power dissipated in the gatecathode
junction should not exceed this value for gate current pulses wider than 100 s.
Peak forward gate current (I
GRM
): The forward gate current should not exceed this limit even
on instantaneous basis.
Exercise 4.3
1) Fill in the blank(s) with the appropriate word(s)
i. Peak nonrepetitive over voltage may appear across a thyristor due to ________________
or ________________ surges in a supply network.
ii. V
RSM
rating of a thyristor is greater than the ________________ rating but less than the
________________ rating.
iii. Maximum average current a thristor can carry depends on the ________________ of the
thyristor and the ________________ of the current wave form.
iv. The I
SM
rating of a thyristor applies to current waveforms of duration ________________
than half cycle of the power frequency where as the i
2
dt rating applies to current durations
________________ than half cycle of the power frequency.
v. The gate nontrigger voltage specification of a thyristor is useful for avoiding unwanted
turn on of the thyristor due to ________________ voltage signals at the gate.
Answer: (i) switching, lightning; (ii) V
RRM
, V
BRR
; (iii) case temperature, conduction
angle; (iv) greater, less; (v) noise
2. A thyristor has a maximum average current rating 1200 Amps for a conduction angle of 180.
Find the corresponding rating for = 60. Assume the current waveforms to be half cycle sine
wave.
Answer: The form factor of half cycle sine waves for a conduction angle is given by
( )
2
o RMS
o
1
1
 Sin 2 Sin d
I
2 2
F.F = = =
Iav 1 1 Cos
Sin d
2
For = 180, F.F =
2
RMS current rating of the thyristor =
i
a
ON
2 V Sin
t
i =
t R
Total switching energy loss
ON ON
2
t t
2
ON ak a
o o
ON ON
2 2
2 2 ON
ON
2Vi
t t
E = v i dt = Sin 1  dt
t t R
2Vi t 2 Vi
= Sin 1  = Sin t
R 2 3 3R
E
ON
occurs once every cycle. If the supply frequency is f then average turn on power loss is
given by.
2
2
ON ON ON
Vi
P = E f = Sin t f
3R
(ii) If the firing angle is the thyristor conducts for  angle. Instantaneous current through the
device during this period is
i
a
2 V Sin t
i = R < t
R
Where t
ON
& V
H
have been neglected for simplicity.
total conduction energy loss over one cycle is
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( )
i i H
C ak a H
1 2 V 2 V V
E = V i dt = V Sin d = 1 + Cos
R R
Average conduction power loss ( )
i H
C c
2 V V
= P = E f = 1 + Cos
2 R
Fuse
i
f
220 V
50 HZ
V
i
i
1
3. In the ideal single phase fully controlled converter T
1
& T
2
are fired at a firing angle after
the positive going zero crossing of V
i
while T
3
& T
4
are fired angle after the negative going
zero crossing of V
i
, If all thyristors have a turn off time of 100 s, find out maximum allowable
value of .
Answer: As T
1
& T
2
are fired at an angle after positive going zero crossing of V
i
, T
3
& T
4
are
subjected to a negative voltage of V
i
. Since this voltage remain negative for a duration ()
angle (after which V
i
becomes positive) for safe commutation
0
off Max
(  Max) t = 178.2 .
4.7 The Triac
The Triac is a member of the thyristor family. But unlike a thyristor which conducts only in one
direction (from anode to cathode) a triac can conduct in both directions. Thus a triac is similar to
two back to back (anti parallel) connected thyristosr but with only three terminals. As in the case
of a thyristor, the conduction of a triac is initiated by injecting a current pulse into the gate
terminal. The gate looses control over conduction once the triac is turned on. The triac turns off
only when the current through the main terminals become zero. Therefore, a triac can be
categorized as a minority carrier, a bidirectional semicontrolled device. They are extensively
used in residential lamp dimmers, heater control and for speed control of small single phase
series and induction motors.
4.7.1 Construction and operating principle
Fig. 4.12 (a) and (b) show the circuit symbol and schematic cross section of a triac respective. As
the Triac can conduct in both the directions the terms anode and cathode are not used for
Triacs. The three terminals are marked as MT
1
(Main Terminal 1), MT
2
(Main Terminal 2) and
the gate by G. As shown in Fig 4.12 (b) the gate terminal is near MT
1
and is connected to both
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N
3
and P
2
regions by metallic contact. Similarly MT
1
is connected to N
2
and P
2
regions while
MT
2
is connected to N
4
and P
1
regions.
MT2
MT1
G
MT2
(b)
N
4
N
2
N
3
N
3
N
2
N
1
N
1
P
1
P
1
P
2
P
2
P
2
G
MT1
Fig. 4.12: Circuit symbol and schematic construction of a Triac
(a) Circuit symbol (b) Schematic construction.
(a)
Since a Triac is a bidirectional device and can have its terminals at various combinations of
positive and negative voltages, there are four possible electrode potential combinations as given
below
1. MT
2
positive with respect to MT
1
, G positive with respect to MT
1
2. MT
2
positive with respect to MT
1
, G negative with respect to MT
1
3. MT
2
negative with respect to MT
1
, G negative with respect to MT
1
4. MT
2
negative with respect to MT
1
, G positive with respect to MT
1
The triggering sensitivity is highest with the combinations 1 and 3 and are generally used.
However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2
and 3 are used. Trigger mode 4 is usually averded. Fig 4.13 (a) and (b) explain the conduction
mechanism of a triac in trigger modes 1 & 3 respectively.
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N
2
N
1
P
2
P
1
I
G
I
G
MT1
(  )
MT2
( + )
G
(a)
N
3
N
1
P
2
P
1
I
G
I
G
MT1
( + )
MT2
(  )
(b)
N
4
Fig. 4.13: Conduction mechanism of a triac in trigger modes 1
and 3
(a) Mode 1 , (b) Mode 3 .
In trigger mode1 the gate current flows mainly through the P
2
N
2
junction like an ordinary
thyristor. When the gate current has injected sufficient charge into P
2
layer the triac starts
conducting through the P
1
N
1
P
2
N
2
layers like an ordinary thyristor.
In the trigger mode3 the gate current I
g
forward biases the P
2
P
3
junction and a large number of
electrons are introduced in the P
2
region by N
3
. Finally the structure P
2
N
1
P
1
N
4
turns on
completely.
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4.7.2 Steady State Output Characteristics and Ratings of a Triac
Fig. 4.14: Steady state V I characteristics of a Triac
V
I
V
BO
V
BO
I
g3
> I
g2
> I
g1
> I
g
= 0
I
g3
< I
g2
< I
g1
I
g
= 0
From a functional point of view a triac is similar to two thyristors connected in anti parallel.
Therefore, it is expected that the VI characteristics of Triac in the 1
st
and 3
rd
quadrant of the VI
plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with no
signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak
value is lower than the break over voltage (V
BO
) of the device. However, the turning on of the
triac can be controlled by applying the gate trigger pulse at the desired instance. Mode1
triggering is used in the first quadrant where as Mode3 triggering is used in the third quadrant.
As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current).
However, in a triac the two conducting paths (from MT
1
to MT
2
or from MT
1
to MT
1
) interact
with each other in the structure of the triac. Therefore, the voltage, current and frequency ratings
of triacs are considerably lower than thyristors. At present triacs with voltage and current ratings
of 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop compared
to a thyristor. Manufacturers usually specify characteristics curves relating rms device current
and maximum allowable case temperature as shown in Fig 4.15. Curves relating the device
dissipation and RMS on state current are also provided for different conduction angles.
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Maximum allowable case temperature (T
C
)
B
i
d
i
r
e
c
t
i
o
n
a
l
O
N
s
t
a
t
e
c
u
r
r
e
n
t
(
R
M
S
)
200
150
100
50
0
20
40 60 80 100 120
C
For all conduction angles
Fig. 4.15: RMS ON state current Vs maximum case temperature.
A
4.7.3 Triac Switching and gate trigger circuit
Unlike a thyristor a triac gets limited time to turn off due to bidirectional conduction. As a result
the triacs are operated only at power frequency. Switching characteristics of a triac is similar to
that of a thyristor. However, turn off of a triac is extremely sensitive to temperature variation and
may not turn off at all if the junction temperature exceeds certain limit. Problem may arise when
a triac is used to control a lagging power factor load. At the current zero instant (when the triac
turns off) a reverse voltage will appear across the triac since the supply voltage is negative at that
instant. The rate of rise of this voltage is restricted by the triac junction capacitance only. The
resulting
dv
dt
may turn on the triac again. Similar problem occurs when a triac is used to
control the power to a resistive element which has a very low resistance before normal working
condition is reached. If such a load (e.g. incandescent filament lamp) is switch on at full supply
voltage very large junction capacitance charging current will turn ON the device. To prevent
such condition an RC snubber is generally used across a triac.
The triac should be triggered carefully to ensure safe operation. For phase control application,
the triac is switched on and off in synchronism with the mains supply so that only a part of each
half cycle is applied across the load. To ensure clean turn ON the trigger signal must rise
rapidly to provide the necessary charge. A rise time of about 1 s will be desirable. Such a triac
gate triggering circuit using a diac and an RC timing network is shown in Fig 4.16.
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R
1
R
2
C
1
D
1
R
C
V
1
LOAD
Fig. 4.16: Triac triggering circuit using a diac.
In this circuit as Vi increases voltage across C
1
increases due to current flowing through load, R
1
,
R
2
and C
1
. The voltage drop across diac D
1
increases until it reaches its break over point. As D
1
conducts a large current pulse is injected into the gate of the triac. By varying R
2
the firing can
be controlled from zero to virtually 100%.
Exercise 4.5
1) Fill in the blank(s) with the appropriate word(s)
i. A Triac is a ________________ minority carrier device
ii. A Triac behaves like two ________________ connected thyristors.
iii. The gate sensitivity of a triac is maximum when the gate is ________________ with
respect to MT
1
while MT
2
is positive with respect to MT
1
or the gate is
________________ with respect to MT
1
while MT
2
is negative with respect to MT
1
iv. A Triac operates either in the ________________ or the ________________ quadrant of
the iv characteristics.
v. In the ________________ quadrant the triac is fired with ________________ gate
current while in the ________________ quadrant the gate current should be
________________.
vi. The maximum possible voltage and current rating of a Triac is considerably
________________ compared to thyristor due to ________________ of the two current
carrying paths inside the structure of the triac.
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vii. To avoid unwanted turn on of a triac due to large
dv
dt
________________ are used
across triacs.
viii. For clean turn ON of a triac the ________________ of the gate current pulse should be
as ________________ as possible.
Answer: (i) bidirectional; (ii) anti parallel; (iii) positive, negative; (iv) first, third; (v) first,
positive, third, negative (vi) lower, interaction; (vii) RC shubbers; (viii) rise time,
small.
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References
1. Dr. P.C. Sen, Power Electronics; Tata McGrow Hill Publishing Company Limited;
New Delhi.
2. Dr. P.S. Bimbhra, Power Electronics Khanna Publishers
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Lesson Summary
Thyristor is a four layer, three terminal, minority carrier, semicontrolled device.
The three terminals of a thyristor are called the anode, the cathode and the gate.
A thyristor can be turned on by increasing the voltage of the anode with respect to the
cathode beyond a specified voltage called the forward break over voltage.
A thyristor can also be turned on by injecting a current pulse into the gate terminal when
the anode voltage is positive with respect to the cathode. This is called gate triggering.
A thyristor can block voltage of both polarity but conducts current only from anode to
cathode.
After a thyristor turns on the gate looses control. It can be turned off only by bringing the
anode current below holding current.
After turn on the voltage across the thyristor drops to a very low value (around 1 volt). In
the reverse direction a thyristor blocks voltage up to reverse break down voltage.
A thyristor has a very low conduction voltage drop but large switching times. For this
reason thyristors are preferred for high power, low frequency line commutated
application.
A thyristor is turned off by bringing the anode current below holding current and
simultaneously applying a negative voltage (cathode positive with respect to anode) for a
minimum time called turn off time.
A triac is functionally equivalent to two anti parallel connected thyristors. It can block
voltages in both directions and conduct current in both directions.
A triac has three terminals like a thyristor. It can be turned on in either half cycle by
either a positive on a negative current pulse at the gate terminal.
Triacs are extensively used at power frequency ac load (eg heater, light, motors) control
applications.
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Practice Problems and Answers
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1. Explain the effect of increasing the magnitude of the gate current and junction
temperature on (i) forward and reverse break down voltages, (ii) forward and reverse
leakage currents.
Th
i
B
R
N
1 N
2
15 V
2. The thyristor Th is triggered using the pulse transformer shown in figure. The pulse
transformer operates at 10 KHZ with a duty cycle of 40%. The thyristor has maximum
average gate power dissipation limit of 0.5 watts and a maximum allow able gate voltage
limit of 10 volts. Assuming ideal pulse transformer, find out the turns ratio N
1
/N
2
and the
value of R.
Fuse
i
f
220 V
50 HZ
V
i
i
1
3. A thyristor full bridge converter is used to drive a dc motor as shown in the figure. The
thyristors are fired at a firing angle = 0 when motor runs at rated speed. The motor has
on armature resistance of 0.2 and negligible armature inductance. Find out the peak
surge current rating of the thyristors such that they are not damaged due to sudden loss of
field excitation to the motor. The protective fuse in series with the motor is designed to
disconnect the motor within
1
2
cycle of fault. Find out the rating of the
thyristors.
2
i dt
4. Why is it necessary to maximize the peripheral contact area of the gate and the cathode
regions? A thyristor used to control the voltage applied to a load resistance from a 220v,
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50HZ single phase ac supply has a maximum
a
di
dt
rating of 50 A / s. Find out the
value of the
a
di
dt
limiting inductor to be connected in series with the load resistance.
20 A
THM
THA
200V
200V
+
C

5. In a voltage commutated dc dc thyristor chopper the main thyristor THM is
commutated by connecting a precharged capacitor directly across it through the auxiliary
thyristor THA as shown in the figure. The main thyristor THM has a turn off time off
50s and maximum
dv
dt
rating of 500v/ s. Find out a suitable value of C for safe
commutation of THM.
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Answers to Practice Problems
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1.
i. Forward break down voltage reduces with increasing gate current. It increases with
junction temperature up to certain value of the junction temperature and then falls rapidly
with any further increase in temperature.
Reverse break down voltage is independent of the gate current magnitude but decreases
with increasing junction temperature.
ii. Forward leakage current is independent of the gate current magnitude but increases with
junction temperature.
Reverse leakage current increases with both the junction temperature and the magnitude
of the gate current.
20 A
THM
THA
200V
200V
+
C

2. Figure shows the equivalent gate drive circuit of the thyristor. For this circuit one can write
g g g g
= R i + V OR V = E  R i E
The diode D clamps the gate voltage to zero when E goes negative.
Now for i
g
= O, V
g
= E. Since
g Max
V =10 v E =10 v
2 2
1 1
N N
15
But E = 15 = = 1.5
N N 1
0
Gate pulse width = 0.4 10
4
Sec = 40s. <100s.
instantaneous gate power dissipation limit can be used.
av Max
g g Max
P 0.2
V i = = = 0.5 watts
0.4
For maximum utilization of the gate power dissipation limit the gate load line ie V
g
= E i
g
R =
10 i
g
R should be tangent to the maximum power dissipation curve V
g
i
g
= 0.5
Let the operating V
g
and i
g
be V
go
& i
go
go go
go go
2
go go
V = 10  i R
V i = 0.5
i R  10 i + 0.5 = 0
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Since V
g
= 10 i
g
R is tangent to V
g
i
g
= 0.5 at V
go
, i
go
.
Slope of the tangent of V
g
i
g
= 0.5 at (V
go
, i
go
) = R
( ) ( ) go go go go
g g
v ,i v ,i
g g
go go go
2 2
go
go go
dv  v v
 R = = = 
di i i
v v i 0.5
R = = =
i
i i
go
go
2
2 go go go go
go
2
go
0.5
i  10i + 0.5 = 0 or 10i = 1 or i = 0.1
i
0.5
0.5
R = = = 50
.01 i
i
a
V
a
i
a
(normal)
(with field loss)
Back emf.
t
t
t
3. Figure shows the armature voltage (firm line) and armature current of the motor under normal
operating condition at rated speed. If there is a sudden loss of field excitation back emf will
become zero and armature current will be limited solely by the armature resistance.
The peak magnitude of the fault current will be
220 2
= 1556(Amps)
.2
.
It the thyristors have to survive this fault at least for
1
2
cycle (after which the fuse blows) I
sM
>
1556 Amps.
The fuse blows within
1
2
cycle of the fault occurring. Therefore the thyristors must withstand
the fault for at least
1
2
cycle.
Therefore, the i
2
t rating of the thyristor should be
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( )
( )
[ ]
( )
2
2
10
2
2
0
2
10
0
2
2 4 2
i dt = 1556 Sin 100 t
1556
= 1  Cos 200 t dt
2
1
= 10 1556 = 1.21 10 A Sec
2
4. At the beginning of the turn on process the thyristor starts conducting through the area
adjacent to the gate. This area spreads at a finite speed. However, if rate of increase of anode
current is lager than the rate of increase of the current conduction are, the current density
increases with time. This may lead to thyristor failure due to excessive local heating. However, if
the contact area between the gate and the cathode is large a thyristor will be able to handle a
relatively large
a
di
dt
without being damaged.
The maximum
a
di
dt
will occur when the thyristor is triggered at = 90. Then
0 a
di
L = 2 220 Sin 90
dt
Since
6
a
Max
di
= 50 10 A Sec
dt
6
min
a
Max
2 220
L = = 6.22 10 H = 6.22 H
di
dt
200 V
20 Amps.
dv / dt
t
off
i
C
v
THM
V
C
t
t
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5. As soon as THA is turned on the load current transfer from THM to C. the voltage across
THM is the negative of the capacitance voltage. Figure shows the waveforms of voltage across
the capacitor (v
c
), voltage across the main thyristor (V
THM
) and the capacitor current i
c
. From
figure
c
dv
i
=
c dt
Now i
c
= 20 Amps &
Max
dv
= 500 v s
dt
8
c
6 Min
Max
20
i
C = = = 4 10 F = 0.04 F
dv
50010
dt
The circuit turn off time is the time taken by the capacitor voltage to reach zero from an initial
value of 200v. This time must be greater than the turn off time of the device.
Now
c
c
dv
C = i = 20
dt
c
off
6
6
20 t
v = v = 200  0 = 200
c
t = t
20 50 10
200 =
C
20 50 10
C = = 5 F
200
For safe commutation of THM the higher value of C must the chosen
the required value of C = 5 F.
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Module
1
Power Semiconductor
Devices
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Lesson
5
Gate Turn Off Thyristor
(GTO)
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Instructional objective
On completion the student will be able to
Differentiate between the constructional features of a GTO and a Thyristor.
Explain the turn off mechanism of a GTO.
Differentiate between the steady state output and gate characteristics of a GTO and a
thyristor.
Draw and explain the switching characteristics of a GTO.
Draw the block diagram of a GTO gate drive unit and explain the functions of different
blocks.
Interpret the manufacturers data sheet of a GTO.
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Introduction
The thyristor has reigned supreme for well over two decades in the power electronics industry
and continues to do so at the very highest level of power. It, however, has always suffered from
the disadvantage of being a semicontrolled device. Although it could be turned on by applying a
gate pulse but to turn it off the main current had to be interrupted. This proved to be particularly
inconvenient in DC to AC and DC to DC conversion circuits, where the main current does not
naturally becomes zero. A bulky and expensive commutation circuit had to be used to ensure
proper turning off of the thyristor. The switching speed of the device was also comparatively
slow even with fast inverter grade thyristor. The development of the Gate Turn off thyristor
(GTO) has addressed these disadvantages of a thyristor to a large extent. Although it has made a
rather late entry (1973) into the thyristor family the technology has matured quickly to produce
device comparable in rating (5000V, 4000Amp) with the largest available thyristor.
Consequently it has replaced the forced commutated inverter grade thyristor in all DC to AC and
DC to DC converter circuits.
Like thyristor, the GTO is a current controlled minority carrier (i.e. bipolar) device. GTOs differ
from conventional thyristor in that, they are designed to turn off when a negative current is sent
through the gate, thereby causing a reversal of the gate current. A relatively high gate current is
need to turn off the device with typical turn off gains in the range of 45. During conduction, on
the other hand, the device behaves just like a thyristor with very low ON state voltage drop.
Several different varieties of GTOs have been manufactured. Devices with reverse blocking
capability equal to their forward voltage ratings are called symmetric GTOs. However, the
most poplar variety of the GTO available in the market today has no appreciable reverse voltage
(2025v) blocking capacity. These are called Asymmetric GTOs. Reverse conducting GTOs
(RCGTO) constitute the third family of GTOs. Here, a GTO is integrated with an antiparallel
freewheeling diode on to the same silicon wafer. This lesson will describe the construction,
operating principle and characteristic of Asymmetric GTOs only.
5.2 Constructional Features of a GTO
Fig 5.1 shows the circuit symbol and two different schematic cross section of a GTO.
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A
G
K
(a)
Fig. 5.1: Circuit symbol and schematic cross section of a GTO
(a) Circuit Symbol, (b) Anode shorted GTO structure,
(c) Buffer layer GTO structure.
Anode
Short.
p
+
n
p
n
+
n
+
C
G
(b)
p
+
p
+
n
+
n
+
(c)
Anode
Contact
n

p
n
+
n
+
C
G
p
+
n
Buffer
Layer
J
1
J
2
J
3
Like a thyristor, a GTO is also a four layer three junction pnpn device. In order to obtain high
emitter efficiency at the cathode end, the n
+
cathode layer is highly doped. Consequently, the
break down voltage of the function J
3
is low (typically 2040V). The p type gate region has
conflicting doping requirement. To maintain good emitter efficiency the doping level of this
layer should be low, on the other hand, from the point of view of good turn off properties,
resistively of this layer should be as low as possible requiring the doping level of this region to
be high. Therefore, the doping level of this layer is highly graded. Additionally, in order to
optimize current turn off capability, the gate cathode junction must be highly interdigitated. A
3000 Amp GTO may be composed of upto 3000 individual cathode segments which are a
accessed via a common contact. The most popular design features multiple segments arranged in
concentric rings around the device center.
The maximum forward blocking voltage of the device is determined by the doping level and the
thickness of the n type base region next. In order to block several kv of forward voltage the
doping level of this layer is kept relatively low while its thickness is made considerably higher (a
few hundred microns). Byond the maximum allowable forward voltage either the electric field at
the main junction (J
2
) exceeds a critical value (avalanche break down) or the n base fully
depletes, allowing its electric field to touch the anode emitter (punch through).
The junction between the n base and p+ anode (J
1
) is called the anode junction. For good turn
on properties the efficiency of this anode junction should be as high as possible requiring a
heavily doped p+ anode region. However, turn off capability of such a GTO will be poor with
very low maximum turn off current and high losses. There are two basic approaches to solve this
problem.
In the first method, heavily doped n+ layers are introduced into the p+ anode layer. They make
contact with the same anode metallic contact. Therefore, electrons traveling through the base can
directly reach the anode metal contact without causing hole injection from the p+ anode. This is
the classic anode shorted GTO structure as shown in Fig 5.1 (b). Due to presence of these
anode shorts the reverse voltage blocking capacity of GTO reduces to the reverse break down
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voltage of junction J
3
(2040 volts maximum). In addition a large number of anode shorts
reduces the efficiency of the anode junction and degrades the turn on performance of the device.
Therefore, the density of the anode shorts are to be chosen by a careful compromise between
the turn on and turn off performance.
In the other method, a moderately doped n type buffer layer is juxtaposed between the n

type
base and the anode. As in the case of a power diode and BJT this relatively high density buffer
layer changes the shape of the electric field pattern in the n

base region from triangular to
trapezoidal and in the process, helps to reduce its width drastically. However, this buffer layer in
a conventional anode shorted GTO structure would have increased the efficiency of the anode
shorts. Therefore, in the new structure the anode shorts are altogether dispensed with and a thin
p+ type layer is introduce as the anode. The design of this layer is such that electrons have a high
probability of crossing this layer without stimulating hole injection. This is called the
Transparent emitter structure and is shown in Fig 5.1 (c).
Exercise 5.1
Fill in the blank(s) with the appropriate word(s)
i. A GTO is a _______________ controlled _______________ carrier device.
ii. A GTO has _______________ layers and _______________ terminals.
iii. A GTO can be turned on by injecting a _______________ gate current and turned off by
injecting a _______________ gate current.
iv. The anode shorts of a GTO improves the _______________ performance but degrades
the _______________ performance.
v. The reverse voltage blocking capacity of a GTO is small due to the presence of
_______________.
Answer: (i) current, minority; (ii) four, three; (iii) positive, negative; (iv) turn off, turn on; (v)
anode shorts.
5.3 Operating principle of a GTO
GTO being a monolithic pnpn structure just like a thryistor its basic operating principle can be
explained in a manner similar to that of a thyristor. In particular, the pnpn structure of a GTO
can be though of consisting of one pnp and one npn transistor connected in the regenerative
configuration as shown in Fig 5.2.
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Hole current
Electron
current
A
p
n
p
n
n
p
G
C
(a)
A
n
G
C
p
I
K
I
G
I
A
i
C2
i
C1
i
B
i
B2
Hole current
Electron
current
A
p
n
p
n
n
p
C
(b)
G
p
n
p
G
A
Fig 5.2: Current distribution in a GTO
(a) During turn on; (b) During turn off.
From the two transistor analogy (Fig 5.2 (a)) of the GTO structure one can write.
( )
( )
( )
C1 p A CBO1
B1 C 2 n k CBO2
k A G A B1 C1
i = I + I 5.1
i = i = I + I 5.2
I = I + I and I = i + i 5.3
( )
( )
( )
n G CBO1 CBO2
A
n p
I + i +i
Combining I = 5.4
1 +
With applied forward voltage V
AK
less than the forward break over voltage both I
CBO1
and I
CBO2
are small. Further if I
G
is zero I
A
is only slightly higher than (I
CBO1
+ I
CBO2
). Under this condition
both
n
and
p
are small and (
p
+
n
) <<1. The device is said to be in the forward blocking
mode.
To turn the device on either the anode voltage can be raised until I
CBO1
and I
CBO2
increases by
avalanche multiplication process or by injecting a gate current. The current gain of silicon
transistors rises rapidly as the emitter current increases. Therefore, any mechanism which causes
a momentary increase in the emitter current can be used to turn on the device. Normally, this is
done by injecting current into the p base region via the external gate contract. As
n
+
p
approaches unity the anode current tends to infinity. Physically as
n
+
p
nears unity the device
starts to regenerate and each transistor drives its companion into saturation. Once in saturation,
all junctions assume a forward bias and total potential drop across the device becomes
approximately equal to that of a single pn diode. The anode current is restricted only by the
external circuit. Once the device has been turned on in this manner, the external gate current is
no longer required to maintain conduction, since the regeneration process is selfsustaining.
Reversion to the blocking mode occurs only when the anode current is brought below the
holding current level.
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To turn off a conducting GTO the gate terminal is biased negative with respect to the cathode.
The holes injected from the anode are, therefore, extracted from the p base through the gate
metallization into the gate terminal (Fig 5.2 (b)). The resultant voltage drop in the p base above
the n emitter starts reverse biasing the junction J
3
and electron injection stops here. The process
originates at the periphery of the p base and the n emitter segments and the area still injecting
electron shrinks. The anode current is crowded into higher and higher density filaments in most
remote areas from the gate contact. This is the most critical phase in the GTO turn off process
since highly localized high temperature regions can cause device failure unless these current
filaments are quickly extinguished. When the last filament disappears, electron injection stops
completely and depletion layer starts to grow on both J
2
and J
3
. At this point the device once
again starts blocking forward voltage. However, although the cathode current has ceased the
anode to gate current continues to flow (Fig 5.2 (b)) as the n base excess carriers diffuse towards
J
1
. This tail current then decays exponentially as the n base excess carriers reduce by
recombination. Once the tail current has completely disappeared does the device regain its steady
state blocking characteristics. Anode Shorts (or transparent emitter) helps reduce the tail
current faster by providing an alternate path to the n base electrons to reach the anode contact
without causing appreciable hole injection from anode.
Exercise 5.2
Fill in the blank(s) with the appropriate word(s)
i. After a GTO turns on the gate current can be _______________.
ii. A conducting GTO reverts back to the blocking mode when the anode current falls below
_______________ current.
iii. To turn off a conducting GTO the gate terminal is biased _______________ with respect
to the _______________.
iv. Current filaments produced during the turn off process of a GTO can destroy the device
by creating local _______________.
v. Anode shorts help to reduce the _______________ current in a GTO.
Answer: (i) removed; (ii) holding; (iii) negatively, cathode; (iv) hot spot; (v) tail.
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5.4 Steady state and dynamic characteristics of a GTO
5.4.1 Steady state output and gate characteristics
I
G
v
g
Min Max
(b)
Fig. 5.3: Steady state characteristics of a GTO
(a) Output characteristics; (b) Gate characteristics.
V
AK
I
G
I
A
v
g
+

V
BRR
V
BRF
V
AK
I
A
I
L
I
L
+

(a)
This characteristic in the first quadrant is very similar to that of a thyristor as shown in Fig. 5.3
(a). However, the latching current of a GTO is considerably higher than a thyristor of similar
rating. The forward leakage current is also considerably higher. In fact, if the gate current is not
sufficient to turn on a GTO it operates as a high voltage low gain transistor with considerable
anode current. It should be noted that a GTO can block rated forward voltage only when the gate
is negatively biased with respect to the cathode during forward blocking state. At least, a low
value resistance must be connected across the gate cathode terminal. Increasing the value of this
resistance reduces the forward blocking voltage of the GTO. Asymmetric GTOs have small (20
30 V) reverse break down voltage. This may lead the device to operate in reverse avalanche
under certain conditions. This condition is not dangerous for the GTO provided the avalanche
time and current are small. The gate voltage during this period must remain negative.
Fig 5.3 (b) shows the gate characteristics of a GTO. The zone between the min and max curves
reflects parameter variation between individual GTOs. These characteristics are valid for DC and
low frequency AC gate currents. They do not give correct voltage when the GTO is turned on
with high
dia
dt
and
G
dI
dt
. V
G
in this case is much higher.
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5.4.2 Dynamic characteristics of a GTO
Fig. 5.4: Switching characteristics of a GTO.
i
A
, V
AK
V
D
0.9V
D
0.1V
D
I
g
Vg
t
d
t
r
I
GM
t
ON
V
T
I
G
I
gQ
Q
gQ
V
gR
t
tail
I
tail
0.9I
L
0.1I
L
V
DM I
L
V
D
t
f
t
s
t
t
dig/dt
gQ
di
dt
i
g
v
g
V
d
R
L
I
L
di/dt
limiting
L
di
dt
Fig 5.4 shows the switching characteristics of a GTO and refers to the resistive dc load switching
circuit shown on the right hand side. When the GTO is off the anode current is zero and V
AK
=
V
d
. To turn on the GTO, a positive gate current pulse is injected through the gate terminal. A
substantial gate current ensure that all GTO cathode segments are turned on simultaneously and
within a short time. There is a delay between the application of the gate pulse and the fall of
anode voltage, called the turn on delay time t
d
. After this time the anode voltage starts falling
while the anode current starts rising towards its steady value I
L
. Within a further time interval t
r
they reach 10% of their initial value and 90% of their final value respectively. t
r
is called the
current rise time (voltage fall time). Both t
d
and maximum permissible on state
A
di
dt
are very
much gate current dependent. High value of I
gM
and
dig
dt
at turn on reduces these times and
increases maximum permissible on state
A
di
dt
. It should be noted that large value of i
g
(I
gM
)
and
dig
dt
are required during t
d
and t
r
only. After this time period both v
g
and i
g
settles down to
their steady value. A minimum ON time period t
ON
(min) is required for homogeneous anode
current conduction in the GTO. This time is also necessary for the GTO to be able to turn off its
rated anode current.
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To turn off a GTO the gate terminal is negatively biased with respect to the cathode. With the
application of the negative bias the gate current starts growing in the negative direction.
However, the anode voltage,current or the gate voltage does not change appreciably from their
on state levels for a further time period called the storage time (t
s
). The storage time increases
with the turn off anode current and decrease with
gQ
di
dt
. During storage time the load current at
the cathode end is gradually diverted to the gate terminal. At the end of the storage time gate
current reaches its negative maximum value I
gQ
. At this point both the junctions J
2
& J
3
of the
GTO starts blocking voltage. Consequently, both the gate cathode and the anode cathode voltage
starts rising towards their final value while the anode current starts decreasing towards zero. At
the end of current fall time t
f
the anode current reaches 10% of its initial value after which both
the anode current and the gate current continues to flow in the form of a current tail for a further
duration of t
tail.
A GTO is normally used with a RC turn off snubber. Therefore, V
AK
does not
start to rise appreciably till t
f
. At this point V
AK
starts rising rapidly and exceeds the dc voltage
V
d
(V
dM
) (due to resonance of snubber capacitor with
di
dt
limiting inductor) before setting
down at its steady value V
d
. A GTO should not be retriggered within a minimum off period off
(min) to avoid the risk of failure due to localized turn ON. GTOs have typically low turn off gain
in the range of 45.
5.4.3 GTO gate drive circuit
A GTO gate drive has to fulfill the following functions.
Turn the GTO on by means of a high current pulse (I
GM
)
Maintain conduction through provision of a continuous gate current (I
G
, also known as
the backporch current).
Turn the GTO off with a high negative gate current pulse.
Reinforce the blocking state of the device by a negative gate voltage.
A typical gate drive arrangement for a large power GTO is show in Fig 5.5.
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Fig. 5.5: Gate drive circuit of a GTO.
(a) Block diagram,
(b) Circuit diagram of the output stage
ON
OFF
R
1
R
2
R
3
C
2
T
1
T
2
A
K
G
+
+
+



(b)
H.F.DC to
AC INV.
H.F TXF
H.F. AC to DC
Rectifier
Output
Stage
Control
Logic
Electrical
Optical
Fiber optic
cable
Optical 
Electrical
Converter
A B C D
E
F
(a)
In the block diagram of Fig 5.5 (a) it is assumed that there is a potential difference of several kVs
between the master control and individual gate units.
The ON and OFF pulses for a GTO is communicated to individual gate units through fiber optic
cables. These optical signals are converted to electrical signals by a optical electrical converter.
These electrical signals through the control logic then produces the ON and OFF signal for the
out put stage which in turn sends positive and negative gate current to the GTO. Depending on
the requirement the control logic may also supervise GTO conduction by monitoring the gate
cathode voltage. Any fault is relayed back via fiber optic cable to the master control. Power
supply for the Gate drive units are derived from a common power supply through a high
frequency SMPS (Blocks A, B & C) arrangement.
Fig 5.5 (b) shows the circuit implementation of the output stage. The top switch T
1
sends positive
gate pulse to the GTO gate. At the instant of turn on of T
1
,C
2
acts almost as a short circuit and
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the positive gate current is determined by the parallel combination of R
1
and R2. However, at
steady state only R
1
determines the gate current I
G
.
The bottom switch T
2
is used for biasing the GTO gate negative with respect to the cathode.
Since, relatively large negative gate current flows during turn off, no external resistance is used
in series with T
2
. Instead, the ON state resistance of T
2
is utilized for this purpose. In practice, a
large number of switches are connected in parallel to obtain the required current rating of T
2
. A
low value resistance R
3
is connected between the gate and the cathode terminals of the GTO to
ensure minimum forward blocking voltage.
Exercise 5.3
Fill in the blank(s) with the appropriate word(s)
i. The _______________ current and forward _______________ current of a GTO are
considerably higher compared to a thyristor.
ii. If the gate current is insufficient a GTO can operate as a low gain _______________.
iii. Reverse blocking voltage of _______________ GTO is small.
iv. To ensure that all GTO cathode segments are turned on simultaneously the magnitude of
the _______________ current should be _______________.
v. High value of gate current and dig/dt enhances the _______________ capability of a
GTO during turn on.
vi. During storage time the load current in a GTO is diverted from the _______________ to
the _______________ terminal.
vii. GTOs have low turn off _______________ gain.
viii. After the current fall time during turn off of a GTO the anode current continuous for
some more time in the form of a _______________.
ix. The gate drive unit of a GTO should provide continuous positive gate _______________
during ON period and continuous negative gate _______________ during OFF period.
x. In the gate drive unit of a GTO a low value resistance is connected between the gate and
the cathode terminals to ensure minimum _______________ voltage.
Answer: (i) latching, leakage; (ii) transistor; (iii) asymmetric; (iv) gate, high; (v) di/dt;
(vi) cathode, gate; (vii) current; (viii) current tail; (ix) current, voltage; (x)
forward blocking.
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5.5 GTO Ratings
5.5.1 Steady state voltage and current rating
V
DRM
: It is the maximum repetitive forward voltage the GTO can block in the forward
direction assuming line frequency sinusoidal voltage waveform. It is important to note that GTO
can block rated voltage only if the gate is reverse biased or at least connected to the cathode
through a low value resistance. Manufactures usually provide the forward voltage withstanding
capacity of the GTO as a functions of the gate cathode reverse voltage (and /or resistance) for a
given forward
dv
dt
.
V
RRM
: It is the maximum repetitive reverse voltage the GTO is able to withstand. For all
asymmetric GTOs this value is in the range of 2030 V, since it is determined by the gate
cathode junction break down voltage. Due to the anode shorted structure of the GTO the anode
base junction (J
1
) does not block any reverse voltage. Unlike V
DRM
, V
RRM
rating may be
exceeded for a short time without destroying the device. This reverse avalanche capability of
the GTO is useful in certain situations as explained in Fig 5.6.
V
D
I
G1
V
G1
V
G2
G
1
G
2
D
1
D
2
I
D2
I
L
(a)
(b)
V
G1
I
G1
I
L
I
G1
V
G1
I
L
V
D
V
D
V
G2
I
D2
V
fr
> V
RRM
t
t
Fig. 5.6: Reverse avalanche capability of a GTO
(a) Voltage source inverter phase leg;
(b) Voltage, current waveforms.
In the voltage source inverter phase leg shown in Fig 5.6 (a), as the GTO G
1
is turned off the
current through it (I
G1
) starts reducing. The difference current (I
L
 I
G1
) is transferred to the
snubber capacitance of G
1
and the voltage across G
1
(V
G1
) starts increasing. When if becomes
equal to the dc link voltage V
D
, D
2
is forward biased. However, due to the forward recovery
voltage of D
2
(V
fr
) the reverse voltage across G
2
may exceed V
RRM
rating of G
2
and drive it into
reverse avalanche. This condition is not dangerous for G
2
provided the avalanche time and
current are small (typically within 10 s and 1000 A respectively). However, the gate voltage
must remain negative during this time.
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V
DC
: This is the maximum continuous DC voltage the device can withstand. Exceeding this
voltage does not immediately lead to device failure, but the probability of a cosmic radiation
failure increases progressively with the applied dc voltage.
I
FAVM
and I
FRMS
: These are maximum average and RMS on state current respectively. They are
specified at a given case temperature assuming half wave sinusoidal on state current at power
frequency.
I
FSM
: This is the maximum allowed peak value of a power frequency half sinusoidal non
repetitive surge current. The pulse is assumed to be applied at an instant when the GTO is
operating at its maximum junction temperature. The voltage across the device just after the surge
should be zero.
2
i dt : This is the limiting value of the surge current integral assuming half cycle sine wave
surge current. The junction temperature is assumed to be at the maximum value before the surge
and the voltage across the device following the surge is assumed to be zero. The i
2
t rating of a
semiconductor fuse must be less than this value in order to protect the GTO. Plots of both I
FSM
and as functions of surge pulse width are usually provided by the manufacturer.
2
i dt
V
F
: This is the plot of the instantaneous forward voltage drop vs instantaneous forward
current at different junction temperatures.
P
av
: For some frequently encountered current waveforms (e.g. sine wave, square wave) the
plot of the average on state power dissipation as a function of the average on state current is
provided by the manufacturers at a given junction temperature.
I
H
: This is the holding current of the GTO. This current, in case of a GTO
1
, is considerably
higher compared to a similarly rated thyristor. Serious problem may arise due to anode current
variation because the GTO may unlatch at an in appropriate moment. This problem can be
avoided by feeding a continuous current into the gate (called the back porch current) during
ON period of the device. This DC gate current should be about 20% higher than the gate trigger
current (I
GT
) at the lowest expected junction temperature.
crit
di
:
dt
This is the maximum permissible value of the rate of change of forward current during
turn on. This value is very much dependent on the peak gate current magnitude and the rate of
increase of the gate current. A substantial gate current ensures that all GTO cathode segments are
turned ON simultaneously and within a short time so that no local hot spot is created.
The
g
di
dt
and I
gM
values specified in the operating conditions should, therefore, be considered as
minimum values.
5.5.2 Gate specification
I
g
vs V
g
: It is a plot of instantaneous gate current as a function of the gate voltage. This
characteristic is valid for DC and low frequency AC gate currents. They do not define the gate
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voltage when the GTO is turned on from high anode voltage with high di/dt and
g
di
dt
. Vg in this
case is much higher. Generally the gate cathode impedance of a GTO is much lower than that of
a conventional thyristor.
V
gt
, I
gt
: I
gt
is the gate trigger current and V
gt
, the instantaneous gate cathode voltage when I
gt
is
flowing into the gate. I
gt
has a strong junction temperature dependence and increases very rapidly
with reduced junction temperature. I
gt
merely specifies the minimum back porch current
necessary to turn on the GTO at a low
di
dt
and maintain it in conduction.
V
grm
: It is the maximum repetitive reverse gate voltage, exceeding which drives the gate
cathode junction into avalanche breakdown.
I
grm
: It is the peak repetitive reverse gate current at V
grm
and T
j
(max).
I
gqm
: It is the maximum negative turn off gate current. The gate unit should be designed to
deliver this current under any condition. It is a function of turn off anode current,
g
di
dt
during
turn off and the junction temperature.
5.5.3 Specifications related to the switching performance
t
d
, t
r
, : These are turn on delay time and anode voltage fall time respectively. Both of them can
be reduced with higher
g
di
dt
and I
gM
for a given turn on anode voltage, current and
di
dt
.
t
on
(min) : This is the minimum time the GTO requires to establish homogeneous anode current.
This time is also necessary for the GTO to be able to turn off its rated anode current.
E
ON
: It is the energy dissipated during each turn on operation. Manufacturers specify them as
functions of turn on anode current for different turn on di/dt and anode voltage E
ON
reduces with
increased I
gM
.
I
Fgqm
: It is the maximum anode current that can be repetitively turned off by a negative gate
current. It can be increased by increasing the value of the turn off snubber capacitance which
limits the dv/dt at turn off. A large negative dig/dt during turn off also helps to increase I
Fgqm
.
t
s
: The storage time t
s
is defined as the time between the start of negative gate current and
the decrease in anode current. High value of the turn off anode current and junction temperature
increases it while a large negative dig/dt during turn off decreases it.
t
f
: This is the anode current fall time. It can not be influenced much by gate control.
t
off
(min) : This is the minimum off time before the GTO may be triggered again by a positive
gate current. If the device is retriggered during this time, localized turn on may destroy it.
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E
off
: This is the energy dissipated during each turn off operation of the GTO. E
off
increases
with increase in the turn off anode current and junction temperature while it reduces with turn off
snubber capacitance.
Exercise 5.4
Fill in the blank(s) with the appropriate word(s)
i. A GTO can block rated forward voltage only when the gate is _______________ biased
with respect to the _______________.
ii. A GTO can operate in the reverse _______________ region for a short time.
iii. The holding current of a GTO is much _______________ compared to a thyristor.
iv. After a current surge the voltage across a GTO should be reduced to _______________.
v. The gate cathode impedance of a GTO is much _______________ compared to a
thyristor.
vi. The turn on di/dt capability of a GTO can be increased by in creasing the
_______________ magnitude of the gate current and _______________ during turn on.
vii. The turn on delay time and current rise time of a GTO can be reduced by increasing the
gate current _______________ and _______________ during turn ON.
viii. The maximum anode current that can be turned off repetitively can be increased by
increasing the turn off snubber _______________ and negative _______________.
Answer: (i) negatively, cathode; (ii) avalanche; (iii) larger; (iv) zero; (v) smaller; (vi)
peak, dig/dt; (vii) magnitude, dig/dt; (viii) capacitance, dig/dt.
Reference
1) GTO and GCT product guide, ABB semiconductors AG, 1997.
2) GTO Thyristors , Makoto Azuma and Mamora Kurata, Proceedings of the IEEE,
Vol.76, No. 4, April 1988, pp 419427.
3) Power Electronics, P. S. Bimbhra, Khanna Publlishers, 1993.
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Lesson Summary
GTO is a four layer, three terminal current controlled minority carrier device.
A GTO can be turned on by applying a positive gate current pulse when it is forward
biased and turned off by applying a negative gate current.
A GTO has a shorted anode and highly interdigitized gate cathode structure to
improve the gate turn off performance.
Due to the presence of anode shorts a GTO can block only a small reverse voltage.
These are called asymmetric GTOs.
The forward iv characteristics of a GTO is similar to that of a thyristor. However, they
have relatively larger holding current and gate trigger current.
The turn on di/dt capability of a GTO is significantly enhanced by using higher peak gate
current and large rate of rise of the gate current.
Due to relatively larger holding current of a GTO a continuous low value gate current
(called the back porch current) should be injected through out the on period of the GTO.
GTOs have relatively low turn off current gain.
The GTO gate drive unit should be capable of injecting large positive and negative gate
currents with large rate of rise for satisfactory switching of the device.
A GTO can block rated forward voltage only when the gate cathode junction is reverse
biased.
A GTO can operate safely in the reverse avalanche region for a short time provided the
gate cathode junction is reverse biased.
The switching delay times and energy loss of a GTO can be reduced by increasing the
gate current magnitude and its rate of rise.
The maximum turn off anode current of a GTO can be increased by increasing the turn
off snubber capacitance.
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Practice Problems and Answers
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1. What are the constructional features of a GTO that bestows it with a gate turn off
capability? How do they affect the turn on performance of the GTO?
2. What are the main differences in the steady state output characteristics of a GTO and a
thyristor? What effect do they have on the gate drive requirement of a GTO?
3. What are the desirable characteristics of the gate drive circuit of a GTO? How do they
influence the switching performance of a GTO?
4. What is the significance of the specifications I
FAVM
and I
FRMS
in relation to a GTO? Is the
specification I
Fgqm
. Same as I
FAVM
/ I
FRMS
? If not, then which current should one use in a
particular application?
5. Which paramers of the gate current waveform reduces the turn on energy loss (E
ON
) of a
GTO? How does one reduce the turn off energy lass of a GTO?
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Answers to practice problems
1. Although a GTO is a four layer (pnpn) three junction devices like a thyristor it has two
important constructional differences with a thyristor which bestows it with the gate turn off
capability.
The Gatecathode junction of a GTO is far more inter digitized compared to a thyristor.
Thousands of cathode segments, normally arranged in concentric rings around the device
center, from the cathode structure of a GTO. This highly inter digitized structure of the
GTO cathode ensures that any current filament formed during the turn off process of a
GTO is quickly extinguished.
Anode shorts are introduced at the p+ type anode and n type base junction of a GTO.
Anode shorts consists of heavily doped n+ type region introduced inside the p+ type
anodes. They make direct contact with the anode metal plate and provide an alternate path
for the electrons traveling through the n base to reach the anode metal contact without
causing bole injection from the p+ anode. This helps to reduce the tail current during turn
off of a GTO.
Highly inter digitized gatecathode structure of a GTO helps to enhance the turn on di/dt
capability of the device due to faster and more even spreading of the injected gate current
to adjacent cathodes.
On the other hand, presence of anode shorts has adverse effect on the turn on performance
of a GTO. Referring to Fig 5.2 (a), introduction of anode shorts effectively reduces the
current gain p of the top pnp transistor. This has the effect of increasing the latching
and holding current of a GTO compared to a thyristor. The minimum gate current required
to trigger a GTO also increases.
2. In the first quadrant of the output iv plane the steady state output characteristics of a GTO
appears to be similar to that of a thyristor. There are some important differences however.
Both holding and latching current of a GTO are considerably higher compared to a
similarly rated thyrisstor.
The minimum gate current require to trigger a GTO at a given forward blocking voltage is
higher compared to a thyristor.
The forward leakage current of a GTO is considerably higher compared to a thyristor of
equal rating. In fact, if the gate current is not sufficient to turn on a GTO it may operate as
a high voltage low gain transistor with considerable anode current.
A GTO can block rated forward voltage only when the gate voltage is negative with respect
to the cathode or at least the gate is connected to the cathode through a low value
resistance.
In the reverse blocking region (i.e third quadrant of the output iv plane) an asymmetric
GTO has much lower reverse break down voltage (2030V) compared to a thyristors.
Exceeding this reverse voltage forces the GTO to operate in the reverse avalanche mode.
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This mode of operation does not destroy the device provided the gate is negatively biased
and the time of such operation is small.
Since the holding current of a GTO is considerably higher than that of a thyristor anode
current variations can generate serious problem because the GTO might unlatch at an
inappropriate moment. To avoid this problem the gate drive unit of a GTO must feed the
gate terminal with a continuous back porch current during the entire on period of the
GTO. This back porch current must be larger than the gate trigger current.
To avoid localized transistor operation during turn on from a high anode voltage with large
di/dt, the gate drive unit must inject a peak gate current considerably larger (310 times)
than the gate trigger current with fast rate of rise.
To ensure that the GTO blocks rated forward voltage and operates safely in the reverse
avalanche mode the gate voltage must be maintained negative with respect to the cathode
for the entire off duration of the GTO.
3. The gate drive unit of a GTO should.
Turn the GTO on with a large (310 times the minimum gate trigger current) positive gate
current pulse with high rate of rise.
Maintain conduction of the GTO through out the ON period by injecting a positive back
porch gate current which is larger than the minimum gate trigger current.
Turn the GTO off with a large negative gate current with high rate of fall. The peak
magnitude of the negative gate current should be at least 2025% of the maximum anode
current during turn off.
Reinforce the blocking state of the device by applying a negative voltage to the gate with
respect to cathode for the entire off duration of the GTO.
Both the turn on delay time (t
d
) and the voltage fall time (t
r
) of a GTO can be reduced by
increasing the peak positive gate current and its rate of rise during turn on. Energy loss per
turn on (E
ON
) also reduces.
A large negative gate current during turn off with a stiff slope considerably reduces the
storage time (t
s
) and enhances maximum anode current turn off (I
Fgqm
) capability.
4. The specifications of I
FAVM
and I
FRMS
are given with reference to power frequency half
cycle sine wave anode current. If the GTO is employed in a line commutated phase
controlled converter application then these specifications give the maximum allowable
average and RMS current through the device respectively. However, in most GTO
applications the current waveform is for removed from a sinusoidal shape and the
switching losses are a considerable part of the total power losses. I
FAVM
/ I
FRMS
ratings, in
such cases, does not have any practical significance except for comparison of current
carrying capacity of different devices.
On the other hand, I
Fgqm
rating of a GTO gives the maximum anode current that can be
repetitively turned off by gate control. This rating is usually lower than I
FAVM
/ I
FRMS
. In
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high frequency switching application this specification gives the absolute peak value of any
desired current waveform the GTO can conduct.
5. E
on
is reduced by increasing the peak magnitude of the positive gate current during turn on.
E
off
is reduced by increasing the turn off snubber capacitance across the GTO.
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Module
1
Power Semiconductor
Devices
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Lesson
6
Metal Oxide
Semiconductor Field
Effect Transistor
(MOSFET)
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Constructional Features, operating principle and characteristics of Power Metal Oxide
Semiconductor Field Effect Transistor (MOSFET).
Instructional Objectives
On completion the student will be able to
Differentiate between the conduction mechanism of a MOSFET and a BJT.
Explain the salient constructional features of a MOSFET.
Draw the output iv characteristics of a MOSFET and explain it in terms of the operating
principle of the device.
Explain the difference between the safe operating area of a MOSFET and a BJT.
Draw the switching characteristics of a MOSFET and explain it.
Design the gate drive circuit of a MOSFET.
Interpret the manufacturers data sheet rating of a MOSFET.
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6.1 Introduction
Historically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc)
have been the front runners in the quest for an ideal power electronic switch. Ever since the
invention of the transistor, the development of solidstate switches with increased power
handling capability has been of interest for expending the application of these devices. The BJT
and the GTO thyristor have been developed over the past 30 years to serve the need of the power
electronic industry. Their primary advantage over the thyristors have been the superior switching
speed and the ability to interrupt the current without reversal of the device voltage. All bipolar
devices, however, suffer from a common set of disadvantages, namely, (i) limited switching
speed due to considerable redistribution of minority charge carriers associated with every
switching operation; (ii) relatively large control power requirement which complicates the
control circuit design. Besides, bipolar devices can not be paralleled easily.
The reliance of the power electronics industry upon bipolar devices was challenged by the
introduction of a new MOS gate controlled power device technology in the 1980s. The power
MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The
new device promised extremely low input power levels and no inherent limitation to the
switching speed. Thus, it opened up the possibility of increasing the operating frequency in
power electronic systems resulting in reduction in size and weight. The initial claims of infinite
current gain for the power MOSFET were, however, diluted by the need to design the gate drive
circuit to account for the pulse currents required to charge and discharge the high input
capacitance of these devices. At high frequency of operation the required gate drive power
becomes substantial. MOSFETs also have comparatively higher on state resistance per unit area
of the device cross section which increases with the blocking voltage rating of the device.
Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts)
applications where the ON state resistance reaches acceptable values. Inherently fast switching
speed of these devices can be effectively utilized to increase the switching frequency beyond
several hundred kHz.
From the point of view of the operating principle a MOSFET is a voltage controlled
majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is
controlled by the voltage applied on the control electrode (called gate) which is insulated by a
thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate
voltage modulate the conductivity of the semiconductor material in the region between the main
current carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just like
their integrated circuit counterpart, can be of two types (i) depletion type and (ii) enhancement
type. Both of these can be either n channel type or pchannel type depending on the nature of
the bulk semiconductor. Fig 6.1 (a) shows the circuit symbol of these four types of MOSFETs
along with their drain current vs gatesource voltage characteristics (transfer characteristics).
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G
D
I
D
S
G
D
I
D
S
D
I
D
G
S
D
I
D
G
S
I
D
V
GS
nchannel depletion type
MOSFET
I
D
V
GS
pchannel depletion type
MOSFET
I
D
V
GS
nchannel enhancement
type MOSFET
I
D
V
GS
pchannel enhancement
type MOSFET
(a)
(b)
Fig 6.1: Different types of power MOSFET.
(a) Circuit symbols and transfer characteristics
(b) Photograph of nchannel enhancement type MOSFET.
From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type
switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This
is not convenient in many power electronic applications. Therefore, the enhancement type
MOSFETs (particularly of the nchannel variety) is more popular for power electronics
applications. This is the type of MOSFET which will be discussed in this lesson. Fig 6.1 (b)
shows the photograph of some commercially available nchannel enhancement type Power
MOSFETs.
6.2 Constructional Features of a Power MOSFET
As mentioned in the introduction section, Power MOSFET is a device that evolved from
MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs were
by redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting
technology was called lateral double deffused MOS (DMOS). However it was soon realized that
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much larger breakdown voltage and current ratings could be achieved by resorting to a vertically
oriented structure. Since then, vertical DMOS (VDMOS) structure has been adapted by virtually
all manufacturers of Power MOSFET. A power MOSFET using VDMOS technology has
vertically oriented three layer structure of alternating p type and n type semiconductors as shown
in Fig 6.2 (a) which is the schematic representation of a single MOSFET cell structure. A large
number of such cells are connected in parallel (as shown in Fig 6.2 (b)) to form a complete
device.
FIELD OXIDE
n
+
n
+
n
+
n
+
n
+
p(body)
p(body)
n

(drain drift)
Drain
Gate conductor
Gate oxide
(a)
Source
Field oxide
Gate
Contact to source
Source
Conductor
Gate
Oxide
Conductor
Single
MOSFET
Cell
n
+
n
+
n
+
n
+
n
+
n
+
n

n

p
p
(b)
Fig. 6.2: Schematic construction of a power MOSFET
(a) Construction of a single cell.
(b) Arrangement of cells in a device.
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The two n
+
end layers labeled Source and Drain are heavily doped to approximately the
same level. The p type middle layer is termed the body (or substrate) and has moderate doping
level (2 to 3 orders of magnitude lower than n
+
regions on both sides). The n

drain drift region
has the lowest doping density. Thickness of this region determines the breakdown voltage of the
device. The gate terminal is placed over the n

and p type regions of the cell structure and is
insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate
oxide). The source and the drain region of all cells on a wafer are connected to the same metallic
contacts to form the Source and the Drain terminals of the complete device. Similarly all gate
terminals are also connected together. The source is constructed of many (thousands) small
polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source
regions, to same extent, influences the ON state resistance of the MOSFET.
G
S
D
Parasitic BJT
MOSFET
G
S
D
Body diode
Fig. 6.3: Parasitic BJT in a MOSFET cell.
n
+
n
+
n
+
n

D
Body spreading
resistance
Parasitic BJT
G
S
p
One interesting feature of the MOSFET cell is that the alternating n
+
n

p n
+
structure
embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into
each MOSFET cell as shown in Fig 6.3. The nonzero resistance between the base and the
emitter of the parasitic npn BJT arises due to the body spreading resistance of the p type
substrate. In the design of the MOSFET cells special care is taken so that this resistance is
minimized and switching operation of the parasitic BJT is suppressed. With an effective
short circuit between the body and the source the BJT always remain in cut off and its
collectorbase junction is represented as an anti parallel diode (called the body diode) in
the circuit symbol of a Power MOSFET.
6.3 Operating principle of a MOSFET
At first glance it would appear that there is no path for any current to flow between the
source and the drain terminals since at least one of the p n junctions (source body and
bodyDrain) will be reverse biased for either polarity of the applied voltage between the
source and the drain. There is no possibility of current injection from the gate terminal
either since the gate oxide is a very good insulator. However, application of a positive
voltage at the gate terminal with respect to the source will covert the silicon surface
beneath the gate oxide into an n type layer or channel, thus connecting the Source to the
Drain as explained next.
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The gate region of a MOSFET which is composed of the gate metallization, the gate
(silicon) oxide layer and the pbody silicon forms a high quality capacitor. When a small
voltage is application to this capacitor structure with gate terminal positive with respect to
the source (note that body and source are shorted) a depletion region forms at the interface
between the SiO
2
and the silicon as shown in Fig 6.4 (a).
+++++++++++
Gate Electrode
Depletion layer
boundary.
Source
Electrode
Si0
2
Ionized
acceptor
V
GS1
n
+
n

p
(a)
+++++++++++
Gate Electrode
Depletion layer
boundary.
Source
Electrode
Si0
2
Ionized
acceptor
V
GS2
n
+
n

p
(b)
Free
electron
V
GS2
> V
GS1
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+++++++++++
Gate Electrode
Depletion layer
boundary.
Source
Electrode
Si0
2
Ionized
acceptor
V
GS3
n
+
n

p
(c)
V
GS3
> V
GS2
> V
GS1
Inversion layer
with free electrons
Fig. 6.4: Gate control of MOSFET conduction.
(a) Depletion layer formation;
(b) Free electron accumulation;
(c) Formation of inversion layer.
The positive charge induced on the gate metallization repels the majority hole carriers from
the interface region between the gate oxide and the p type body. This exposes the
negatively charged acceptors and a depletion region is created.
Further increase in V
GS
causes the depletion layer to grow in thickness. At the same time
the electric field at the oxidesilicon interface gets larger and begins to attract free electrons
as shown in Fig 6.4 (b). The immediate source of electron is electronhole generation by
thermal ionization. The holes are repelled into the semiconductor bulk ahead of the
depletion region. The extra holes are neutralized by electrons from the source.
As V
GS
increases further the density of free electrons at the interface becomes equal to the
free hole density in the bulk of the body region beyond the depletion layer. The layer of
free electrons at the interface is called the inversion layer and is shown in Fig 6.4 (c). The
inversion layer has all the properties of an n type semiconductor and is a conductive path or
channel between the drain and the source which permits flow of current between the
drain and the source. Since current conduction in this device takes place through an n type
channel created by the electric field due to gate source voltage it is called Enhancement
type nchannel MOSFET.
The value of V
GS
at which the inversion layer is considered to have formed is called the
Gate Source threshold voltage V
GS
(th). As V
GS
is increased beyond V
GS
(th) the
inversion layer gets some what thicker and more conductive, since the density of free
electrons increases further with increase in V
GS
. The inversion layer screens the depletion
layer adjacent to it from increasing V
GS
. The depletion layer thickness now remains
constant.
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Exercise 6.1 (after section 6.3)
1. Fill in the blank(s) with the appropriate word(s)
i. A MOSFET is a ________________ controlled ________________ carrier device.
ii. Enhancement type MOSFETs are normally ________________devices while depletion
type MOSFETs are normally ________________ devices.
iii. The Gate terminal of a MOSFET is isolated from the semiconductor by a thin layer of
________________.
iv. The MOSFET cell embeds a parasitic ________________ in its structure.
v. The gatesource voltage at which the ________________ layer in a MOSFET is formed
is called the ________________ voltage.
vi. The thickness of the ________________ layer remains constant as gate source voltage
is increased byond the ________________ voltage.
Answer: (i) voltage, majority; (ii) off, on; (iii) SiO
2
, (iv) BJT, (v) inversion, threshold; (vi)
depletion, threshold.
2. What are the main constructional differences between a MOSFET and a BJT? What
effect do they have on the current conduction mechanism of a MOSFET?
Answer: A MOSFET like a BJT has alternating layers of p and n type semiconductors.
However, unlike BJT the p type body region of a MOSFET does not have an external
electrical connection. The gate terminal is insulated for the semiconductor by a thin layer of
SiO
2
. The body itself is shorted with n
+
type source by the source metallization. Thus
minority carrier injection across the sourcebody interface is prevented. Conduction in a
MOSFET occurs due to formation of a high density n type channel in the p type body
region due to the electric field produced by the gatesource voltage. This n type channel
connects n
+
type source and drain regions. Current conduction takes place between the
drain and the source through this channel due to flow of electrons only (majority carriers).
Where as in a BJT, current conduction occurs due to minority carrier injection across the
BaseEmitter junction. Thus a MOSFET is a voltage controlled majority carrier device
while a BJT is a minority carrier bipolar device.
6.4 Steady state output iv characteristics of a MOSFET
The MOSFET, like the BJT is a three terminal device where the voltage on the gate
terminal controls the flow of current between the output terminals, Source and Drain. The
source terminal is common between the input and the output of a MOSFET. The output
characteristics of a MOSFET is then a plot of drain current (i
D
) as a function of the Drain
Source voltage (v
DS
) with gate source voltage (v
GS
) as a parameter. Fig 6.5 (a) shows such a
characteristics.
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Electron Drift
Velocity
Electric
Field (c)
i
D
V
GS V
GS
(th)
Source
region
resistance
Drain
resistance
n
+
n

p
(b)
n
+
Drift
region
resistance
Channel
resistance
i
D
D
G
S
Fig. 6.5: Output iv characteristics of a Power MOSFET
(a) iv characteristics;
(b) Components of ONstate resistance;
(c) Electron drift velocity vs Electric field;
(d) Transfer
Cut off (V
GS
< V
GS
(th))
v
gs1
V
GS2
V
GS3
V
GS4
V
GS5
V
GS6
Increasing V
GS
V
GS
V
GS
(th) = V
DS
Active
[V
GS
V
GS
(th)]<V
DS
ohmic
r
DS
(ON)
i
D
V
DSS
v
DS
(a)
(d)
With gatesource voltage (V
GS
) below the threshold voltage (v
GS
(th)) the MOSFET
operates in the cutoff mode. No drain current flows in this mode and the applied drain
source voltage (v
DS
) is supported by the bodycollector pn junction. Therefore, the
maximum applied voltage should be below the avalanche break down voltage of this
junction (V
DSS
) to avoid destruction of the device.
When V
GS
is increased beyond v
GS
(th) drain current starts flowing. For small values of v
DS
(v
DS
< (v
GS
v
GS
(th)) i
D
is almost proportional to v
DS
. Consequently this mode of operation
is called ohmic mode of operation. In power electronic applications a MOSFET is
operated either in the cut off or in the ohmic mode. The slope of the v
DS
i
D
characteristics
in this mode is called the ON state resistance of the MOSFET (r
DS
(ON)). Several physical
resistances as shown in Fig 6.5 (b) contribute to r
DS
(ON). Note that r
DS
(ON) reduces with
increase in v
GS
. This is mainly due to reduction of the channel resistance at higher value of
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v
GS
. Hence, it is desirable in power electronic applications, to use as large a gatesource
voltage as possible subject to the dielectric break down limit of the gateoxide layer.
At still higher value of v
DS
(v
DS
> (v
GS
v
GS
(th)) the i
D
v
DS
characteristics deviates from
the linear relationship of the ohmic region and for a given v
GS
, i
D
tends to saturate with
increase in v
DS
. The exact mechanism behind this is rather complex. It will suffice to state
that, at higher drain current the voltage drop across the channel resistance tends to decrease
the channel width at the drain drift layer end. In addition, at large value of the electric field,
produced by the large Drain Source voltage, the drift velocity of free electrons in the
channel tends to saturate as shown in Fig 6.5 (c). As a result the drain current becomes
independent of V
DS
and determined solely by the gate source voltage v
GS
. This is the
active mode of operation of a MOSFET. Simple, first order theory predicts that in the
active region the drain current is given approximately by
2
D GS GS
i = K(v  v (th)) (6.1)
Where K is a constant determined by the device geometry.
At the boundary between the ohmic and the active region
DS GS GS
v = v  v (th) (6.2)
Therefore,
2
D DS
i = Kv (6.3)
Equation (6.3) is shown by a dotted line in Fig 6.5 (a). The relationship of Equation (6.1)
applies reasonably well to logic level MOSFETs. However, for power MOSFETs the
transfer characteristics (i
D
vs v
GS
) is more linear as shown in Fig 6.5 (d).
At this point the similarity of the output characteristics of a MOSFET with that of a BJT
should be apparent. Both of them have three distinct modes of operation, namely, (i)cut off,
(ii) active and (iii) ohmic (saturation for BJT) modes. However, there are some important
differences as well.
Unlike BJT a power MOSFET does not undergo second break down.
The primary break down voltage of a MOSFET remains same in the cut off and in
the active modes. This should be contrasted with three different break down
voltages (V
SUS
, V
CEO
& V
CBO
) of a BJT.
The ON state resistance of a MOSFET in the ohmic region has positive temperature
coefficient which allows paralleling of MOSFET without any special arrangement
for current sharing. On the other hand, v
CE
(sat) of a BJT has negative temperature
coefficient making parallel connection of BJTs more complicated.
As in the case of a BJT the operating limits of a MOSFET are compactly represented in a
Safe Operating Area (SOA) diagram as shown in Fig 6.6. As in the case of the FBSOA of a
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BJT the SOA of a MOSFET is plotted on a loglog graph. On the top, the SOA is restricted
by the absolute maximum permissible value of the drain current (I
DM
) which should not be
exceeded even under pulsed operating condition. To the left, operating restriction arise due
to the non zero value of r
DS
(ON) corresponding to v
GS
= v
GS
(Max). To the right, the first
operating restriction is due to the limit on the maximum permissible junction temperature
rise which depends on the power dissipation inside the MOSFET. This limit is different for
DC (continuous) and pulsed operation of different pulse widths. As in the case of a BJT the
pulsed safe operating areas are useful for shaping the switching trajectory of a MOSFET. A
MOSFET does not undergo second break down and no corresponding operating limit
appears on the SOA. The final operation limit to the extreme right of the SOA arises due to
the maximum permissible drain source voltage (V
DSS
) which is decided by the avalanche
break down voltage of the drain body pn junction. This is an instantaneous limit. There is
no distinction between the forward biased and the reverse biased SOAs for the MOSFET.
They are identical.
Log (i
D
)
I
DM
Max.
Power
Dissipation
Limit (T
imax
)
10
5
sec
10
4
sec
10
3
sec
Primary voltage breakdown
limit
Fig. 6.6: Safe operating area of a MOSFET.
DC
r
DS
(ON) limit
(V
GS
= V
GS
(max))
Log (v
DS
) V
DSS
Due to the presence of the anti parallel body diode, a MOSFET can not block any reverse
voltage. The body diode, however, can carry an RMS current equal to I
DM
. It also has a
substantial surge current carrying capacity. When reverse biased it can block a voltage
equal to V
DSS
.
For safe operation of a MOSFET, the maximum limit on the gate source voltage (V
GS
(Max)) must be observed. Exceeding this voltage limit will cause dielectric break down of
the thin gate oxide layer and permanent failure of the device. It should be noted that even
static charge inadvertently put on the gate oxide by careless handling may destroy it. The
device user should ground himself before handling any MOSFET to avoid any static charge
related problem.
Exercise 6.2
Fill in the blank(s) with the appropriate word(s)
i. A MOSFET operates in the ________________ mode when v
GS
< v
GS
(th)
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ii. In the ohmic region of operation of a MOSFET v
GS
v
GS
(th) is greater than
________________.
iii. r
DS
(ON) of a MOSFET ________________ with increasing v
GS
.
iv. In the active region of operation the drain current i
D
is a function of ________________
alone and is independent of ________________.
v. The primary break down voltage of MOSFET is ________________ of the drain
current.
vi. Unlike BJT a MOSFET does not undergo ________________.
vii. ________________ temperature coefficient of r
DS
(ON) of MOSFETs facilitates easy
________________ of the devices.
viii. In a Power MOSFET the relation ship between i
D
and v
GS
v
GS
(th) is almost
________________ in the active mode of operation.
ix. The safe operating area of a MOSFET is restricted on the left hand side by the
________________ limit.
Answer: (i) Cut off; (ii) v
DS
; (iii) decreases; (iv) v
GS
, v
DS
; (v) independent; (vi) second
break down; (vii) Positive, paralleling; (viii) linear; (ix) r
DS
(ON);
6.5 Switching characteristics of a MOSFET
6.5.1 Circuit models of a MOSFET cell
Like any other power semiconductor device a MOSFET is used as a switch in all power
electronic converters. As a switch a MOSFET operates either in the cut off mode (switch
off) or in the ohmic mode (switch on). While making transition between these two states it
traverses through the active region. Being a majority carrier device the switching process in
a MOSFET does not involve any inherent delay due to redistribution of minority charge
carriers. However, formation of the conducting channel in a MOSFET and its
disappearance require charging and discharging of the gatesource capacitance which
contributes to the switching times. There are several other capacitors in a MOSFET
structure which are also involved in the switching process. Unlike bipolar devices,
however, these switching times can be controlled completely by the gate drive circuit
design.
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C
GD
C
GD1
C
GD2
idealized
Actual
V
GS
V
GS
(th) = V
DS
V
DS
(b)
G
D
S
C
GD
C
GS
(cut off)
G
D
S
C
GD
C
GS
i
D
= f(v
GS
)
(Active)
G
D
S
C
GD
C
GS
r
DS
(ON)
(Ohmic)
(c)
Fig. 6.7: Circuit model of a MOSFET
(a) MOSFET capacitances
(b) Variation of C
GD
with V
DS
(c) Circuit models.
Drain body
depletion
layer
n
+
n

p
(a)
n
+
C
GD
D
G
S
Fig 6.7 (a) shows three important capacitances inherent in a MOSFET structure. The most
prominent capacitor in a MOSFET structure is formed by the gate oxide layer between the
gate metallization and the n
+
type source region. It has the largest value (a few nano farads)
and remains more or less constant for all values of v
GS
and v
DS
. The next largest capacitor
(a few hundred pico forwards) is formed by the drain body depletion region directly
below the gate metallization in the n

drain drift region. Being a depletion layer capacitance
its value is a strong function of the drain source voltage v
DS
. For low values of v
DS
(v
DS
<
(v
GS
v
GS
(th))) the value of C
GD
(C
GD2
) is considerably higher than its value for large v
DS
as shown in Fig 6.7 (b). Although variation of C
GD
between C
GD1
and C
GD2
is continuous a
step change in the value of C
GD
at v
DS
= v
GS
v
GS
(th) is assumed for simplicity. The lowest
value capacitance is formed between the drain and the source terminals due to the drain
body depletion layer away form the gate metallization and below the source metallization.
Although this capacitance is important for some design considerations (such as snubber
design, zero voltage switching etc) it does not appreciably affect the hard switching
performance of a MOSFET. Consequently, it will be neglected in our discussion. From the
Gate oxide
C
DS
C
GS
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above discussion and the steady state characteristics of a MOSFET the circuit models of a
MOSFET in three modes of operation can be drawn as shown in Fig 6.7 (c).
6.5.2 Switching waveforms
The switching behavior of a MOSFET will be described in relation to the clamped
inductive circuit shown in Fig 6.8. For simplicity the load current is assumed to remain
constant over the small switching interval. Also the diode D
F
is assumed to be ideal with
no reverse recovery current. The gate is assumed to be driven by an ideal voltage source
giving a step voltage between zero and V
gg
in series with an external gate resistance R
g
.
V
D
D
F
i
f
I
O
V
gg
R
g
C
GD
C
GS
i
g
i
D
V
DS
+

Fig. 6.8: Clamped inductive switching circuit using a MOSFET.
+

To turn the MOSFET on, the gate drive voltage changes from zero to V
gg
. The gate
source voltage which was initially zero starts rising towards V
gg
with a time constant
1
=
R
g
(C
GS
+ C
GD1
) as shown in Fig 6.9.
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V
gg
t
t
t
t
i
g
i
D
, i
f
2
= R
g
(C
GS
+C
GD2
)
i
D
2
t
ON
I
0
r
os
(ON)
V
GS
V
GS
I
0
V
GS
(th)
i
g
I
0
V
DS
gg
g
V
R
1
= R
g
(C
GS
+C
GD1
)
1
gg
g
V
R
i
g
I
0
I
0
I
0
i
f
i
f
i
D
t
off
t
d
(off)
t
rvi
t
rv2 t
fi t
dON
t
ri t
fv1 t
fv2
Fig. 6.9: Switching waveforms of a clamped inductive switching circuit using MOSFET
Note that during this period the drain voltage v
DS
is clamped to the supply voltage V
D
through the free wheeling diode D
F
. Therefore, C
GS
and C
GD
can be assumed to be
connected in parallel effectively. A part of the total gate current ig charges C
GS
while the
other part discharges C
GD
.
Till v
GS
reaches v
GS
(th) no drain current flows. This time period is called turn on delay
time (t
d
(ON)). Note that t
d
(ON) can be controlled by controlling R
g
. Byond t
d
(ON) i
D
increases linearly with v
GS
and in a further time t
ri
(current rise time) reaches I
o
. The
corresponding value of v
GS
and i
g
are marked as V
GS
I
o
and i
g
I
o
respectively in Fig 6.9.
At this point the complete load current has been transferred to the MOSFET from the free
wheeling diode D
F
. i
D
does not increase byond this point. Since in the active region i
D
and
v
GS
are linearly related, v
GS
also becomes clamped at the value v
GS
I
o
. The gate current i
g
now discharges C
GD
and the drain voltage starts falling.
( ) ( )
g
GG GS o
DS GS GD GD
GD GD g
i
V  V I d d d
v = v + v = v = = 6.4
dt dt dt C C R
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The fall of v
DS
occurs in two distinct intervals. When the MOSFET is in the active region
(v
DS
> (v
GS
v
GS
(th)) C
GD
= C
GD1
.Since C
GD1
<< C
GD2
, v
DS
falls rapidly. This fast fall
time of v
DS
is marked t
fv1
in Fig 6.9. However, once in the ohmic region, C
GD
= C
GD2
>>
C
GD1
. Therefore, rate of fall of v
DS
slows down considerably (t
fv2
). Once v
DS
reaches its
on state value (r
DS
(ON) I
o
) v
GS
becomes unclamped and increases towards V
gg
with a
time constant
2
= R
g
(C
GS
+ C
GD2
). Note that all switching periods can be reduced by
increasing Vgg or / and decreasing Rg. The total turn on time is t
ON
= t
d
(ON) + t
ri
+ t
fv1
+
t
fv2
.
To turn the MOSFET OFF, V
gg
is reduced to zero triggering the exact reverse process of
turn on to take place. The corresponding waveforms and switching intervals are show in
Fig 6.9. The total turn off time t
off
= t
d
(off) + t
rv1
+ t
rv2
+ t
fi
.
6.5.3 MOSFET Gate Drive
MOSFET, being a voltage controlled device, does not require a continuous gate current
to keep it in the ON state. However, it is required to charge and discharge the gatesource and the
gatedrain capacitors in each switching operation. The switching times of a MOSFET essentially
depends on the charging and discharging rate of these capacitors. Therefore, if fast charging and
discharging of a MOSFET is desired at fast switching frequency the gate drive power
requirement may become significant. Fig 6.10 (a) shows a typical gate drive circuit of a
MOSFET.
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Logic level
gate pulse
V
GG V
D
R
G
R
1
Q
1
Q
2
Q
3
(a)
V
GG
1
G
1
R
R +
( +1)
V
GG
G
R
(b)
V
D
D
F
I
L
G
S
D
B
R
B
(c)
D
R
G G
R
R
S
(d)
Fig. 6.10: MOSFET gate drive circuit.
(a) Gate drive circuit; (b) Equivalent circuit during turn on and off;
(b) Effect of parasitic BJT; (d) Parallel connection of MOSFETs.
To turn the MOSFET on the logic level input to the inverting buffer is set to high state so
that transistor Q
3
turns off and Q
1
turns on. The top circuit of Fig 6.10 (b) shows the
equivalent circuit during turn on. Note that, during turn on Q
1
remains in the active
region. The effective gate resistance is R
G
+ R
1
/ (
1
+ 1). Where,
1
is the dc current gain
of Q
1
.
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To turn off the MOSFET the logic level input is set to low state. Q
3
and Q
2
turns on
whole Q
1
turns off. The corresponding equivalent circuit is given by the bottom circuit of
Fig 6.10 (b)
The switching time of the MOSFET can be adjusted by choosing a proper value of R
G
.
Reducing R
G
will incase the switching speed of the MOSFET. However, caution should
be exercised while increasing the switching speed of the MOSFET in order not to turn on
the parasitic BJT in the MOSFET structure inadvertently. The drainsource capacitance
(C
DS
) is actually connected to the base of the parasitic BJT at the p type body region. The
body source short has some nonzero resistance. A very fast rising drainsource voltage
will send sufficient displacement current through C
DS
and R
B
as shown in Fig 6.10 (c).
The voltage drop across R
B
may become sufficient to turn on the parasitic BJT. This
problem is largely avoided in a modern MOSFET design by increasing the effectiveness
of the bodysource short. The devices are now capable of dv
DS
/dt in excess to 10,000
V/s. Of course, this problem can also be avoided by slowing down the MOSFET
switching speed.
Since MOSFET on state resistance has positive temperature coefficient they can be
paralleled without taking any special precaution for equal current sharing. To parallel two
MOSFETs the drain and source terminals are connected together as shown in Fig 6.10
(d). However, small resistances (R) are connected to individual gates before joining them
together. This is because the gate inputs are highly capacitive with almost no losses.
Some stray inductance of wiring may however be present. This stray inductance and the
MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate
voltage that can result in puncture of the gate qxide layer due to voltage increase during
oscillations. This is avoided by the damping resistance R.
Exercise 6.3
1. Fill in the blank(s) with the appropriate word(s)
i. The GateSource capacitance of a MOSFET is the ________________ among all three
capacitances.
ii. The GateDrain transfer capacitance of a MOSFET has large value in the
________________ region and small value in the ________________ region.
iii. During the turn on delay time the MOSFET gate source voltage rises from zero to the
________________ voltage.
iv. The voltage fall time of a MOSFET is ________________ proportional to the gate
charging resistance.
v. Unlike BJT the switching delay times in a MOSFET can be controlled by proper design
of the ________________ circuit.
Answer: (i) largest; (ii) ohmic, active; (iii) threshold; (iv) inversely; (v) gate drive.
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2. A Power MOSFET has the following data
C
GS
= 800 pF ; C
GD
= 150 pF; g
f
= 4; v
GS
(th) = 3V;
It is used to switch a clamped inductive load (Fig 6.8) of 20 Amps with a supply voltage V
D
=
200V. The gate drive voltage is v
gg
= 15V, and gate resistance R
g
= 50. Find out maximum
value of
d di
dt
and
DS
dv
dt
during turn ON.
Answer: During turn on
( )
D f gs gs
i g v  v (th)
gs
D
f
dv
di
= g
dt dt
But ( )
gs gg gs
GS GD
g
dv V  v
C +C =
dt R
( )
( )
gs
D f
f g
g GS GD
dv
di g
= g = V  v
dt dt R C +C
g gs
( )
( )
( )
( )
f gg gs
D f
gg gs Min
Max g GS GD g GS GD
g V  v (th)
di g
= V  v =
dt R C +C R C +C
D
gs gs D
di
since for v < v (th) i = = 0
dt
( )
9 D
12
Max
di 4
= 15 3 =1.0110 A sec
dt 5095010
From equation (6.4)
gg GS o
DS
GD g
V  V , I
dv
=
dt C R
For I
o
= 20 A, v
gs
(th) = 3V, and g
f
= 4
o
GS o gs
f
I 20
V , I = + v (th) = +3 = 8 volts
g 4
6 DS
12
dv 158
= = 93310 V sec.
dt 15010 50
6.6 MOSFET Ratings
Steady state operating limits of a MOSFET are usually specified compactly as a safe
operating area (SOA) diagram. The following limits are specified.
V
DSS
: This is the drainsource break down voltage. Exceeding this limit will destroy the
device due to avalanche break down of the bodydrain pn junction.
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I
DM
: This is the maximum current that should not be exceeded even under pulsed current
operating condition in order to avoid permanent damage to the bonding wires.
Continuous and Pulsed power dissipation limits: They indicate the maximum
allowable value of the V
DS
, i
D
product for the pulse durations shown against each limit.
Exceeding these limits will cause the junction temperature to rise beyond the acceptable
limit.
All safe operating area limits are specified at a given case temperature.
In addition, several important parameters regarding the dynamic performance of the
device are also specified. These are
Gate threshold voltage (V
GS
(th)): The MOSFET remains in the cut off region when v
GS
in below this voltage. V
GS
(th) decreases with junction temperature.
Drain Source on state resistance (r
DS
(ON)): This is the slope of the i
D
v
DS
characteristics in the ohmic region. Its value decreases with increasing v
GS
and increases
with junction temperature. r
DS
(ON) determines the ON state power loss in the device.
Forward Transconductance (g
fs
): It is the ratio of i
D
and (v
GS
v
GS
(th)). In a MOSFET
switching circuit it determines the clamping voltage level of the gate source voltage and
thus influences dv
DS
/dt during turn on and turn off.
GateSource breakdown voltage: Exceeding this limit will destroy the gate structure of
the MOSFET due to dielectric break down of the gate oxide layer. It should be noted that
this limit may by exceeded even by static charge deposition. Therefore, special
precaution should be taken while handing MOSFETs.
Input, output and reverse transfer capacitances (C
GS
, C
DS
& C
GD
): Value of these
capacitances are specified at a given drainsource and gatesource voltage. They are
useful for designing the gate drive circuit of a MOSFET.
In addition to the main MOSFET, specifications pertaining to the body diode are also
provided. Specifications given are
Reverse break down voltage: This is same as V
DSS
Continuous ON state current (I
S
): This is the RMS value of the continuous current that
can flow through the diode.
Pulsed ON state current (I
SM
): This is the maximum allowable RMS value of the ON
state current through the diode given as a function of the pulse duration.
Forward voltage drop (v
F
): Given as an instantaneous function of the diode forward
current.
Reverse recovery time (t
rr
) and Reverse recovery current (I
rr
): These are specified as
functions of the diode forward current just before reverse recovery and its decreasing
slope (di
F
/dt).
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Exercise 6.4
Fill in the blank(s) with the appropriate word(s)
i. The maximum voltage a MOSFET can with stand is ________________ of drain current.
ii. The FBSOA and RBSOA of a MOSFET are ________________.
iii. The gate source threshold voltage of a MOSFET ________________ with junction
temperature while the on state resistance ________________ with junction temperature.
iv. The gate oxide of a MOSFET can be damaged by ________________ electricity.
v. The reverse break down voltage of the body diode of a MOSFET is equal to
________________ while its RMS forward current rating is equal to ________________.
Answer: (i) independent; (ii) identical; (iii) decreases, increases; (iv) static; (v) V
DSS
; I
DM
.
Reference
[1] Evolution of MOSBipolar power semiconductor Technology, B. Jayant Baliga,
Proceedings of the IEEE, VOL.76, No4, April 1988.
[2] Power Electronics ,Converters Application and Design Third Edition, Mohan,
Undeland, Robbins. John Wiley & Sons Publishers 2003.
[3] GE Power MOSFET data sheet.
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Lesson Summary
MOSFET is a voltage controlled majority carrier device.
A Power MOSFET has a vertical structure of alternating p and n layers.
The main current carrying terminals of an n channel enhancement mode MOSFET are
called the Drain and the Source and are made up of n
+
type semiconductor.
The control terminal is called the Gate and is isolated form the bulk semiconductor by a
thin layer of SiO
2
.
p type semiconductor body separates n
+
type source and drain regions.
A conducting n type channel is produced in the p type body region when a positive voltage
greater than a threshold voltage is applied at the gate.
Current conduction in a MOSFET occurs by flow of electron from the source to the drain
through this channel.
When the gate source voltage is below threshold level a MOSFET remains in the Cut Off
region and does not conduct any current.
With v
GS
> v
GS
(th) and v
DS
< (v
GS
v
GS
(th)) the drain current in a MOSFET is
proportional to v
DS
. This is the Ohmic region of the MOSFET output characteristics.
For larger values of v
DS
the drain current is a function of v
GS
alone and does not depend on
v
Ds
. This is called the active region of the MOSFET.
In power electronic applications a MOSFET is operated in the Cut Off and Ohmic
regions only.
The on state resistance of a MOSFET (V
DS
(ON)) has a positive temperature coefficient.
Therefore, MOSFETs can be easily paralleled.
A MOSFET does not undergo second break down.
The safe operating area (SOA) of a MOSFET is similar to that of a BJT except that it does
not have a second break down limit.
Unlike BJT the maximum forward voltage withstanding capability of a MOSFET does not
depend on the drain current.
The safe operating area of a MOSFET does not change under Forward and Reverse bias
conditions.
The drain body junction in a MOSFET structure constitute an anti parallel diode
connected between the source and the drain. This is called the MOSFET body diode.
The body diode of a MOSFET has the same break down voltage and forward current rating
as the main MOSFET.
The switching delays in a MOSFET are due to finite charging and discharging time of the
input and output capacitors.
Switching times of a MOSFET can be controlled completely by external gate drive design.
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The input capacitor along with the gate drive resistance determine the current rise and fall
time of a MOSFET during switching.
The transfer capacitor (C
gd
) determines the drain voltage rise and fall times.
r
DS
(ON) of a MOSFET determines the conduction loss during ON period.
r
DS
(ON) reduces with higher v
gs
. Therefore, to minimize conduction power loss maximum
permissible v
gs
should be used subject to dielectric break down of the gate oxide layer.
The gate oxide layer can be damaged by static charge. Therefore MOSFETs should be
handled only after discharging one self through proper grounding.
For similar voltage rating, a MOSFET has a relatively higher conduction loss and lower
switching loss compared to a BJT. Therefore, MOSFETs are more popular for high
frequency (>50 kHz) low voltage (<100 V) circuits.
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Practice Problems and Answers
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Practice Problems
1. How do you expect the gate source capacitance of a MOSFET to varry with gate source
voltage. Explain your answer.
2. The gate oxide layer of a MOSFET is 1000 Angstrom thick Assuming a break down field
strength of 5 10
6
V/cm and a safely factor of 50%, find out the maximum allowable
gate source voltage.
3. Explain why in a high voltage MOSFET switching circuit the voltage rise and fall time is
always greater than current fall and rise times.
4. A MOSFET has the following parameters
V
GS
(th) = 3V, g
fs
= 3, C
GS
= 800 PF, C
GD
= 250 PF. The MOSFET is used to switch an
inductive load of 15 Amps from 150V supply. The switching frequency is 50 kHz. The
gate drive circuit has a driving voltage of 15V and output resistance of 50. Find out the
switching loss in the MOSFET.
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Answer to practice problems
1. When the gate voltage is zero the thickness of the gatesource capacitance is
approximately equal to the thickness of the gate oxide layer. As the gate source voltage
increases the width of the depletion layer in the p body region also increases. Since the
depletion layer is a region of immobile charges it in effect increases the thickness of the
gatesource capacitance and hence the value of this capacitances decreases with
increasing v
GS
. However, as v
GS
is increased further free electrons generated by thermal
ionization get attracted towards the gate oxidesemiconductor interface. These free
electrons screen the depletion layer partially and the gatesource capacitance starts
increasing again. When v
GS
is above v
gs
(th) the inversion layer completely screens the
depletion layer and the effective thickness of the gatesource capacitance becomes once
again equal to the thickness of the oxide layer. There after the value of C
GS
remains more
or less constant.
2. From the given data the break down gate source voltage
GS BD BD gs
v = E t
where E
BD
= Break down field strength
t
gs
= thickness of the oxide layer.
So
6 8
GS BD
v = 510 100010 = 50V
Let
gs Max
v be the maximum allowable gate source voltage assuming 50% factor of
safety.
gs Max GS BD
gs Max
1.5 v = v = 50 V
50
v = V 33 Volts.
1.5
3. We Know that for MOSFET
( )
( )
D fs GS GS
gg GS
D
fs GS fs
g GS
i = g V  V (th)
V  v
di d
= g v = g
dt dt R C
During current rise V
gg
>> v
GS
fs D
gg
g GS
o
ri fi g GS o
fs gg
g di
V
dt R C
I
t = t R C where I = load current.
g V
Now From equation (6.4)
gg g s o gg
DS
g GD g GD
V  V , I V
d
v =
dt R C R C
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Since V
gg
>> V
gs
, I
o
D
rr fv g GD D
gg
V
t = t R C where V = Load voltage.
V
o G S ri fi
rr fr D fs G D
I C t t
= =
t t V g C
That is current rise and fall times are much shorter than voltage rise and fall times.
4. Referring to Fig 6.9 energy loss during switching occurs during intervals t
ri
, t
fv1
, t
fv2
, t
rv2
,t
rv1
,
and t
fi
. For simplicity it will be assumed that t
fv2
= t
rv2
= 0. Also the rise and fall of i
D
and v
DS
will be assumed to be linear.
During t
ri
D fs gs gs
i = g (v  v (th))
gg gs
D
fs gs fs
GS GD g
V  v
di d
= g v = g
dt dt (C +C )R
fs gg
D
gg gs
GS GD g
g V
di
sinceV >> v during current rise
dt (C +C )R
o
ri GS GD g
fs gg
I
t = (C +C )R
g V
Energy loss during t
ri
is
2
D o
ON1 ri D GS GD g
fs gg
V I 1
E = t V Io = (C +C )R
2 2g V
During t
fv
gg gs, o
DS
GD g
V  V I
dV
=
dt C R
o
gs o gs
fs
I
But V , I = + v (th)
g
o
gg gs
DS fs
g GD
I
V  v (th) 
dV g
=
dt R C
D
fv g GD
o
gg gs
fs
V
t = R C
I
V  V (th) 
g
Energy loss during t
fv
is
ON2 fv o D
1
E = t I V
2
2
D o
g GD
o
gg gs
fs
V I
= R
I
2 V  v (th) 
g
C
Energy loss during Turn on is
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( )
( )
D o g o GS GD D GD
ON ON1 ON2
fs gg gg gs
V I R I C +C V C
E = E +E = +
2 g V V  V (th)
From the symmetry of the Turn ON and the Turn OFF operation of MOSFET (i.e. t
ri
= t
fi
, t
fv
=
t
rv
)
ON OFF
E = E
Total switching energy lass is E
sw
= E
ON
+ E
OFF
= 2 E
ON
gg
o fs GS
sw D o g GD
gs
o fs gg GD
gg gg
VD V
I g C
E = V I R C 1+ +
V (th)
I g V C

V V
gg
GS o fs
sw sw D o g GD sw
gs
o fs GD gg
gg gg
VD V
C I g
P E = V I R C f 1+ +
v (th)
I g C V
1 
V v
Substituting the values given
P
sw
= 32 mw,
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Module
1
Power Semiconductor
Devices
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Lesson
7
Insulated Gate Bipolar
Transistor (IGBT)
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Constructional features, operating principle and characteristics of Insulated Gate Bipolar
Transistors (IGBT)
Instructional objects
On completion the student will be able to
Differentiate between the constructional features of an IGBT and a MOSFET.
Draw the operational equivalent circuit of an IGBT and explain its operating principle in
terms of the schematic construction and the operational equivalent circuit.
Draw and explain the steady state output and transfer characteristics of an IGBT.
Draw the switching characteristics of an IGBT and identify its differences with that of a
MOSFET.
Design a basic gate drive circuit for an IGBT.
Interpret the manufacturers date sheet of an IGBT.
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7.1 Introduction
The introduction of Power MOSFET was originally regarded as a major threat to the power
bipolar transistor. However, initial claims of infinite current gain for the power MOSFETs were
diluted by the need to design the gate drive circuit capable of supplying the charging and
discharging current of the device input capacitance. This is especially true in high frequency
circuits where the power MOSFET is particularly valuable due to its inherently high switching
speed. On the other hand, MOSFETs have a higher on state resistance per unit area and
consequently higher on state loss. This is particularly true for higher voltage devices (greater
than about 500 volts) which restricted the use of MOSFETs to low voltage high frequency
circuits (eg. SMPS).
With the discovery that power MOSFETs were not in a strong position to displace the BJT,
many researches began to look at the possibility of combining these technologies to achieve a
hybrid device which has a high input impedance and a low on state resistance. The obvious first
step was to drive an output npn BJT with an input MOSFET connected in the Darlington
configuration. However, this approach required the use of a high voltage power MOSFET with
considerable current carrying capacity (due to low current gain of the output transistor). Also,
since no path for negative base current exists for the output transistor, its turn off time also tends
to get somewhat larger. An alternative hybrid approach was investigated at GE Research center
where a MOS gate structures was used to trigger the latch up of a four layer thyristor. However,
this device was also not a true replacement of a BJT since gate control was lost once the thyristor
latched up.
After several such attempts it was concluded that for better results MOSFET and BJT
technologies are to be integrated at the cell level. This was achieved by the GE Research
Laboratory by the introduction of the device IGT and by the RCA research laboratory with the
device COMFET. The IGT device has undergone many improvement cycles to result in the
modern Insulated Gate Bipolar Transistor (IGBT). These devices have near ideal characteristics
for high voltage (> 100V) medium frequency (< 20 kHZ) applications. This device along with
the MOSFET (at low voltage high frequency applications) have the potential to replace the BJT
completely.
7.2 Constructional Features of an IGBT
Vertical cross section of a n channel IGBT cell is shown in Fig 7.1. Although p channel IGBTs
are possible n channel devices are more common and will be the one discussed in this lesson.
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Emitter
p
+
n
+
J
3
n
+
n

Collector
SiO
2
(Gate oxide)
Gate
Fig. 7.1: Vertical cross section of an IGBT cell.
Body region
n

p
J
2
J
1
Injecting layer
Buffer layer
Drain drift
region
SiO
2
(Gate oxide)
The major difference with the corresponding MOSFET cell structure lies in the addition of a p+
injecting layer. This layer forms a pn junction with the drain layer and injects minority carriers
into it. The n type drain layer itself may have two different doping levels. The lightly doped n
region is called the drain drift region. Doping level and width of this layer sets the forward
blocking voltage (determined by the reverse break down voltage of J
2
) of the device. However, it
does not affect the on state voltage drop of the device due to conductivity modulation as
discussed in connection with the power diode. This construction of the device is called Punch
Trough (PT) design. The NonPunch Through (NPT) construction does not have this added n+
buffer layer. The PT construction does offer lower on state voltage drop compared to the NPT
construction particularly for lower voltage rated devices. However, it does so at the cost of lower
reverse break down voltage for the device, since the reverse break down voltage of the junction
J
1
is small. The rest of the construction of the device is very similar to that of a vertical
MOSFET (Link to 6.2) including the insulated gate structure and the shorted body (p type)
emitter (n+ type) structure. The doping level and physical geometry of the p type body region
however, is considerably different from that of a MOSFET in order to defeat the latch up action
of a parasitic thyristor embedded in the IGBT structure. A large number of basic cells as shown
in Fig 7.1 are grown on a single silicon wafer and connected in parallel to form a complete IGBT
device.
The IGBT cell has a parasitic pnpn thyristor structure embedded into it as shown in Fig 7.2(a).
The constituent pnp transistor, npn transistor and the driver MOSFET are shown by dotted
lines in this figure. Important resistances in the current flow path are also indicated.
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npn
n
+
n
+
n

Collector
Body spreading resistance
Gate
p
+
Emitter
MOSFET
Drift
resistance pnp
p
J
3
J
2
J
1
(a)
Fig 7.2(b) shows the exact static equivalent circuit of the IGBT cell structure. The top pnp
transistor is formed by the p+ injecting layer as the emitter, the n type drain layer as the base and
the p type body layer as the collector. The lower npn transistor has the n+ type source, the p
type body and the n type drain as the emitter, base and collector respectively. The base of the
lower npn transistor is shorted to the emitter by the emitter metallization. However, due to
imperfect shorting, the exact equivalent circuit of the IGBT includes the body spreading
resistance between the base and the emitter of the lower npn transistor. If the output current is
large enough, the voltage drop across this resistance may forward bias the lower npn transistor
and initiate the latch up process of the pnpn thyristor structure. Once this structure latches up
the gate control of IGBT is lost and the device is destroyed due to excessive power loss.
A major effort in the development of IGBT has been towards prevention of latch up of the
parasitic thyristor. This has been achieved by modifying the doping level and physical geometry
of the body region. The modern IGBT is latchup proof for all practical purpose. Fig 7.3(a) and
(b) shows the circuit symbol and photograph of an IGBT.
Gate
(c)
Drift
region
resistance
Collector
Emitter
Gate
(b)
Drift
region
resistance
Collector
Emitter
Body
spreading
resistance
Fig. 7.2: Parasitic thyristor in an IGBT cell.
(a) Schematic structure
(b) Exact equivalent circuit.
(c) Approximate equivalent circuit
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G
C
E
(a)
(b)
Fig. 7.3: Circuit symbol of an IGBT.
(a) Circuit symbol.
(b) Photograph.
Exercise 7.1
Fill in the blank(s) with the appropriate word(s).
i. An IGBT is a __________________ device combining the advantages of a
__________________ and a __________________.
ii. IGBT is suitable for __________________ voltage __________________ frequency
applications.
iii. In an IGBT cell structure a __________________ type injecting layer is added on top of
the drain of an n channel MOSFET.
iv. The forward blocking voltage of an IGBT is determined by the __________________
and __________________ of the drain drift layer.
v. A punch through IGBT has __________________ reverse break down voltage while
the Non punch through IGBT has __________________ voltage blocking capacity.
vi. The IGBT cell has a parasitic __________________ structure embedded into it.
vii. The parasitic __________________ structure of an IGBT cell can __________________
at large collector current due to imperfect body emitter shorting.
viii. The doping level and physical geometry of the IGBT __________________ region is
designed to be considerably different from that of a MOSFET to prevent its
__________________.
Answers:
i) hybrid, MOSFET, BJT ; ii) high, medium ; iii) p+ ; iv) thickness, doping level ; v) low,
symmetrical ; vi) thyristor; vii) thryistor, latch up ; viii) body, latch up.
7.3 Operating principle of an IGBT
Operating principle of an IGBT can be explained in terms of the schematic cell structure and
equivalent circuit of Fig 7.2(a) and (c). From the input side the IGBT behaves essentially as a
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MOSFET. Therefore, when the gate emitter voltage is less then the threshold voltage no
inversion layer is formed in the p type body region and the device is in the off state. The forward
voltage applied between the collector and the emitter drops almost entirely across the junction J
2
.
Very small leakage current flows through the device under this condition. In terms of the
equivalent current of Fig 7.2(c), when the gate emitter voltage is lower than the threshold voltage
the driving MOSFET of the Darlington configuration remains off and hence the output pnp
transistor also remains off.
When the gate emitter voltage exceeds the threshold, an inversion layer forms in the p type body
region under the gate. This inversion layer (channel) shorts the emitter and the drain drift layer
and an electron current flows from the emitter through this channel to the drain drift region. This
in turn causes substantial hole injection from the p+ type collector to the drain drift region. A
portion of these holes recombine with the electrons arriving at the drain drift region through the
channel. The rest of the holes cross the drift region to reach the p type body where they are
collected by the source metallization.
From the above discussion it is clear that the n type drain drift region acts as the base of the
output pnp transistor. The doping level and the thickness of this layer determines the current
gain of the pnp transistor. This is intentionally kept low so that most of the device current
flows through the MOSFET and not the output pnp transistor collector. This helps to reduced
the voltage drop across the body spreading resistance shown in Fig 7.2 (b) and eliminate the
possibility of static latch up of the IGBT.
The total on state voltage drop across a conducting IGBT has three components. The
voltage drop across J
1
follows the usual exponential law of a pn junction. The next component of
the voltage drop is due to the drain drift region resistance. This component in an IGBT is
considerably lower compared to a MOSFET due to strong conductivity modulation by the
injected minority carriers from the collector. This is the main reason for reduced voltage drop
across an IGBT compared to an equivalent MOSFET. The last component of the voltage drop
across an IGBT is due to the channel resistance and its magnitude is equal to that of a
comparable MOSFET.
7.4 Steady state characteristics of an IGBT
The iv characteristics of an n channel IGBT is shown in Fig 7.4 (a). They appear
qualitatively similar to those of a logic level BJT except that the controlling parameter is not a
base current but the gateemitter voltage.
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Cut off
V
gE1
V
gE2
V
gE3
V
gE4
V
gE5
V
gE6
Increasing
V
gE
Active
Saturation
i
C
V
CC
V
CES
V
CE
(a)
G
C
E
V
gE
V
cE
V
CC
R
L
i
c
+

V
RM
Load line
Fault
Load line
A
B
C
F
V
gE V
gE
(th)
g
fs
i
C
(b)
Fig. 7.4: Static characteristics of an IGBT
(a) Output characteristics; (b) Transfer characteristics
CC
L
V
R
When the gate emitter voltage is below the threshold voltage only a very small leakage
current flows though the device while the collector emitter voltage almost equals the supply
voltage (point C in Fig 7.4(a)). The device, under this condition is said to be operating in the cut
off region. The maximum forward voltage the device can withstand in this mode (marked V
CES
in Fig 7.4 (a)) is determined by the avalanche break down voltage of the body drain pn
junction. Unlike a BJT, however, this break down voltage is independent of the collector current
as shown in Fig 7.4(a). IGBTs of Nonpunch through design can block a maximum reverse
voltage (V
RM
) equal to V
CES
in the cut off mode. However, for Punch Through IGBTs V
RM
is
negligible (only a few tens of volts) due the presence of the heavily doped n+ drain buffer layer.
As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the
active region of operation. In this mode, the collector current i
c
is determined by the transfer
characteristics of the device as shown in Fig 7.4(b). This characteristic is qualitatively similar to
that of a power MOSFET and is reasonably linear over most of the collector current range. The
ratio of i
c
to (V
gE
v
gE(th)
) is called the forward transconductance (g
fs
) of the device and is an
important parameter in the gate drive circuit design. The collector emitter voltage, on the other
hand, is determined by the external load line ABC as shown in Fig 7.4(a).
As the gate emitter voltage is increased further i
c
also increases and for a given load resistance
(R
L
) v
CE
decreases. At one point v
CE
becomes less than vgE v
gE
(th). Under this condition the
driving MOSFET part of the IGBT (Fig 7.2(c)) enters into the ohmic region and drives the
output pnp transistor to saturation. Under this condition the device is said to be in the
saturation mode. In the saturation mode the voltage drop across the IGBT remains almost
constant reducing only slightly with increasing v
gE
.
In power electronic applications an IGBT is operated either in the cut off or in the saturation
region of the output characteristics. Since v
CE
decreases with increasing v
gE,
it is desirable to use
the maximum permissible value of v
gE
in the ON state of the device. v
gE
(Max) is limited by the
maximum collector current that should be permitted to flow in the IGBT as dictated by the
latchup condition discussed earlier. Limiting V
gE
also helps to limit the fault current through
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the device. If a short circuit fault occurs in the load resistance R
L
(shown in the inset of Fig
7.4(a)) the fault load line is given by CF. Limiting v
gE
to v
gE6
restricts the fault current
corresponding to the operating point F. Most IGBTs are designed to with stand this fault current
for a few microseconds within which the device must be turned off to prevent destruction of the
device.
It is interesting to note that an IGBT does not exibit a BJTlike second break down failure. Since,
in an IGBT most of the collector current flows through the drive MOSFET with positive
temperature coefficient the effective temperature coefficient of v
CE
in an IGBT is slightly
positive. This helps to prevent second break down failure of the device and also facilitates
paralleling of IGBTs.
Exercise 7.2
Fill in the blank(s) with the appropriate word(s).
i. From the input side the IGBT behaves essentially as a __________________.
ii. When the gate emitter voltage is below __________________ no __________________
layer is formed in the p type body region.
iii. Electrons arriving through the drive MOSFET causes __________________ injection
from the __________________ to the drain drift region.
iv. In an IGBT most of the collector current flows through the __________________ and not
through the __________________.
v. When the gateemitter voltage of an IGBT is below threshold if operates in the
__________________ region.
vi. In the active region of operation the collector current of an IGBT is determined by the
__________________ characteristics which is reasonably __________________ over
most of the collector current range.
vii. For the same load resistance as the v
gE
of an IGBT is increased it enters
__________________ region.
viii. The forward voltage drop of an IGBT in the saturation region remains approximately
__________________.
ix. An IGBT has small __________________ temperature coefficient of on state voltage
drop.
x. An IGBT does not exhibit __________________ failure mode.
Answers:
i) MOSFET; ii) threshold, inversion; iii) hole, collector; iv) MOSFET, BJT; v) cutoff; vi)
transfer, linear; vii)saturation; viii) constant; ix) positive; x) second break down.
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7.5 Switching characteristics of IGBT
Switching characteristics of the IGBT will be analyzed with respect to the clamped inductive
switching circuit shown in Fig 7.5(a). The equivalent circuit of the IGBT shown in Fig 7.5 (b)
will be used to explain the switching waveforms.
V
gg
R
g i
g
i
C
V
CC
i
L i
D
D
F
G
C
E
Q
1
V
CE

+
C
E
D
S
G
C
GD
C
gE
(b)
(a)
Fig. 7.5: Inductive switching circuit using an IGBT
itching circuit; (b) Equivalent circuit of the IGBT (a) Sw
The switching waveforms of an IGBT is, in many respects, similar to that of a Power MOSFET.
This is expected, since the input stage of an IGBT is a MOSFET as shown in Fig 7.5(b). Also in
a modern IGBT a major portion of the total device current flows through the MOSFET.
Therefore, the switching voltage and current waveforms exhibit a strong similarity with those of
a MOSFET. However, the output pnp transistor does have a significant effect on the switching
characteristics of the device, particularly during turn off. Another important difference is in the
gate drive requirement. To avoid dynamic latch up, (to be discussed later) the gate emitter
voltage of an IGBT is maintained at a negative value when the device is off.
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V
gg
t
t
t
i
D
2
= R
g
(C
GS
+C
GD2
)
The switching waveforms of an IGBT is shown in Fig 7.6. Similarity of these waveforms with
those of a MOSFET is obvious. To turn on the IGBT the gate drive voltage changes from V
gg
to
+V
gg
. The gate emitter voltage v
gE
follows V
gg
with a time constant
1
. Since the drain source
voltage of the drive MOSFET is large the gate drain capacitor assumes the lower value C
GD1
.
The collector current i
c
does not start increasing till v
gE
reaches the threshold voltage v
gE
(th).
Thereafter, i
c
increases following the transfer characteristics of the device till v
gE
reaches a value
v
gE
I
L
corresponding to i
c
= i
L
. This period is called the current rise time t
ri
. The free wheeling
diode current falls from I
L
to zero during this period. After i
c
reaches I
L,
v
gE
becomes clamped at
v
gE
I
L
similar to a MOSFET. v
CE
also starts falling during this period. First v
CE
falls rapidly (t
fv1
)
and afterwards the fall of v
CE
slows down considerably. Two factors contribute to the slowing
down of voltage fall. First the gatedrain capacitance C
gd
will increase in the MOSFET portion of
the IGBT at low drainsource voltages. Second, the pnp transistor portion of the IGBT traverses
the active region to its on state more slowly than the MOSFET portion of the IGBT. Once the
pnp transistor is fully on after t
fv2,
the on state voltage of the device settles down to v
CE
(sat). The
turn ON process ends here.
The turn off process of an IGBT follows the inverse sequence of turn ON with one major
difference. Once v
gE
goes below v
gE
(th) the drive MOSFET of the IGBT equivalent circuit turns
off. During this period (t
fi1
) the device current falls rapidly. However, when the drive MOSFET
turns off, some amount of current continues of flow through the output pnp transistor due to
stored charge in its base. Since there is no reverse voltage applied to the IGBT terminals that
could generate a negative drain current, there is no possibility for removing the stored charge by
carrier sweepout. The only way these excess carriers can be removed is by recombination within
the IGBT. During this recombination period (t
fi2
) the remaining current in the IGBT decays
relatively slowly forming a current fail. A long t
fi2
is undesirable, because the power dissipation
V
gE
V
gE,
I
L
V
gE
(th)
1
= R
g
(C
GS
+C
GD1
)
I
L
I
L
t
rv1
t
rv2
t
fi1
t
dON
t
ri
t
fv1
t
fv2
Fig. 7.6: Switching waveforms of an IGBT.
V
gE
(th)
V
gE,
I
L
V
CE
V
CC
V
CC
V
CE
(sat)
i
C
I
L
I
L
t
fi2
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in this interval will be large due to full collectoremitter voltage. t
fi2
can be reduced by
decreasing the excess carrier life time in the pnp transistor base. However, in the process, on
state losses will increase. Therefore, judicious design trade offs are made in a practical IGBT to
give minimum total loss.
The gate drive circuit of an IGBT should ensure fast and reliable switching of the device. In
particular, it should.
Apply maximum permissible V
gE
during ON period.
Apply a negative voltage during off period.
Control
d c
d
i
t
during turn ON and turn off to avoid excessive Electro magnetic
interference (EMI).
Control
ce
d
d
v
t
during switching to avoid IGBT latch up.
Minimize switching loss.
Provide protection against short circuit fault.
Detailed discussion on IGBT gate drive circuit is beyond the scope of this lesson. References [4]
& [5] provide good discussion on this subject. Fig 7.7(a) shows a simplified IGBT gate drive
circuit.
R
i
V
i
(Logic level)
Opto isolator
Level
Shifting
Comparator
V
gg
+V
gg
R
B
+V
cc
V
cc
R
G
IGBT
Q
1
Q
2
E
Totem pole
gate drive
amplifier
(a)
+

R
C
V
gg
R
G
E
To IGBT
Gate
Turn on equivalent circuit
V
gg
R
B
2
R
+1
G
E
To IGBT
Gate
Turn off equivalent circuit
(b)
Fig. 7.7: IGBT gate drive circuit
(a) Gate drive
(b) Equivalent circuit of the gate drive during turn on and turn off.
B
1
R
+1
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The logic level gate drive signal is first optoisolated and fed to a level shifting comparator. This
stage converts the unipolar (usually positive) out put voltage of the optoisolator to a bipolar
(V
gg
) signal compatible to the IGBT gate drive levels. The output of the comparator feeds a
totem pole output amplifier stage which drives the IGBT. The equivalent circuit of the gate drive
during turn on and off are shown in Fig 7.7(b). If
CC gg
V > V then both Q
1
and Q
2
will operate
in the active region and reasonably constant value of
1
&
2
of these two transistors can be used
for analysis purpose. These equivalent circuits along with the model of the IGBT input MOSFET
can be used to analyze the switching performance of the device. Conversely, for a desired
switching performance a suitable gate drive circuit can be designed.
7.6 IGBT ratings and safe operating area
Maximum collectoremitter voltage (V
CES
): This rating should not be exceeded even on
instantaneous basis in order to prevent avalanche break down of the drainbody pn junction.
This is specified at a given negative gate emitter voltage or a specified resistance connected
between the gate and the emitter.
Maximum continuous collector current (I
C
): This is the maximum current the IGBT can
handle on a continuous basis during ON condition. It is specified at a given case temperature
with derating curves provided for other case temperatures.
Maximum pulsed collector current (I
CM
): This is the maximum collector current that can flow
for a specified pulse duration. This current is limited by specifying a maximum gateemitter
voltage.
Maximum gateemitter voltage (V
gES
): This is the maximum allowable magnitude of the gate
emitter voltage (of both positive and negative polarity) in order to
Prevent break down of the gate oxide insulation.
Restrict collector current to I
CM
.
Collector leakage current (I
CES
): This is the leakage collector current during off state of the
device at a given junction temperature. This is usually specified at V
gE
= 0V and v
CE
= V
CES
.
Gateemitter leakage current (I
GES
): Usually specified at v
CE
= 0V & v
gE
= v
gES
.
Collector emitter saturation voltage (V
CE
(sat)): This is specified at a given junction
temperature, gateemitter voltage and collector current. For more detailed data the output
characteristics of the device for different v
gE
and expanded near the saturation zone is also
provided.
Gateemitter threshold voltage (v
gE
(th)): It is specified at a low collector emitter voltage and
collector current.
Forward Transconductance (g
fs
): This is again specified at a low value of v
CE
. For more
detailed data the transfer characteristics of the device (i
c
v
s
v
gE
) is also provided.
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Input, output and transfer capacitances (C
ies
, C
oes
& C
res
): These are, gateemitter, collector
emitter and gatedrain capacitances of the device respectively, specified at a given collector
emitter voltage. Variation of these parameters as functions of v
CE
are also supplied.
Switching times (t
d
(ON) t
ri
, t
fv
, t
rv
, t
fi
): These times are specified for inductive load switching as
functions of gate charging resistance and collector current. In addition turn on and turn off
energy losses per switching operation are also specified.
Maximum total power dissipation (P
tmax
): This is the maximum allowable power lass in the
device (both switching and conduction) on a continuous basis at a given case temperature.
Derating curve at other temperatures are also specified.
The IGBT has robust SOA both during turn on and turn off. Fig 7.8 (a) shows the FBSOA. On
the left side it is restricted by the forward voltage drop characteristics. Up to maximum
continuous collector current this voltage remains reasonably constant at a low value. However, at
I
CM
this voltage starts increasing as the IGBT starts entering active region. On the top the
FBSOA is restricted by I
CM
.
10
5
sec
10
4
sec
10
3
sec
10
2
sec
DC
V
CES V
CE
I
C
I
CM
i
C
(a)
V
CE
V
CES
I
CM
i
C
(b)
1000V/S
2000V/S
3000V/S
Fig. 7.8: Safe operating area of an IGBT
(a) FBSOA; (b) RBSOA.
The other two limits are formed by the maximum power dissipation limit and the maximum
forward voltage limit. Like other devices the maximum power dissipation limit increases with
reduction in the on pulse width.
The RBSOA for low values of
CE
dv
dt
is rectangular. However, for increased
CE
dv
dt
the upperright
hand corner is progressively cut out. The reason for this restriction on the RBSOA is to avoid
dynamic latch up. The device user can easily control
CE
dv
dt
by proper choice of V
gg
and the gate
drive resistance.
Exercise 7.3
Fill in the blank(s) with the appropriate word(s).
i. In a modern IGBT most of the collector current flows through the _________________
and not the _________________.
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ii. To avoid _________________ the gate emitter voltage of an IGBT is maintained at a
_________________ value when the device is off.
iii. During turn on of an IGBT the rate of fall of voltage slows down towords the end since
the output pnp transistor traverses its _________________ region more
_________________ compared to the drive MOSFET.
iv. During turn off of an IGBT a _________________ is formed due to excess stored charge
in the _________________ region of the output pnp transistor.
v. The gate drive circuit of an IGBT should control
dic
dt
to avoid excessive
_________________.
vi.
CE
dv
dt
of an IGBT during turn off should be controlled to prevent _________________ of
the device.
vii. A specified maximum gate emitter voltage of an IGBT helps to limit the collector current
during _________________ fault.
viii. Collector emitter saturation voltage of an IGBT _________________ with increasing
gateemitter voltage.
ix. The FBSOA of an IGBT is similar to that of a _________________ except that the on
state voltage drop is much _________________.
x. The upper right hand corner of the IGBT RBSOA is gradually cut out with increasing
_________________ to avoid _________________ of the device.
Answer: (i) MOSFET, BJT; (ii) latch up, negative; (iii) active, slowly; (iv) current tail, base; (v)
EMI; (vi) Latch up; (vii) short circuit; (viii) decreases; (ix) MOSFET, lower; (x)
CE
dv
dt
, latch up.
Reference
[1] B. Jayanta Baliga, Evolution of MOS Bipolar Power Semiconductor Technology,
Proceedings of the IEEE, vol. 76, No. 4, April 1988, pp 409418.
[2] Power electronics, Converters, Applications and Design, Mohan, Undeland, Robbins;
John Wiley & Sons, 2003
[3] B. Jayanta Baliga et. al, The Insulated Gate Transistor: A new ThreeTerminal MOS
Controlled Bipolar. Power Device, IEEE transaction on Electron Devices, vol. ED31,
No. 6 June 1984 pp 421828.
[4] Allen R. Hefner, An Investigation of the drive circuit requirements for the Power
Insulated Gate Bipolar Transistor, IEEE Transactions on Power Electronics. Vol. 6 No.
2. April 1991.
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[5] Carmelo Licitra et. al, A New Driving circuit for IGBT Devices, IEEE Transaction on
Power Electronics, Vol. 10, No3 may 1995.
[6] SEMIKRON Power Electronics News 2001, SEMIKRON International, Germany.
Lesson Summary
IGBT is a hybrid device which combines the advantages of MOSFET and BJT.
An IGBT is formed by adding a p+ collector layer on the drain drift layer of a Power
MOSFET.
Punch through IGBT has a thin n+ buffer layer between the p+ collector layer and n
drain drift layer. They have significantly lower conduction loss.
The IGBT cell structure embeds a parasitic thyristor in it. Latching up of this thyristor is
prevented by special structuring of the body region and increasing the effectiveness of the
body shorting.
From the operational point of view an IGBT is a voltage controlled bipolar device.
The operational equivalent circuit of an IGBT has an n channel MOSFET driving a pnp
BJT.
Like other semiconductor devices on IGBT can also operate in the cut off active and
saturation regions.
When the gateemitter voltage of an IGBT is below threshold it operates in the cut off
region.
For a given load resistance the operating point of an IGBT can be moved from cut off to
saturation through the active region by increasing the gateemitter voltage.
In the active region, the collector current of an IGBT is determined by the gateemitter
voltage which can be limited to a given maximum value to limit the fault current through
the device in the event of a load short circuit.
The IGBTs have a slightly positive temperature coefficient of the onstate voltage drop
which makes paralleling of these devices simpler.
An IGBT does not exhibit second break down phenomena as in the case of a BJT.
The switching characteristics of an IGBT is similar to that of a MOSFET.
To avoid dynamic latch up of the parasitic thryrstor in an IGBT, the gate emitter voltage
of the device is maintained at a negative value during its off period.
During turn off, the collector current of an IGBT can exhibit current tailing due to
stored base change in the base region of the output pnp transistor.
The forward bias SOA of an IGBT is similar to that of a MOSFET except the on state
voltage drop being much lower.
The maximum allowable collector current in an IGBT is restricted by the static latch up
consideration.
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The RBSOA of an IGBT is rectangular for low values of
CE
dv
dt
. For higher
CE
dv
dt
the upper
right half corner of the RBSOA is progressively cutout to prevent dynamic latch up of
the device.
The IGBT can switch at moderately high frequency (<20 kHZ) and in this range is likely
to replace the BJTs in all medium to high power applications.
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Practice Problems and Answers
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Q1. What effects do the width and doping level of the drain drift region of an IGBT have on
its performance.
Q2. (a) In an IGBT a major portion of the collector current flow through the driver MOSFET
section which has a voltage rating almost same as the device. Then how does the on state
voltage drop of an IGBT remain low compared to an equivalent MOSFET?
(b) An IGBT is used to switch a resistive load of 5 from a DC supply of 350 volts as
shown in the inset of Fig 7.4 (a). The ON state gate voltage is v
gE
= 15v. For the IGBT,
v
gE
(th) = 4 volts and g
ts
= 25. Find out the maximum current flowing through the IGBT
in the event of a short circuit fault across the load. Also find out the power dissipation
inside the device.
Q3. What do you under stand by dynamic latch up of an IGBT. How can it be prevented?
Q4. What steps are taken in the cell structure design of an IGBT to minimize the tail current
during turn off operation.
Q5. In the basic gate drive circuit of an IGBT shown in Fig 7.7 (a) following data are given
V
gg
= 15 V, V
cc
= 20 V,
1
for Q
1
= 50,
2
for Q
2
= 50.
R
B
= 2.2 K, R = 30, V
gE
(th) of IGBT = 4V, g
fs
= 40
CgE = 4nF, CgD = 500pF,
The IGBT is used to switch a clamed inductive load of 50 Amps from a 400 volts supply.
Find out maximum values of
dic
dt
and
CE
dv
dt
during Turn on and Turn off of the IGBT.
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Answers to Practice Problems
1. The width and doping level of the drain drift layer of an IGBT affects the performance of
the IGBT in several ways.
They determine the forward break down voltage of the IGBT.
Referring to Fig 7.2 (b), the drain drift region constitutes the base of the upper pnp
transistor. The width and the doping level of this layer determines the current gain of
this transistor. This is intentionally kept low so that most of the device current flows
through the MOSFET and not the output pnp transistor collector. This helps to reduce
the voltage drop across the body spreading resistance between the base and emitter of the
lower pnp transistor. Thus the possibility of turning on this transistor and consequent
latch up of the device is minimized.
Since the major part of the device current flows through the MOSFET which has a
positive temperature coefficient of drain source voltage drop, the collectoremitter
voltage drop across the device exhibits a slightly positive temperature coefficient. This
eliminates the possibility of second break down failure in IGBTs and simplifies
paralleling of these devices.
2. (a) The total voltage drop across a conducting IGBT has three components. The voltage
drop across the emitterbase junction of the output pnp transistor follows the usual
exponential low of a pn junction. The next component of the voltage drop is due to the
drain drift region resistance. In a normal high voltage MOSFET this component of the
voltage drop is large due to lower doping level (necessary for blocking high voltage) of
this region. However, in a conducting IGBT electrons arriving at the drain drift region
through the MOSFET channel causes large minority carrier injection from the p+
collector. The consequent conductivity modulation reduces the resistance (and hence the
voltage drop) in this region. The third component of the IGBT voltage drop occurs across
the channel of the driving MOSFET and is same as that of an equivalent high voltage
MOSFET. Therefore, the reduced voltage drop across a conducting IGBT is due to
reduction of the drain drift region resistance by conductivity modulation.
(b) In the event of a short circuit across the load the voltage across the device will be 350
volts and the IGBT will operate in the active region. In this region
( )
C fs gE gE
i = g v  v (th)
Substituting the given values
( )
C Max
i = 25 15 4 = 275 Amps
Power dissipation inside the device will be
D CE C Max
P = v i = 350 275 = 96.25 kW
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3. Static latch up in an IGBT occurs when the continuous ON state current exceeds a critical
value. However, under dynamic conditions, when the IGBT is switching from on to off
state if may latch up at drain current less than this value. During turn off, the voltage
across the driver MOSFET increases rapidly. This voltage is blocked by the drainbody
pn junction. To block the rapid build up of the voltage the width of the depletion region
in the drain drift layer also increases rapidly. This rapid increase in the depletion layer
width temporally increases the current gain of the output pnp transistor and causes
latch up of the device at a lower collector current than would have been necessary for
static latch up.
4. Punch Through and Nonpunch through IGBTs solve the problem of tail current by two
different approaches. Punch through IGBT s attempt to minimize the current tailing
problem by shortening the duration of the tailing time. This is done by reducing the
excess carrier life time in the n+ buffer layer compared to the n drain drift layer. This n+
buffer layer acts as a sink for excess holes and greatly enhances the removal rate of holes
from the drain drift layer. Thus the tail time is reduced.
Non punch through IGBTs attack the current tailing problem by minimizing the
magnitude of the current during the failing interval. This is done by designing the IGBT
so that the MOSFET section carries as much of the total current as possible. Newer NPT
IGBT designs have more than 90% of the total current carried by the MOSFET section of
the device.
5. During turn on and turn off the IGBT passes through the active region.
When v
gE
is greater than v
gE
(th) the collector current is given by
( )
C fs gE gE
fs gE
i = g v  v (th)
dic d
= g v
dt dt
But from the equivalent circuit of the IGBT gate drive circuit during turn on
( ) ( )
( )
( ) ( )
B
1
B
1
gg gE
gE
R
gE gD +1
fs gg gE
fs gE
R
gE gD +1
V  v
d
v =
dt
C + C R +
g V  v
dic d
= g v =
dt dt
C + C R +
In the active region V
gg
>> v
gE
Also since V
cc
> V
gg
, Q
1
& Q
2
operates in the active region.
Substituting the given values
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( )
9
12
2200
51
dic 40 15
= = 1.82 10 A/Sec
dt 4500 10 30 +
Since
1
=
2
,
dic
dt
during turn off will also have the same value
So
dic
=1.82 A/ns
dt
Since load current is 50 Amps and g
fs
= 40
L
ge L gE
fs
I
v I = v (th) + = 5.25 volts
g
Daring turn on
B
gg gE L
CE
gD g L R
+1
V  v I
dv
C = i I =
dt R +
CE
dv
dt
during turn ON is
( )
( )
B
1
gg gE L
CE
12 R 2200
51
gD +1
8
V  v I
dv 15 5.25
= =
dt 500 10 30 +
C R +
= 2.67 10 V/Sec
Since V
gg+
=V
gg
and
1
=
2
CE
dv
dt
during turn off will be same
So
8 CE
dv
= 2.67 10 V/Sec or 267 V/s.
dt
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Module
1
Power Semiconductor
Devices
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Lesson
8
Hard and Soft Switching
of Power Semiconductors
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This lesson provides the reader the following
(i) To highlight the issues related to device stresses under Hard switching;
(ii) To suggest means of reducing such stresses with external circuitry;
(iii) To propose alternative switching methods for stress reduction;
(iv) Enable the choice of the appropriate switching strategy
Soft and Hard Switching
Semiconductors utilised in Static Power Converters operate in the switching mode to
maximise efficiency. Switching frequencies vary from 50 Hz in a SCR based ACDC Phase
Angle Controller to over 1.0 MHz in a MOSFET based power supply. The switching or dynamic
behaviour of Power Semiconductor devices thus attracts attention specially for the faster ones for
a number of reasons: optimum drive, power dissipation, EMI/RFI issues and switchingaid
networks.
With SCRs 'forced commutation' and 'natural (line) commutation' usually described the type of
switching. Both refer to the turnoff mechanism of the SCR, the turnon dynamics being
inconsequential for most purposes. A protective inductive snubber to limit the turnon
di
/
dt
is
usually utilised. For the SCRs the turnoff data helps to dimension the 'commutation
components' or to set the 'margin angle'. Conduction losses account for the most significant part
of total losses.
Present day fast converters operate at much higher switching frequencies chiefly to reduce
weight and size of the filter components. As a consequence, switching losses now tend to
predominate, causing the junction temperatures to rise. Special techniques are employed to
obtain clean turnon and turnoff of the devices. This, along with optimal control strategies and
improved evacuation of the heat generated, permit utilisation of the devices with a minimum of
deration.
This chapter first examines the switching process, estimates the device dissipation and indicates
design procedures for the cooling system.
Losses in Power Semiconductors
A converter consists of a few controlled and a few uncontrolled devices (diodes). While the first
device is driven to turnon or off, the uncontrolled device operates mainly as a slave to the
former. Power loss in the converter is the aggregate of these losses. Occasionally the diode and
the controlled device are housed in the same module. The losses corresponding to each
contribute to the temperature rise of the integrated module.
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The losses can be segregated as follows:
Total module dissipation
Controlled device losses Diode losses
Conduction Losses
Conduction losses are caused by the forward voltage drop when the power semiconductor is on
and can be described by (with reference to an IGBT)
W
C
= V
ce (sat)
(I
c
).I
c
where I
c
is the current carried by the device and V
ce(sat)
(I
c
)
is the current dependant forward
voltage drop. This drop may be expressed as
V
ce (sat)
(I
c
)
= V
0
+ R . I
c
This relation defines the forward drop of an IGBT in a similar manner to a diode. A part of the
drop is constant while another part is collector current dependent.
The given data should be used as follows: Using the numerical value is the most simple way to
determine conduction losses. The numerical value can be applied if the current in the device is
equal or close to the specified current  data sheet numerical values are specified for typical
application currents.
The graph most accurately determines conduction losses. The conditions in which the data are
used should correspond to the application. To estimate if a power semiconductor rating is
appropriate, usually the values valid for elevated temperature, close to the maximum junction
temperature T
Jmax
, should be used to calculate power losses because this is commonly the
operating point at nominal load.
Fig. 3.1 Approximate forward voltage of IGBT and diode
Turnoff
switching
Turnon
Turnoff Turnoff
conduction conduction switching
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Blocking Losses
Blocking losses are generated by a low leakage current through the device with a high blocking
voltage.
W
B
= V
b
(I).I
L
Where I
L
is the leakage current and V
b
(I) is the current dependemt blocking voltage. Data sheets
indicates leakage current at certain blocking voltage and temperature. The dependence between
leakage current and applied voltage typically is exponential; this means that using a data sheet
value given for a blocking voltage higher than applied overestimates blocking losses. However in
general, blocking losses are small and can often, but not always, be neglected.
Switching Losses
IGBTs are designed for use in switching converters and not for linear operation. This means
switching time intervals are short compared to the pulse duration at typical switching
frequencies, as can be seen from their switching times, such as rise time t
r
and fall time t
f
in the
data sheets. Switching losses occur during these switching intervals.
Fig. 3.2 Switching losses (appx)
For IGBTs they are specified as an amount of energy, E
on/off
for a certain switching operation.
E
on/off
are the energy dissipated at turnon/turnoff respectively. Using the numerical value is
again the most simple way to determine switching losses. The numerical value can be applied if
the switching operations are carried out at the same or similar conditions as indicated in the data
sheet. Graphs for E
on
(I
C
)/(R
G
), E
off
(I
C
)/(R
G
) with collector current I
C
and gate resistance R
G
are
provided.
The graphs permit the most accurate determination of switching losses, given the parameters of
the converter: R
G
and converter current I
C
.
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Diode
A surge voltage occurs when the freewheel diode recovers. Consider a converter leg. The lower
device is off and that the load current is circulating through the freewheeling diode of the upper
device. Now if the lower device turns on, the current in the freewheel diode of the upper device
decreases during the overlap period and the load current begins to commutate to the lower
device. It becomes negative during reverse recovery of the upper freewheel diode. When the
freewheel diode recovers, the current in the circuit associated to the diode jumps to zero. The
parasitic line inductance L
p
develops a surge voltage equal to Lp di/dt in opposition to the
decreasing current. This di/dt is dictated by the recovery characteristic of the freewheel diode.
Fast recovery snappy diodes can develop very high recovery di/dt when they are hard
recovered by the rapid turnon of a device in series with it in the same converter leg. These
diodes take a smaller time to quench the reverse recovery current compared to a soft recovery
diode.
The offstate losses of the main device and the turnon dissipation may be neglected for most
cases. With an IGBT driven DCDC chopper as an example, the dissipation can be estimated as:
IGBT dissipation = Conduction losses + Switching losses
= [ .V
ce(sat)
I
c
] +[f
c
(E
on
+ E
off
)] Watts
Diode dissipation = Conduction losses + Reverse recovery losses
= [ (1 
F
V
F
]+ [f
c
E
rr
]
where, is the conduction duty ratio, f
c
the switching frequency and E
on
, E
off
, E
rr
are the
respective energy losses, Fig 3.2, data for which is provided by the device manufacturer.
The values of E
on
, E
off
, E
rr
are at the rated values only and have to be adjusted to the working
values of voltage (DC bus), V
CE
(working) and load current, I
c
.
( ) ( ) ( ) (
/ / / / /
on off rr working on off rr working CE working CE rated
E E E E E E V V
)
=
/ /
( ) ( )
/ / / / /
a b c
on off rr working on off rr C C rated
E E E E E E I I =
Where, a, b and c are constants.
The power device in a converter mostly sees an inductive load. A simple circuit illustrating such
a situation is shown in Fig. 3.3. Corresponding ideal waveforms are also indicated. The free
wheeling diode FWD, across the load is essential for clamping the induced voltages across the
inductance when the device switches off. However, its presence causes the supply voltage, V
s
to
appear across the transistor whenever it carries part of the inductor current in overlap mode with
the FWD during both turnon and turnoff modes. This causes the transistor switching dissipation
to increase.
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Fig. 3.3 Typical current and voltage transients during turnon and turn
off of a clampedinductive load and transitions in the VI plane.
An RCD Switchingaidnetwork connected across the device reduces turnoff dissipation, Fig.
3.2. The controlled rise of the collector voltage of the transistor aids this process. However, turn
off energy is accumulated in the SAN, which is ultimately dissipated in the resistor. The RCD
does not also help reduce turnon dissipation when the reverse recovery current of the diode and
the SAN current add up with the load current with V
s
again appearing across the device.
Example 3.1
Derive the expression for the power dissipation during turnon and turnoff of a transistor
unassisted by a SAN. The supply voltage is V
m
, peak load current I
m
, and t
r
, t
off
being the turn on
and turnoff times. Assume idealised waveforms.
Solution
The transition of the swichings in the V
C
 I
C
plane is rectangular. The energy dissipated in each
turnoff switching cycle is
f
t
M
I
M
V dt I V
T
W
off
t
T T
. . .
2
1
0
.
= =
If actual waveforms are considered the dissipation is close to about double the above figure.
The dissipation at turnon is, similarly 1/2. V
M
.I
M
.t
on.
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Fig. 3.4 Current and voltage waveforms at the Main Terminals of the switch with an
RCD SAN, and in the associated FWD and SAN diode
Example 3.2
For a transistor carrying a collector current I
M
and having a turnoff time t
f
, find the details of a
RCD SAN to restrict the voltage rise at the end of t
f
to half the supply voltage. Calculate the
corresponding losses in the transistor and in the SAN.
Solution
The action of the SAN in restricting the rise of transistor voltage till the current in it is
extinguished is illustrated in Fig. 3.4.
Since the current is assumed to fall linearly during the period t
f
, the collector voltage rises as:
2 2
0
2
.
=
f
f M
f
t
t
C
t I
t
t
V V
Where V
0
is the voltage at the capacitor at the end of turnoff time t
f
.
Thus,
C
t I
V
f M
2
0
=
=
f
M
t
t
I i 1
The Transistor current can be written as:
The dissipation in the transistor is
2
2 2
0 0
. .
1
. 1 .
2 2
f f
t t
M f M f
T
f f
I t I t
t t
W v idt dt Wa
C t t C
= = =
2
12
tts
When the transistor switches off, the nearly constant load current linearly charges up the
capacitor till it reaches the supply voltage. Subsequently, The FWD is positively biased and there
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is a short period of overlap between the FWD and the SAN diode. During this period, the
capacitor overcharges to some extent.
If V
0
is the capacitor voltage when the transistor current is extinguished,
= =
2
1
2
1
.
0
t
t
f M
t I dt i CV
If this V
0
is about 1/2 V
s
,
s
f M
V
t I
C
The energy dissipated in the SAN resistor which is also the energy shifted to the SAN from the
transistor during turnoff is
Where F is the switching frequency. The resistance should be able to limit the transistor current
to its peak rating. Thus,
F CV P
M R
2
2
1
=
rr M CM
s
I I I
V
R
I
rr
is the reverse recovery current of the FWD.
If the capacitor has to discharge completely during the ON time,
M s
f M
I R V
t I
C
.
.
In a SinePWM controlled converter with a peak value of the fundamental current equal to I
cp
,
the conduction losses in the IGBT would be
+ = R I V I T
cp o cp
.
2 2
.
2
2
1
d V I T Wc
sat ce c ) (
0
.
=
Where V
o
and R are as shown in Fig 3.1. For the diode the dissipation is
[ ]
d cp od cp F
R I V I W
2
2 2
. 1
2
1
+ =
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Soft switching
Fig. 3.5 Basic topologies for a) Hard switch, b) Zerovoltage switch
and c) for a Zero current switch
Hard switching and its consequences have been discussed above. Reduction of size and weight
of converter systems require higher operating frequencies, which would reduce sizes of inductors
and capacitors. However, stresses on devices are heavily influenced by the switching frequencies
accompanied by their switching losses. It is obvious that switchingaidnetworks do not mitigate
the dissipation issues to a great extent. Turnon snubbers though not discussed, are rarely used.
Even if used, it would not be able to prevent the energy stored in the junction capacitance to
discharge into the transistor at each turnon. Soft switching techniques use resonant techniques to
switch ON at zero voltage and to switch OFF at zero current. There are negligible switching
losses in the devices, though there is a significant rise in conduction losses. There is no transfer
of dissipation to the resonant network which is nondissipative. The two basic configurations are
as shown in Fig. 3.5.
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Fig. 3.6 Switching loci for a HardSwitched converter without SwitchingAidNetworks,
with the SAN and for a SoftSwitched converter operation
The switching trajectory in the voltagecurrent plane of a device is illustrated in Fig. 3.6
comparing the paths for that of a Hardswitched operation without any SAN, a Hardswitched
with a RCD SwitchingAidNetwork and a resonant converter. It is indicatve of the stresses and
losses. A designer would prefer the path to be as close as possible to the origin.
A Zero Current Switch based converter is provided as illustration to the soft switching
mechanism. It is equivalent to the topology shown above. The input capacitor and the one across
the diode may be combined to arrive at this topology.
Fig. 3.7 A ZCS resonant buck converter
The ZCS converter is considered to be in stable operation with Load current I
trans
flowing through
the diode and the inductor L
f
. The Capacitor C
r
is charged to V
s.
On switching the transistor ON
the current in it ramps up from zero but the diode continues conduction till this current reaches
the load current I
out
level. Subsequently, the load current and the resonating current flows
through the transistor. This current reaches a natural zero when the negative magnitude of the
resonating current equals the load current. The transistor thus switches in the Zero Current mode
for both turn on and turn off. The diode, on the other hand switches in the Zero Voltage mode
under both situations. It must be noted that the peak current stress on the transistor is high . The
peak voltage stress on the diode is also about twice the supply voltage. Both these stresses are
significantly higher than that in a comparable Hard switched buck converter. Consequently,
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while switching losses are practically eliminated in this resonant converter, conduction losses
increase along with the device stresses. There is no scope of a SANs in resonant switching.
Objective type questions
Qs#1 Which component of power dissipation in a Power Semiconductor device is reduced by
an RCD Switching Aid Network?
a) Off state losses
b) Turnon losses
c) Turnoff losses
d) Onstate losses
Ans: c) turnoff losses
Qs#2 Does an RCD SAN reduce total switching losses?
Ans: No. It transfers the losses from the device to itself.
Qs#3 Are resonant converters superior to the hard switched converter on all counts?
Ans: No. The resonant converter reduces switching losses at the cost of higher voltage/current
stresses on the devices.
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Module
2
AC to DC Converters
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Lesson
9
Single Phase Uncontrolled
Rectifier
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Operation and Analysis of single phase uncontrolled rectifiers
Instructional Objectives
On completion the student will be able to
Classify the rectifiers based on their number of phases and the type of devices used.
Define and calculate the characteristic parameters of the voltage and current waveforms.
Analyze the operation of single phase uncontrolled half wave and full wave rectifiers
supplying resistive, inductive, capacitive and back emf type loads.
Calculate the characteristic parameters of the input/output voltage/current waveforms
associated with single phase uncontrolled rectifiers.
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9.1 Introduction
One of the first and most widely used application of power electronic devices have been in
rectification. Rectification refers to the process of converting an ac voltage or current source to
dc voltage and current. Rectifiers specially refer to power electronic converters where the
electrical power flows from the ac side to the dc side. In many situations the same converter
circuit may carry electrical power from the dc side to the ac side where upon they are referred to
as inverters. In this lesson and subsequent ones the working principle and analysis of several
commonly used rectifier circuits supplying different types of loads (resistive, inductive,
capacitive, back emf type) will be presented. Points of interest in the analysis will be.
Waveforms and characteristic values (average, RMS etc) of the rectified voltage and
current.
Influence of the load type on the rectified voltage and current.
Harmonic content in the output.
Voltage and current ratings of the power electronic devices used in the rectifier circuit.
Reaction of the rectifier circuit upon the ac network, reactive power requirement, power
factor, harmonics etc.
Rectifier control aspects (for controlled rectifiers only)
In the analysis, following simplifying assumptions will be made.
The internal impedance of the ac source is zero.
Power electronic devices used in the rectifier are ideal switches.
The first assumption will be relaxed in a latter module. However, unless specified otherwise, the
second assumption will remain in force.
Rectifiers are used in a large variety of configurations and a method of classifying them
into certain categories (based on common characteristics) will certainly help one to gain
significant insight into their operation. Unfortunately, no consensus exists among experts
regarding the criteria to be used for such classification. For the purpose of this lesson (and
subsequent lessons) the classification shown in Fig 9.1 will be followed.
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This Lesson will be concerned with single phase uncontrolled rectifiers.
9.2 Terminologies
Certain terms will be frequently used in this lesson and subsequent lessons while characterizing
different types of rectifiers. Such commonly used terms are defined in this section.
Let f be the instantaneous value of any voltage or current associated with a rectifier
circuit, then the following terms, characterizing the properties of f, can be defined.
Peak value of f : As the name suggests
( )
f
max
f : By definition
pp max mi
f = f  f
n
Over period T (9.5)
Fundamental component of f(F
1
): It is the RMS value of the sinusoidal component in the
Fourier series expression of f with frequency 1/T.
( )
2 2
1 A1
1
F = f +f
2
B1
....(9.6)
where
( )
T
A1
0
2
t
f = f t cos 2 dt
T
T
(9.7)
( )
T
B1
0
2
2 t
f = f t sin dt
T
T
.(9.8)
K
th
harmonic component of f(F
K
): It is the RMS value of the sinusoidal component in the
Fourier series expression of f with frequency K/T.
( )
2 2
K AK
1
F = f +f
2
BK
(9.9)
where
T
AK
0
2
f = f(t) cos2Kt T dt
T
...(9.10)
T
BK
0
2
f = f(t) sin2Kt T dt
T
(9.11)
Crest factor of f(C
f
) : By definition
f
RMS
f
C =
F
(9.12)
Distortion factor of f(DF
f
) : By definition
1
f
RMS
F
DF =
F
..(9.13)
Total Harmonic Distortion of f(THD
f
): The amount of distortion in the waveform of f is
quantified by means of the index Total Harmonic Distortion (THD). By definition
2
k
f
1
K=0
K 1
F
THD =
F
..(9.14)
From which it can be shown that
2
f
f
f
1 DF
THD =
DF
(9.15)
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Displacement Factor of a Rectifier (DPF): If v
i
and i
i
are the per phase input voltage and input
current of a rectifier respectively, then the Displacement Factor of a rectifier is defined as.
DPF =
i
cos (9.16)
Where
i
is the phase angle between the fundamental components of v
i
and i
i
.
Power factor of a rectifier (PF): As for any other equipment, the definition of the power factor
of a rectifier is
Actual power input to the Rectifier
PF
Apparent power input to the Rectifier
= .(9.17)
if the per phase input voltage and current of a rectifier are v
i
and i
i
respectively then
PF =
i1 i1 i
iRMS iRMS
V I cos
V I
(9.18)
If the rectifier is supplied from an ideal sinusoidal voltage source then
i1 iRMS
V = V
so,
i1
i i1
iRMS
I
PF = cos = DF DPF
I
..(9.19)
In terms of THD
ii
2
ii
DPF
PF =
1+THD
...(9.20)
Majority of the rectifiers use either diodes or thyristors (or combination of both) in their
circuits. While designing these components standard manufacturers specifications will be
referred to. However, certain terms are used in relation to the rectifier as a system. They are
defined next.
Pulse number of a rectifier (p): Refers to the number of output voltage/current pulses in a
single time period of the input ac supply voltage. Mathematically, pulse number of a rectifier is
given by
Time period of the input supply voltage
p =
Time period of the minium order harmonic in the output voltage/current.
.
Classification of rectifiers can also be done in terms of their pulse numbers. Pulse number of a
rectifier is always an integral multiple of the number of input supply phases.
Commutation in a rectifier: Refers to the process of transfer of current from one device (diode
or thyristor) to the other in a rectifier. The device from which the current is transferred is called
the out going device and the device to which the current is transferred is called the incoming
device. The incoming device turns on at the beginning of commutation while the out going
device turns off at the end of commutation.
Commutation failure: Refers to the situation where the out going device fails to turn off at the
end of commutation and continues to conduct current.
Firing angle of a rectifier (): Used in connection with a controlled rectifier using thyristors. It
refers to the time interval from the instant a thyristor is forward biased to the instant when a gate
pulse is actually applied to it. This time interval is expressed in radians by multiplying it with
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the input supply frequency in rad/sec. It should be noted that different thyristors in a rectifier
circuit may have different firing angles. However, in the steady state operation, they are usually
the same.
Extinction angle of a rectifier (): Also used in connection with a controlled rectifier. It refers
to the time interval from the instant when the current through an outgoing thyristor becomes zero
(and a negative voltage applied across it) to the instant when a positive voltage is reapplied. It is
expressed in radians by multiplying the time interval with the input supply frequency () in
rad/sec. The extinction time (/) should be larger than the turn off time of the thyristor to avoid
commutation failure.
Overlap angle of a rectifier (): The commutation process in a practical rectifier is not
instantaneous. During the period of commutation, both the incoming and the outgoing devices
conduct current simultaneously. This period, expressed in radians, is called the overlap angle
of a rectifier. It is easily verified that + + = radian.
Exercise 9.1
Fill in the blank(s) with the appropriate word(s).
i) In a rectifier, electrical power flows from the _________ side to the ________ side.
ii) Uncontrolled rectifiers employ _________ where as controlled rectifiers employ
________ in their circuits.
iii) For any waveform Form factor is always _______ than or equal to unity.
iv) The minimum frequency of the harmonic content in the Fourier series expression of
the output voltage of a rectifier is equal to its _________.
v) THD is the specification used to describe the quality of ___________ waveforms
where as Ripple factor serves the same purpose for _________ for waveforms.
vi) Input power factor of a rectifier is given by the product of the _________ factor
and the ________ factor.
vii) The sum of firing angle, Extinction angle and overlap angle of a controlled
rectifier is always equal to _________.
Answers: (i) ac, dc; (ii) diodes, thyristors; (iii) greater; (iv) pulse number; (v) ac, dc; (vi)
displacement, distortion; (vii)
9.3 Single phase uncontrolled half wave rectifier
This is the simplest and probably the most widely used rectifier circuit albeit at relatively small
power levels. The output voltage and current of this rectifier are strongly influenced by the type
of the load. In this section, operation of this rectifier with resistive, inductive and capacitive
loads will be discussed.
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Fig 9.2 shows the circuit diagram and the waveforms of a single phase uncontrolled half
wave rectifier. If the switch S is closed at at t = 0, the diode D becomes forward biased in the
the interval 0 < t . If the diode is assumed to be ideal then
For 0 < t
v
0
= v
i
= 2 V
i
sin t
v
D
= v
i
v
0
= 0 (9.21)
Since the load is resistive
0
0 0
2V
i = v R = sint
R
..(9.22)
i
i
= i
0
For t > , v
i
becomes negative and D becomes reverse biased. So in the interval < t 2
i
i
= i
0
= 0
v
0
= i
0
R = 0...(9.23)
v
D
= v
i
v
0
= v
i
= 2 V
i
sint
From these relationships
2
i
0AV 0 i
0 0
2V 1 1
V = v dt = 2 sintdt =
2 2
V
.(9.24)
2 2
i
DRMS i
0
V 1
V = 2V sin tdt =
2
2
...(9.25)
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It is evident from the waveforms of v
0
and i
0
in Fig 9.2 (b) that they contain significant amount
of harmonics in addition to the dc component. Ripple factor of v
0
is given by
2 2
2
DRM DAV
0RF
DAV
V  V
1
v = =  4
V 2
(9.26)
With a resistive load ripple factor of i
0
will also be same.
Because of such high ripple content in the output voltage and current this rectifier is
seldom used with a pure resistive load.
The ripple factor of output current can be reduced to same extent by connecting an
inductor in series with the load resistance as shown in Fig 9.3 (a). As in the previous case, the
diode D is forward biased when the switch S is turned on. at t = 0. However, due to the load
inductance i
0
increases more slowly. Eventually at t = , v
0
becomes zero again. However, i
0
is still positive at this point. Therefore, D continues to conduct beyond t = while the negative
supply voltage is supported by the inductor till its current becomes zero at t = . Beyond this
point, D becomes reverse biased. Both v
0
and i
0
remains zero till the beginning of the next cycle
where upon the same process repeats.
From the preceding discussion
For 0 t
v
D
= 0
v
0
= v
i
i
0
= i
i
(9.27)
for t 2
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v
0
= 0
i
0
= i
i
= 0
v
D
= v
i
v
0
= v
i
2
0AV 0 i
0 0
1 1
V = v dt = 2Vsintdt
2 2
(9.28)
or
(
i
0AV
2V 1 cos
V =
2
)
... (9.29)
2 2
0RMS i
0
1
V = 2V sin tdt
2
=
( )
2
i i
V V 1 2  sin2
 sin2 =
2 2
2
2
..(9.30)
Form factor of the voltage waveform is
0RMS
OFF 2
0AV
V 2  sin2
v = =
V
2(1 cos)
.(9.31)
The ripple factor.
2
0RF OFF 2
(2  sin2)
v = v 1 = 
2(1 cos)
1(9.32)
All these quantities are functions of which can be found as follows.
For 0 t
i i
dio
v = 2Vsint = L +Ri
dt
0
.(9.33)
i
0
(t = 0) = i
0
(t = ) = 0
The solution is given by
t

tan
i
0 0
2V
i = I e + sin(t  )
Z
(9.34)
where tan =
L
R
and Z =
2 2
R + L
2
..(9.35)
Putting the initial conditions of (9.33)
(
t

tan
i
0
2V
i = sine +sin t 
Z
(9.36)
( )

tan
i
0
2V
i (t = ) = sine +sin  = 0
Z
or (

tan
sine = sin  ) .(9.37)
as a function of can be obtained by solving equation 9.37.
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It can be shown that increases with . From Equation (9.29), V
0AV
decreases with
increasing while V
0RMS
increases with . Therefore, with increasing (and hence increasing
L) the form factor and the ripple factor of v
0
worsens. However, the ripple factor of i
0
decreases
with increasing L. Therefore, in certain applications, where a smooth dc current is of prime
importance (e.g. the field supply of a dc motor) this configuration of the rectifier is preferred.
The problem of poor form factor (ripple factor) of the output voltage can be solved to
some extent by connecting a capacitor across the load resistance of Fig 9.2 (a). This single phase
half wave rectifier supplying a capacitive load is shown in Fig 9.5 (a). Corresponding
waveforms are shown in Fig 9.5 (b).
If the capacitor was initially discharged the diode D is forward biased when the switch
S is turned on at t = 0. The output voltage follows the input voltage. The diode D carries both
the capacitor charging current and the load current. At t = the sum of these two currents
becomes zero and tends to grow in the negative direction. At this point the diode becomes
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reverse biased and disconnects the load (along with the capacitor) from the supply. The
capacitor then discharges with the load current. Diode D does not become forward biased till the
input supply voltage becomes equal to the capacitor voltage in the next cycle at t = (2 + ).
The same process repeats thereafter.
From the preceding discussion
For 2 + t 2 +
0 i 1
v = v = 2Vsint ..(9.38)
0 0
i c 0
dv v
i = i +i = c +
dt R
or
[ ]
i
i
2V
i = RCcost +sint
R
( )
1
2 2 2
2
i
2V
= 1+ R C cos(t  )
R
..(9.39)
where
1 1
= tan
RC
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At t = + 2, i
i
= 0 so = /2 or = + /2
or
1 1
= + tan
2 RC
.(9.40)
Again for t 2 +
( )
0 0
i 0
dv v
i = 0, C + = 0, v t = = 2Vcos
dt R
i
.
(t ) tan
0 i
v = 2Vcos e ..(9.41)
at
0 i
t = 2 +, v = 2Vsin
(2+ ) tan
2
i i
2Vsin = 2Vcos e
or
3
( +) tan
2
sin = cos e
or
3
( ) tan
 tan
2
sin = cos e e
...(9.42)
From which can be solved. Peak to peak ripple in v
0
is
0pp i
v = 2V(1 sin ) .(9.43)
As c , 0 and and /2 and 0
0pp
v
Therefore, a very large capacitor helps to improve the ripple factor of the output voltage of this
rectifier. However, as indicated by Equation (9.39) the peak current through the diode increases
proportionately. It is also interesting to observe that unlike the previous cases the peak reverse
voltage appearing across D is given by.
D i 0M
v max = 2V + v 2 2V
i
(9.44)
This is sometimes referred to as the peak inverse voltage rating (PIV) of the diode.
Exercise 9.2
1. Fill in the blank(s) with the appropriate word(s).
i) The ripple factor of the output voltage and current waveforms of a single phase
uncontrolled half wave rectifier is ____________ than unity.
ii) With an inductive load, the ripple factor of the output __________ of the half wave
rectifier improves but that of the output __________ becomes poorer.
iii) In both single phase half wave and full wave rectifiers the form factor of the output
voltage approaches _________ with capacitive loads provided the capacitance is
________ enough.
iv) The PIV rating of the rectifier diode used in a single phase half wave rectifier
supplying a capacitive load is approximately ________ the __________ input supply
voltage.
v) The % THD of the input current of the rectifiers supplying capacitive loads is
__________.
Answers: (i) greater; (ii) current, voltage; (iii) unity, large; (iv) double, peak; (v) high.
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2. An unregulated dc. power supply of average value 12 V and peak to peak ripple of 20% is to
be designed using a single phase half wave rectifier. Find out the required input voltage, the
output capacitance and the diode RMS current and PIV ratings. The equivalent load
resistance is 50 ohms.
Answer: From equation 9.43.
opp i
v = 2V(1 sin ) = 0.212 = 2.4 V.
omax i i
V = 2V =12+2.4 2 =13.2V V = 9.33V
o
sin = 0.818 or = 54.9 = 0.96 rad.
Then from equation 9.42
(3 2 +  ) tan
0.818 = cos e
(5.67  ) tan
or 0.818 e = cos
From which 2.035
1
tan = = 0.03553, R = 50, C = 1790 F
RC
PIV of the diode =
i
2 2V = 26.4V.
RMS. Diode current =
( )
o
92.035
2 2 2 2 2
i
i
54.9
V 1 1
i dt = 2 1+ R C cos (t  )dt
2 R 2
1  1 1
= 7.432 + sin2(  )  sin2(  ) 0.8564
2 2 4 4
=
Amps.
9.4 Single phase uncontrolled full wave rectifier
Single phase uncontrolled half wave rectifiers suffer from poor output voltage and/or
input current ripple factor. In addition, the input current contains a dc component which may
cause problem (e.g. Transformer saturation etc) in the power supply system. The output dc
voltage is also relatively less. Some of these problems can be addressed using a full wave
rectifier. They use more number of diodes but provide higher average and rms output voltage.
There are two types of full wave uncontrolled rectifiers commonly in use. If a split
power supply is available (e.g. output from a split secondary transformer) only two diode will be
required to produce a full wave rectifier. These are called split secondary rectifiers and are
commonly used as the input stage of a linear dc voltage regulator. However, if no split supply is
available the bridge configuration of the full wave rectifier is used. This is the more commonly
used full wave uncontrolled rectifier configuration. Both these configurations are analyzed next.
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9.4.1 Split supply single phase uncontrolled full wave rectifier.
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Fig 9.6 shows the circuit diagram and waveforms of a single phase split supply,
uncontrolled full wave rectifier supplying an R L load. The split power supply can be thought
of to have been obtained from the secondary of a center tapped ideal transformer (i.e. no internal
impedance).
When the switch is closed at the positive going zero crossing of v
1
the diode D
1
is
forward biased and the load is connected to v
1
. The currents i
0
and i
i1
start rising through D
1
.
When v
1
reaches its negative going zero crossing both i
0
and i
i1
are positive which keeps D
1
in
conduction. Therefore, the voltage across D
2
is . Beyond the negative going zero
crossing of v
CB 2 1
v = v  v
i,
D
2
becomes forward biased and the current i
0
commutates to D
2
from D
1
. The
load voltage v
0
becomes equal to v
2
and D
1
starts blocking the voltage . The current
i
AB 1 2
v = v  v
0
however continues to increase through D
2
till it reaches the steady state level after several
cycles. Steady state waveforms of the variables are shown in Fig 9.6 (b) from t = 0 onwards. It
should be noted that the current i
0,
once started, always remains positive. This mode of operation
of the rectifier is called the Continuous conduction mode of operation. This should be
compared with the i
0
waveform of Fig 9.3 (b) for the half wave rectifier where i
0
remains zero
for some duration of the input supply waveform. This mode is called the discontinuous
conduction mode of operation.
From the above discussion
For 0 t <
v
0
= v
1
i
0
= i
i1
....(9.45)
for t < 2
v
0
= v
2
i
0
= i
i2
........(9.46)
Since v
0
is periodic over an interval
i
0AV 0
0 0
2V 2 2V 1
V = v dt = sintdt =
i
..(9.47)
2 2
0RMS i i
0
1
V = 2V sin t dt = V
........(9.48)
0RMS
0FF
0AV
V
v = =
V
2 2
.(9.49)
2
2
0RF 0FF
8
v = v 1 =
2 2
..(9.50)
Both the form factor and the ripple factor shows considerable improvement over their half wave
counter parts.
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The single phase full wave rectifier still does not offer a smooth dc voltage. With
resistive load, considerable ripple current will flow into the load. This problem can be solved by
connecting a capacitor across the load resistance just as in the case of a half wave rectifier.
If the capacitor was initially discharged, the diode D
1
is forward biased when the switch S
is turned on at t = 0. The diode D
2
remains reverse biased. The output voltage follows the
input voltage. D
1
carries both the capacitor charging current and the load current. At t = the
sum of these two currents becomes zero and tends to grow in the negative direction. At this
point the diode D
1
becomes reverse biased and disconnects the load along with the capacitor
from the supply. The capacitor then discharges through the load until at t = + , v
2
becomes
greater than v
0
and forward biases D
2
. D
1
now remains reverse biased. D
2
conducts up to t =
+ . The same process repeats thereafter.
From the discussion above
For + t +
0 2 i
v = v =  2Vsint
0
i2 c 0
dv v
i = i +i = C +
dt R
0
(9.51)
or
[ ]
i
i2
2V
i =  RCcost +sint
R
( ) ( )
1
2 2 2
2
i
2V
= 1+ R C cos +  t
R
where
1 1
= tan
RC
.(9.52)
at t = + , i
i1
= 0 so
 =
2
or
= +
2
or
1 1
= + tan
2 RC
(9.53)
Again for t +
( )
0 0
i1 0 i i
dv v
i = 0 C + = 0 v t = = 2Vsin = 2Vcos
dt R
.(9.54)
( )  t tan
0 i
v = 2Vcos e .(9.55)
at t = + ,
0
v = 2sin
( )
+ tan
2
i i
2Vsin = 2Vcos e
or
( )
 + tan
2
sin = cos e
or
( )
  tan
tan
2
sin = cos e e
(9.56)
From which can be solved. Peak to peak ripple in v
0
is
0pp i
v = 2V(1 sin) .(9.57)
It can be shown that for the same R and C, given by Equation (9.57) is smaller than that
given by Equation (9.43) for the half wave rectifier. The diode PIV ratings remain equal to
0pp
v
i
2 2V however.
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Exercise 9.3
1. Fill in the blank(s) with the appropriate word(s).
i) The output voltage form factor of a single phase full wave rectifier is ___________.
ii) The output voltage of a single phase full wave rectifier supplying an inductive load is
___________ of the load parameters.
iii) The peak to peak output voltage ripple of a single phase split supply full wave
rectifier supplying a capacitive load is ___________ compared to an equivalent half
wave rectifier.
Answers: (i)
2 2
; (ii) independent ; (iii) smaller.
2. An unregulated dc power supply is built around a single phase split supply full wave rectifier
using the same input voltage and output capacitor found in the problem 2 of Exercise 9.2.
The load resistance is 50 . Find out the average output voltage, the peak to peak ripple in
the output voltage and the RMS current ratings of the diodes.
Answer: From the given data C = 1790 F, R = 50 , = 2.035
From equation 9.56
Sin = cos e
(/2 + )
tan
Or sin =
0.03553(1.5353+ )
0.99937 e
=
0.03553
0.946316 e
From which = 65.33
V
i
= 9.33 volts.
opp i
v 2V(1 sin ) =1.20 = volts.
opp
0AV 0Max i
v
V = V  = 2V  0.6V =13.2 0.6V =12.6V
2
.
% ripple = 9.5%
RMS diode current =
( )
2+
2 2 2 2 2
i
i
V 1 1
i dt = 2 1+ R C cos (t  )dt
2 R 2
1  1
= 7.432  sin2(  ) 0.53
2 2 4
=
3 Amps.
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9.4.2 Single phase uncontrolled full bridge rectifier
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The split supply full wave single phase rectifier offers as good performance as possible from a
single phase rectifier in terms of the output voltage form factor and ripple factor. They have a
few disadvantages however. These are
They require a split power supply which is not always available.
Each half of the split power supply carries current for only one half cycle. Hence they are
underutilized.
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The ratio of the required diode PIV to the average out put voltage is rather high.
These problems can be mitigated by using a single phase full bridge rectifier as shown in Fig 9.8
(a). This is one of the most popular rectifier configuration and are used widely for applications
requiring dc. power output from a few hundred watts to several kilo watts. Fig 9.8 (a) shows the
rectifier supplying an RLE type load which may represent a dc. motor or a storage battery.
These rectifiers are also very widely used with capacitive loads particularly as the front end of a
variable frequency voltage source inverter. However, in this section analysis of this rectifier
supplying an RLE load will be presented. Its operation with a capacitive load is very similar to
that of a split supply rectifier and is left as an exercise.
When the switch S is turned on at the positive going zero crossing of vi no current flows in the
circuit till vi crosses E at point A. Beyond this point, D
1
& D
2
are forward biased by vi and
current starts increasing through them till the point B. After point B, vi falls below E and i
o
starts
decreasing. Now depending on the values of R, L & E one of the following situations may arise.
i
o
may become zero before the negative going zero crossing of vi at point C.
i
o
may continue to flow beyond C and become zero before the point D.
i
o
may still be non zero at point D.
It should be noted that if i
o
>0 either D
1
D
2
or D
3
D
4
must conduct. Fig 9.4 (b) shows the
waveforms for the third situation.
If i
o
>0 at point C the negative going input voltage reverse biases D1 & D2. Current i
o
commutates to D3 and D4 as shown in the associated conduction Diagram in Fig 9.8 (b). It
shows pictorially the conduction interval of different devices. The current i
o
continues to
decrease up to the point D beyond which it again increases. It should be noted that in this mode
of conduction i
o
always remain greater than zero. Consequently, this is called the continuous
conduction mode of operation of the rectifier. In the other two situations the mode of operation
will be discontinuous.
The steady state waveforms of the rectifier under continuous conduction mode is shown to the
right of the point t = 0 in Fig 9.4 (b).
From this figure and preceding discussion
For 0 < t
o i i
v = v = 2 sin t V (9.58)
i
i
= i
o
for < t 2
o i i
v =  v =  2 sin t V (9.59)
i
i
=  i
o
2
oAV i i
o
1
V = 2 sin t d t = V
V
2 2
(9.60)
2 2
oRMS i i
o
1
V = 2V sin t d t = V
(9.61)
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oRMS
OFF
oAV
V
v = =
V
2 2
2
2
oRF OFF
 8
v = v 1 =
2 2
(9.62)
Finding out the characterizing quantities for i
i
will be difficult owing to its complicated
waveform. Considerable, simplification is achieved (without significant loss of accuracy) by
replacing the actual i
o
waveform by its average value I
oAV
= V
oAV
/ R.
Fig 9.9 shows the approximate input current wave form and its fundamental component.
From Fig 9.9
Displacement angle
i
= 0
Input displacement factor (DPF) = cos
i
= 1 (9.63)
Distortion factor (DF
il
) =
il
oAV
I 2
=
I
2
(9.64)
Power Factor (PF) =
il
2 2
DPF DF =
(9.65)
i
2 2
i
i 2
i
1  DFi  8
% TH D = 100 = 100
DFi
2 2
(9.66)
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The exact analytical expression for i
o
(and hence i
i
) can be obtained as follows.
for 0 < t
o
i i o
Ldi
v = 2 sin t = Ri + + E
dt
V (9.67)
o t =0 o t =
i = i (steady state periodic boundary cond.)
The general solution can be written as
( )
t
tan
 i
o o
2V sin
i = I e + sin t  
Z
cos
(9.68)
where
2 2 2
i
L E
tan = ; Z = R + L ; sin =
R
2V
From the boundary condition
tan
 i i
o o
2V sin 2V sin
I  sin + = I e + sin 
Z cos Z c
os
tan
i
o

2V 2 sin
I =
Z
1  e
(9.69)
( )
t
tan
tan
 i
o

2 V 2 sin sin
i = e + sin t  
Z
1  e
cos
(9.70)
From which the condition for continuous conduction can be obtained.
for continuous conduction
o
i 0 for all 0 < t
hence
o Min o t =
i 0 or i 0
Condition for continuous conduction is
( )
tan
tan


2 sin sin
e = sin  +
cos
1  e
(9.71)
If the parameters of the load (i.e, R, L &E) are such that the left hand side of equation 9.71 is less
than the right hand side conduction of the rectifier becomes discontinuous i.e, the load current
becomes zero for a part of the input cycle. Discontinuous conduction mode of operation of this
rectifier is discussed next.
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Fig. 9.10(b) shows the waveforms of different variables under discontinuous conduction mode of
operation. In this mode of operation D
1
D
2
are not forward biased till vi exceed E at t = .
Consequently, no current flows into the load till this time. After t = , the load is connected to
the input source through D
1
D
2
and i
o
starts building up. Beyond t =  , i
o
starts decreasing
and becomes zero at t = < . D
1
D
2
are reverse biased at this point. D
3
D
4
are forward biased
at t = + when i
o
starts increasing again. Thus none of the diodes conduct during the interval
< + + and i
o
remains zero during this period.
Form the preceding discussion
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i
o i
i o
for < t <
v = v = 2V sin t
i = i
(9.72)
for < + < + + < 2
o i i
i o
o
v =  v =  2V sin t
i =  i
v = E
(9.73)
(9.74)
i o
i = i = 0 other wise
+ +
i
oAV o
1 1
V = v d t = 2V sin t + E d t
( ) [
i
oAV
2V
OR V = cos  cos + +  sin
] (9.75)
can be found in the following manner
for < t
o
o
Ldi
v = 2 sin t = R i + + E
dt
(9.76)
o t = o t =
i = i = 0
The general solution is
( )
t
tan
 i
o o
2V sin
i = I e + sin t  
Z
cos
(9.77)
where
2 2 2
i
L E
tan = , Z = R + L , sin =
R
2V
From the initial condition
o t =
i = 0
( )
i
o
2V
sin
I = sin  +
cos
Z
(9.78)
( )
( )
(
t t
tan tan
 i
o
2V sin
i = sin  e  1 e + sin t 
Z cos
)
(9.79)
Putting
o t =
i = 0 in Equation 9.79.
( ) ( )
 
tan tan
sin
sin  = 1  e  sin  e
cos
(9.80)
Form which can be solved.
Exercise 9.4
1. Fill in the blank(s) with the appropriate word(s).
i) The average output voltage of a full wave bridge rectifier and a split supply full wave
rectifier are __________ provided the input voltages are ___________.
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ii) For the same input voltage the bridge rectifier uses ___________ the number of
diodes used in a split supply rectifier with _________ the PIV rating.
iii) For continuous conduction, the load impedance of a bridge rectifier should be
__________.
iv) In the ___________ conduction mode the output voltage of a bridge rectifier is
__________ of load parameters.
Answers: (i) equal, equal; (ii) double, half; (iii) inductive; (iv) continuous, independent.
2. A battery is to be charged using a full bridge single phase uncontrolled rectifier. On full
discharge the battery voltage is 10.2 V. and on full charge it is 12.7 volts. The battery
internal resistance is 0.1. Find out the input voltage to the rectifier so that the battery
charging current under full charge condition is 10% of the charging current under fully
discharged condition. Assume continuous conduction under all charging condition and find
out the inductance to be connected in series with the battery for this condition.
Answer: Let the rectifier input voltage be V
i
and the charging current under fully discharged
condition be I.
Then assuming continuous conduction
i
2 2V
 0.1I =10.2
and
i
2 2
V  0.01I =12.7
0.09I = 2.5 V I = 27.78 Amps and V
i
= 14.415 volts.
If conduction is continuous at full charge condition it will be continuous for all other
charging conditions.
For continuous conduction
 tan
 tan
2sin sin
e = sin(  ) +
cos
1 e
From given data
i
E
sin = = 0.623,
2V
= 38.535
From which = 86.5
L
tan = =16.35
R
or L = 1.635 ohms
L = 5.2 mH.
References
[1] P.C. Sen, Power Electronics, Tata McGraw Hill Publishing Company Limited. 1995
[2] Muhammad H. Rashid, Power Electronics, circuits, Devices and applications Prentice
Hall of India Private Limited, Second Edition, 1994
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Module Summary
A rectifier is a power electronic converter which converts ac voltage or current sources to
dc voltage and current.
In a rectifier, electrical power flows from the ac input to the dc output.
In many rectifier circuits, power can also flow from the dc side to the ac side, where
upon, the rectifier is said to be operating in the inverter mode.
Rectifiers can be classified based on the type of device they use, the converter circuit
topology, number of phases and the control mechanism.
All rectifiers produce unwanted harmonies both at the out put and the input. Performance
of a rectifier is judged by the relative magnitudes of these harmonies with respect to the
desired output.
For a given input voltage and load, the output voltage (current) of an uncontrolled
rectifier can not be varied. However, the output voltage may vary considerably with load.
Single phase uncontrolled half wave rectifier with resistive or inductive load have low
average output voltage, high from factor and poor ripple factor of the output voltage
waveform.
Single phase uncontrolled full wave rectifier have higher average output voltage and
improved ripple factor compared to a half wave rectifier with resistive and inductive load.
With highly inductive load the output voltage waveform of a full wave rectifier may be
independent of the load parameters.
With a capacitive load the output voltage form factor approaches unity with increasing
capacitance value for both the half wave and the full wave rectifiers. However, THD of
the input current also increases.
A full wave bridge rectifier generates higher average dc voltage compared to a split
supply full wave rectifier. However it also uses more number of diodes.
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Practice Problems and Answers
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Q1. What will be the load voltage and current waveform when a single phase half wave
uncontrolled rectifier supplies a purely inductive load? Explain your answer with
waveforms.
Q2. The split supply of a single phase full wave rectifier is obtained from a single phase
transformer with a single primary and a center tapped secondary. The rectifier supplies a
purely resistive load. Assuming the transformer to be ideal find out the, displacement
factor, distortion factor and the power factor at the primary side of the transformer.
Q3. A single phase split supply full wave rectifier is designed to supply an inductive load.
The average load current is 20 A, and the ripple current is negligible. Can the same
rectifier be used with a capacitive load drawing the same 20 Amps average current?
Justify your answer.
Q4. A 200V, 15 Amps, 1500 rpm separately excited dc motor has an armature resistance of 1
and inductance of 50 mH. The motor is supplied from a single phase full wave bridge
rectifier with input voltage of 230 V, 50 HZ. Neglecting all no load losses, find out the
no load speed of the machine. Also find out the torque and speed at the boundary
between continuous and discontinuous conduction.
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Answer 1
Without loss of generality it can be assumed that S is turned ON at t = 0. Since, if it is turned
ON anytime after t = 0, the voltsec. across the inductor will dictate that the current through it
becomes zero before the next positive going zero crossing of v
i
.
In the region 0 t <
D is forward biased and v
0
= v
i
0
i 0
di
L = 2Vsint i (0) 0
dt
=
or
0
i
di
L = 2Vsint
dt
0
i
= 0
t = 0
i
0 0
2V
i = I  cost
L
i
0
2V
I =
L
i
0
2V
i = (1 cost)
L
at t = ,
i
0
2 2V
i = 0
L
>
D conducts beyond t = until i
0
is zero again.
Let the extinction angle be t = > .
Then for 0 t
`
i
0
2V
i = (1 cost)
L
i
0
2V
i
= (1 cos)
t =
L
for 2 the only solution is = 2
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v
0
= v
i
for 0 t 2 and
i
0
2V
i = (1 cost)
L
0 t 2
Answer 2
Figure shows the secondary voltage and current waveforms of the rectifier.
From the given data
S
S1 P
P
N
v = 2V sint
N
S P
S1
P
N V
i = 2 sint for 0 t
N R
i
S1
= 0 otherwise.
S
S2 P
P
N
v =  2V sint
N
S P
S2
P
N V
i =  2 sint for t 2
N R
i
S2
= 0 otherwise
From the MMF balance of an ideal transformer
P P S S1 S S2
N i  N i + N i = 0
or
S P
P S1 S2 2
P
P
S
N 2V
i = (i  i ) = sint
N
N
R
N
At the input
Displacement factor = Distortion factor = Power factor = 1.0
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Answer 3
If the load current is 20A with negligible ripple. The required RMS current rating of the rectifier
diode, with reference to Fig 9.6 (b) will be
D1RMS D2RMS
20
I = I = Am
2
ps .
However from Fig 9.7 (b) and Problem 2 of Exercise 9.3 the required RMS current for a
capacitive load will be much larger than 20 Amps. Therefore the same rectifier can not be used.
Answer 4
Since all no load losses are neglected the developed power at no load and hence the no load
torque will be zero. Therefore, the average armature current will also be zero. However, since a
diode rectifier can not conduct instantaneous negative load current, zero average current will
imply that the instantaneous value of the armature current at all time will be zero at no load.With
reference to Fig 9.10 this condition will require the rectifier diodes to remain reverse biased at all
time. Hence at no load
i
E 2 V
However E will not exceed
i
2V , since once i
a
becomes zero when
i
E = 2V there will be no
developed torque to accelerate the motor. Hence the motor speed and E will not increase any
further.
Thus at no load
i
E = 2V 325.27 volts = .
Under the rated condition at 1500 rpm
E
rated
= 200 15 1.0 = 185 volts.
Now
rated rated
E N
=
E N
rated
rated
E 325.27
N = N =1500 = 2637 rpm
E 185
.
At the boundary between the continuous and discontinuous mode of conduction.
 tan
 tan
2sin sin
e = sin( ) +
cos
1 e
or [ ]
tan
 tan
2sin
= cos sin( ) +sin e
1 e
where
3
L 1005010
tan = = =15.708
R 1
cos = 0.0635 = 1.507 rad. and sin2 = 0.1268
[ ]
0.06366
0.6995 = 0.0635 sin(1.507  ) + sin e
from which
1 o
i
E
= sin = 38.5
2V
E = 202.48 V
but E at 1500 RPM = 185 volts.
Speed at the junction of continuous and discontinuous condition is
202.48
1500 1642
185
= RPM.
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Average armature current is
i
2 2V
R = 4.593
Amps.
Torque =
4.593
100 = 30.62%
15
of rated torque.
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Module
2
AC to DC Converters
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Lesson
10
Single Phase Fully
Controlled Rectifier
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Operation and Analysis of single phase fully controlled converter.
Instructional Objectives
On completion the student will be able to
Differentiate between the constructional and operation features of uncontrolled and
controlled converters
Draw the waveforms and calculate their average and RMS values of different variables
associated with a single phase fully controlled half wave converter.
Explain the operating principle of a single phase fully controlled bridge converter.
Identify the mode of operation of the converter (continuous or discontinuous) for a given
load parameters and firing angle.
Analyze the converter operation in both continuous and discontinuous conduction mode
and there by find out the average and RMS values of input/output, voltage/currents.
Explain the operation of the converter in the inverter mode.
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10.1 Introduction
Single phase uncontrolled rectifiers are extensively used in a number of power electronic based
converters. In most cases they are used to provide an intermediate unregulated dc voltage source
which is further processed to obtain a regulated dc or ac output. They have, in general, been
proved to be efficient and robust power stages. However, they suffer from a few disadvantages.
The main among them is their inability to control the output dc voltage / current magnitude when
the input ac voltage and load parameters remain fixed. They are also unidirectional in the sense
that they allow electrical power to flow from the ac side to the dc side only. These two
disadvantages are the direct consequences of using power diodes in these converters which can
block voltage only in one direction. As will be shown in this module, these two disadvantages
are overcome if the diodes are replaced by thyristors, the resulting converters are called fully
controlled converters.
Thyristors are semicontrolled devices which can be turned ON by applying a current pulse at its
gate terminal at a desired instance. However, they cannot be turned off from the gate terminals.
Therefore, the fully controlled converter continues to exhibit load dependent output voltage /
current waveforms as in the case of their uncontrolled counterpart. However, since the thyristor
can block forward voltage, the output voltage / current magnitude can be controlled by
controlling the turn on instants of the thyristors. Working principle of thyristors based single
phase fully controlled converters will be explained first in the case of a single thyristor halfwave
rectifier circuit supplying an R or RL load. However, such converters are rarely used in
practice.
Full bridge is the most popular configuration used with single phase fully controlled rectifiers.
Analysis and performance of this rectifier supplying an RLE load (which may represent a dc
motor) will be studied in detail in this lesson.
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10.2 Single phase fully controlled halfwave rectifier
10.2.1 Resistive load
Fig.10. 1(a) shows the circuit diagram of a single phase fully controlled halfwave rectifier
supplying a purely resistive load. At t = 0 when the input supply voltage becomes positive the
thyristor T becomes forward biased. However, unlike a diode, it does not turn ON till a gate
pulse is applied at t = . During the period 0 < t , the thyristor blocks the supply voltage
and the load voltage remains zero as shown in fig 10.1(b). Consequently, no load current flows
during this interval. As soon as a gate pulse is applied to the thyristor at t = it turns ON. The
voltage across the thyristor collapses to almost zero and the full supply voltage appears across
the load. From this point onwards the load voltage follows the supply voltage. The load being
purely resistive the load current i
o
is proportional to the load voltage. At t = as the supply
voltage passes through the negative going zero crossing the load voltage and hence the load
current becomes zero and tries to reverse direction. In the process the thyristor undergoes reverse
recovery and starts blocking the negative supply voltage. Therefore, the load voltage and the load
current remains clamped at zero till the thyristor is fired again at t = 2 + . The same process
repeats there after.
From the discussion above and Fig 10.1 (b) one can write
For < t
0 i i
v = v = 2 V sint (10.1)
0 i
0
v V
i = = 2 sint
R R
(10.2)
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v
0
= i
0
= 0 otherwise.
Therefore
2
OAV 0 i
0
1 1
V = v dt = 2 V sint dt
2 2
(10.3)
Or
i
OAV
V
V = (1+cos)
2
(10.4)
2
2
ORMS 0
0
1
V = v dt
2
(10.5)
2 2
i
1
= 2v sin tdt
2
2
V
= (1 cos2t)dt
2
2
i
V
sin2
=  +
2 2
1
2
i
V sin2
1 +
2 2
=
1
2
ORMS
VO
OAV
sin2
1 +
V
2
FF = =
V (1+cos)
(10.6)
Similar calculation can be done for i
0
. In particulars for pure resistive loads FF
io
= FF
vo
.
10.2.2 ResistiveInductive load
Fig 10.2 (a) and (b) shows the circuit diagram and the waveforms of a single phase fully
controlled halfwave rectifier supplying a resistive inductive load. Although this circuit is hardly
used in practice its analysis does provide useful insight into the operation of fully controlled
rectifiers which will help to appreciate the operation of single phase bridge converters to be
discussed later.
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As in the case of a resistive load, the thyristor T becomes forward biased when the supply
voltage becomes positive at t = 0. However, it does not start conduction until a gate pulse is
applied at t = . As the thyristor turns ON at t = the input voltage appears across the load
and the load current starts building up. However, unlike a resistive load, the load current does
not become zero at t = , instead it continues to flow through the thyristor and the negative
supply voltage appears across the load forcing the load current to decrease. Finally, at t = (
> ) the load current becomes zero and the thyristor undergoes reverse recovery. From this point
onwards the thyristor starts blocking the supply voltage and the load voltage remains zero until
the thyristor is turned ON again in the next cycle. It is to be noted that the value of depends on
the load parameters. Therefore, unlike the resistive load the average and RMS output voltage
depends on the load parameters. Since the thyristors does not conduct over the entire input
supply cycle this mode of operation is called the discontinuous conduction mode.
From above discussion one can write.
For t
0 i i
v = v = 2 V sint (10.7)
v
0
= 0 otherwise
Therefore
2
OAV 0
0
1
V = v dt
2
(10.8)
1
2 V sint dt
2
=
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i
V
= (cos  cos)
2
2
2
ORMS 0
0
1
V = v dt
2
(10.9)
2 2
i
1
= 2v sin t dt
2
1
2
i
V  sin2  sin2
= +
2 2
OAV i
OAV
V V
I = = (cos  cos)
R
2R
(10.10)
Since the average voltage drop across the inductor is zero.
However, I
ORMS
can not be obtained from V
ORMS
directly. For that a closed from expression for i
0
will be required. The value of in terms of the circuit parameters can also be found from the
expression of i
0
.
For t
o
o 0 i
di
Ri +L = v = 2Vsint
dt
(10.11)
The general solution of which is given by
(t )

tan i
0 0
2V
i = I e + sin(t  )
Z
(10.12)
Where
L
tan =
R
and
2 2
Z = R + L
2
0
t =
i = 0
i
0
2V
0 = I + sin(  )
Z
( ) t 
i 
tan
0
2V
i =
sin(  )e + sin(t  )
Z
(10.13)
i
0
= 0 otherwise.
Equation (10.13) can be used to find out I
ORMS
. To find out it is noted that
0
t =
i = 0

tan
sin( )e = sin(  ) (10.14)
Equation (10.14) can be solved to find out
Exercise 10.1
Fill in the blank(s) with appropriate word(s)
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i) In a single phase fully controlled converter the _________ of an uncontrolled converters
are replaced by ____________.
ii) In a fully controlled converter the load voltage is controlled by controlling the _________
of the converter.
iii) A single phase half wave controlled converter always operates in the ________
conduction mode.
iv) The voltage form factor of a single phase fully controlled half wave converter with a
resistive inductive load is _________ compared to the same converter with a resistive
load.
v) The load current form factor of a single phase fully controlled half wave converter with a
resistive inductive load is _________ compared to the same converter with a resistive
load.
Answers: (i) diodes, thyristors; (ii) firing angle; (iii) discontinuous (iv) poorer; (v) better.
2) Explain qualitatively, what will happen if a freewheeling diode(cathode of the diode
shorted with the cathode of the thyristor) is connected across the load in Fig 10.2.(a)
Answer: Referring to Fig 10.2(b), the free wheeling diode will remain off till t = since the
positive load voltage across the load will reverse bias the diode. However, beyond this point as
the load voltage tends to become negative the free wheeling diode comes into conduction. The
load voltage is clamped to zero there after. As a result
i) Average load voltage increases
ii) RMS load voltage reduces and hence the load voltage form factor reduces.
iii) Conduction angle of load current increases as does its average value. The load
current ripple factor reduces.
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10.3 Single phase fully controlled bridge converter
Fig 10.3 (a) shows the circuit diagram of a single phase fully controlled bridge converter. It is
one of the most popular converter circuits and is widely used in the speed control of separately
excited dc machines. Indeed, the RLE load shown in this figure may represent the electrical
equivalent circuit of a separately excited dc motor.
The single phase fully controlled bridge converter is obtained by replacing all the diode
of the corresponding uncontrolled converter by thyristors. Thyristors T
1
and T
2
are fired together
while T
3
and T
4
are fired 180 after T
1
and T
2
. From the circuit diagram of Fig 10.3(a) it is clear
that for any load current to flow at least one thyristor from the top group (T
1
, T
3
) and one
thyristor from the bottom group (T
2
, T
4
) must conduct. It can also be argued that neither T
1
T
3
nor T
2
T
4
can conduct simultaneously. For example whenever T
3
and T
4
are in the forward
blocking state and a gate pulse is applied to them, they turn ON and at the same time a negative
voltage is applied across T
1
and T
2
commutating them immediately. Similar argument holds for
T
1
and T
2
.
For the same reason T
1
T
4
or T
2
T
3
can not conduct simultaneously. Therefore, the only
possible conduction modes when the current i
0
can flow are T
1
T
2
and T
3
T
4
. Of coarse it is
possible that at a given moment none of the thyristors conduct. This situation will typically
occur when the load current becomes zero in between the firings of T
1
T
2
and T
3
T
4
. Once the
load current becomes zero all thyristors remain off. In this mode the load current remains zero.
Consequently the converter is said to be operating in the discontinuous conduction mode.
Fig 10.3(b) shows the voltage across different devices and the dc output voltage during
each of these conduction modes. It is to be noted that whenever T
1
and T
2
conducts, the voltage
across T
3
and T
4
becomes v
i
. Therefore T
3
and T
4
can be fired only when v
i
is negative i.e, over
the negative half cycle of the input supply voltage. Similarly T
1
and T
2
can be fired only over
the positive half cycle of the input supply. The voltage across the devices when none of the
thyristors conduct depends on the off state impedance of each device. The values listed in Fig
10.3 (b) assume identical devices.
Under normal operating condition of the converter the load current may or may not
remain zero over some interval of the input voltage cycle. If i
0
is always greater than zero then
the converter is said to be operating in the continuous conduction mode. In this mode of
operation of the converter T
1
T
2
and T
3
T
4
conducts for alternate half cycle of the input supply.
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However, in the discontinuous conduction mode none of the thyristors conduct over some
portion of the input cycle. The load current remains zero during that period.
10.3.1 Operation in the continuous conduction mode
As has been explained earlier in the continuous conduction mode of operation i
0
never becomes
zero, therefore, either T
1
T
2
or T
3
T
4
conducts. Fig 10.4 shows the waveforms of different
variables in the steady state. The firing angle of the converter is . The angle is given by
1
E
sin =
2V
(10.15)
It is assumed that at t = 0

T
3
T
4
was conducting. As T
1
T
2
are fired at t = they turn on
commutating T
3
T
4
immediately. T
3
T
4
are again fired at t = + . Till this point T
1
T
2
conducts. The period of conduction of different thyristors are pictorially depicted in the second
waveform (also called the conduction diagram) of Fig 10.4.
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The dc link voltage waveform shown next follows from this conduction diagram and the
conduction table shown in Fig 10.3(b). It is observed that the emf source E is greater than the dc
link voltage till t = . Therefore, the load current i
0
continues to fall till this point. However,
as T
1
T
2
are fired at this point v
0
becomes greater than E and i
0
starts increasing through RL and
E. At t = v
0
again equals E. Depending upon the load circuit parameters i
o
reaches its
maximum at around this point and starts falling afterwards. Continuous conduction mode will be
possible only if i
0
remains greater than zero till T
3
T
4
are fired at t = + where upon the same
process repeats. The resulting i
0
waveform is shown below v
0
. The input ac current waveform i
i
is obtained from i
0
by noting that whenever T
1
T
2
conducts i
i
= i
0
and i
i
=  i
0
whenever T
3
T
4
conducts. The last waveform shows the typical voltage waveform across the thyristor T
1
. It is to
be noted that when the thyristor turns off at t = + a negative voltage is applied across it for a
duration of . The thyristor must turn off during this interval for successful operation of the
converter.
It is noted that the dc voltage waveform is periodic over half the input cycle. Therefore,
it can be expressed in a Fourier series as follows.
[
0 OAV an bn
n=1
v = V + v cos2nt + v sin2nt
]
(10.16)
Where
+
OAV 0 i
1 2 2
V = v dt = V cos
(10.17)
an 0 i
0
2 2 2 cos(2n +1) cos(2n 1)
v = v cos2nt dt = V 
2n +1 2n 1
(10.18)
bn 0 i
0
2 2 2 sin(2n +1) sin(2n 1)
v = v sin2nt dt = V 
2n +1 2n 1
(10.19)
Therefore the RMS value of the nth harmonic
2 2
OnRMS an bn
1
V = v + v
2
(10.20)
RMS value of v
0
can of course be completed directly from.
+
2
ORMS 0 i
1
V = v dt = V
(10.21)
Fourier series expression of v
0
is important because it provides a simple method of estimating
individual and total RMS harmonic current injected into the load as follows:
The impedance offered by the load at nth harmonic frequency is given by
2
n
Z = R +(2nL)
2
(10.22)
1
2
2 onRMS
onRMS OHRMS onRMS
n=1
n
V
I = ; I = I
Z
(10.23)
From (10.18) (10.23) it can be argued that in an inductive circuit I
onRMS
0 as fast as 1/n
2
. So
in practice it will be sufficient to consider only first few harmonics to obtain a reasonably
accurate estimate of I
OHRMS
form equation 10.23. This method will be useful, for example, while
calculating the required current derating of a dc motor to be used with such a converter.
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However to obtain the current rating of the device to be used it is necessary to find out a
closed form expression of i
0
. This will also help to establish the condition under which the
converter will operate in the continuous conduction mode.
To begin with we observe that the voltage waveform and hence the current waveform is
periodic over an interval . Therefore, finding out an expression for i
0
over any interval of
length will be sufficient. We choose the interval t + .
In this interval
0
0 i
di
L +Ri +E = 2V sint
dt
(10.24)
The general solution of which is given by
( ) t 

tan i
0
sin 2V
sin(t  )  i = Ie +
cos Z
(10.25)
Where,
2 2 2
i
L
Z = R + L ; tan = ; E = 2Vsin; R = Zcos
R
Now at steady state
0 0
t = t =+
i = i since i
0
is periodic over the chosen interval. Using this
boundary condition we obtain
( ) t 

tan
i
0

tan
2sin( ) s
2V
e + sin(t  ) 
i =
cos
Z
1 e
in
(10.26)
The input current i
i
is related to i
0
as follows:
i 0
i = i for t + (10.27)
i
i
=  i
0
otherwise.
Fig 10.5 shows the waveform of i
i
in relation to the v
i
waveform.
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It will be of interest to find out a Fourier series expression of i
i
. However, using actual
expression for i
i
will lead to exceedingly complex calculation. Significant simplification can be
made by replacing i
0
with its average value I
0
. This will be justified provided the load is highly
inductive and the ripple on i
0
is negligible compared to I
0.
Under this assumption the idealized
waveform of i
i
becomes a square wave with transitions at t = and t = + as shown in Fig
10.5. i
i1
is the fundamental component of this idealized i
i
.
Evidently the input current displacement factor defined as the cosine of the angle
between input voltage (v
i
) and the fundamental component of input current (i
i1
) waveforms is
cos (lagging).
It can be shown that
i1RMS 0
2 2
I =
I (10.28)
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and
iRMS 0
I = I (10.29)
Therefore the input current distortion factor =
i1RMS
iRMS
I 2 2
I
= (10.30)
The input power factor =
i i1RMS
i iRMS
VI cos Actual Power
=
Apparent Power VI
2 2
= cos
(lagging) (10.31)
Therefore, the rectifier appears as a lagging power factor load to the input ac system. Larger the
poorer is the power factor.
The input current i
i
also contain significant amount of harmonic current (3
rd
, 5
th
, etc) and
therefore appears as a harmonic source to the utility. Exact composition of the harmonic currents
can be obtained by Fourier series analysis of i
i
and is left as an exercise.
Exercise 10.2
Fill in the blank(s) with the appropriate word(s).
i) A single phase fully controlled bridge converter can operate either in the _________ or
________ conduction mode.
ii) In the continuous conduction mode at least _________ thyristors conduct at all times.
iii) In the continuous conduction mode the output voltage waveform does not depend on the
________ parameters.
iv) The minimum frequency of the output voltage harmonic in a single phase fully controlled
bridge converter is _________ the input supply frequency.
v) The input displacement factor of a single phase fully controlled bridge converter in the
continuous conduction mode is equal to the cosine of the ________ angle.
Answer: (i) continuous, discontinuous; (ii) two; (iii) load; (iv) twice; (v) firing.
2. A single phase fully controlled bridge converter operates in the continuous conduction
mode from a 230V, 50HZ single phase supply with a firing angle = 30. The load
resistance and inductances are 10 and 50mH respectively. Find out the 6
th
harmonic
load current as a percentage of the average load current.
Answer: The average dc output voltage is
i
OAV
2 2
V = V cos =179.33 Volts
Average output load current =
OAV
L
V
=17.93 Amps
R
From equation (10.18) V
a3
= 10.25 Volts
From equation (10.19) V
b3
= 35.5 Volts
2 3 2
03RMS 3 L
V = 26.126 Volts, Z = R +(62505010 ) = 94.78 ohms
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03RMS
3RMS OAV
3
V
I = = 0.2756 Amps =1.54% of I
Z
.
10.3.2 Operation in the discontinuous conduction mode
So far we have assumed that the converter operates in continuous conduction mode without
paying attention to the load condition required for it. In figure 10.4 the voltage across the R and
L component of the load is negative in the region  t + . Therefore i
0
continues to
decrease till a new pair of thyristor is fired at t = + . Now if the value of R, L and E are such
that i
0
becomes zero before t = + the conduction becomes discontinuous. Obviously then,
at the boundary between continuous and discontinuous conduction the minimum value of i
0
which occurs at
t = and t = + will be zero. Putting this condition in (10.26) we obtain the
condition for continuous conduction as.

tan
2sin( ) sin
 sin(  )  0
cos
1 e
(10.32)
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Fig 10.6 shows waveforms of different variables on the boundary between continuous and
discontinuous conduction modes and in the discontinuous conduction mode. It should be stressed
that on the boundary between continuous and discontinuous conduction modes the load current is
still continuous. Therefore, all the analysis of continuous conduction mode applies to this case as
well. However in the discontinuous conduction mode i
0
remains zero for certain interval. During
this interval none of the thyristors conduct. These intervals are shown by hatched lines in the
conduction diagram of Fig 10.6(b). In this conduction mode i
0
starts rising from zero as T
1
T
2
are
fired at t = . The load current continues to increase till t = . After this, the output
voltage v
0
falls below the emf E and i
0
decreases till t = when it becomes zero. Since the
thyristors cannot conduct current in the reverse direction i
0
remains at zero till t = + when
T
3
and T
4
are fired. During the period t + none of the thyristors conduct. During this
period v
0
attains the value E.
Performance of the rectifier such as V
OAV
, V
ORMS
, I
OAV
, I
ORMS
etc can be found in terms of ,
and . For example
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+ +
OAV 0 i i
1 1
V = v dt = 2V sint dt + 2V sin dt
(10.33)
Or
[
i
OAV
2V
V = cos  cos +sin( +  )
]
(10.34)
OAV OAV i
OAV
V  E V  2Vsin
I = =
R Zcos
(10.35)
Or [
i
OAV
2V
I = cos  cos +sin(  )
Zcos
] (10.36)
It is observed that the performance of the converter is strongly affected by the value of . The
value of in terms of the load parameters (i.e, , and Z) and can be found as follows.
In the interval t
o
o i
di
L +Ri +E = 2Vsint
dt
(10.37)
0
t =
i = 0
From which the solution of i
0
can be written as
( )
( )
{ }
t 

t
i tan

tan 0
2V
sin
i =
sin( )e  + sin(t  )
1 e
Z
cos
(10.38)
Now
0
t =
i = 0


tan
tan
sin
sin( )e  + sin(  ) = 0
1 e
cos
(10.39)
Given , and , the value of can be found by solving equation 10.39.
10.3.3 Inverter Mode of operation
The expression for average dc voltage from a single phase fully controlled converter in
continuous conduction mode was
0 i
2 2
V = Vcos
(10.40)
For < /2, V
d
> 0. Since the thyristors conducts current only in one direction I
0
> 0 always.
Therefore power flowing to the dc side P = V
0
I
0
> 0 for < /2. However for > /2, V
0
< 0.
Hence P < 0. This may be interpreted as the load side giving power back to the ac side and the
converter in this case operate as a line commutated current source inverter. So it may be
tempting to conclude that the same converter circuit may be operated as an inverter by just
increasing beyond /2. This might have been true had it been possible to maintain continuous
conduction for < /2 without making any modification to the converter or load connection. To
supply power, the load EMF source can be utilized. However the connection of this source in
Fig 10.3 is such that it can only absorb power but can not supply it. In fact, if an attempt is made
to supply power to the ac side (by making > /2) the energy stored in the load inductor will be
exhausted and the current will become discontinuous as shown in Fig 10.7 (a).
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Therefore for sustained inverter mode of operation the connection of E must be reversed as
shown in Fig 10.7(b).
Fig 10.8 (a) and (b) below shows the waveforms of the inverter operating in continuous
conduction mode and discontinuous conduction mode respectively. Analysis of the converter
remains unaltered from the rectifier mode of operation provided is defined as shown.
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Exercise 10.3
Fill in the blank(s) with the appropriate word(s)
i) In the discontinuous conduction mode the load current remains __________ for a
part of the input cycle.
ii) For the same firing angle the load voltage in the discontinuous conduction mode
is __________ compared to the continuous conduction mode of operation.
iii) The load current ripple factor in the continuous conduction mode is _______
compared to the discontinuous conduction mode.
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iv) In the inverter mode of operation electrical power flows from the ________ side
to the __________side.
v) In the continuous conduction mode if the firing angle of the converter is increased
beyond _________ degrees the converter operates in the _______ mode.
Answers: (i) zero; (ii) higher; (iii) lower; (iv) dc, ac; (v) 90, inverter.
2. A 220 V, 20A, 1500 RPM separately excited dc motor has an armature resistance of
0.75 and inductance of 50mH. The motor is supplied from a 230V, 50Hz, single phase
supply through a fully controlled bridge converter. Find the no load speed of the motor
and the speed of the motor at the boundary between continuous and discontinuous modes
when = 25.
Answer: At no load the average motor torque and hence the average motor armature current is
zero. However, since a converter carries only unidirectional current, zero average armature
current implies that the armature current is zero at all time. From Fig 10.6(b) this situation can
occur only when = /2, i.e the back emf is equal to the peak of the supply voltage. Therefore,
b b
no load 1500
E = 2 230 V = 325.27 V, Under rated condition E = 205 V
no load
325.27
N = 1500 = 2380 RPM
205
At the boundary between continuous and discontinuous conduction modes from equation 10.32
/tan
/tan
1+e
sin = cossin(  )
1 e
From the given data = 87.27, = 25
sin = 0.5632
b i
E = 2V sin =183.18 Volts
183.18
Motor speed N = 1500 =1340 RPM
205
.
Summary
Single phase fully controlled converters are obtained by replacing the diodes of an
uncontrolled converter with thyristors.
In a fully controlled converter the output voltage can be controlled by controlling the
firing delay angle () of the thyristors.
Single phase fully controlled half wave converters always operate in the discontinuous
conduction mode.
Half wave controlled converters usually have poorer output voltage form factor compared
to uncontrolled converter.
Single phase fully controlled bridge converters are extensively used for small dc motor
drives.
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Depending on the load condition and the firing angle a fully controlled bridge converter
can operate either in the continuous conduction mode or in the discontinuous conduction
mode.
In the continuous conduction mode the load voltage depends only on the firing angle and
not on load parameters.
In the discontinuous conduction mode the output voltage decreases with increasing load
current. However the output voltage is always greater than that in the continuous
conduction mode for the same firing angle.
The fully controlled bridge converter can operate as an inverter provided (i)
2
> , (ii) a
dc power source of suitable polarity exists on the load side.
References
1) Power Electronics P.C.Sen; Tata McGrawHill 1995
2) Power Electronics; Circuits, Devices and Applications, Second Edition, Muhammad
H.Rashid; PrenticeHall of India; 1994.
3) Power Electronics; Converters, Applications and Design Third Edition, Mohan,
Undeland, Robbins, John Wileys and Sons Inc, 2003.
Practice Problems and Answers
Q1. Is it possible to operate a single phase fully controlled half wave converter in the
inverting mode? Explain.
Q2. A 220V, 20A 1500 RPM separately excited dc motor has an armature resistance of 0.75
and inductance of 50 mH. The motor is supplied from a single phase fully controlled
converter operating from a 230 V, 50 Hz, single phase supply with a firing angle of =
30. At what speed the motor will supply full load torque. Will the conduction be
continuous under this condition?
Q3. The speed of the dc motor in question Q2 is controlled by varying the firing angle of the
converter while the load torque is maintained constant at the rated value. Find the
power factor of the converter as a function of the motor speed. Assume continuous
conduction and ripple free armature current.
Q4. Find the load torque at which the dc motor of Q2 will operate at 2000 RPM with the field
current and remaining same.
Q5. A separately excited dc motor is being braked by a single phase fully controlled bridge
converter operating in the inverter mode as shown in Fig 10.7 (b). Explain what will
happen if a commutation failure occurs in any one of the thyristors.
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Answers
1. As explained in section 10.3.3, the load circuit must contain a voltage source of proper
polarity. Such a load circuit and the associated waveforms are shown in the figure next.
Figure shows that it is indeed possible for the half wave converter to operate in the inverting
mode for some values of the firing angle. However, care should be taken such that i
0
becomes
zero before v
i
exceeds E in the negative half cycle. Otherwise i
0
will start increasing again and
the thyristor T will fail to commutate.
2. For the machine to deliver full load torque with rated field the armature current should be
20 Amps.
Assuming continuous conduction
o
0
2 2 230
v = cos30 =179.33
volts.
For 20 Amps armature current to flow the back emf will be
E
b
= V
a
I
a
R
a
= 179.33 20 0.75 = 164.33 volts
b
i
E
sin = = 0.505
2V
.
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For the given machine,
o a
a
L
tan = = 20.944, = 87.266
R
.
Now from equation (10.32)
/tan
2sin( )
 sin( ) =11.2369.
1 e
and
sin
=10.589
cos
the conduction is continuous.
At 1500 RPM the back emf is 220 20 0.75 = 205 volts.
The speed at which the machine delivers rated torques
is
r
164.33
N = 1500 =1202 RPM
205
.
3. To maintain constant load torque equal to the rated value the armature voltage should be
a a a b
rated rated
rated
N
V = r I + E
N
N
= 0.75 20 + 205 = 0.137 N + 15 V
1500
In a fully controlled converter operating in the continuous conduction mode
a i
2 2
V = V cos = 207.073 cos
 4
cos = 6.616 10 N+0.0724
Now the power factor from equation 10.31 is
 4
2 2
pf = cos = 5.9565 10 N + 0.0652
This gives the input power factor as a function of speed.
4. At 2000 RPM,
b
2000
E = 205 = 273.33 volts
1500
o o b
i
E
sin = = 0.84, = 87.266 , = 30
2V
From equation 10.32 it can be shown that the conduction will be discontinuous.
Now from equation 10.39
( ) ( ) ( )

tan
sin sin
+sin  sin  + e =  
cos cos
or [ ] ( )
.0477(  ) o
e  sin =17.61 57.266 +  17.61+.8412
( )
.0477(  ) o
18.4515 e  sin =17.61 + 57.266 
Solving which 140
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from equation 10.36
[ ]
i
oav
2V
I = = 2.676 Amps cos  cos +sin(  )
Zcos
the load torque should be
2.676
100 =13.38%
20
of the full load torque.
5. Referring to Fig 10.8 (a) let there be a commutation failure of T
1
at t = . In that case
the conduction mode will be T
3
T
2
instead of T
1
T
2
and v
0
will be zero during that period.
As a result average value of V
0
will be less negative and the average armature current
will increase. However the converter will continue to operate in the inverter mode and
the motor will be braked.
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Module
2
AC to DC Converters
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Lesson
11
Single Phase Half
Controlled Bridge
Converter
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Operation and analysis of single phase half controlled converters
Instructional Objectives
On completion the student will be able to
Draw different topologies of single phase half controlled converter.
Identify the design implications of each topology.
Construct the conduction table and thereby draw the waveforms of different system
variables in the continuous conduction mode of operation of the converter.
Analyze the operation of the converter in the continuous conduction mode to find out the
average and RMS values of different system variables.
Find out an analytical condition for continuous conduction relating the load parameters
with the firing angle.
Analyze the operation of the converter in the discontinuous conduction mode of
operation.
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11.1 Introduction
Single phase fully controlled bridge converters are widely used in many industrial applications.
They can supply unidirectional current with both positive and negative voltage polarity. Thus
they can operate either as a controlled rectifier or an inverter. However, many of the industrial
application do not utilize the inverter mode operation capability of the fully controlled converter.
In such situations a fully controlled converter with four thyristors and their associated control
and gate drive circuit is definitely a more complex and expensive proposition. Single phase fully
controlled converters have other disadvantages as well such as relatively poor output voltage
(and current for lightly inductive load) form factor and input power factor.
The inverter mode of operation of a single phase fully controlled converter is made
possible by the forward voltage blocking capability of the thyristors which allows the output
voltage to go negative. The disadvantages of the single phase fully controlled converter are also
related to the same capability. In order to improve the output voltage and current form factor the
negative excursion of the output voltage may be prevented by connecting a diode across the
output as shown in Fig 11.1(a). Here as the output voltage tries to go negative the diode across
the load becomes forward bias and clamp the load voltage to zero. Of course this circuit will not
be able to operate in the inverter mode. The complexity of the circuit is not reduced, however.
For that, two of the thyristors of a single phase fully controlled converter has to be replaced by
two diodes as shown in Fig 11.1 (b) and (c). The resulting converters are called single phase half
controlled converters. As in the case of fully controlled converters, the devices T
1
and D
2
conducts in the positive input voltage half cycle after T
1
is turned on. As the input voltage
passes through negative going zero crossing D
4
comes into conduction commutating D
2
in Fig
11.1 (b) or T
1
in Fig 11.1 (c). The load voltage is thus clamped to zero until T
3
is fired in the
negative half cycle. As far as the input and output behavior of the circuit is concerned the
circuits in Fig 11.1 (b) and (c) are identical although the device designs differs. In Fig 11.1 (c)
the diodes carry current for a considerably longer duration than the thyristors. However, in Fig
11.1 (b) both the thyristors and the diodes carry current for half the input cycle. In this lesson the
operating principle and characteristics of a single phase half controlled converter will be
presented with reference to the circuit in Fig 11.1 (b).
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11.2 Operating principle of a single phase half controlled bridge
converter
With reference of Fig 11.1 (b), it can be stated that for any load current to flow one device from
the top group (T
1
or T
3
) and one device from the bottom group must conduct. However, T
1
T
3
or
D
2
D
4
cannot conduct simultaneously. On the other hand T
1
D
4
and T
3
D
2
conducts
simultaneously whenever T
1
or T
3
are on and the output voltage tends to go negative. Therefore,
there are four operating modes of this converter when current flows through the load. Of course
it is always possible that none of the four devices conduct. The load current during such periods
will be zero. The operating modes of this converter and the voltage across different devices
during these operating modes are shown in the conduction table of Fig 11.2. This table has been
prepared with reference to Fig 11.1 (b).
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It is observed that whenever D
2
conducts the voltage across D
4
is v
i
and whenever D
4
conducts
the voltage across D
2
is v
i
. Since diodes can block only negative voltage it can be concluded that
D
2
and D
4
conducts in the positive and the negative half cycle of the input supply respectively.
Similar conclusions can be drawn regarding the conduction of T
1
and T
3
. The operation of the
converter can be explained as follows when T
1
is fired in the positive half cycle of the input
voltage. Load current flows through T
1
and D
2
. If at the negative going zero crossing of the
input voltage load current is still positive it commutates from D
2
to D
4
and the load voltage
becomes zero. If the load current further continuous till T
3
is fired current commutates from T
1
to T
3
. This mode of conduction when the load current always remains above zero is called the
continuous conduction mode. Otherwise the mode of conduction becomes discontinuous.
Exercise 11.1
Fill in the blanks(s) with the appropriate word(s)
i. In a half controlled converter two ___________________ of a fully controlled converter
are replaced by two ___________________.
ii. Depending on the positions of the ___________________ the half controlled converter
can have ___________________ different circuit topologies.
iii. The input/output waveforms of the two different circuit topologies of a half controlled
converter are ___________________ while the device ratings are
___________________.
iv. A half controlled converter has better output voltage ___________________ compared to
a fully controlled converter.
v. A half controlled converter has improved input ___________________ compared to a
fully controlled converter.
Answer: (i) thyristors, diodes; (ii) diodes, two; (iii) same, different; (iv) form factor; (v) power
factor.
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2. Find out an expression of the ration of the thyristor to diode RMS current ratings in the single
phase half controlled converter topologies of Fig. 11.1(b) & (c). Assume ripple free continuous
output current.
Answer
In the first conduction diagram the diodes and the thyristors conduct for equal periods, since the
load current is constant. The ration of the thyristors to the diode RMS current ratings will be
unity for the circuit of Fig 11.1 (b).
From the second conduction diagram the thyristors conduct for  radians while the diodes
conduct for + radians. Since the load current is constant.
Thyristor RMS current rating 1 /
Diode RMS current rating 1 /
=
+
in this case
11.2.1 Single phase half controlled converter in the continuous
conduction mode
From the conduction table and the discussion in the previous section it can be concluded that the
diode D
2
and D
4
conducts for the positive and negative half cycle of the input voltage waveform
respectively. On the other hand T
1
starts conduction when it is fired in the positive half cycle of
the input voltage waveform and continuous conduction till T
3
is fired in the negative half cycle.
Fig. 11.3 shows the circuit diagram and the waveforms of a single phase half controlled
converter supplying an R L E load.
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Referring to Fig 11.3 (b) T
1
D
2
starts conduction at t = . Output voltage during this period
becomes equal to v
i
. At t = as v
i
tends to go negative D
4
is forward biased and the load
current commutates from D
2
to D
4
and freewheels through D
4
and T
1
. The output voltage
remains clamped to zero till T
3
is fired at t = + . The T
3
D
4
conduction mode continues upto
t = 2. Where upon load current again free wheels through T
3
and D
2
while the load voltage is
clamped to zero.
From the discussion in the previous paragraph it can be concluded that the output voltage (hence
the output current) is periodic over half the input cycle. Hence
i
oav o i
o
2V 1 1
V = v dt = 2V sin t dt = (1+cos)
(11.1)
oav i
ov
V  E 2V
I = = (1+cos  sin)
R R
(11.2)
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Clearly in addition to the average component, the output voltage (and current) contains a large
number of harmonic components. The minimum harmonic voltage frequency is twice the input
supply frequency. Magnitude of the harmonic voltages can be found by Fourier series analysis of
the load voltage and is left as an exercise.
The Fourier series representation of the load current can be obtained from the load voltage by
applying superposition principle in the same way as in the case of a fully controlled converter.
However, the closed form expression of i
o
can be found as explained next.
In the period t
o
o i
di
L + Ri + E = 2V sin t
dt
(11.3)
(t)

tan i
o 1
2V sin
i = I e + sin(t  ) 
Z c
os
(11.4)
Where
2 2 2
i
E L
sin = ; Z = R + L ; tan =
R 2V
i
o 1
2V sin
i = I + sin( ) 
Z c
os
(11.5)
i
o 1
2V (  )
i = I  + sin
tan Z co
sin
s
(11.6)
In the period t +
o
o
di
L +Ri +E =
dt
0 (11.7)
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(t) (t)
 
tan tan i
o o
2V sin
i = i e  1 e
Z cos
(11.8)
(t) (t)
 
tan tan i
o 1
2V sin
i = I e + sin e 
Z c
os
(11.9)
 
tan tan i
o 1
+
2V sin
i = I e + sin e 
Z c os
(11.10)
Due to periodic operation
o o
+
i = i

tan
i
1

tan
2V sin( ) + sin e
I =
Z
1 e
(11.11)
For t
(t)

tan

tan i
o

tan
2V e sin
i = sin( ) +sine +sin(t  ) 
Z c
1 e
os
(11.12)
For t +
(t)

(t)
tan
 
tan tan i
o

tan
2V e sin
i = sin( ) +sine +sin e 
Z c
1 e
os
(11.13)
The input current i
i
is given by
i
i
= i
0
for t
i
i
=  i
0
for + t 2
i
i
= 0 otherwise (11.14)
However, it will be very difficult to find out the characteristic parameters of i
i
using equation
11.14 since the expression of i
0
is considerably complex. Considerable simplification can
however be obtained if the actual i
i
waveform is replaced by a quasisquare wave current
waveform with an amplitude of I
oav
as shown in Fig 11.5.
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From Fig 11.5
iRMS oav
I = 1 / I (11.15)
The displacement factor = cos /2 (11.16)
i
i i1 o oav OAV
2V
V I cos = V I = (1+cos)I
2
(11.17)
i1 OAV
2 2
I = I cos
2
(11.18)
Distortion factor =
i1
iRMS
I 2
= 2 cos
2
I (  )
(11.19)
Power factor = displacement factor distortion factor
=
2
(1+cos)
(  )
(11.20)
Exercise 11.2
Fill in the blank(s) with the appropriate word(s).
i. In a half controlled converter the output voltage can not become ___________________
and hence it can not operate in the ___________________ mode.
ii. For the same firing angle and input voltage the half controlled converter gives
___________________ output voltage form factor compared to a fully controlled
converter.
iii. For ripplefree continuous output current the input current displacement factor of a half
controlled converter is given by ___________________.
iv. For the same supply and load parameters the output current form factor of a half
controlled converter is ___________________ compared to a fully controlled converter.
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v. The free wheeling operating mode of a half controlled converter helps to make the output
current ___________________.
Answer: (i) negative, inverter; (ii) lower; (iii) cos
2
In order to increase N
no load
by 30%
f
should be reduced by 23%. Therefore the applied field
voltage must by 23%.
Now by (11.1)
( ) ( )
f f
1 cos
V V 0
2
+
= =
1 cos 1 cos
1 0
2 2
+
.23 = =
o
57.4 =
11.2.2 Single phase half controlled converter in the discontinuous
conduction mode.
So far we have discussed the operating characteristics of a single phase half controlled converter
in the continuous conduction mode without identifying the condition required to achieve it. Such
a condition exists however and can be found by carefully examining the way this converter
works.
Referring to Fig 11.3 (b), when T
1
is fired at t = the output voltage (instantaneous value) is
larger than the back emf. Therefore, the load current increases till v
o
becomes equal to E again at
t = . There, onwards the load current starts decreasing. Now if i
o
becomes zero before T
3
is fired at t = + the conduction becomes discontinuous. So clearly the condition for
continuous conduction will be
o
t
i = 0 (11.21)
Which in conjunction with the equation (11.12) gives

tan

tan
sin( ) + sin e s
 sin( )
cos
1 e
in
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or
 
tan tan

tan
sin( )e + sin e si
cos
1 e
n
(11.22)
If the condition in Eq. 11.22 is violated the conduction will become discontinuous. Clearly, two
possibilities exist. In the first case the load current becomes zero before t = . In the second
case i
o
continuous beyond t = but becomes zero before t = + . In both cases however, i
o
starts from zero at t = .
Fig. 11.6 shows the wave forms in these two cases.
Of these two cases the second one will be analyzed in detail here. The analysis of the first case
is left as an exercise.
For this case
v
o
= v
i
for t
v
o
= 0 for t (11.23)
v
o
= E for t +
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Therefore V
OAV
=
+
o
1
v dt
=
+
i i
1
2v sint dt + 2v sin dt
=
[
i
2V
1+cos +( +  )sin
]
(11.24)
[
OAV i
OAV
V  E 2V
I = = 1+cos +(  )sin
R Z cos
] (11.25)
+
2
ORMS o
1
V = v dt
1
+
2
2 2 2 2
i i
1
= 2v sin t dt + 2v sin dt
1
2
2 i
2V  1
= +( +  ) sin + sin 2
2 4
(11.26)
However I
ORMS
cannot be computed directly from V
ORMS
. For this the closed form expression for
i
o
has to be obtained. This will also help to find out an expression for the conduction angle .
For t
o
i o
di
2V sin t = Ri +L +E
dt
(11.27)
The general solution is given by
(t)

tan i
o o
2V 2V sin
i = I e + sin(t  ) 
Z Z
i
cos
(11.28)
Where
2 2 2
i
L
Z = R + L ; tan = ; E = 2V sin
R
At t = , i
o
= 0
i
o
2V sin
I = + sin( )
Z cos
(11.29)
t

tan i
o
2V sin sin
i = +sin( ) e + sin(t  ) 
Z cos cos
(11.30)
i
o
at t = =

tan i
2V sin sin
+sin( ) e + sin 
Z cos cos
(11.31)
For t
o
o
di
O = Ri +L +E
dt
(11.32)
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t

tan i
o 1
2V sin
i = I e 
Z cos
(11.33)
i
o 1
t =
2V sin
i = I 
Z cos
=

tan i
2V sin sin
+sin( ) e + sin 
Z cos cos
(11.34)

tan i
1
2V sin
I +sin( ) e + sin
Z cos
=
(11.35)
t t
 
tan tan i
o
2V sin sin
i = +sin( ) e + sine 
Z cos cos
(11.36)
Equations (11.30) and (11.36) gives closed from expression of i
o
in this conduction mode. To
find out we note that at t = , i
o
= 0. So from equation (11.36)
 
tan tan
sin sin
+sin( ) e + sin e  =
cos cos
0 (11.37)
or
tan tan tan tan
sin sin
e = sin e +sin( ) e + e
cos cos
(11.38)
Given the values of , and the value of can be obtained from equation 11.38.
Exercise 11.3 (After section 11.2.2)
Fill in the blank(s) with the appropriate word(s).
i. At the boundary between continuous and discontinuous conduction the value of the
output current at t = is ___________________.
ii. The output voltage and current waveform of a single phase fully controlled and half
controlled converter will be same provided the extinction angle is less than
___________________.
iii. For the same value of the firing angle the average output voltage of a single phase half
controlled converter is ___________________ in the discontinuous conduction mode
compared to the continuous conduction mode.
iv. Single phase half controlled converters are most suitable for loads requiring
___________________ voltage and current.
Answer: (i) zero; (ii) ; (iii) higher; (iv) unidirectional.
2. A single phase half controlled converter charges a 48v 50Ah battery from a 50v, 50Hz single
phase supply through a 50mH line inductor. The battery has on interval resistance of 0.1. The
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firing angle of the converter is adjusted such that the battery is charged at C/5 rate when it is
fully discharged at 42 volts. Find out whether the conduction will be continuous or discontinuous
at this condition. Up to what battery voltage will the conduction remain continuous? If the
charging current of the battery is to become zero when it is fully charged at 52 volts what should
be the value of the firing angle.
Answer: From the given data assuming continuous conduction the output voltage of the
converter to charge the battery at C/5 (10 Amps) rate will be
o b b
V E I r 42 0.1 10 43volts = + = + =
o
24.43 =
1 o 3
L
tan 89.63 , tan 157.08, sin 0.99998 cos 6.3 10
R
= = = = =
Putting these values in equation (11.22) one finds that the conduction will be continuous.
The conduction will remain continuous till
( )
tan
tan
tan
i
1
cos sin e sin 2 e
E
2
sin
2v
1 e
+
= =
From the given value this gives.
E 2 50 0.606 42.8V = =
At E = 52 volts i
o
is zero. Therefore
i
2V sin E 52 = =
o o
sin52
= 180 132.66
2 50
=
References
[1] Power Electronics; P.C. Sen; Tata McGraw Hill Publishing Company Limited 1995.
[2] Power Electronics, circuits, devices and applications; Second Edition; Muhammad H.
Rashid; Prentice Hall of India; 1994.
[3] Power Electronics, converters, applications and design; Third Edition; Mohan,
Undeland, Robbins; John Wiley and Sons Inc., 2003.
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Lesson Summary
Single phase half controlled converters are obtained from fully controlled converters by
replacing two thyristors by two diodes.
Two thyristors of one phase leg or one group (top or bottom) can be replaced resulting in
two different topologies of the half controlled converter. From the operational point of
view these two topologies are identical.
In a half controlled converter the output voltage does not become negative and hence the
converter cannot operate in the inverter mode.
For the same firing angle and input voltage the half controlled converter in the continuous
conduction mode gives higher output voltage compared to a fully controlled converter.
For the same input voltage, firing angle and load parameters the half controlled converter
has better output voltage and current form factor compared to a fully controlled
converter.
For the same firing angle and load current the half controlled converter in the continuous
conduction mode has better input power factor compared to a fully controlled converter.
Half controlled converters are most favored in applications requiring unidirectional
output voltage and current.
Practice Problems and Answers
Q1. The thyristor T
3
of Fig 1.1(b) fails to turn on at the desired instant. Describe how this
circuit will work in the presence of the fault.
Q2. A single phase half controlled converter is used to boost the no load speed of a
separately excited dc machine by weakening its field supply. At = 0 the half
controlled converter produces the rated field voltage. If the field inductance is large enough
to make the field current almost ripple face what will be the input power factor when the dc
motor no load speed is bossed to 150%?
Q3. A single phase half controlled converter supplies a 220V, 1500rpm, 20A dc motor from a
230V 50HZ single phase supply. The motor has a armature resistance of 1.0 and
inductance of 50mH. What will be the operating modes and torques for = 30; and
speed of 1400 RPM.
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Answer to practice problems
Figure above explains the operation of the circuit following the fault. T
1
is tired at t = and the
load current commutates from T
3
to T
1
. The conduction periods T
1
D
2
& T
1
D
4
commences as
usual. However at t = + when T
3
is fired it fails to turn ON and as a consequences T
1
does
not commutate. Now if the load is highly inductive T
1
D
4
will continue to conduct till t = 2
and the load voltage will be clamped to zero during this period.
However, since T
1
does not stop conduction fining angle control on it is lost after words. Hence
T
1
D
2
conduction period starts right after t = 2 instead of at t = 2 + . Thus the full positive
half cycle of supply voltage is applied across the load followed by a entire half cycle of zero
voltage. Thus the load voltage becomes a half wave rectified sine wave and voltage control
through fining angle is last. This is the effect of the fault.
[Note: This phenomenon is known as half cycle brusting. It can be easily verified that this
possibility does not existion the circuit shown in Fig 11.1 (c)]
2. For a separately excited dc motor
NO load
f f
1 1
V
f
Vf rated
V for boosting no load speed by 150%
1.5
=
but
f
Vf 1 cos 1
V rated 2 1.5
+
= =
o
= 70.53
using equation 11.20 the power factor will be 0.77.
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3. From the given data, tan =
o
L
15.7, = 86.36
R
=
i
E 14 220 20 1.0
sin = 0.578
15 2V 2 230
= =
= =
6.53
Motor torque will be 100 32.67% of full load torque.
20
=
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Module
2
AC to DC Converters
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Lesson
12
Single Phase Uncontrolled
Rectifier
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Operation and Analysis of three phase uncontrolled rectifier.
Instructional Objectives
On completion the student will be able to
Draw the conduction table and waveforms of a three phase half wave uncontrolled
converter supplying resistive and resistive inductive loads.
Calculate the average and RMS values of the input / output current and voltage
waveforms of a three phase uncontrolled half wave converter.
Analyze the operation of a three phase full wave uncontrolled converter to find out the
input / output current and voltage waveforms along with their RMS and Average values.
Find out the harmonic components in the input / output voltage and current waveforms of
a three phase uncontrolled full wave converter.
Analyze the operation of a three phase full wave uncontrolled converter supplying a
Capacitive Resistive load.
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12.1 Introduction
Single phase rectifiers, as already discussed, are extensively used in low power applications
particularly for power supplies to electronic circuits. They are also found useful for supplying
small dc loads rarely exceeding 5 KW. Above this power level three phase ac dc power
supplies are usually employed. Single phase ac dc converters have several disadvantages such
as
Large output voltage and current form factor.
Large low frequency harmonic ripple current causing harmonic power loss and reduced
efficiency.
Very large filter capacitor for obtaining smooth output dc voltage.
Low frequency harmonic current is injected in the input ac line which is difficult to filter.
The situation becomes worse with capacitive loads.
Many of these disadvantages are mitigated to a large extent by using three phase ac dc
converters. In a way it is also natural that bulk loads are supplied by three phase converters since
bulk electrical power is always transmitted and distributed in three phases and high power should
load three phases symmetrically. Polyphase rectifiers produce less ripple output voltage and
current compared to single phase rectifiers. The efficiency of polyphase rectifier is also higher
while the associated equipments are smaller.
A three phase supply gives the choice of a number of circuits. These can be placed in one of two
groups according to whether three or six diodes are used. These topologies will be analyzed in
detail in this section.
12.2 Operating principle of three phase half wave uncontrolled
rectifier
The half wave uncontrolled converter is the simplest of all three phase rectifier
topologies. Although not much used in practice it does provide useful insight into the operation
of three phase converters. Fig. 12.1 shows the circuit diagram, conduction table and wave forms
of a three phase half wave uncontrolled converter supplying a resistive inductive load.
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For simplicity the load current (i
o
) has been assumed to be ripple free. As shown in Fig.
12.1 (a), in a three phase half wave uncontrolled converter the anode of a diode is connected to
each phase voltage source. The cathodes of all three diodes are connected together to form the
positive load terminal. The negative terminal of the load is connected to the supply neutral.
Fig. 12.1 (b) shows the conduction table of the converter. It should be noted that for the
type of load chosen the converter always operates in the continuous conduction mode. The
conduction diagram for the diodes (as shown in Fig. 12.1 (c) second waveform) can be drawn
easily from the conduction diagram. Since the diodes can block only negative voltage it follows
from the conduction table that a phase diode conducts only when that phase voltage is maximum
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of the three. (In signal electronics the circuit of Fig. 12.1 (a) is also known as the maximum
value circuit). Once the conduction diagram is drawn other waveforms of Fig. 12.1 (c) are
easily obtained from the supply voltage waveforms in conjunction with the conduction table.
The phase current waveforms of Fig. 12.1 (c) deserve special mention. All of them have a
dc component which flows through the ac source. This may cause dc saturation in the ac side
transformer. This is one reason for which the converter configuration is not preferred very much
in practice.
From the waveforms of Fig. 12.1 (c)
5/6
OAV i
/6
3
V = 2V sin t d(t)
2
i
3 6
=
2
V (12.1)
1
2 5/6
2 2
ORMS i
/6
3
V = 2V sin t d(t)
2
1
2
i
3 3
= 1 V
4
+
(12.2)
The output voltage form factor =
ORMS
OAV
V
=1.01
V
(12.3)
OAV
O
av
V
I =
R
,
O
i RMS a RMS b RMS c RMS
I
I = I = I = I =
3
(12.4)
Input power factor =
i O
O O
av AV
O
i i RMS
i
3 6
V I
V I
3
2
= =
I
3V I 2
3V
3
(12.5)
The harmonics present in v
o
and i
i
can be found by Fourier series analysis of the
corresponding waveforms of Fig. 12.1 (c) and is left as an exercise.
Exercise 12.1
Fill in the blank(s) with the appropriate word(s).
i) Three phase half wave uncontrolled rectifier uses ________ diodes.
ii) Three phase half wave uncontrolled rectifier requires ________ phase ______ wire
power supply.
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iii) In a three phase half wave uncontrolled rectifier each diode conduct for _________
radians.
iv) The minimum frequency of the output voltage ripple in a three phase half wave
uncontrolled rectifier is _________ times the input voltage frequency.
v) The input line current of a three phase half wave uncontrolled rectifier contain ________
component.
Answers: (i) three; (ii) three, four; (iii) 2/3; (iv) three; (v) dc.
2. Assuming ripple free output current, find out the, displacement factor, distortion factor
and power factor of a three phase half wave rectifier supplying an R L load.
With reference to Fig 12.1 the expression for phase current i
a
can be written as
a d
5
i = I t
6 6
i
a
= 0 otherwise.
Fundamental component of i
a
can be written as
a1 a1
i = 2 I sin(t + )
where
2
a1 1 1
2 I = A +B
2
and
1 1
1
A
= tan
B
2
1 a
0
1
A = i cost dt
2
1 a
0
1
B = i sint dt
5
6
1 d
6
1
A = I cost dt = 0
5
6
1 d
6
1 3
B = I sint dt = I
d
a1 1 d
3
2I = B = I
d
a1
I 3
I =
2
= 0 Displacement factor = cos = 1.
R.M.S value of i
a
= I
a
=
d
I
3
Distortion factor =
a1
a
I 3
=
I 2
Power Factor = Disp. Factor Dist. Factor =
3
2
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12.3 Three phase full wave uncontrolled converter
As has been explained earlier three phase half wave converter suffers from several
disadvantages. Chief among them are dc component in the input ac current, requirement of
neutral connection and comparatively lower output voltage. In addition the input and output
waveforms contain lower order harmonics which require heavy filtering.
Most of these disadvantages can be mitigated by using a three phase full wave bridge rectifier.
This is probably the most extensively used rectifier topology from low (>5 KW) to moderately
high power (> 100 KW) applications. In this section the operation of a three phase full wave
uncontrolled bridge rectifier with two different types of loads namely the R L E type load and
the capacitive load will be described.
12.3.1 Operation of a 3 phase full wave uncontrolled bridge
rectifier supplying an R L E load
This type of load may represent a dc motor or a battery. Usually for driving these loads a
variable output voltage is required. This requirement has to be met by using a variable ac source
(e.g a 3 phase variable) since the average output voltage of an uncontrolled rectifier is constant
for a given ac voltage.
It will also be assumed in the following analysis that the load side inductance is large enough to
keep the load current continuous. The relevant condition for continuous conduction will be
derived but analysis of discontinuous conduction mode will not be attempted. Compared to
single phase converters the cases of discontinuous conduction in 3 phase bridge converter are
negligible.
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Since the load current is assumed to be continuous at least one diode from the top group
(D
1
, D
3
and D
5
) and one diode from the bottom group (D
2
, D
4
and D
6
) must conduct at all time.
It can be easily verified that only one diode from each group (either top or bottom) conducts at a
time and two diodes from the same phase leg never conducts simultaneously. Thus the converter
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has six different diode conduction modes. These are D
1
D
2
, D
2
D
3
, D
3
D
4
, D
4
D
5
, D
5
D
6
and D
6
D
1
.
Each conduction mode lasts for /3 rad and each diode conducts for 120.
Fig. 12.2 (b) shows voltages across different diodes and the output voltage in each of
these conduction modes. The time interval during which a particular conduction mode will be
effective can be ascertained from this table. For example the D
1
D
2
conduction mode will occur
when the voltage across all other diodes (i.e. v
ba
, v
ca
and v
cb
) are negative. This implies that
D
1
D
2
conducts in the interval 0 t /3 as shown in Fig. 12.2 (c). The diodes have been
numbered such that the conduction sequence is D
1
D
2
D
3
D
4
D
5
D
6
D
1
.
When a diode stops conduction its current is commutated to another diode in the same group (top
or bottom). This way the sequence of conduction modes become, D
1
D
2
D
2
D
3
D
3
D
4
D
4
D
5
D
5
D
6
D
6
D
1
D
1
D
2
. The conduction diagram in Fig. 12.2 (c) is constructed
accordingly.
The output dc voltage can be constructed from this conduction diagram using appropriate
line voltage segments as specified in the conduction table.
The input ac line currents can be constructed from the conduction diagram and the output
current. For example
i
a
= i
o
for 0 t /3 and 5/3 t 2
i
a
=  i
o
for 2/3 t 4/3
i
a
= 0 otherwise. (12.6)
The line current wave forms and their fundamental components are shown in Fig. 12.2 (c).
It is clear from Fig 12.2 (c) that the dc voltage output is periodic over one sixth of the input ac
cycle.
For /3 t 2/3
o L
v = 2V sin t (12.7)
2/3
OAV L L
/3
3
V = 2V sin t dt = V
3 2
(12.8)
2/3
2 2
ORMS L
/3
3
V = 2V sin t dt
L
3 3
= 1 V
2
+
(12.9)
OAV
i RMS OAV OAV
V 2
I = I ; I =
3 R
E
(12.10)
I
i1
RMS can be found as follows
L i 1 OAV OAV
3 V I = V I (12.11)
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Since input displacement factor is unity
OAV
i1 OAV OAV
L
V 6
I = I = I
3V
(12.12)
Power factor = distortion factor =
i1
i RMS
I 3
=
I
(12.13)
A closed form expression for i
o
can be found as follows
for /3 t 2/3
o
o o L
di
L +Ri +E = v = 2V sint
dt
(12.14)
The general solution is given by
t  /3

tan L
o 1
2V sin
i = I e + sin(t  ) 
Z c os
(12.15)
Where
2 2
L
L E
tan = ; sin = ; Z = R + L
R 2V
2
Now since the current waveform is periodic over one sixth of the input ac cycle
o o
2
i t = = i t =
3 3
(12.16)

3tan L L
1 1
2V 2V sin 2 sin
I + sin   = I e + sin  
Z 3 cos Z 3 co
s
(12.17)
L
1

3tan
2V sin
I =
Z
1 e
(12.18)
( )
t  /3

3tan L
o

3tan
2V sin sin
i = e +sin t  
Z c
1 e
os
(12.19)
Exercise 12.2
Fill in the blank(s) with the appropriate word(s).
i) Three phase full wave uncontrolled rectifier uses _________ diodes.
ii) Three phase full wave uncontrolled rectifier does not require ________ wire connection.
iii) In a three phase full wave uncontrolled rectifier each diode conducts for _______ radians.
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iv) The minimum frequency of the output voltage ripple in a three phase full wave rectifier is
_________ times the input voltage frequency.
v) The input ac line current of a three phase full wave uncontrolled rectifiers supplying an R
L E load contain only ________ harmonics but no ________ harmonic or
__________ component.
vi) A three phase full wave uncontrolled rectifier supplying an R L E load normally
operates in the ________ conduction mode.
Answers: (i) six; (ii) neutral; (iii) 2/3; (iv) six; (v) odd, tripler, dc; (vi) continuous.
2. A 220 V, 1500 rpm 20 A separately excited dc motor has armature resistance of 1 and
negligible armature inductance. The motor is supplied from a three phase full wave
uncontrolled rectifier connected to a 220 V, 3 phase, 50 Hz supply through a /Y
transformer. Find out the transformer turns ratio so that the converter applies rated
voltage to the motor. What is the maximum torque as a percentage of the rated torque the
motor will be able to supply without over heating. Assume ideal transformer and
continuous conduction.
Answer: Average output voltage of the converter is
0 L
3 2
V = V = 220V
V
L
= 163 Volts. This is the line voltage of the secondary side of the transformer.
The secondary is star connected. So
Secondary phase voltage =
163
= 94 volts
3
.
Primary side is delta connected. So
Primary phase voltage = 220 V.
The required turns ratio =
220
2.34:1
94
=
Output voltage can be written as
0 0 h
n=1
v = V + v
n
Where v
hn
= nth harmonic voltage magnitude.
0 hn
0
n=1
V  E v
i = +
r r
Where E = back emf and r = armature resistance
0RMS
2 2
2 0 hn
n=1
V  E V
I = +
r r
2
2 2
2 0AV 0AV hn
0AV 2 2
n=1
V V V
= I  + +
r r r
2 2
2 0AV 0RMS
0AV 2 2
V V
= I  +
r r
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( )
2
2 2 0AV
0AV 2
V
= I + FF 1
r
To prevent over heating I
0RMS
= 20 A
For the given converter
2
2 0RMS
0AV
V
FF = =1.00176
V
( )
2
2 2
0AV
220
20 = I + 1.001761
1
2
0AV
I = 314.816 I
0AV
= 17.743 Amps.
In a separately excited dc machine T
e
I
0AV
Maximum allowable torque =
17.743
100
20
= 88.715 % of full load torque.
12.3.2 Operation of a three phase uncontrolled bridge rectifier
supplying a capacitive load
A three phase uncontrolled bridge rectifier supplying a capacitive load is a very popular
power electronic converter. It is very widely used as the front end of a variable voltage variable
frequency dc ac inverter. Fig. 12.3 (a) shows the power circuit diagram of such a converter.
Operation of the converter can be explained as follows. The top group diodes (D
1
, D
3
, D
5
) form
a Maximum value circuit and therefore the maximum of the phase voltages v
an
, v
bn
, v
cn
appears
at the positive dc bus. On the other hand, the bottom group diodes (D
2
, D
4
, D
6
) form a
Minimum value circuit. Therefore the minimum of the phase voltages v
an
, v
bn
and v
cn
appears
at the negative dc bus. Therefore, the output voltage waveform at any instant is equal to the
maximum of the six line voltages v
ab
, v
bc
, v
ca
, v
ba
, v
cb
and v
ac
provided at least one diode from the
top group and one from the bottom group conducts at that instant. None of the diodes will
conducts, however if the output capacitor voltage is larger than the maximum line voltage. All
the six operating modes of a 3 phase bridge rectifier namely, D
1
D
2
, D
2
D
3
, D
3
D
4
, D
4
D
5
, D
5
D
6
and
D
6
D
1
appear in that order. In addition an additional operating mode in which none of the diodes
conduct appears in the conduction diagram as shown in Fig. 12.3 (b). During these periods the
output capacitor discharges through the load. As the capacitor voltage decreases its voltage
becomes equal to the incoming line voltage. At this instant the appropriate diodes from both the
top and the bottom group starts conducting and continuous to do so till the sum of the capacitor
charging current and the load current becomes zero.
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From Fig. 12.3 (b)
In the interval t
o L
v = 2V sin t (12.20)
o
c L
dv
i = c = 2V c cos t
dt
(12.21)
o L
o
v V
i = = 2 sin t
R R
(12.22)
[ ]
L
i o c
V
i = i +i = 2 RC cos t +sin t
R
2 2 2 L
V
= 2 1+ R C cos (t  )
R
(12.23)
Where
1
tan =
RC
At t = , i
i
= 0
cos (  ) = 0 or = +
2
(12.24)
in the interval
t + /3
o o
dv v
c + =
dt R
0
o L L L
2 2 2
RC
v = 2V sin = 2V cos = 2V
1+ R C
(12.25)
(t  ) (t  )

RC RC
o o L
2 2 2
RC
v = v e = 2V e
1+ R C

(12.26)
at t = + /3
/6  +
RC
o L
2 2 2
RC
v = 2V e
1+ R C
(12.27)
Also at t = + /3
o L
t = +
3
v = 2V sin t 
3
L
= 2V sin
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1 1
RC
/6  + tan
RC
2 2 2
RC
sin = e
1+ R C
(12.28)
From which the value of can be found. Equation 12.23 gives the expression of the
output current i
i
of the rectifier.
It is observed that i
i
is discontinuous and contains large ripple. This is a major
disadvantage of this converter. This ripple is also reflected in the input current of the rectifier as
shown in Fig 12.3 (b). However, the displacement factor of the converter still remains unity.
The current i
i
can be made continuous by connecting an inductor of appropriate value
between the rectifier and the capacitor. Analysis of such a converter is similar to a converter
supplying an R L E load where the value of E is
L
V
3 2
.
Exercise 12.3
Fill in the blank(s) with the appropriate word(s)
i) A three phase full wave uncontrolled rectifier supplying a capacitive load can operate in
the _________ conduction mode.
ii) The output _________ ripple factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is very low.
iii) The output _________ ripple factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is very high.
iv) The input current displacement factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is ___________.
v) The input current distortion factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is very ________.
Answers: (i) discontinuous; (ii) voltage; (iii) current; (iv) unity; (v) high.
2. A three phase full wave rectifier operates from 220 volts, three phase 50 Hz supply and
supplies a capacitive resistive load of 20 Amps. An inductor of negligible resistance is
inserted between the rectifier and the capacitor. Assuming the capacitor to be large
enough so that the output voltage is almost ripple free. Calculate the value of the
inductor so that the rectifier output current is continuous.
Answers: The following figure shows the circuit arrangement and the corresponding waveforms.
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Since the conduction is continuous
0 L
3 2
V = V
and
0
L
V 3
sin = =
2V
or = 72.73
In the interval
2
t
3 3
L
0 L
di
v +L = 2V sint
dt
Since v
0
is almost ripple free v
0
= V
0
=
L
3 2
V
L
L L
di 3 2
V +L = 2V sint
dt
L
L 0 L
2V 3 2
i = I  cost  V t
L L
Now
L
av
i = 20A
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2
0 L
3 2 1 3
I  V = 20A
L 2 3
or
L
0
3V
I = 20 +
2L
L
L
2V 3 3
i = 20 +  cost  t
L 2
For just continuous conduction i
L
= 0 at t =
L
2V 3 3
0 = 20 +  cos 
L 2
or L = 1.0306 or L = 3.28 mH.
References
[1] Power Electronics, P.C. Sen; Tata MC Grawhill publishing company limited; 1995.
[2] Power Electronics, Converters, Applications and Design; Mohan, Undeland, Robbins;
John Willey and Sons Ine, Third Edition, 2003.
Lesson Summary
Three phase uncontrolled rectifiers are available in half wave and full wave
configuration.
Three phase uncontrolled half wave rectifier require three phase four wire power supply.
The input ac line current in a three phase uncontrolled half wave rectifier contain dc
component which may cause dc saturation of input transformer.
Three phase full wave uncontrolled rectifier is most widely used in the medium power
applications particularly as the input stage of the dc link inverter.
Three phase full wave uncontrolled rectifier uses six diodes instead of three of the half
wave rectifier.
Full bridge rectifier does not require neutral connection.
The output voltage of a three phase full bridge rectifier contains multiplies of 6
th
harmonic of input cycle.
The input ac current of a three phase full bridge rectifier contain only odd harmonics but
no dc component or triplen harmonics.
The input displacement factor of the three phase bridge rectifier is always unity.
Three phase full bridge converter supplying an R L E load usually operate in the
continuous conduction mode.
Compared to single phase rectifiers, three phase bridge converter require smaller inductor
to obtain the same output current ripple factor.
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Three phase bridge rectifier supplying a capacitive load has very good output voltage
form factor but very poor input current THD.
Compared to single phase converters three phase bridge rectifier require smaller capacitor
to obtain a given output voltage form factor.
Practice Problems and Answers
Q1. A three phase half wave rectifier operates from a three phase 220 V, 50 Hz supply and
supplies a resistive load rated at 200 Volts 1 KW through an inductance large enough to
make the load current ripple free. Find out the power consumed by the load? What will
be the load power if the inductor is shorted?
Q2. A three phase full wave rectifier operates from a three phase 220 V 50 Hz supply through
a three phase /Y transformer and supplies a 200 V 1500 R.P.M, 50 Amps separately
excited dc motor. Find out the turns ratio of the transformer so that the motor operates at
rated speed at full load. If the motor armature resistance is 0.5 find out the inductance
to be connected in series with the motor such that the rectifier operates in the continuous
conduction mode at 50 % of the full load torque.
Q3. A three phase full wave rectifier supplies a resistive capacitive load of 50 Amps from a
220 V. 3 phase 50 Hz supply. Find out the value of the load capacitance such that the
load voltage ripple is less than 5 %.
Answers to practice problems
1. Since the load current is ripple free the power consumed by the load will be
2
2 0AV
L 0AV LOAD
LOAD
V
P = I R =
R
Now
L
0AV
3 2V 3 2 220
V = = =148.55 volts
2 2
2
2
0AV
L
LOAD
V 148.55
P = = 1 KW= 551.7 watts
R 200
When the inductor is shorted
2
0RMS
L
LOAD
V
P =
R
Now from Equ. (12.2)
0RMS L
1 3
V = + V =151.01 volts
3 4
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2
2
0RMS
L
LOAD
V 151.01
P = = 1 KW= 570 watts
R 200
2. To run at rated speed at full load the motor terminal voltage must be 200 volts.
0AL L
3 2
V = V = 200 volts,
V
L
= 148.1 volts
Where V
L
is the secondary line voltage. Secondary is star connected. So secondary
phase voltage
L
2
V
V = = 85.5 volts
3
Primary is delta connected. So primary phase voltage
V
1
= 220 V
Required turns ratio =
1
V
=1: 0.38865
2
At 50% of the full load torque motor current is 25 Amps
back Emf = 200 0.5 25 = 187.5 Volts.
speed at 50% of full load torque =
187.5
1500 =1607 RPM
200 0.550
.
At 50% of full load torque the motor operates in the continuous conduction mode,
with reference to Fig. 12.2 and equation 12.19.
t /3

tan L
0

3tan
2V sin sin
i = e +sin(t  ) 
z c
1 e
os
Where
L
E 187.5
sin = = = 0.9375
200 2V
= 69.64 = 1.2154 rad.
At the junction of continuous and discontinuous conduction
0 0
Min t =
i = i = 0
( ) /3

tan

3tan
sin sin
e +sin(  )  = 0
cos
1 e
OR
( ) /3 
tan

3tan
1 sin2e 1 1
+ sin  sin(  2) = sin
2 2 2
1 e
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OR
( ) /3 
tan

3tan
e
sin2  sin(  2) = sin
1 e
Solving which = 34.65.
L
= tan = 0.6911
R
L = 0.3456 or L = 1.1 mH.
3. Assuming linear ripple
0Max 0Min
0AV
V +V
V =
2
0pp 0Max 0Min
V = V  V
( )
0pp 0Max 0Min
0Max 0Min 0AV
V 2 V + V
= = 0.
V + V V
05
0Min 0Max
0Min 0Max
1 V /V
= 0.025
1+ V /V
0Min 0Max
V /V = 0.9512 .
From Fig. 12.3,
0Max L
V = 2V = 2220 V = 311 volts
V
0Min
= 295.943 Volts V
0AV
= 303.47 V.
I
0AV
= 50 Amps R = 6.0694 .
From Fig. 12.3. V
0Min
occurs at t =
V
0Min
=
L
2V sin = 295.943
sin = 0.9512 or = 72
But from Equation (12.28)
tan  +
6
sin = cos e
where
1
tan =
RC
from which = 3.5 tan = 0.06116
1
RC = =16.35
tan
, R = 6.0694
C = 2.6938, C = 8575 F.
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Module
2
AC to DC Converters
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Lesson
13
Operation and Analysis of
the Three Phase Fully
Controlled Bridge
Converter
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Instructional Objectives
On completion the student will be able to
Draw the circuit diagram and waveforms associated with a three phase fully controlled
bridge converter.
Find out the average, RMS valves and the harmonic spectrum of the output voltage /
current waveforms of the converter.
Find out the closed form expression of the output current and hence the condition for
continuous conduction.
Find out the displacement factor, distortion factor and the power factor of the input
current as well as its harmonic spectrum.
Analyze the operation of higher pulse number converters and dual converter.
Design the triggering circuit of the three phase fully controlled bridge converter.
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13.1 Introduction
The three phase fully controlled bridge converter has been probably the most widely used power
electronic converter in the medium to high power applications. Three phase circuits are
preferable when large power is involved. The controlled rectifier can provide controllable out
put dc voltage in a single unit instead of a three phase autotransformer and a diode bridge
rectifier. The controlled rectifier is obtained by replacing the diodes of the uncontrolled rectifier
with thyristors. Control over the output dc voltage is obtained by controlling the conduction
interval of each thyristor. This method is known as phase control and converters are also called
phase controlled converters. Since thyristors can block voltage in both directions it is possible
to reverse the polarity of the output dc voltage and hence feed power back to the ac supply from
the dc side. Under such condition the converter is said to be operating in the inverting mode.
The thyristors in the converter circuit are commutated with the help of the supply voltage in the
rectifying mode of operation and are known as Line commutated converter. The same circuit
while operating in the inverter mode requires load side counter emf. for commutation and are
referred to as the Load commutated inverter.
In phase controlled rectifiers though the output voltage can be varied continuously the load
harmonic voltage increases considerably as the average value goes down. Of course the
magnitude of harmonic voltage is lower in three phase converter compared to the single phase
circuit. Since the frequency of the harmonic voltage is higher smaller load inductance leads to
continuous conduction. Input current wave shape become rectangular and contain 5
th
and higher
order odd harmonics. The displacement angle of the input current increases with firing angle.
The frequency of the harmonic voltage and current can be increased by increasing the pulse
number of the converter which can be achieved by series and parallel connection of basic 6 pulse
converters. The control circuit become considerably complicated and the use of coupling
transformer and / or interphase reactors become mandatory.
With the introduction of high power IGBTs the three phase bridge converter has all but been
replaced by dc link voltage source converters in the medium to moderately high power range.
However in very high power application (such as HV dc transmission system, cycloconverter
drives, load commutated inverter synchronous motor drives, static scherbius drives etc.) the basic
B phase bridge converter block is still used. In this lesson the operating principle and
characteristic of this very important converter topology will be discussed in source depth.
13.2 Operating principle of 3 phase fully controlled bridge
converter
A three phase fully controlled converter is obtained by replacing all the six diodes of an
uncontrolled converter by six thyristors as shown in Fig. 13.1 (a)
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For any current to flow in the load at least one device from the top group (T
1
, T
3
, T
5
) and one
from the bottom group (T
2
, T
4
, T
6
) must conduct. It can be argued as in the case of an
uncontrolled converter only one device from these two groups will conduct.
Then from symmetry consideration it can be argued that each thyristor conducts for 120 of the
input cycle. Now the thyristors are fired in the sequence T
1
T
2
T
3
T
4
T
5
T
6
T
1
with 60 interval between each firing. Therefore thyristors on the same phase leg are fired at an
interval of 180 and hence can not conduct simultaneously. This leaves only six possible
conduction mode for the converter in the continuous conduction mode of operation. These are
T
1
T
2
, T
2
T
3
, T
3
T
4,
T
4
T
5
, T
5
T
6
, T
6
T
1
. Each conduction mode is of 60 duration and appears in the
sequence mentioned. The conduction table of Fig. 13.1 (b) shows voltage across different
devices and the dc output voltage for each conduction interval. The phasor diagram of the line
voltages appear in Fig. 13.1 (c). Each of these line voltages can be associated with the firing of a
thyristor with the help of the conduction table1. For example the thyristor T
1
is fired at the end
of T
5
T
6
conduction interval. During this period the voltage across T
1
was v
ac
. Therefore T
1
is
fired angle after the positive going zero crossing of v
ac
. Similar observation can be made about
other thyristors. The phasor diagram of Fig. 13.1 (c) also confirms that all the thyristors are fired
in the correct sequence with 60 interval between each firing.
Fig. 13.2 shows the waveforms of different variables (shown in Fig. 13.1 (a)). To arrive at the
waveforms it is necessary to draw the conduction diagram which shows the interval of
conduction for each thyristor and can be drawn with the help of the phasor diagram of fig. 13.1
(c). If the converter firing angle is each thyristor is fired angle after the positive going zero
crossing of the line voltage with which its firing is associated. Once the conduction diagram is
drawn all other voltage waveforms can be drawn from the line voltage waveforms and from the
conduction table of fig. 13.1 (b). Similarly line currents can be drawn from the output current
and the conduction diagram. It is clear from the waveforms that output voltage and current
waveforms are periodic over one sixth of the input cycle. Therefore this converter is also called
the six pulse converter. The input current on the other hand contains only odds harmonics of
the input frequency other than the triplex (3
rd
, 9
th
etc.) harmonics. The next section will analyze
the operation of this converter in more details.
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Exercise 13.1
Fill in the blank(s) with the appropriate word(s)
i) The three phase fully controlled bridge converter is obtained by replacing six
_________ of an uncontrolled converter by six __________.
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ii) The pulse number of a three phase fully controlled bridge converter is _________.
iii) In a three phase fully controlled converter each device conducts for an interval of
__________ degrees.
iv) In a three phase fully controlled converter operating in continuous conduction there
are ________ different conduction modes.
v) The output voltage of a three phase fully controlled converter operating in the
continuous conduction mode consists of segments of the input ac ________ voltage.
vi) The peak voltage appearing across any device of a three phase fully controlled
converter is equal to the ________ input ac ________ voltage.
vii) The input ac current of a three phase fully controlled converter has a ________ step
waveform.
viii) The input ac current of a three phase fully controlled converter contains only
_________ harmonics but no _________ harmonic.
ix) A three phase fully controlled converter can also operate in the _________ mode.
x) Discontinuous conduction in a three phase fully controlled converter is _________.
Answers: (i) diodes, thyristors; (ii) six; (iii) 120; (iv) six; (v) line; (vi) peak, line; (vii) six; (viii)
odd, tripler; (ix) inverting; (x) rare.
13.2.1 Analysis of the converter in the rectifier mode
The output voltage waveform can be written as
0 0 AK BK
K=1,2 K=1,2
v = V + V cos 6 Kt + V sin 6 Kt
(13.1)
+ +
3 3
0 0 L
3 3 2
V = v dt = V sin t + dt
3
L
3 2
= V cos
(13.2)
+
3
AK 0
6
V = v cos6 Kt dt
+
3
L
6
= 2 V sin t + cos6 t dt
3
L
3 2 cos(6K+1) cos(6K1)
= V 
6K+1 6K1
(13.3)
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+
3
BK 0
6
V = v sin6 Kt dt
+
3
L
6
= 2 V sin t + sin6 t dt
3
L
3 2 sin(6K+1) sin(6K1)
= V 
6K+1 6K1
(13.4)
1
2
+
2
3
0RMS 0 L
3 3
V = v dt = V 1+ cos2
4
3
The input phase current i
a
is expressed as
a 0
i = i t +
3
a 0
2 4
i =  i + t +
3 3
a 0
5
i = i + t + 2
3
a
i = 0 otherwise
From Fig. 13.2 it can be observed that i
0
itself has a ripple at a frequency six times the input
frequency. The closed from expression of i
0
, as will be seen later is some what complicated.
However, considerable simplification in the expression of i
a
can be obtained if i
0
is replaced by
its average value I
0
. This approximation will be valid provided the ripple on i
0
is small, i.e, the
load is highly inductive. The modified input current waveform will then be i
a
which can be
expressed in terms of a fourier series as
A0
a a An Bn
n=1 n=1
I
i i = + I cos nt + I sin nt
2
(13.5)
Where
+2
A0 a
1
I = i dt = 0
2
(13.6)
+2
An a
1
I = i cos nt n 0
0
4I n n
= cos sin cos n
n 6 2
(13.7)
( )
( )
( )
K
0
An
2 3I
I = 1 sin K cos 6K 1
6K 1 2
for n = 6K 1, K = 0, 1, 2, 3 ....
(13.8)
I
An
= 0 otherwise.
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+2
Bn a
1
I = i sin nt dt
0
4I n n
= cos sin nsin
n 6 2
(13.9)
( )
( )
( )
K
0
Bn
2 3I
I = 1 sin K sin 6K 1
6K 1 2
for n = 6K 1, K = 0, 1, 2, ....
(13.10)
I
Bn
= 0 otherwise.
( )
( )
( )(
K
0
a
K=0
1 2 3I
i = sin K cos 6K 1 t 
6K 1 2
)
(13.11)
in particular i
a1
= fundamental component of i
a
(
0
2 3
= I cos t 
) (13.12)
From Fig. 13.2
L
an
2V
v = cos t
3
(13.13)
displacement angle = . displacement factor = cos (13.14)
distortion factor =
0
I
a1
0
a
I 6 2
=
3 I
3
I = (13.15)
Power factor = Displacement factor Distortion factor =
3
cos
(13.16)
The closed form expression for i
0
in the interval
t +
3
can be found as follows
in this interval
0
0 0 L
di
Ri +L +E = v = 2V sin t +
dt 3
(13.17)
( ) t 

tan L
0 1
2V E
i = I e + sin t +  
Z 3
R
(13.18)
Where
2 2 2
L
Z = R + L , tan =
R
L
R = Zcos, E = 2V sin (from Fig. 13.2) (13.19)
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( ) t 

tan L
0 1
2V sin
i = I e + sin t +  
Z 3 c
os
(13.20)
Since i
0
is periodic over /3
0 0
t = t =+
3
i = i (13.21)
L
1

3tan L
1
2V sin
I + sin +  
Z 3 cos
2V 2 sin
= I e + sin +  
Z 3 c
os
OR
( )
L
1

3tan
sin 
2V
I =
Z
1 e
(13.22)
( )
( ) t 

tan L
0

3tan
sin  2V sin
i = e +sin t +  
Z 3
1 e
cos
(13.23)
To find out the condition for continuous conduction it is noted that in the limiting case of
continuous conduction.
0
min=0
i , Now if +
3
then i
0
is minimum at t = . Condition
for continuous conduction is
0
t =
i 0. However discontinuous conduction is rare in these
conversions and will not be discussed any further.
13.2.2 Analysis of the converter in the inverting mode.
In all the analysis presented so far it has been assumed that < 90. It follows from equation
13.2 that the output dc voltage will be positive in this case and power will be flowing from the
three phase ac side to the dc side. This is the rectifier mode of operation of the converter.
However if is made larger than 90 the direction of power flow through the converter will
reverse provided there exists a power source in the dc side of suitable polarity. The converter in
that case is said to be operating in the inverter mode. It has been explained in connection with
single phase converters that the polarity of EMF source on the dc side [Fig. 13.1(a)] would have
to be reversed for inverter mode of operator. Fig. 13.3 shows the circuit connection and wave
forms in the inverting mode of operation where the load current has been assumed to be
continuous and ripple free.
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Analysis of the converter in the inverting mode is similar to its rectifier mode of operation. The
same expressions hold for the dc and harmonic compounds in the output voltage and current.
The input supply current Fourier series is also identical to Equation 13.8. In particular
0 L
3 2
V = V cos
(13.24)
a1 0
2 3
i = I cos(t  )
(13.25)
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For values of in the range 90 < < 180 it is observed from Fig. 13.3(b) that the average dc
voltage is negative and the displacement angle of the fundamental component of the input ac
line current is equal to > 90. Therefore, power in the ac side flows from the converter to the
source.
It is observed form Fig. 13.3(b) that an outgoing thyristor (thyristor T
6
in Fig. 13.3(b)) after
commutation is impressed with a negative voltage of duration = . For successful
commutation of the outgoing thyristor it is essential that this interval is larger than the turn off
time of the thyristor i.e,
tq , tq is the thyristor turn off time
Therefore  tq or  tq .
Which imposes an upper limit on the value of . In practice this upper value of is further
reduced due to commutation overlap.
Exercise 13.2
1. A three phase fully controlled bridge converter operating from a 3 phase 220 V, 50 Hz
supply is used to charge a battery bank with nominal voltage of 240 V. The battery bank
has an internal resistance of 0.01 and the battery bank voltage varies by 10% around
its nominal value between fully charged and uncharged condition. Assuming continuous
conduction find out.
(i) The range of firing angle of the converter.
(ii) The range of ac input power factor.
(iii) The range of charging efficiency.
When the battery bank is charged with a constant average charging current of 100 Amps through
a 250 mH lossless inductor.
Answer: The maximum and minimum battery voltages are, V
B Min
= 0.9 V
B Nom
= 216 volts
and V
B Max
= 1.1 V
B Nom
= 264 volts respectively.
Since the average charging current is constant at 100 A.
V
0 Max
= V
B Max
+ 100 R
B
= 264 + 100 0.01 = 265 volts
V
0 Min
= V
B Min
+ 100 R
B
= 216 + 100 0.01 = 217 volts.
(i) But
0 Max L Min
3 2
V = V cos
Min
= 26.88
0 Min L Max
3 2
V = V cos
Max
= 43.08
(ii) Input power factor is maximum at minimum and vice versa
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Max min
3
p.f. max = Distortion factor Displacement factor = cos = 0.85
Max
3
p.f. Min = cos = 0.697
(iii) Power loss during charging =
2
0RMs B
I R
But
2 2 2 2
0RMs 0 1 2
I I +I +I +........ = and
2 2
AK BK K
K
V + V V
I =
6KL
6 2KL
For =
Min
V
A1
= 0.439 V, V
B1
= 48.48 V, I
1
= 0.073 Amps
V
A2
= 10.76, V
B2
= 20.15 V, I
2
= 0.017 Amps.
2 2 2 2
0RMs
J 100 +(0.073) +(0.017) =10000.00562
P
loss
= 100 watts.
At
Min
, P
0
= I
0
V
B Max
= 26400 watts.
Charging efficiency =
26400
26400 + 100
= 99.6%
Similarly for
Max
,
2 2
0RMs 0
I I
P
loss
= 100 watts
P
0
= I
0
V
B Min
= 21600 watts.
Charging efficiency =
21600
21600 + 100
= 99.54%
2. A three phase fully controlled converter operates from a 3 phase 230 V, 50 Hz supply
through a Y/ transformer to supply a 220 V, 600 rpm, 500 A separately excited dc
motor. The motor has an armature resistance of 0.02 . What should be the transformer
turns ratio such that the converter produces rated motor terminal voltage at 0 firing
angle. Assume continuous conduction. The same converter is now used to brake the
motor regeneratively in the reverse direction. If the thyristors are to be provided with a
minimum turn off time of 100 s, what is the maximum reverse speed at which rated
braking torque can be produced.
Answer: From the given question
L
3 2
V = 220
V
L
= 162.9 V
Where V
L
is the secondary side line and also the phase voltage since the secondary
side is connected.
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Primary side phase voltage =
230
V
3
= 132.79 V
Turns ratio =
132.79
1:1.2267
162.9
= .
During regenerative braking in the reverse direction the converter operates in the
inverting mode.
Min
tq =100S
o
Min Min
= tq =1.8
Max
= 180
Min
= 178.2
Maximum negative voltage that can be generated by the converter is
o
L
3 2
V cos 178.2 =  219.89 V
For rated braking torque I
a
= 500 A
E
b
= V
a
I
a
r
a
=  229.89 V.
At 600 RPM E
b
= 220 500 0.02 = 210 V.
Max reverse speed is
229.89
600 = 656.83 RPM
210
.
13.3 Higher pulse number converters and dual converter
The three phase fully controlled converter is widely used in the medium to moderately high power
applications. However in very large power applications (such as HV DC transmission systems)
the device ratings become impractically large. Also the relatively low frequency (6
th
in the dc
side, 5
th
and 7
th
in the ac side) harmonic voltages and currents produced by this converter become
unacceptable. Therefore several such converters are connected in series parallel combination in
order to increase the voltage / current rating of the resulting converter. Furthermore if the
component converters are controlled properly some lower order harmonics can be eliminated both
from the input and output resulting in a higher pulse converter.
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Fig. 13.4(a) schematically represents series connection of two six pulse converters where as Fig.
13.4(b) can be considered to be a parallel connection. The inductance in between the converters
has been included to limit circulating harmonic current. In both these figures CONV I and
CONV II have identical construction and are also fired at the same firing angle . Their input
supplies also have same magnitude but displaced in phase by an angle . Then one can write
01 L AK BK
K=1 K=1
3 2
v = V cos + V cos 6 Kt + V sin 6 Kt
(13.26)
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( ) (
02 L AK BK
K=1 K=1
3 2
v = V cos + V cos 6 K t  + V sin 6 K t 
)
(13.27)
Therefore for Fig 13.4(a)
( ) ( )
0 01 02 L
AK BK
K=1
6 2
v = v + v = V cos +
(13.28)
Now if cos 3K = 0 for some K then the corresponding harmonic disappear from the fourier
series expression of v
0.
In particular if = 30 then cos 3K = 0 for K = 1, 2, 3, 5.
This phase difference can be obtained by the arrangement shown in Fig. 13.4(c).
Then
[ ]
0 L Am Bm
m=1
6 2
v = V cos +2 V cos 12mt +V sin 12mt
(13.29)
It can be seen that the frequency of the harmonics present in the output voltage has the form
12, 24, 36 ..
Similarly it can be shown that the input side line current i
ABC
have harmonic frequency of the
form
11, 13, 23, 25, 35, 37, .
Which is the characteristic of a 12 pulse converter.
In a similar manner more number of 3 phase 6 pulse converters can be connected in series /
parallel and the angle can be adjusted to obtain 18 and 24 pulse converters.
One of the shortcomings of a three phase fully controlled converter is that although it can
produce both positive and negative voltage it can not supply current in both directions.
However, some applications such as a four quadrant dc motor drive require this capability from
the dc source. This problem is easily mitigated by connecting another three phase fully
controlled converter in anti parallel as shown in Fig. 13.5 (a). In this figure converterI supplies
positive load current while converterII supplies negative load current. In other words converter
I operates in the first and fourth quadrant of the output v i plane whereas converterII operates
in the third and fourth quadrant. Thus the two converters taken together can operate in all four
quadrants and is capable of supplying a four quadrant dc motor drive. The combined converter is
called the Dual converter.
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Obviously since converterI and converterII are connected in antiparallel they must produce the
same dc voltage. This requires that the firing angles of these two converters be related as
2
=
1
(13.30)
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Although Equations 13.30 ensures that the dc voltages produced by these converters are equal
the output voltages do not match on an instantaneous basis. Therefore to avoid a direct short
circuit between two different supply lines the two converters must never be gated
simultaneously. ConverterI receives gate pulses when the load current is positive. Gate pulses
to converterII are blocked at that time. For negative load current converterII thyristors are fired
while converterI gate pulses are blocked. Thus there is no circulating current flowing through
the converters and therefore it is called the noncirculating current type dual converter. It
requires precise sensing of the zero crossing of the output current which may pose a problem
particularly at light load due to possible discontinuous conduction. To overcome this problem an
interphase reactor may be incorporated between the two converters. With the interphase reactor
in place both the converters can be gated simultaneously with
2
=
1
. The resulting
converter is called the circulating current type dual converter.
13.4 Gate Drive circuit for three phase fully controlled converter
Several schemes exist to generate gate drive pulses for single phase or three phase converters. In
many application it is required that the output of the converter be proportional to a control
voltage. This can be achieved as follows.
In either single or three phase converters
0
1
V 1
K 0
V cos or = cos (13.31)
To get
c
V 1
K 0 c
V v = cos (13.32)
The following circuit can be used to generate according to equation 13.32.
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In the circuit of Fig. 13.6(a) a phase shift network is used to obtain a waveform leading v
i
by 90.
The phasor diagram of the phase shift circuit is shown in Fig. 13.6(b). The output of the phase
shift waveform (and its inverse) is compared with v
c
. The firing pulse is generated at the point
when these two waveforms are equal. Obviously atthis instant
c
s
v 1
V c s
v Vcos or = cos (13.33)
Therefore this method of generation of converter firing pulses is called inverse cosine control.
The output of the phase shift network is called carrier waveform.
Similar technique can be used for three phase converters. However the phase shift network here
consists of a three phase signal transformer with special connections as shown in Fig. 13.7.
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The signal transformer uses three single phase transformer each of which has two secondary
windings. The primary windings are connected in delta while the secondary windings are
connected in zigzag. From Fig. 13.1 (c) T
2
is fired angle after the positive going zero crossing
of v
bc
. Therefore, to implement inverse cosine the carrier wave for T
2
must lead v
bc
by 90. This
waveform is obtained from zigzag connection of the winding segments a
1
a
2
and c
1
c
2
as shown in
Fig. 13.7(a). The same figure also shows the zigzag connection for other phase. The voltage
across each zigzag phase can be used to fire two thyristors belonging to the same phase leg using
a circuit similar to Fig. 13.6 (a). The phase shift network will not be required in this case.
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Exercise 13.3
1. Fill in the blank(s) with the appropriate word(s)
i) Higher pulse number converters can be realized by __________ and _______
connection of six pulse converters.
ii) Constituent six pulse converters of a 12 pulse converter have _________ firing
angles.
iii) The input supply voltages to the converters of a 12 pulse converter have ________
magnitudes and are phase shifted from one another by _________ degrees.
iv) The input supply to a 12 pulse converter can be obtained through a _________
connected transformer.
v) Dual converters are used for supplying ________ quadrant dc motor drives.
vi) In a dual converter if one converter is fired at an angle the other has to be fired
at _________.
vii) In ___________ current dual converter only one converter conducts at any time.
viii) In a circulating current type dual converter an __________ is used between the
converters to limit the circulating current.
ix) To obtain a linear control relation between the control voltage and the output dc
voltage of a converter ___________ control logic is used.
x) In a three phase fully controlled converter the carrier waves for firing pulse
generation are obtained using three ___________ connected single phase
transformers.
Answers: (i) Series, parallel; (ii) same, (iii) equal, 30, (iv) star star delta; (v) four; (vi)  ,
(vii) noncirculating ; (viii) inductor, (ix) inversecosine; (x) deltazigzag.
2. A 220V, 750 RPM, 200A separately excited dc motor has an armature resistance of 0.05
. The armature is fed from a three phase non circulating current dual converter. If the
forward converter operates at a firing angle of 70
i) At what speed will the motor deliver rated torque.
ii) What should be the firing angle in the regenerative braking mode when the motor
delivers half the rated torque at 600 rpm.
Assume continuous conduction. Supply voltage is 400 V.
Answer:
i) The output voltage =
o
3 2
400 cos 70 = 184.7 V
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E
b
= V
a
I
a
r
a
= 184.7 200 0.05 = 174.75 V.
Operating speed =
174.75
750 = 624 RPM
220  0.05 200
.
ii)
b 600RPM 1 a
600
E =  210 = 168V I =100A
750
V
a
=  E
b
+ I
a
r
a
= 173 r.
V
a
=  173 =
3 2
400 cos
= 108.67
3. What will happen if the signal transformers generating the carrier wave have delta
double star connection instead of deltazigzag connection.
Answer: With deltadouble star connection of the signal transformers the carrier wave forms
will be in phase with the line voltage waveforms. Therefore, without a phase shift
network it will not be possible to generate carrier waveforms which are in quadrature
with the line voltages. Hence inverse casine control law cannot be implemented.
References
1. Power Electronics; P.C. Sen; TataMcGrawhill publishing company limited; 1995.
2. Power Electronics, Converters, Applications and Design, Mohan, Undeland, Robbins;
John Willey and Sons Inc; Third Edition, 2003.
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Lesson Summary
A three phase fully controlled converter is realized by replacing the diodes of an
uncontrolled converter with thyristors.
A three phase fully controlled converter can operate either as a rectifier or as an inverter.
The output voltage of a three phase fully controlled converter contains multiple of sixth
harmonic of the input frequency in addition to the dc component.
The input current of a three phase fully controlled converter contains only odd harmonics
other than tripler harmonics.
The input current displacement factor of a three phase fully controlled converter is cos .
being the firing angle.
In the continuous conduction mode a three phase fully controlled converter may operate
in the inverting mode by increasing beyond 90.
In the inverting mode the firing angle should be less than 180 for safe commutation of
the thyristors.
Several units of three phase fully controlled converters can be connected in series parallel
to form higher pulse number (12, 18, 24 etc) converters.
In higher pulse number converters all component converters are fired at the same firing
angle while their input supplies are phase shifted from one another by a predetermined
angle.
Two three phase fully controlled converter can be connected in anti parallel to form a
dual converter which can operate in all four quadrants of the VI plane.
Dual converters can be of circulating and non circulating current type.
Fully controlled converters employ inverse casine control strategy for generating firing
pulses which gives linear relationship between the output voltage and the control voltage.
In a three phase fully controlled converter, a three phase delta/zigzag connected signal
transformer is used to generate the required carrier waves for this purpose.
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Practice problems and answers
1. A three phase fully controlled converter operates from a 3 phase 230 V, 50 Hz supply and
supplies a resistive load of 25 at a firing angle 90. Find out the power supplied to the
load.
2. A three phase fully controlled converter supplies a 220 V 1500 RPM, 50 A separately
excited dc motor from a 230 V, 3 phase, 50 Hz supply. The motor holds an overhauling
load at 1000 RPM while producing full load torque. The motor has an armature
resistance of 0.2 . What should be the firing angle? Assume continuous conduction.
3. What precaution should be taken in the gate drive circuit so that a three phase fully
controlled converter can continue to operate even when the load current becomes
discontinuous.
Answers
1.
The figure above shows the output voltage with = 90 and a resistive load. Since the load is
resistive the load current becomes zero when the voltage becomes zero. Both the voltage and
amount remains zero thereafter till the next thyristor is fired.
Therefore for
5
t
6
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0 bc L
v = V = 2V sint
7
t
6
v
0
= 0
2 2
0 RMS L 5
6
3
V = 2V sin t dt
( )
L 5
6
3
= V 1  cos2t dt
0 RMS
0 L 5
6
V
1 3
P = = V cos2t dt
R 2
= 183 Watts
L
3 3 1
= V
2 4
= 67.65 V
2. To hold the overhauling load the motor must operate in the regenerative braking mode.
At 1000 RPM E
b
=
220 500.2
1000 =140 volts
1500
To supply full load torque, the motor armature current = 50 A.
Supply voltage = V
a
= E
b
+ I
a
r
a
= 140 + 50 0.2 = 150 V in the reverse direction.
L
3 2
V cos =  150V
= 118.9.
3. With reference to the conduction diagram of problem 1 it can be seen that the load
current becomes zero 30 after a new thyristor is fired (for example, T
2
). Therefore, both
the conducting thyristor (T
1
and T
2
in this case) turns off. However, when T
3
is fired the
converter will be unable to resume operation from T
2
T
3
mode unless T
2
is fired
simultaneously. Similar explanation holds for all other thyristor firing. Therefore, to
ensure that the converter operates properly even under discontinuous load current
condition the final gate pulse for a particular thyristors must be generated by logically
ANDing the outputs of its own firing circuit with the output of the firing circuit of the
thyristor in the commutation sequence as shown in the table next below
To generate the
gate pulse of : T
1
T
2
T
3
T
4
T
5
T
6
AND the outputs of : T
1
& T
2
T
2
& T
3
T
3
& T
4
T
4
& T
5
T
5
& T
6
T
6
& T
1
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Module
2
AC to DC Converters
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Lesson
14
Operation and Analysis of
Three Phase Half
Controlled Converter
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Instructional Objectives
On completion the student will be able to
Draw the circuit diagram and waveforms of different variables associated with a three
phase half controlled converter.
Identify the constructional and operational difference between a three phase fully
controlled and half controlled converter.
Calculate the average and RMS value of the output dc voltage.
Calculate the displacement factor, distortion factor and power factor of the input ac line
current.
Calculate the Fourier series components of the output voltage and input current
waveforms.
Derive the closed form expression for output dc current and hence identify continuous or
discontinuous conduction mode of the converter.
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14.1 Introduction
Three phase fully controlled converters are very popular in many industrial applications
particularly in situations where power regeneration from the dc side is essential. It can handle
reasonably high power and has acceptable input and output harmonic distortion. The
configuration also lends itself to easy series and parallel connection for increasing voltage and
current rating or improvement in harmonic behavior. However, this versatility of a three phase
fully controlled converters are obtained at the cost of increased circuit complexity due to the use
of six thyristors and their associated control circuit. This complexity can be considerably reduced
in applications where power regeneration is not necessary. In that case three thyristors of the top
group or the bottom group of a three phase fully controlled converter can be replaced by three
diodes. The resulting converter is called a three phase half controlled converter. Replacing three
thyristors by three diodes reduces circuit complexity but at the same time prevents negative
voltage appearing at the output at any time. Therefore the converter cannot operate in the
inverting mode.
The three phase half controlled converter has several other advantages over a three phase
fully controlled converter. For the same firing angle it has lower input side displacement factor
compared to a fully controlled converter. It also extends the range of continuous conduction of
the converter. It has one serious disadvantage however. The output voltage is periodic over one
third of the input cycle rather than one sixth as is the case with fully controlled converters. This
implies both input and output harmonics are of lower frequency and require heavier filtering.
For this reason half controlled three phase converters are not as popular as their fully controlled
counterpart.
Although, from the point of view of construction and circuit complexity the half controlled
converter is simpler compared to the fully controlled converter, its analysis is considerably more
difficult. In this lesson the operating principle and analysis of a three phase half controlled
converter operating in the continuous conduction mode will be presented.
14.2 Operating principle of three phase half controlled converter
Fig. 14.1(a) shows the circuit diagram of three phase half controlled converter supplying an RL
E load. In the continuous conduction mode only one thyristor from top group and only one diode
from the bottom group conduct at a time. However, unlike fully controlled converter here both
devices from the same phase leg can conduct at the same time. Hence, there are nine conducting
modes as shown in Fig. 14.1(b).
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Now consider the conducting and blocking state of D
2
. In the blocking state the voltage across
D
2
is either v
ac
or v
bc
. Hence, D
2
can block only when these voltages are negative. Taking v
bc
as
the reference phasor (i.e.,
bc L
v = 2V sint ) D
2
will block during 2/3 t 2 and will
conduct in the interval 0 t 2/3 . Similarly it can be shown that D
4
and D
6
will conduct
during 2/3 t 4/3 and 4/3 t 2 respectively.
Next consider conduction of T
1
. The firing sequence of the thyristor is T
1
T
3
T
5
.
Therefore before T
1
comes into conduction T
5
conducts and voltage across T
1
is
ac L
v = 2V sin (t + /3) . If the firing angle of T
1
is then T
1
starts conduction at
t =  /3and conducts upto + /3. Similarly T
3
and T
5
conducts during + /3 t +
and + t 2 +  /3 . From this discussion the following conduction diagrams can be
drawn for continuous conduction mode.
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Exercise 14.1
Fill in the blanks(s) with appropriate word(s).
i. A three phase half controlled converter has ________________ thyristors and
________________ diodes.
ii. A three phase half controlled converter has ________________ conduction modes as
compared to ________________ of a fully controlled converter.
iii. A three phase half controlled converter can not operate in the ________________ mode.
iv. Unlike a three phase fully controlled converter the devices in the ________________ phase
leg of a half controlled converter can conduct at a given time. These conduction modes are
called ________________ modes.
v. In a three phase half controlled converter only ________________ conduction modes
appear at the same time.
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vi. ________________ modes appear only when the firing angle of the converter is greater
than ________________ degrees.
vii. In a three phase half controlled converter the diodes conduct in a manner similar to a
________________ converter where as the thyristors conducts similar to a
________________ converter.
viii. The input current of a three phase half controlled converter does not have
________________ cycle symmetry.
Answer: (i) three, three; (ii) nine, six; (iii) inverter; (iv) same, free wheeling; (v) six; (vi) free
wheeling, 60; (vii) uncontrolled, controlled; (viii) quarter.
14.3 Analysis of three phase half controlled converters
Fig. 14.2 (a) and (b) also shows the waveforms of v
0
and i
0
(for < /3 and > /3 ) both of
which are periodic over one third of the input voltage time period. Therefore examining v
0
for
the conduction period of any one thyristor (for example T
1
) will be sufficient to deduce
information regarding output voltage. For example the average value of v
0
can be found as
follows.
With T
1
conducting there can be three conduction modes namely, T
1
D
6
, T
1
D
2
and T
1
D
4
.
Now T
1
conducts in the interval
 +
3 3
t
D
2
conducts in the interval
0 t 2
3
D
4
conducts in the interval
2 t 4
3 3
D
6
conducts in the interval
4 t 2
3
Conduction interval T
1
D
6
exists only if
3
Conduction interval T
1
D
4
exists only if
3
>
So for
3
In the interval
 t 0
3
( 0 ab L
2
v = v = 2V sin t +
3
)
(14.1)
0 t +
3
( 0 ac L
v = v = 2V sin t +
3
)
(14.2)
0 +
L 3
0
 0
3
3 2V
V = sin t + 2 dt+ sin t + dt
2 3 3
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( ) ( )
L
3 2V
2 2
= cos +  cos + cos  cos +
2 3 3 3 3
(14.3)
or,
0 L
3 2
V = V (1 + cos)
2
(14.4)
For
3
> , In the interval
2
 t
3 3
( 0 ac L
v = v = 2V sin t +
3
)
(14.5)
for
2
t +
3 3
v
0
= 0 (14.6)
2
L
0

3
3 2V
V = sin t + dt
2 3
L
3 2
= V (1 + cos)
2
RMS value of v
0
can be found in a similar manner and is left as an exercise.
From the waveforms of Fig. 14.2, v
0
is periodic over one third of the input cycle. Therefore one
can write
[
0 0 An Bn
n=1
v = V + V cos 3nt + V sin 3nt
] (14.8)
+
3
An 0

3
3
V = v cos 3nt dt
(14.9)
+
3
Bn 0

3
3
V = v sin 3nt dt
(14.10)
For
3
From equations 14.1 and 14.2
0 +
3
An L L
 0
3
3
V = 2V sin t + 2 cos3ntdt + 2V sin t + cos3ntdt
3 3
0

3
L
+
3
0
sin (3n + 1)t + 2 + sin (1  3n)t + 2 dt
3 3
3 2V
=
2
+ sin (3n + 1)t +  sin (3n 1)t  dt
3 3
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{ } { }
{ } { }
 0
3
0 
3
L
0 +
3
+ 0
3
cos (3n + 1)t + 2/3 cos (3n  1)t  2/3
+
3n + 1 3n  1
3 2V
=
2
cos (3n + 1)t + /3 cos (3n  1)t  /3
+ +
3n + 1 3n  1
(14.11)
Therefore
[ ] [ ]
[ ] [ ]
L
An
1 +cos (3n + 1)(  /3) + 2/3  cos (3n + 1)( + /3) + /3
3 2V
3n + 1
V =
2 cos (3n  1)( + /3)  /3  cos (3n  1)(  /3)  2/3 1
+
3n  1
[ ] [ ]
[ ] [ ]
L
1  2sin (3n + 1) + /2 sin /6  (3n + 1) /3
3 2V
3n + 1
=
2 1 +2sin (3n  1)  /2 sin /6 + (3n  1) /3

3n  1
L
3 2V 1+2sin(6n + 1)/6 cos(3n + 1) 1 2sin(6n  1)/6 cos(3n  1)
= 
2 3n + 1 3n  1
n n
L
3 2V 1+(1) cos(3n + 1) 1+(1) cos(3n  1)
= 
2 3n + 1 3n  1
(14.12)
Similarly,
0 +
L 3
Bn
 0
3
3 2V
V = sin t + 2 sin3ntdt + sin t + sin3ntdt
3 3
(14.13)
or,
0

3
L
Bn
+
3
0
cos (3n  1)t  2  cos (3n + 1)t + 2 dt
3 3
3 2V
V =
2
+ cos (3n  1)t   cos (3n + 1)t + dt
3 3
{ } { }
{ } { }
0 0
 
3 3
L
+ +
3 3
0 0
sin (3n  1)t  2/3 sin (3n + 1)t + 2/3

3n  1 3n + 1
3 2V
=
2
sin (3n  1)t  /3 sin (3n + 1)t + /3
+ 
3n  1 3n + 1
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[ ] [ ]
[ ] [ ]
L
sin (3n  1)( + /3)  /3  sin (3n  1)(  /3)  2/3
3 2V
3n  1
=
2 sin (3n + 1)( + /3) + /3  sin (3n + 1)(  /3) + 2/3

3n + 1
[ ] [ ]
[ ] [ ]
L
cos (3n  1)  /2 sin /6 + (3n  1) /6
3 2V
3n  1
=
cos (3n + 1) + /2 sin (3n + 1)/6  /6

3n + 1
L
3 2V sin(3n + 1) sin(3n  1) n
= +
3n + 1 3n  1 2
sin
Bn L
3 2 n sin(3n + 1) sin(3n  1)
V = V sin +
2 3n + 1 3n  1
(14.14)
Similar analysis can be done for
3
>
To find out the Fourier series of the input ac line current the load may be replaced by a constant
current source having the same value as the average load current. This approximation will be
valid provided the load current ripple is relatively small. With this assumption the last waveform
of Fig. 14.2(b) can be redrawn as follows.
2
 t
3
3
i
a
= I
0
4
+ t
3
3
i
a
=  I
0
otherwise i
a
= 0
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[
a an bn
n = 1
i = I cos nt + I sin nt
]
(14.15)
2
an a
0
1
I = i cos nt dt
2 4
3 3
0 0
 +
3 3
1
= I cos nt dt  I cos nt dt
2 4
3 3
0
 +
3 3
I
sin nt sin nt
= 
n n
( ) ( )
0
I
2n 4n
= sin  sin n  + sin n +  sin
n 3 3 3
3
0
2I
2n n
= sin + cos n sin
n 3 3
or,
0 n
an
2I
n
I = cos n  ( 1) sin
n 3
(14.16)
2
bn a
0
1
I = i sin nt dt
2 4
3 3
0 0
 +
3 3
1
= I sin nt dt  I sin nt dt
 4
0
3
2 +
3 3
I
= cos nt + cos nt
n
3
( ) ( )
0
I
4n 2n
= sin  cos + cos n   cos n +
n 3 3 3
3
0
2I
n
= sin n sin
n 3
(14.17)
For the fundamental component n = 1
[ ]
0
a1
3I
i = cost + cos cost + sin sint
[ ]
0
3I
= cost + cos(t  )
( )
0
2 3I
= cos cos t 
2
2
(14.18)
Displacement factor =
cos
2
(14.19)
Distortion factor =
( )
0
a1
a
0
6
I cos
I
6 2
= = cos
I 

I
2
(14.20)
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Power factor = Distortion factor Displacement factor
( )
( )
2
3 6
cos = (1 + cos)
2 
2 
(14.21)
A closed form expression for i
0
can be found as follows
In the interval
0 t +
3
< v
0
= v
ac
( )
0
0 ac L
di
L + Ri + E = v = 2V sin t +
dt 3
(14.22)
( )
t

L tan
0
2V
sin
i = Ie + sin t +  
Z 3
cos
(14.23)
Where
L
tan =
R
,
2 2
Z = R + L
2
and
L
E = 2V sin (14.24)
At
t = +
3
( )
( )
+ /3

L tan
0 1
2V
2 sin
i = I = Ie + sin  + 
Z 3 cos
(14.25)
In the interval
2
+ t
3
3
v
0
= v
bc
0
0 bc L
di
L + Ri + E = v = 2V sint
dt
(14.26)
( )
( )
t   /3

L tan
0 2
2V
sin
i = I e + sin t  
Z
cos
(14.27)
At
t = +
3
( )
L
0 2
2V
sin
i = I + sin +   I
Z 3 cos
(14.28)
( )
(
+ /3

L tan
2
2V
I = Ie  sin 
Z
) (14.29)
( )
( )
( )
( )
t t   /3
 
L tan tan
0
2V
sin
i = Ie + sin  e + sin t  
Z c
os
(14.30)
( )
( )
( )
 /3
2

L 3tan tan
2
0
t =
3
2V
2 sin
i = Ie + sin  e  sin  
Z
3 cos
(14.31)
( )
L
2
0 0
t = t = 0
3
2V
sin
i = i = I + sin  
Z 3 co s
(14.32)
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( )
( )  /3
2

L 3tan tan
2V
I 1  e = sin  e + sin
Z
for
0 t +
3
<
( )
( )
( )
t   /3 t


tan
tan
L
0
2 2
 
3tan 3tan
2V sin e
e sin
i = sin  + + sin t +  
Z 3
1 e 1 e
cos
(14.33)
for
2
+ t
3 3
( )
( )
( )
t
 /3  t

t   /3
tan
tan 
L tan
0
2 2
 
3tan 3tan
2V sin e
e s
i = sin  e + + + sin t  
Z c
1 e 1 e
in
os
(14.34)
Exercise 14.2
1. Fill in the blank(s) with the appropriate word(s).
i. In a three phase half controlled converter each thyristor and diode conduct for
________________ degrees.
ii. The output voltage waveform of a three phase half controlled converter is periodic over
________________ of the input voltage cycle.
iii. The output voltage waveform of a three phase half controlled converter operating with >
/3 and /3 are ________________ and have ________________ formula for the
average voltage.
iv. The output voltage and current of a three phase half controlled converter contain
________________ harmonics of the input ac frequency.
v. The ac input current of a half controlled three phase converter can be zero for larger than
________________ of the input ac cycle provided the value of is ________________
than 60.
vi. The input ac current of a three phase half controlled converter contain ________________
harmonics but no ________________ harmonics.
vii. For the same output load current and firing angle the three phase half controlled converter
has better ________________ factor but poorer ________________ factor compared to a
fully controlled converter.
Answer: (i) 120; (ii) one third; (iii) different, same; (iv) triplen; (v) one third, greater; (vi) even,
triplen; (vii) displacement, distortion.
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2. A 200V, 1450 RPM, 100A separately excited dc machine has an armature resistance of
0.04. The machine is driven by a three phase half controlled converter operating from a
three phase 220V, 50Hz supply. The motor operates at the rated speed and rated load torque.
Assuming continuous conduction find out (i) the firing angle of the converter; (ii) RMS
fundamental component of the input current, (iii) Input current displacement factor and
distortion factors.
Answer:
(i) Under rated operating condition the motor must be supplied with rated voltage.
Therefore
( )
o L
3 2
V = V 1+cos = 200V
2
Where V
L
= 230V
o
70
(ii) I
o
= 100A
From equation (14.18)
i1 o
6
I = I cos = 63.87 amps
2
(iii) From equation (14.19)
Input displacement factor = cos 0.819
2
=
From equation (14.20)
Input distortion factor =
( )
6
cos 0.712
2
=
References
1. Power Electronics P.C. Sen, Tata McGrawhill publishing company limited, 1995.
2. Power Electronics, Converters, Applications and Design; Mohan, Undeland, Robins;
John Willey and Sons Inc, Third Edition, 2003.
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Lesson Summary
Three phase half controlled converters are obtained by replacing three thyristors of either
the top group or the bottom group of fully controlled converters by three diodes.
Three phase half controlled converters can not operate in the inverting mode.
Three phase half controlled converters have nine operating modes as compared to six of a
fully controlled converter.
The three free wheeling modes of a half controlled converters appears only when the
firing angle is larger than 60.
The output voltage and current waveforms of a three phase half controlled converter
consist of a dc component and triplen harmonics of the input voltage frequency.
For the same input ac voltage and firing angle a half controlled converter has higher
output average dc voltage compared to a fully controlled converter.
The input ac line current of a three phase half controlled converter contains harmonics of
all (odd and even) order except triplen harmonics.
For the same average dc load current and firing angle the half controlled converter has
better input current displacement factor but poorer distortion factor compared to a fully
controlled converter.
The triggering circuit of a three phase half controlled converter is similar to that of a fully
controlled converter. However, only three are required.
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Practice Problems and Answers
1. If a free wheeling diode is connected across the output terminals of a three phase fully
controlled converter will the performance of converter will be similar to a half controlled
converter? Justify your answer.
2. A 220V, 1500 rpm, 50A, separately excited dc motor with armature resistance of 0.5 if
fed from a 3 phase half controlled rectifier. The available ac source is 440V, 50Hz. A star
delta connected transformer is used to feed the armature so that the motor terminal
voltage equals rated voltage when converter firing angle is zero.
(i) Calculate the transformer turns ratio
(ii) Firing angle when (a) motor is running at 1200 rpm and rated torque; (b) 1500 rpm
and half the rated torque.
3. A battery with a nominal voltage of 200V and internal resistance of 10m has to be
charged at a constant current of 20 amps from a 3 phase 220V 50 Hz power supply.
Which of the following converters will give better performance with respect to input
current displacement factor, distortion factor and power factor?
(i) 3 phase fully controlled converter; (ii) 3 phase half controlled converter.
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Answers to Practice Problems
1) Connecting a diode at the output of a three phase fully controlled converter will not make
it performs as a half controlled converter. For example
i) When /3 the free wheeling diode will not come into conduction and therefore,
the converter will continue to perform like a fully controlled converter which is very
different from that of a half controlled converter for this range of .
ii) For /3 > the output voltage will be clamped to zero for certain part of the input
cycle. However, the output voltage will still have six pulse characteristics unlike a
half controlled converter. Similarly the input current waveform will retain its quarter
cycle symmetry which is not the case with a half controlled converter.
2) For a half controlled converter
i)
0 L
3 2
V = V (1 + cos)
2
at = 0, V
0
= 220 V, V
L
= 163 V,
supply voltage = 440 V, Primary phase voltage = 254 V
Turns ratio = 1 : 0.64.
ii) (a)
b
1500
E = 220  0.5 50 = 195V
b
1200
12
E = 195 = 156 V
15
Torque is rated, I
a
= 50 A, V
1200
= 156 + 0.5 50 = 181 volts
3 2
181 = 163(1 + cos)
2
= 49.87
(b) V
1500
at half rated torque = 195 + 0.5 25 = 207.5V
3 2
207.5 = 163(1 + cos)
2
= 27.7
3) The output voltage of the converter should be
V
0
= 200 + 20 10 10
3
= 200.2 V
(i) with a fully controlled converter
3 2
200.2 = 220 cos
= 47.64
Displacement factor = cos = 0.674
Distortion factor =
3
= 0.955
Power factor = Displacement factor Distortion factor = 0.6436
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(ii) with a half controlled converter
3 2
200.2 = 220 (1 + cos)
2
= 69.65
Displacement factor =
cos
2
= 0.82
Distortion factor =
6
cos
() 2
= 0.8166
Power factor = 0.6695
Displacement factor and power factor of a half controlled converter are better
compared to a fully controlled converter while the distortion factor is poorer.
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Module
2
AC to DC Converters
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Lesson
15
Effect of Source
Inductance on the
Performance of AC to DC
Converters
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Instructional Objectives
On completion the student will be able to
Draw the voltage and current waveforms associated with a converter taking into account
the effect of source inductance.
Find the average output voltage of the converter as a function of the firing angle and
overlap angle.
Estimate overlap angles under a given operating condition and hence determine the turn
off time available for the thyristors.
Draw the dc equivalent circuit of a converter and parameterize it.
Find out the voltage stress on the thyristors due to commutation overlap.
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15.1 Introduction
In the previous lessons the input ac power sources supplying an ac to dc power converter have
been assumed to be ideal with no source impedance. Although this assumption simplifies the
analysis of the converters, in most practical situations, they are not fully justified. Most ac dc
converters are supplied from transformers. The series impedance of the transformer can not
always be neglected. Even if no transformer is used, the impedance of the feeder line comes in
series with the source. In most cases this impedance is predominantly inductive with negligible
resistive component. The presence of source inductance does have significant effect on the
performance of the converter. With source inductance present the output voltage of a converter
does not remain constant for a given firing angle. Instead it drops gradually with load current.
The converter output voltage and input current waveforms also change significantly. In this
lesson a quantitative analysis of these effects will be taken up in some detail.
15.2 Single phase fully controlled converter with source
inductance
Fig. 15.1(a) shows a single phase fully controlled converter with source inductance. For
simplicity it has been assumed that the converter operates in the continuous conduction mode.
Further, it has been assumed that the load current ripple is negligible and the load can be
replaced by a dc current source the magnitude of which equals the average load current. Fig.
15.1(b) shows the corresponding waveforms. It is assumed that the thyristors T
3
and T
4
were
conducting at t = 0. T
1
and T
2
are fired at t = . If there were no source inductance T
3
and T
4
would have commutated as soon as T
1
and T
2
are turned ON. The input current polarity would
have changed instantaneously. However, if a source inductance is present the commutation and
change of input current polarity can not be instantaneous. Therefore, when T
1
and T
2
are turned
ON T
3
T
4
does not commutate immediately. Instead, for some interval all four thyristors
continue to conduct as shown in Fig. 15.1(b). This interval is called overlap interval.
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During this period the load current freewheels through the thyristors and the output voltage is
clamped to zero. On the other hand, the input current starts changing polarity as the current
through T
1
and T
2
increases and T
3
T
4
current decreases. At the end of the overlap interval the
current through T
3
and T
4
becomes zero and they commutate, T
1
and T
2
starts conducting the full
load current. The same process repeats during commutation from T
1
T
2
to T
3
T
4
at t = + .
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From Fig. 15.1(b) it is clear that, commutation overlap not only reduces average output dc
voltage but also reduces the extinction angle which may cause commutation failure in the
inverting mode of operation if is very close to 180. In the following analysis an expression of
the overlap angle will be determined.
From the equivalent circuit of the converter during overlap period
i
i
di
L = v
dt
for t + (15.1)
i
i
(t = ) =  I
0
(15.2)
i
i
2V
i = I  cost
L
(15.3)
i
i
t =
2V
i = I  cos =  I
L
0
(15.4)
i
0
2V
I = cos  I
L
(15.5)
i
i
2V
i = (cos  cost)  I
L
0
(15.6)
at t = + i
i
= I
0
i
0
2V
I = (cos  cos( + ))  I
L
0
(15.7)
0
i
2L
cos  cos( + ) = I
V
(15.8)
+
0 i
I
V = v dt
(15.9)
or
+
0 i
+
I
V = 2v sint dt
[ ]
i
2v
= cos( + ) cos( + )
[
i
2v
= cos cos( + )
+ ] (15.10)
[ ]
i i
0
v 2v
V = 2 2 cos  cos cos( + )
i
2 2 2
= v cos  L I
0
(15.11)
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Equation 15.11 can be represented by the following equivalent circuit
The simple equivalent circuit of Fig. 15.3 represents the single phase fully controlled converter
with source inductance as a practical dc source as far as its average behaviour is concerned. The
open circuit voltage of this practical source equals the average dc output voltage of an ideal
converter (without source inductance) operating at a firing angle of . The voltage drop across
the internal resistance R
C
represents the voltage lost due to overlap shown in Fig. 15.1(b) by
the hatched portion of the v
0
waveform. Therefore, this is called the Commutation resistance.
Although this resistance accounts for the voltage drop correctly there is no power loss associated
with this resistance since the physical process of overlap does not involve any power loss.
Therefore this resistance should be used carefully where power calculation is involved.
15.3 Three phase fully controlled converter with source
inductance
In lesson 13 the three phase fully controlled converter was analyzed with ideal source with no
internal impedance. When the source inductance is taken into account, the qualitative effects on
the performance of the converter is similar to that in the case of a single phase converter. Fig.
15.4(a) shows such a converter. As in the case of a single phase converter the load is assumed to
be highly inductive such that the load can be replaced by a current source.
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As in the case of a single phase converter, commutations are not instantaneous due to the
presence of source inductances. It takes place over an overlap period of
1
instead. During the
overlap period three thyristors instead of two conducts. Current in the outgoing thyristor
gradually decreases to zero while the incoming thyristor current increases and equals the total
load current at the end of the overlap period. If the duration of the overlap period is greater than
60 four thyristors may also conduct clamping the output voltage to zero for sometime. However,
this situation is not very common and will not be discussed any further in this lesson. Due to the
conduction of two devices during commutation either from the top group or the bottom group the
instantaneous output voltage during the overlap period drops (shown by the hatched portion of
Fig. 15.4 (b)) resulting in reduced average voltage. The exact amount of this reduction can be
calculated as follows.
In the time interval < t + , T
6
and T
2
from the bottom group and T
1
from the top group
conducts. The equivalent circuit of the converter during this period is given by the circuit
diagram of Fig. 15.5.
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Therefore, in the interval < t +
b c
b c
di di
v = L  L + v
dt dt
(15.12)
or,
bc b
d
v = L (i  i )
dt
c
(15.13)
but i
b
+ i
c
+ I
o
= 0
b c
di di
= 
dt dt
(15.14)
b bc L
d
2L i = v = 2V sint
dt
(15.15)
L
b
2V
i = C  cost
2L
(15.16)
at t = , i
b
=  I
0
L
0
2V
C = cos  I
2L
(15.17)
L
b 0
2V
i = (cos  cost)  I
2L
(15.18)
at t = + , i
b
= 0
L
0
2V
(cos  cos( + )) = I
2L
(15.19)
Or,
0
L
2L
cos  cos( + ) = I
V
(15.20)
Equation 15.20 holds for 60. It can be shown that for this condition to be satisfied
( )
L
0
V
I cos 
3
2L
(15.21)
To calculate the dc voltage
For t +
b
0 a b
t
di
3
v = v  v + L = v
d 2
a
(15.22)
for
+ t +
3
v
0
= v
ac
+ +
3
0 a ac
+
3 3
V = v dt + v dt
2
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( )
+ +
3
ac a ac ac
+
3 3
= v v  v + v dt
2
+
+ +
a 3
ac c
v
3
= v dt + v t
2
+
d
+
L
3 2 3
= V cos  v dt
2
bc
(15.23)
or
+
L
0 L
3 2V
3 2
V = V cos  sint dt
2
[
L
L
3 2V
3 2
= V cos  cos  cos( + )
2
] (15.24)
Substituting Equation 15.20 into 15.24
0 L
3 2 3
V = V cos  L I
0
(15.25)
Equation 15.25 suggests the same dc equivalent circuit for the three phase converter with source
inductance as shown in Fig. 15.3 with
OC L
3 2
V = V cos
.
It should be noted that R
C
is a loss less resistance, since the overlap process does not involve
any active power loss.
Exercise 15.1
1. Fill in the blank(s) with appropriate word(s)
i. The internal impedance of an ac source supplying a converter is largely ______________
in nature.
ii. Due to the presence of source ______________ commutation in a converter is not
______________.
iii. The period over which the commutation process continues is called the ______________
period.
iv. Length of the overlap period depends on the valve of the source inductance and load
______________.
v. In a single phase converter ______________ thyristors conduct during the overlap
period.
vi. In a three phase converter ______________ thryistors conduct during the overlap period
provided the overlap angle is less than ______________ degrees.
vii. The average output voltage of a acdc converter ______________ as a result of
commutation overlap.
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viii. In the dc equivalent circuit of a converter the input ac source inductor appears as a loss
less resistance called the ______________ resistance.
ix. Commutation overlap decreases the ______________ angle of a converter and may cause
commutation failure during ______________ mode of operation.
x. Commutation overlap introduces ______________ in the supply voltage waveform.
Answer: (i) inductive; (ii) inductance, instantaneous; (iii) overlap; (iv) current ; (v) four; (vi)
three, sixty; (vii) decreases; (viii) commutation; (ix) inverter, (x) notches.
2. A 220V, 1450 RPM, 100A separately excited dc motor has an armature resistance to
0.1. It is supplied from a 3 phase fully controlled converter connected to a 3 phase 50
Hz ac source. The ac source has an inductive reactance of 0.5 at 50 Hz. The line voltage
is adjusted such that at = 0; the motor operates at rated speed and torque. The motor is
to be braked regeneratively in the reverse direction at rated speed using the converter.
What is the maximum braking torque the motor will be able to produce under this
condition without causing commutation failure?
Answer: Under rated operating condition, the motor terminal voltage is 220V and it draws 100
Amps current. Therefore from eqn. 15.25.
L
3 2 3
220 = V  .5100
or
L
V 198 volts =
b rated speed
E 220 100 0.1 210V = =
Under regenerative braking in the reverse direction at rated speed
o
3 2 3
198cos 0.5 0.1 I 210V
+ =
Also from equation 15.20
( )
o
2 0.5 I
cos cos
198
+ =
At the limiting condition of commutation failure
o
180 +
o
I
cos 1
198 2
=
o o
3 3 2 3
I 198 0.5 0.1 I 210
+ =
or
o
0.377 I 57.4 =
o
I 152.24 Amps =
Maximum braking torque will be approximately 150% of the rated motor torque.
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References
1. Muhammad H. Rashid; Power Electronics, Circuits, Devices and Applications Second
Edition, Prentice Hall of India, New Delhi, 1994.
2. P.C. Sen; Power Electronics, Tata McGrawhill publishing company limited, 1995.
3. Power Electronics, Converters, Applications and Design; Mohan, Undeland, Robbins;
John Willey and Sons Inc, Third Edition, 2003.
Lesson Summary
Ac power sources supplying an acdc converter have internal impedances which are not
always negligible.
The internal impedance of an ac source is predominantly inductive with negligible
resistive component.
Due to the presence of the source inductance in the ac line the thyristors in a acdc
converter can not commutate instantaneously.
The period over which the commutation process continuous is called the overlap period.
The length of the overlap period increases with increasing source inductance and load
current.
In a single phase converter all four thyristors conduct during the overlap period.
In a three phase converter, three thyristors conduct during the overlap period provided it
is less than 60.
The average output voltage of a converter decreases as a result of commutation overlap.
The voltage drop due to commutation overlap can be represented as a drop across a
commutation resistance the value of which is proportional to the ac line reactance per
phase.
The commutation resistance is loss less since the actual process of overlap does not
involve any real power loss.
Commutation overlap reduces the margin angle () of a converter and may cause
commutation failure.
Commutation overlap introduces notches in the ac supply voltage waveform which
may affect other equipment connect to the same power source.
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Module
2
AC to DC Converters
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Lesson
16
Power Factor
Improvement, Harmonic
Reduction, Filter
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Instructional Objectives
Study of the following:
Schemes for the improvement of power factor in ACDC converters.
Methods for harmonic reduction in the current waveforms of the converters.
Types of filters used to obtain ripple free (dc) output voltage and currents, reducing the
harmonics.
2.8.1 Introduction
After the discussion of various types of ac to dc converters (rectifiers), both single and three
phase, in the lessons (#2.12.6) of this module (# 2), the drop in the output voltage due to the
commutation overlap in the converter, was presented, the inductance on the source (ac) side
being taken into account, in the previous lesson (#2.7).
In this (last) lesson (#2.8), three important points power factor improvement, harmonic
reduction, and filters, as applicable to converters, are described. The three schemes for power
factor improvement are discussed. Then, the use of various filters to reduce the harmonics in the
output voltage and current waveforms, are presented. Lastly, the harmonic reduction techniques
are taken up, in brief. In all these cases, the circuit of a single phase full wave half (semi)
controlled bridge converter (acdc) is used mostly as an example.
Power Factor Improvement
For phasecontrolled operation in both single phase full wave half and full controlled bridge
converters as discussed in this module (#2), the displacement factor (or power factor, which is
lagging) decreases, as the average value of output voltage (V
dc
) decreases, with the increase in
firing angle delay, . This is also applicable for both three phase half wave and full wave
(bridge) converters. The three schemes used for power factor (pf) improvement are:
Extinction angle control
Symmetrical angle control
Pulse width modulation (PWM) control
Extinction Angle Control
The circuit diagram of a single phase full wave halfcontrolled (semi) forcecommutated
bridge converter is shown in Fig. 16.1(a). The thyristors, T
1
& T
2,
are replaced by the switches,
selfcommutated devices, such as power transistor or equivalent. The power transistor is turned
on by applying a signal at the base, and turned off by withdrawing the signal at the base. A gate
turnoff thyristor (GTO) also may be used, in which case, it may be turned off by applying a
short negative pulse to its gate, but is turned on by a short positive pulse, like a thyristor.
In extinction angle control, switch, S
1
is turned on at t 0 = , and then turned off by forced
commutation at ( t = ) . The switch, S
2
is turned on at t = , and then turned off at
( t 2 = ) . The output voltage is controlled by varying the extinction angle, . Fig. 16.1(b)
shows the waveforms for input voltage, output voltage, input current, and the current through
thyristor switches. The fundamental component of input current leads the input voltage, and the
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displacement factor (and power factor) is leading. This feature may be desirable to simulate a
capacitive load, thus compensating the line voltage drops.
L
O
A
D
i
DF
D
F
D
1 D
2
v
s
v
0
S
1 S
2
i
T1
i
T2
+
+


i
s
i
0
= I
a
(a) Circuit
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Load current
(b) Waveforms for extinction angle control
t
0
I
a
i
o
 I
a
t
t
t
t
t
t
2
2
2
2 
2 
2 
2
2




I
a
I
a
I
a
v
s
v
0
v
s
= V
m
sint
V
m
0
0
0
0
0
0
i
T1
i
T2
i
DF
i
s1
i
s
I
a
Fig. 16.1 Singlephase forcedcommutated semiconverter.
2 
3 
3 
The average output voltage is
( ) ( )

dc
0
2 2
V = 2Vsin t d t = V 1 + cos
2
The value of V
dc
is varied from (2 2 / )V to 0, as varies from 0 to .
The rms value of output voltage is
( )
1
2

2 2
o
0
2
V = 2V sin t d t
2
( )
1
2
1 1
= V sin 2
2
+
Here also, V
o
varies from V to 0.
This scheme of extinction angle control can also be used for single phase full wave full
controlled bridge converter with four switches, instead of two needed in the earlier case. The
students are requestedto study this matter form text books, but details are not included here.
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Symmetrical Angle Control
This control can be applied for the same halfcontrolled force commutated bridge converter
with two switches, S
1
and S
2
as shown in Fig. 16.1(a). The switch, S
1
is turned on at
( ) t = 2 and then turned off at ( ) t = + 2. The other switch, S
2
is turned on at
( ) t 3 = 2 and then turned off at ( ) t 3 = + 2 . The output voltage is varied by varying
conduction angle, . The gate signals are generated by comparing halfsine waves with a dc
signal as shown in Fig. 16.2(b). The halfsine waves can be obtained using a full wave diode
(uncontrolled) bridge converter. The gate signals can also be generated by comparing triangular
waves with a dc signal as shown in Fig. 16.2(c). In the second case, the conduction angle varies
linearly with the dc signals, but in inverse ratio, i.e., when the dc signal is zero, full conduction
( ) = takes place, and the dc signal being same as the peak of the triangular reference signal,
no conduction ( ) 0 = takes place. Fig. 16.2(a) shows the waveforms for input voltage, output
voltage, input current and the current through the switches. The fundamental component of input
current is in phase with input voltage, and the displacement factor is unity (1.0). Therefore, the
power factor is improved.
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Load current
(a)
t
0
I
a
 I
a
t
t
t
t
t
3 2
2

2
2
2
I
a
I
a
v
s
v
0
v
s
= V
m
sint
V
m
0
0
0
0
0
i
s1
i
s1
i
s
V
m
i
0
i
s2
+
2
/2
5 /2
3 /2
I
a
v
t 3 2
0
t 3 2
0
(b)
S
1 S
2
S
1
v
g
A
r
A
r
v
r
v
c
Fig. 16.2 Symmetrical angle control.
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The average output voltage is
( )
( )
( )
/ 2
dc
/ 2
2 2
V 2Vsin t d t Vsin
2
+
2
= =
The value of V
dc
varies from
( )
2 2 V to 0 as varies from to 0.
The rms value of output voltage is
( ) ( )
( )
( )
1
2
+ / 2
2 2
o
 / 2
2
V = 2V sin t d t
2
( )
1
2
1
= V sin
+
Pulse Width Modulation (PWM) Control
If the output voltage of single phase halfcontrolled converter is controlled by delay angle,
extinction angle or symmetrical, there is only one pulse per half cycle in the input current of the
converter, and as a result, the lowest order harmonic is third. It is difficult to filter out the lower
order harmonic current. In Pulse Width Modulation (PWM) control, the converter switches are
turned on and off several times during a half cycle, and the output voltage is controlled by
varying the width of pulses. The gate signals are generated by comparing a triangular wave with
a dc signal as shown in Fig. 16.3c. In this case, all the pulse widths obtained are equal. Fig. 16.3a
shows the input voltage, output voltage, and input current. The lowest order harmonic can be
eliminated or reduced by selecting the number of pulses per half cycle. However, increasing the
number of pulses would also increase the magnitude of higher order harmonics, which could
easily be filtered out. The earlier case of symmetrical angle control can be considered as single
pulse PWM. For more details of PWM methods used, the students are requested to study the two
lessons (#5.45.5) in module 5 (DCAC converter, or inverter).
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Load current
(a)
t
0
I
a
 I
a
t
t
t
t
t 3
2
2
2
2
I
a
v
v
0
0
0
0
0
0
i
s1
i
s
m
i
0
i
s3
I
a
3
3
3
3
m
2
+
m
+
m
m
I
a
m
S
1
v
c
v
r
A
c
A
r
v
0
v
g2
1
(b)
S
1 S
1
t
m
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v
(c)
Fig. 16.3 Pulsewidthmodulation control.
t
t
0
S
1 S
1
S
1
v
g2
A
r
A
c
v
r
v
c
m
The details of output voltage and current waveforms of the converter are given. The output
voltage (i.e., performance parameters) can be obtained in two steps: (i) by considering only one
pair of pulses such that, if one pulse starts at
1
t = , and ends at
1
t
1
= + , the other pulse
starts at
1
t = + , and ends at ( )
1 1
t = + + , and (2) then by combining the effects of all
pairs of pulse.
If m
th
pulse starts at and its width is
m
t =
m
, the average output voltage due to p number
of pulses is found as
( )
m m
m
p
dc
m 1
2
V 2Vsin t d t
+
=
=
( )
p
m m
m 1
2V
cos cos
=
= +
m
If the load current with an average value of I
a
is continuous and has negligible ripple, the
instantaneous input current is expressed in a Fourier series as
( ) ( )
s dc n n
n 1,3,5,...
i t I a cos n t b sin n t
=
= + +
Due to symmetry of the input current waveform, even harmonics are absent, and I
dc
is zero. The
Fourier coefficients are obtained as
( ) ( )
2
n s
0
1
a i t cos n t d
t
( ) ( )
m m m m
m m
p
a a
m 1
1 1
I cos n t d t I cos n t d t 0
+ + +
+
=
=
=
( ) ( )
2
n s
0
1
b i t sin n t d t
( ) ( )
m m m m
m m
p
a a
m 1
1 1
I sin n t d t I sin n t d t
+ + +
+
=
=
( )
p
a
m m
m 1
2I
cos n cos n
n
=
m
+
=
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So, the equation for i
s
(t) is written as
( ) ( )
s n
n 1,3,...
i t 2 I sin n t
=
=
n
+
where ( )
1
n n n
tan a b 0
= = , and
( )
1
2
2 2
n n n n
I a b 2 b = + = 2
Sinusoidal Pulse Width Modulation (SPWM) Control
Various types of modifications in PWM techniques have been proposed. One important
method is sinusoidal pulse width modulation (SPWM) control, the pulse widths are generated by
comparing a triangular reference voltage v
r
of amplitude A
r
and frequency f
r
, with a carrier half
sinusoidal voltage v
c
of variable amplitude A
c
and frequency 2f
s
. The sinusoidal voltage v
c
is in
phase with the input phase voltage v
s
and has twice the supply frequency f
s
. The widths of the
pulses (and the output voltage) are varied by changing the amplitude A
r
or the modulation index
M from 0 to 1. The modulation index, M is A
c
/A
r
. It may be noted that the width of the pulses
obtained are variable. The width are smaller at the centre of the carrier signal (sinusoidal), and
increases as one goes to the start and end of the above signal. Fig. 16.4 shows the various
waveforms, including the currents through thyristors and the input current and load current
(assumed to be continuous). It may be noted that, in the earlier case (multiple PWM control), the
pulse widths are uniform (equal). In this type of control, the displacement factor is unity, and the
power factor is improved. The lower order harmonics one eliminated or reduced. For example,
width four pulses per half cycle, the lowest order harmonic is the fifth, and so on.
Different modifications have been suggested to take one such example, as the pulse width
one small in the centre as shown in Fig. 16.4, the carrier signal is modified to care of this. The
triangular waveforms are kept same, upto some point from the start and end of the cycle, and
then the pulse widths can be made uniform. For more on the matter as given earlier, the students
can, either study lesson #5.5 (module 5), or text books on various PWM methods applied for
inverters (dcac converters).
So, the power factor is improved with various control methods discussed. For different PWM
methods used, the harmonic components of the voltage waveforms are also decreased or
eliminated.
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Load current
t
0
t
t
t
2 3
I
a
i
o
 I
a
t
2
2
0
0
0
i
s
i
T1
+I
a
3
3
m
+
m
+
m
m
+I
a
+I
a
m
+
m
+
m
A
r
A
c
v
r
v
c
0
i
T2
v
Reference signal
Carrier signal
Fig. 16.4 Sinusoidal pulsewidth modulation control.
Filters
It is known that the output voltage waveform of a single phase full wave diode (uncontrolled)
bridge converter (rectifier) fed from f = 50 Hz (fundamental) supply, contains harmonics of 2f =
100 Hz. So, it is necessary to filter out this and other harmonics from the output voltage to obtain
dc component only. The harmonic frequency present in the output voltage waveforms of three
phase halfwave and full wave (bridge) diode converters, are 150 Hz (3f) and 300 Hz (6f)
respectively. The higher the harmonic frequency, it is easier to filter it. For phasecontrolled
thyristor converters, the harmonic frequency remains same, but magnitudes vary, as the firing
angle delay, is changed. It may also be noted that the harmonics present in the output current
waveforms of the converters with resistive (R) load, remain same. .
For simple filter, a capacitor (C) is connected in parallel across the output of the diode
converters with resistive (R) load. The reactance of the capacitor should be low, such that
harmonics currents pass through it. So, the harmonics in the output voltage decrease. The value
of the capacitor chosen varies with the predominant harmonic frequency present. Thus, the
capacitor of higher value is needed to filter lower harmonic frequency, say 100 Hz, whereas a
lower value of C could be chosen for say, three phase converters. The function of the capacitor
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may also be explained in the following way. The voltage across the capacitor changes as per the
input voltage, which is the output voltage of the converter, fed to it, and the capacitor voltage
tries to stabilize at the overage value of the output voltage, as the capacitor voltage decreases,
load resistance being connected across it.
Same is the case with the filter used to reduce the harmonic content of the output current
waveform for the above converters with resistive (R) load. Instead of a capacitor in parallel, an
inductor (L) is connected in series with the load. The reactance of the inductor increases, thus
reducing the harmonic component in the current waveform. Here, a smaller value of the inductor
is needed to filter higher harmonics, for example a threephase bridge converter. These are all
simple cases, known to those, who have studied the circuit (network) theory. Also, by Faradays
laws, induced voltage (emf) appears across the inductor, L, when the current through it changes,
and the sign of it opposes the cause, thus opposing the changes in current. So, the current is not
allowed to change much, as an inductor is placed in series with the load. In actual practice, a
combination of L, C & R is needed to get an optimum filter needed to reduce or eliminate the
harmonics in both output voltage and current waveforms.
Low Pass (LC) Filter
A passive low pass filter is the ideal choice. But two problems arise; one is the voltage level,
the other is the power or current level. All the elements used, L C or R must be properly rated for
the voltage or current level as needed. A single stage filter (LC) is used to reduce the harmonic
components in both voltage and current waveforms of a single phase full wave diode bridge
converter with resistive (R
L
) load as shown in Fig. 16.5(a). It may be noted that, for the lowest
harmonic frequency of 100 Hz, the value of the inductor needed is high, needing an ironcored
coil. The size also may be large, if the power or current level is high. As stated earlier, such that
n
th
harmonic ripple content passes through the filter capacitor (C), the impedance of the series
path must be much greater than that of the capacitance, i.e.,
( ) ( )
2 2
L L
1
Z R n L
n C
= + >>
The condition to be satisfied is
L
10
Z
n C
=
or ( )
L
Z 10 1 n C =
and the effect of load is negligible. As shown, the capacitive reactance chosen is total load
impedance divided by a factor of 10
The advantages are small ripple factor with just a single stage (LC) used, with higher dc
output voltage. The main advantage is poor voltage regulation, also resulting in higher peak
anode current and peak inverse voltage rating.
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L
O
A
D
R
L
D
2
D
C
L
B
(a)
A
D
1
D
3
D
4
1 
Supply
(50Hz)
H
+
+


i
L
i
s
G
Fig. 16.5 (a) Low pass (LC) filter, (b) Twostage filter
L
O
A
D
R
L
, L
C
1
B
A
C
2
(b)
+

E
R
Two Stage Filter
A twostage filter (Fig. 16.5(b)) may be used, instead of a single stage one given earlier. In
this case, the first one is only capacitive (C
1
) to reduce the harmonic content in voltage
waveform, followed by second stage (RC), instead of LC. The size may be reduced as the size
of R is smaller than that of L, as given earlier. This circuit offers satisfactory operation at light
loads, but considerably poor voltage regulation due to drop in R, resulting in higher ripple
content, at heavy load.
If a single capacitor (C
1
) is used as a single stage one, the ripple factor (RF) is
( )
L 1
RF 1 2 4fR C 1
=
For a chosen ripple factor, the value of C
1
may be computed, if the values of rated output voltage
and current for the converter are known or given.
These filters may also be used at the output of the dcdc converter circuits described in
module 3 (lessons $3.13.2). Only a single stage (LC) filter may be used, as the frequency in the
output voltage in thus case is much higher than the harmonic frequency (100 Hz) for the single
phase full wave acdc converter (rectifier) circuit described here.
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Harmonic Reduction
The harmonic reduction schemes are presented in brief. The important point to be noted is
that, recently due to increasing use of power electronic units, utility or electricity supply agencies
(boards), have restricted that the power is drawn by the consumers, so as to decrease the
harmonic content in the input current, or make it sinusoidal, and at the same time, improved load
power factor is achieved. Two schemes (a) passive (filter) circuits and (b) Active shaping of
input line current, are presented, in brief.
Low pass (LC) filter circuit on ac side
Before going into the aspect, let us take a rebook at the input current drawn in the circuit
shown in Fig. 16.5a. Assuming that output (load) current is constant (dc) without any ripple, the
ac input (source) current is square wave in nature (Fig. 16.6a), as this current changes sign, when
the input voltage changes sign. If a Fourier analysis of the above current is done, there are
harmonic components present in it. Just as filters have been used on the output (dc) side, a low
pass (LC) filter (Fig. 16.6b) is used on the input (source) side to reduce the harmonic
components in the input current. The inductors used tend both to improve the power factor and
also reduce harmonics as given earlier. The overall energy efficiency remains the same, though
additional losses occur in the inductors, but conduction losses in the diodes are reduced.
0
0
(T/2)
2(T)
t
Fig. 16.6(a) Output and input currents.
i
s
i
L
I
a
I
a
I
a
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i
S
H
C
L
1
B
A
+
G
Fig. 16.6 (b) Low pass (LC) filter on source (AC) side
L
2

+

Active Shaping of Input (line) Current
By using a power electronic converter for current shaping, as shown in Fig. 16.7a, it is
possible to shape the input current drawn by the single phase bridge converter (rectifier) to be
sinusoidal and also in phase with the input voltage. The choice of the power electronic converter
is based on the following considerations:
No need for electrical isolation between the input (dc) and output (dc) sides
the power flow is always unidirectional from the utility side to the equipment
the cost, power losses and size of the circuit used should be small.
Based on the above, a stepup (boost) dcdc converter as described in next module (#3),
lesson 3.1, is used as the current shaping circuit. The basic principle of operation is as follows.
At the input side, the current, i
s,
is desired to be sinusoidal, and also in phase with the voltage, v
s
,
as shown in Fig. 16.7b. Therefore, at the full wave bridge converter output, i
L
and
s
v have the
same waveform as shown in Fig. 16.7c.
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v
s
C
d
I
load
i
c
+

v
d
+

v
s
v
s
+

L
d
i
L i
d
Stepup
converter
(a)
d s
(V > V )
t
t
(b)
i
s
0
v
s
i
L
0
(c)
Fig. 16.7 Active harmonic filtering: (a) stepup converter for current
shaping; (b) line waveforms; (c) v
s
and i
L
.
The control used is constant toleranceband one. Here, the current. i
L
, is controlled, such that
peaktopeak ripple I
rip
in i
L
remains constant. The reference input, , is made sinusoidal having
same (line) frequency. With a preselected value of I
*
L
i
rip
, i
L
is forced to be in tolerance band (i
L
+
I
rip
/2) and (i
L
I
rip
/2) by controlling the status of the switch, S. So, the input current, i
L
, follows
the reference input, , which is sinusoidal. As described later (module #3), the switch, S may be
a selfcommutated switching device, power transistor or MOSFET. For detail, any text book may
be used by the student, as only a brief discussion is presented here.
*
L
i
In this lesson, last one in this module, three important points power factor (pf)
improvement, harmonic reduction and filters, are presented. Firstly, three methods, viz extinction
angle control, symmetrical angle control and pulse width modulation (PWM) control, are
described in detail with relevant waveforms. Then, various types of filters (C, LC & RC) used
for the reduction in harmonic content of output voltage and current waveforms of the acdc
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converters, are discussed, with the equations for the value of the filter components needed.
Lastly, in brief, harmonic reduction aspect is taken up. In this module of acdc converter
consisting of eight lessons, all types of singlephase and threephase converters, with other
relevant points, have been thoroughly discussed.
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Module
3
DC to DC Converters
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Lesson
17
Types of Basic DCDC
Converters
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Instructional Objectives
Study of the following:
Three basic types of dcdc converter circuits buck, boost and buckboost
The expressions for the output voltage in the above circuits, with inductive (RL) and battery
(or back emf = E) load
Introduction
In the last module (#2) consisting of eight lessons, the various types of circuits used in both
singlephase and threephase acdc converters, were discussed in detail. This includes halfwave
and fullwave, and also halfcontrolled and fullcontrolled ones.
In this lesson the first one in this module (#3), firstly, three basic types of dcdc converter
circuits buck, boost and buckboost, are presented. Then, the expressions for the output voltage
in the above circuits, with inductive (RL) and battery (or back emf = E), i.e., RLE, load, are
derived, assuming continuous conduction. The different control strategies employed are briefly
described.
Keywords: DCDC converter circuits, Thyristor choppers, Buck, boost and buckboost
converters (dcdc), Stepdown (buck) and stepup (boost) choppers, Output voltage and current.
DCDC Converters
There are three basic types of dcdc converter circuits, termed as buck, boost and buckboost.
In all of these circuits, a power device is used as a switch. This device earlier used was a
thyristor, which is turned on by a pulse fed at its gate. In all these circuits, the thyristor is
connected in series with load to a dc supply, or a positive (forward) voltage is applied between
anode and cathode terminals. The thyristor turns off, when the current decreases below the
holding current, or a reverse (negative) voltage is applied between anode and cathode terminals.
So, a thyristor is to be forcecommutated, for which additional circuit is to be used, where
another thyristor is often used. Later, GTOs came into the market, which can also be turned off
by a negative current fed at its gate, unlike thyristors, requiring proper control circuit. The turn
on and turnoff times of GTOs are lower than those of thyristors. So, the frequency used in GTO
based choppers can be increased, thus reducing the size of filters. Earlier, dcdc converters were
called choppers, where thyristors or GTOs are used. It may be noted here that buck converter
(dcdc) is called as stepdown chopper, whereas boost converter (dcdc) is a stepup chopper.
In the case of chopper, no buckboost type was used.
With the advent of bipolar junction transistor (BJT), which is termed as selfcommutated
device, it is used as a switch, instead of thyristor, in dcdc converters. This device (NPN
transistor) is switched on by a positive current through the base and emitter, and then switched
off by withdrawing the above signal. The collector is connected to a positive voltage. Nowa
days, MOSFETs are used as a switching device in low voltage and high current applications. It
may be noted that, as the turnon and turnoff time of MOSFETs are lower as compared to other
switching devices, the frequency used for the dcdc converters using it (MOSFET) is high, thus,
reducing the size of filters as stated earlier. These converters are now being used for applications,
one of the most important being Switched Mode Power Supply (SMPS). Similarly, when
application requires high voltage, Insulated Gate Bipolar Transistors (IGBT) are preferred over
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BJTs, as the turnon and turnoff times of IGBTs are lower than those of power transistors (BJT),
thus the frequency can be increased in the converters using them. So, mostly selfcommutated
devices of transistor family as described are being increasingly used in dcdc converters.
Buck Converters (dcdc)
A buck converter (dcdc) is shown in Fig. 17.1a. Only a switch is shown, for which a device
as described earlier belonging to transistor family is used. Also a diode (termed as free wheeling)
is used to allow the load current to flow through it, when the switch (i.e., a device) is turned off.
The load is inductive (RL) one. In some cases, a battery (or back emf) is connected in series
with the load (inductive). Due to the load inductance, the load current must be allowed a path,
which is provided by the diode; otherwise, i.e., in the absence of the above diode, the high
induced emf of the inductance, as the load current tends to decrease, may cause damage to the
switching device. If the switching device used is a thyristor, this circuit is called as a stepdown
chopper, as the output voltage is normally lower than the input voltage. Similarly, this dcdc
converter is termed as buck one, due to reason given later.
V
0
+


+
V
s
L
Switch
S
D
F
I
0
L
O
A
D
Fig. 17.1(a): Buck converter (dcdc)
T
ON
V
s
T
OFF
T
V
0
t
t
i
0
v
0
Fig. 17.1(b): Output voltage and current waveforms
The output voltage and current waveforms of the circuit (Fig. 17.1a) are shown in Fig. 17.1b.
The output voltage is same as the input voltage, i.e.,
s
V v =
0
, when the switch is ON, during the
period, . The switch is turned on at 0 t T
ON
0 = t , and then turned off at . This is
ON
T t =
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called ON period. During the next time interval, , the output voltage is zero, i.e.,
, as the diode, now conducts. The OFF period is
ON
T t T
0
0
= v
F
D
ON OFF
T T T = , with the time period
being . The frequency is
OFF ON
T T T + = T f / 1 = . With T kept as constant, the average value of
the output voltage is,
s
ON
s
T
s
T
V k
T
T
V dt V
T
dt v
T
V
ON
=
= = =
0 0
0 0
1 1
The duty ratio is ( ) ( ) [
OFF ON ON ON
T T T T T k ] + = = / / , its range being . Normally, due
to turnon delay of the device used, the duty ratio (k) is not zero, but has some positive value.
Similarly, due to requirement of turnoff time of the device, the duty ratio (k) is less than 1.0. So,
the range of duty ratio is reduced. It may be noted that the output voltage is lower than the input
voltage. Also, the average output voltage increases, as the duty ratio is increased. So, a variable
dc output voltage is obtained from a constant dc input voltage. The load current is assumed to be
continuous as shown in Fig. 17.1b. The load current increases in the ON period, as the input
voltage appears across the load, and it (load current) decreases in the OFF period, as it flows in
the diode, but is positive at the end of the time period, T.
0 . 0 0 . 1 k
Boost Converters (dcdc)
A boost converter (dcdc) is shown in Fig. 17.2a. Only a switch is shown, for which a device
belonging to transistor family is generally used. Also, a diode is used in series with the load. The
load is of the same type as given earlier. The inductance of the load is small. An inductance, L is
assumed in series with the input supply. The position of the switch and diode in this circuit may
be noted, as compared to their position in the buck converter (Fig. 17.1a).
V
0
+
 
+
V
s
D
Switch
S
I
s
L
O
A
D
Fig. 17.2(a): Boost converter (dcdc)
L
I
0
T T
ON 2T
T
OFF
I
2
I
1
Fig. 17.2(b): Waveforms of source current (i
S
)
0
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The operation of the circuit is explained. Firstly, the switch, S (i.e., the device) is put ON
(or turned ON) during the period, , the ON period being . The output voltage is
zero ( ), if no battery (back emf) is connected in series with the load, and also as stated
earlier, the load inductance is small. The current from the source ( ) flows in the inductance L.
The value of current increases linearly with time in this interval, with (
0 t T
ON ON
T
0
0
= v
s
i
di d t ) being positive. As
the current through L increases, the polarity of the induced emf is taken as say, positive, the left
hand side of L being +ve. The equation for the circuit is,
t d
i d
L V
s
s
= or,
L
V
t d
i d
s s
=
The switch, S is put OFF during the period, , the OFF period being
. ( ) is the time period. As the current through L decreases, with its
direction being in the same direction as shown (same as in the earlier case), the induced emf
reverses, the left hand side of L being ve. So, the induced emf (taken as ve in the equation
given later) is added with the supply voltage, being of the same polarity, thus, keeping the
current ( ) in the same direction. The current (
ON
T t T
ON OFF
T T T =
OFF ON
T T T + =
0
i i
s
=
0
i i
s
= ) decreases linearly in the time interval,
, as the output voltage is assumed to be nearly constant at
OFF
T
0 0
V v , with ( t d i d
s
) being
negative, as , which is derived later.
0
V V
s
<
The equation for the circuit is,
t d
i d
L V V
s
s
+ =
0
or,
( )
L
V V
t d
i d
s s 0
=
The source current waveform is shown in Fig. 17.2b. As stated earlier, the current varies
linearly from ( ) to ( ) during the time interval, .
1
I
min
I
2
I
max
I
ON
T
So, using the expression for t d i d
s
during this time interval,
( )
ON s
T L V I I I I /
min max 1 2
= = .
Similarly, the current varies linearly from ( ) to ( ) during the time interval, .
So, using the expression for
2
I
max
I
1
I
min
I
OFF
T
t d i d
s
during this time interval,
( ) [ ]
OFF s
T L V V I I I I /
0 min max 1 2
= = .
Equating the two equations, ( ) ( ) [ ]
OFF s ON s
T L V V T L V / /
0
= , from which the average
value of the output voltage is,
( )
=
k
V
T T
V
T T
T
V
T
T
V V
s
ON
s
ON
s
OFF
s
1
1
/ 1
1
0
The time period is , and the duty ratio is,
OFF ON
T T T + =
( ) ( [
OFF ON ON ON
T T T T T k + = = / / )], with its range as . The ON time interval is
. As stated in the previous case, the range of is reduced. This is, because the
minimum value is higher than the minimum (0.0), and the maximum value is lower than the
maximum (1.0), for reasons given there, which are also valid here. As shown, the source current
is assumed to be continuous. The expression for the output voltage can be obtained by using
other procedures.
0 . 0 0 . 1 k
T k T
ON
= k
In this case, the output voltage is higher than the input voltage, as contrasted with the
previous case of buck converter (dcdc). So, this is called boost converter (dcdc), when a self
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commutated device is used as a switch. Instead, if thyristor is used in its place, this is termed as
stepup chopper. The variation (range) of the output voltage can be easily computed.
BuckBoost Converters (dcdc)
A buckboost converter (dcdc) is shown in Fig. 17.3. Only a switch is shown, for which a
device belonging to transistor family is generally used. Also, a diode is used in series with the
load. The connection of the diode may be noted, as compared with its connection in a boost
converter (Fig. 17.2a). The inductor, L is connected in parallel after the switch and before the
diode. The load is of the same type as given earlier. A capacitor, C is connected in parallel with
the load. The polarity of the output voltage is opposite to that of input voltage here.
When the switch, S is put ON, the supply current ( ) flows through the path, , S and L,
during the time interval, . The currents through both source and inductor ( ) increase and
are same, with (
s
i
s
V
ON
T
L
i
t d i d
L
) being positive. The polarity of the induced voltage is same as that of
the input voltage. The equation for the circuit is,
t d
i d
L V
L
s
= or,
L
V
t d
i d
s L
=
V
0

+
V
s
C
Switch
S
I
s
L
O
A
D
Fig. 17.3(a): Buckboost converter (dcdc)
L
I
0
I
L
+

T T
ON
2T
I
L2
I
L1
T
OFF
Fig. 17.3(b): Inductor current (i
L
) waveform
Then, the switch, S is put OFF. The inductor current tends to decrease, with the polarity of
the induced emf reversing. ( t d i d
L
) is negative now, the polarity of the output voltage,
being opposite to that of the input voltage, . The path of the current is through L, parallel
combination of load & C, and diode D, during the time interval, . The output voltage
remains nearly constant, as the capacitor is connected across the load.
0
V
s
V
OFF
T
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The equation for the circuit is,
0
V
t d
i d
L
L
= or,
L
V
t d
i d
L 0
=
The inductor current waveform is shown in Fig. 17.3b. As stated earlier, the current varies
linearly from to during the time interval, . Note that and are the minimum
and maximum values of the inductor current respectively. So, using the expression for
1 L
I
2 L
I
ON
T
1 L
I
2 L
I
t d i d
L
during this time interval, ( )
ON s L L
T L V I I /
1 2
= .
Similarly, the current varies linearly from to during the time interval, . So, using
the expression for
2 L
I
1 L
I
OFF
T
t d i d
L
during this time interval, ( )
OFF L L
T L V I I /
0 1 2
= .
Equating the two equations, ( ) ( )
OFF ON s
T L V T L V / /
0
= , from which the average value of
the output voltage is,
( )
( )
=
k
k
V
T T
T T
V
T T
T
V
T
T
V V
s
ON
ON
s
ON
ON
s
OFF
ON
s
1 / 1
/
0
The time period is , and the duty ratio is,
OFF ON
T T T + =
( ) ( [
OFF ON ON ON
T T T T T k + = = / / )]. The ON time interval is T k T
ON
= . It may be observed that,
for the range , the output voltage is lower than the input voltage, thus, making it a
buck converter (dcdc). For the range , the output voltage is higher than the input
voltage, thus, making it a boost converter (dcdc). For
5 . 0 0 > k
0 . 1 5 . 0 > k
5 . 0 = k , the output voltage is equal to the
input voltage. So, this circuit can be termed as a buckboost converter. Also it may be called as
stepup/down chopper. It may be noted that the inductor current is assumed to be continuous.
The range of is somewhat reduced due to the reasons given earlier. The expression for the
output voltage can be obtained by using other procedures.
k
Control Strategies
In all cases, it is shown that the average value of the output voltage can be varied. The two
types of control strategies (schemes) are employed in all cases. These are:
(a) Timeratio control, and (b) Current limit control.
Timeratio Control
In the time ratio control the value of the duty ratio, T T k
ON
/ = is varied. There are two ways,
which are constant frequency operation, and variable frequency operation.
Constant Frequency Operation
In this control strategy, the ON time, is varied, keeping the frequency ( ), or
time period
ON
T T f / 1 =
T constant. This is also called as pulse width modulation control (PWM). Two cases
with duty ratios, as (a) 0.25 (25%), and (b) 0.75 (75%) are shown in Fig. 17.4. Hence, the
output voltage can be varied by varying ON time, .
k
ON
T
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T
Loadvoltage
T
OFF
T
ON
T
OFF
T
ON
k = 0.25
k = 0.75
T
v
0
Fig. 17.4: Pulsewidth modulation control (constant frequency)
V
0
t
t
v
0
V
0
Variable Frequency Operation
In this control strategy, the frequency ( T f / 1 = ), or time period T is varied, keeping either
(a) the ON time, constant, or (b) the OFF time, constant. This is also called as
frequency modulation control. Two cases with (a) the ON time, constant, and (b) the OFF
time, constant, with variable frequency or time period (
ON
T
OFF
T
ON
T
OFF
T T ), are shown in Fig. 17.5. The
output voltage can be varied in both cases, with the change in duty ratio, . T T k
ON
/ =
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T
ON
T
OFF
(a) Constant T
ON
t
v
0
v
0
v
0
v
0
T
ON
T
OFF
T
OFF
T
ON
T
ON
Load voltage
t
t
t
(b) Constant T
OFF
T
T
T
k = 0.25
k = 0.75
k = 0.25
k = 0.75
Fig. 17.5: Output voltage waveforms for variable frequency system
There are major disadvantages in this control strategy. These are:
(a) The frequency has to be varied over a wide range for the control of output voltage in
frequency modulation. Filter design for such wide frequency variation is, therefore, quite
difficult.
(b) For the control of a duty ratio, frequency variation would be wide. As such, there is a
possibly of interference with systems using certain frequencies, such as signaling and
telephone line, in frequency modulation technique.
(c) The large OFF time in frequency modulation technique, may make the load current
discontinuous, which is undesirable.
Thus, the constant frequency system using PWM is the preferred scheme for dcdc converters
(choppers).
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Current Limit Control
As can be observed from the current waveforms for the types of dcdc converters described
earlier, the current changes between the maximum and minimum values, if it (current) is
continuous. In the current limit control strategy, the switch in dcdc converter (chopper) is turned
ON and OFF, so that the current is maintained between two (upper and lower) limits. When the
current exceed upper (maximum) limit, the switch is turned OFF. During OFF period, the current
freewheels in say, buck converter (dcdc) through the diode, , and decreases exponentially.
When it reaches lower (minimum) limit, the switch is turned ON. This type of control is
possible, either with constant frequency, or constant ON time, . This is used only, when the
load has energy storage elements, i.e. inductance, L. The reference values are load current or
load voltage. This is shown in Fig. 17.6. In this case, the current is continuous, varying between
and , which decides the frequency used for switching. The ripple in the load current can
be reduced, if the difference between the upper and lower limits is reduced, thereby making it
minimum. This in turn increases the frequency, thereby increasing the switching losses.
F
D
ON
T
max
I
min
I
max
I
min
I
T
ON
T
OFF
t
t
Fig. 17.6: Current limit control
i
0
v
0
T
In this lesson, first one in this module (#3), the three basic circuits buck, boost and buck
boost, of dcdc converters (choppers) are presented, along with the operation and the derivation
of the expressions for the output voltage in each case, assuming continuous conduction. The
different strategies employed for their control are discussed. In the next lesson second one, the
expression for the maximum and currents for continuous conduction in buck dcdc converter will
be derived.
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Module
3
DC to DC Converters
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Lesson
18
Analysis of Buck
Converter (DCDC) Circuit
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Instructional Objectives
Study of the following in respect of the buck converter (dcdc) circuit, with inductive (RL) and
battery (or back emf = E) load, assuming continuous conduction
Derivation of the expressions for the maximum and minimum load currents
Calculation of the following:
(a) the duty ratio for the limit for continuous conduction
(b) the average value and the ripple factor of the load current
(c) the harmonic components of the output voltage waveform
Introduction
In the last lesson first one in the module (#3), firstly the circuits of the various types of dc
dc converters (choppers), such as buck, boost and buckboost, were presented. Then, the
operation and the derivation of the expressions for the output voltage for the above dcdc
converters, including current waveforms, were described in detail. Lastly, the different control
strategies used were briefly discussed.
In this lesson the second one in this module, the analysis of the buck converter (dcdc) or
stepdown chopper circuit, using thyristor as a switching device, with inductive (RL) and
battery (or back emf = E) load, is presented in detail. Starting with the derivation of the
expressions for the maximum and minimum load currents, assuming continuous conduction, the
procedure for the calculation of following expressions the duty ratio for the limit of continuous
conduction, the average value and the ripple factor, of the output (load) current, and the
harmonic components of the output voltage waveform, are described in detail.
Keywords: Buck converter (dcdc), Stepdown chopper, Output (load) current maximum and
minimum values, average value, ripple factor, harmonic analysis.
Buck Converter (DCDC)
The circuit of the buck converter (dcdc) or stepdown chopper using thyristor, with
inductive (RL) and battery (or back emf = E) load, is shown in Fig. 18.1. The switch in Fig.
17.1a is replaced by a thyristor here, where the components of the load, such as R, L & E, are
also shown. The output (load) voltage and current waveforms for both
(a) discontinuous, and (b) continuous conduction are shown in Fig. 18.2.
V
0
+


+
V
s
L
Switch
A
D
F
R
LOAD
Fig. 18.1: Stepdown chopper circuit using thyristor.
K
G
+

i
0
E
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T
ON
T
t
t
t
0
0
0
V
S
v
0
i
D
i
o
I
g
(b) Continuous load current
Fig. 18.2: Two modes operation of the chopper.
T
ON
T
t
t
t
0
E
V
S
v
0
0
i
o
0
I
g
(a) Discontinuous load current
T
OFF
I
max
I
min
V
0
i
T
T
OFF
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Maximum and Minimum Values of the Load Current
The procedure for finding the maximum and minimum of the load current, assuming
continuous conduction, is described. The operation of the chopper circuit has been discussed in
the earlier lesson. There are two modes of operation. Mode 1 starts at 0 = t , when the thyristor is
turned ON, with the diode, being OFF at that time, and continues till . During this
time period, the load current increases. The induced emf in the load inductance L, is positive,
i.e., having the same polarity as that of the input voltage, opposing it. Mode 2 starts at
F
D
ON
T t =
ON
T t = ,
when the thyristor is turned OFF by auxiliary circuit (not shown in Fig. 18.1), and the diode,
turns ON at that time, as the load current starts decreasing, and the induced emf in the load
inductance, L changes polarity, with the voltage across the diode now being positive. This
continues till , end of the time period. Then the cycle repeats.
F
D
T t =
Mode 1: The equation for the load (output) current in the circuit during this time interval,
is,
ON
T t 0
E
t d
i d
L i R V
S
+ + =
0
0
or,
t d
i d
L i R E V
S
0
0
+ =
The current is the load current, same as the source current during this time interval. The values of
the load current ( ) at and
0
i 0 = t
ON
T t = , are and respectively. The expression for the
load current is,
min
I
max
I
B e A i
t
+ =
/
0
where A and B are constants, and time constant is, R L/ = .
At , 0 = t
min 0
I B A i = + =
At , = t ( ) [ ] R E V B i
s
/
0
= =
So, ( ) [ ] R E V I A
s
/
min
=
Substituting the values of A & B, the expression for the load current is,
( )
( )
/
min
/
0
1
t t s
e I e
R
E V
i
+
=
At , . So,
ON
T t =
max 0
I i =
( )
( )
/
min
/
max
1
ON ON
T T s
e I e
R
E V
I
+
=
or,
( )
( )
/ /
min max
1
ON ON
T s T
e
R
E V
e I I
=
This is the first expression obtained for mode 1 between and . Similarly, the second one
will be derived for mode 2.
max
I
min
I
Mode 2: The equation for the load (output) current in the circuit during this time interval,
is,
OFF
T t 0
E
t d
i d
L i R + + =
0
0
0 or,
t d
i d
L i R E
0
0
+ =
It may be noted here that the time ( 0 = t ) is taken here from the start of mode 2, i.e., the end of
mode 1. The current is the load current, and the current through the diode, during this time
interval. The values of the load current ( ) at
F
D
0
i 0 = t and
OFF
T t = , are and respectively.
The expression for the load current is, .
max
I
min
I
B e A i
t
+ =
/
0
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At , 0 = t
max 0
I B A i = + =
At , = t ( ) R E B i /
0
= =
So, ( ) R E I A /
max
+ =
Substituting the values of A & B, the expression for the load current is,
( )
/
min
/
0
1
t t
e I e
R
E
i
+
=
At , . So,
OFF
T t =
min 0
I i =
( )
/
max
/
min
1
OFF OFF
T T
e I e
R
E
I
+
=
or, ( )
/
min
/
max
1
OFF OFF
T T
e
R
E
I e I
=
This is the second expression obtained for mode 2 between and .
max
I
min
I
From these two expressions, the currents, and are derived as,
max
I
min
I
R
E
e
e
R
V
I
T
T
s
ON
/
/
max
1
1
or,
R
E
e
e
R
V
I
L T R
L T R
s
ON
/
/
max
1
1
, and
=
R
E
e
e
R
V
I
T
T
s
ON
1
1
/
/
min
or,
=
R
E
e
e
R
V
I
L T R
L T R
s
ON
1
1
/
/
min
Ripple content in the Load Current
As given earlier, the load (output) current varies between the maximum and minimum values
( and ). Therefore, the ripple content of the current is,
max
I
min
I
( )
( )
( )
( )
( )( )
( )
/
/ /
/
/ /
min max
1
1 1
1
1 1
T
T T
s
T
T T T
s
e
e e
R
V
e
e e
R
V
I I
OFF ON ON ON
The above expression for ripple content is independent of battery voltage or back emf (E). Using
the duty ratio, , the expression becomes, T T k
ON
/ =
( )(
( )
)
/
/ ) 1 ( /
min max
1
1 1
T
T k T k
s
e
e e
R
V
I I ,
its per unit value being,
( )
( )
( )(
( )
)
/
/ ) 1 ( /
min max
1
1 1
/
T
T k T k
s
e
e e
R V
I I
The current ( ) is taken as 1.0 pu (100%). R V
s
/
The Duty Ratio (k) for the Limit of Continuous Conduction
The current waveforms for both continuous and discontinuous conduction are shown in Fig.
18.2. From the waveforms, it is observed that, for a low value of , or duty ratio, k , time
period,
ON
T
T being kept constant, the turnoff time, is large. The output current, may go to
zero during this interval, depending on the circuit parameters. Therefore, the limit of continuous
conduction is reached, when the minimum current, goes to zero. So,
OFF
T
0
i
min
I
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0
1
1
/
/
min
=
=
R
E
e
e
R
V
I
T
T
s
ON
or, g
V
E
e
e
s
T
T
ON
=
1
1
/
/
where ( )
s
V E g / =
So, the duty ratio for limit of continuous conduction is,
( ) [ ] 1 1 log ) / ( ) / (
/
+ = =
T
e ON
e g T T T k
The output (load) current is continuous, if the actual duty ratio, is more than the above duty
ratio, k , and it becomes discontinuous, if is lower than the above duty ratio, k .
k
k
The Average Value of the Output Current
The average value of the output (load) current for continuous conduction (Fig. 18.2b) is
obtained as , as the average value of the output voltage is . This is,
because the average value of over the time period, T is zero.
R E V k I
s av
/ ) ( =
s
V k
) / ( dt di L
This value can also be written as,
av D av T
T T T T
av
I I dt t i
T
dt t i
T
dt t i dt t i
T
I
OFF ON OFF ON
) ( ) ( ) (
1
) (
1
) ( ) (
1
0
02
0
01
0
02
0
01
+ =
=
,
where and are the output (load) currents in the time intervals,
01
i
02
i 0 < < t T
ON
and 0 < < t T
OFF
(the time ( ) is taken as the beginning of OFF period (mode 2)) respectively. If the
expression is derived by substituting the currents, & , its value comes out to be the same as
given earlier. The average values of the currents in the thyristor
0 = t
01
i
02
i
( )
av T
I and diode ( , can also
be computed by using the expressions for the currents separately. These two expressions are not
included here, but are available in text book. All these values of the currents can also be obtained
by using other procedure.
)
av D
I
Fourier Analysis of the Output Voltage Waveform
The output (load) voltage waveform for continuous conduction is shown in Fig. 18.2.b. This
voltage is periodic in nature and also independent of the parameters of the load. The symbols,
including some described earlier, are given here.
0
v = Instantaneous value of the output (load) voltage
s
V = Source (input) voltage (constant)
0
V = Average value of the output voltage
OFF ON
T T T + = = Time period of the thyristor chopper (stepdown)*
ON
T = Time interval for which the thyristor is ON*
ON OFF
T T T = = Time interval for which the thyristor is OFF*
T f / 1 = = Frequency (Hz) for the thyristor chopper (stepdown)*
f 2 = = Angular frequency (rad/s)
t = = Angle (rad)
2 = T = Angle (rad) for time period, T
n
a & are the maximum values of the sine and cosine components of the harmonics of order n,
present in the output voltage waveform respectively.
n
b
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n
c &
n
are the maximum value (amplitude), and phase angle, of n
th
harmonic
component
respectively.
The relationships are
2 2
n n n
b a c + = , and , ) / ( tan
1
n n n
a b
=
and the other relationships are
n n n
c a cos = and
n n n
c b sin = .
The rms value of n
th
harmonic
component 2 /
n
c =
* It may be noted that, when the thyristor (device) in the stepdown chopper (Fig. 18.1), or buck
converter (dcdc), is ON, or conducting, the diode, is not conducting (OFF), and vice versa,
i.e., when the thyristor (device) is OFF, or not conducting, the diode, is conducting (ON).
F
D
F
D
The output (load) voltage waveform for one time period T , is,
s
V v =
0
for ; for 0 < < t T
ON
0
0
= v
ON
T t T < <
In terms of the Fourier components, the expression is,
0 0 0
1 1
( sin cos ) sin ( )
n n n
n n
v V a n b n V c n
n
= =
= + + = + +
where,
= = =
ON
T
k
s
s
T
n
n
n
V
d n V d n v a
0
0
2
0
0
cos ) ( sin
1
) ( sin
1
( ) ( ) ) ( sin
2
2 cos 1
2
k n
n
V
k n
n
V
s s
=
( ) k
n
V
n
n
V
d n V d n v b
s
T
k s
s
T
n
ON
= = =
( ) ) (cos ) (sin
2
2 sin k n k n
n
V
k n
n
V
s s
=
) (sin
2
k n
n
V
c
s
n
=
1
tan (cot ) ( 2) ( )
n
nk nk
= =
The average value (dc) is , which has been derived in lesson #17 (module 3).
s
V k V =
0
Substituting the above values of &
n
c
n
,
( ) ) ) ( ) 2 ( ( sin ) (sin
2
1
0 0
k n n k n
n
V
V v
n
s
+ =
=
[ ] ( ) ( )
0 0
1 1
2 2
(sin ) cos ( ) (sin ) cos[ ( )]
s s
n n
V V
V nk n n k V nk n
n n
= =
= + = +
k The
maximum value of the fundamental component is, ( ) ) (sin ) 2 (
1
k V c
s
= ,
and its phase angle (rad) is, ) ( ) 2 (
1
k = .
The magnitude of the maximum (or rms) value of the harmonic components decreases as its
order (n) increases.
The rms value of the waveform is, ( )
=
=
+ = + =
1
2
2
1
2
0
1
2 2
0
) ( ) ( ) 2 / ( ) (
n
n
n
n or
c V c V V
The rms value is computed as,
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s s
ON
T
s r
V k V
T
T
dt V
T
V
ON
= =
=
0
2
0
) (
1
It can be observed that the amplitude of the harmonic component depends on the order of the
harmonic, n and also on the duty ratio, k. The maximum value of the n
th
harmonic component
occurs, when sin ( ) 1 nk = , and its value (V) is,
n
V
n
V
s s
637 . 0 2
=
The value of the angle for the above condition, i.e., at which the maximum value of the
magnitude of the n
th
harmonic component of the output voltage occurs, is,
) 2 / ( 2 ) 2 / ( ) 1 4 ( + = + = m m k n , or
2
1
2 2 / ) 1 4 ( + = + = m m k n or, ( ) 5 . 0 2 + m
Firstly, the average value or dc component and the rms values of all harmonic components,
of the output (load) voltage, are computed as per the formula given earlier. It may be noted that,
the rms values of only a few harmonic components need be computed, because the rms values
decrease, as the order of harmonic increases (having an inverse relationship with it), as given
earlier. Then, using the expression for the rms value, it (rms value) is computed. Finally, it can
be checked from the expression for the rms value given earlier.
As first example, the case of fundamental frequency ( 1 n = ) is taken up. The value of duty
ratio is (
1
2
0.5( ) k = ) as ( ), at which the magnitude of the output voltage is maximum at
the above frequency. If the third harmonic (
1.0 k <
3 n = ) is chosen as another example, more than one
value, in this case, three values of the duty ratio (
5 1
6
0.167( ) & 0.833( ) k
6
= ), and also the
previous value of (
1
2
0.5( ) k = ), as 1.0 k < , are obtained. If first two values of k are substituted,
the results obtained, using the ascending order, are sin ( / 2) 1 = and
sin (5 / 2) sin ( / 2) 1 = = . But, if the value, (
1
2
0.5( ) k = ) is substituted, the results obtained is
sin (3 / 2) sin ( / 2) sin ( / 2) 1
n
c = = = = 2) . For this value in this case, 3 (3 / k = or
( / 2) . So, the set of values would be 3 (2 (3 / 2 k m )) = + or (2 ( / 2)) m . Earlier, the
value of is chosen as positive only, assuming that its angle would take care of the sign, i.e.,
for ,
n
c
1
n
c = + 0
n
= , and for , 1
n
c = 180 ( )
n
= . The angle (
n
) can be obtained by using the
sign of two components, . But if a close look at the formula of is taken, it can have
both +ve and ve values, i.e.,
&
n
a b
n n
c
sin ( ) 1
n
c nk = = , being square root of a +ve quantity. The
value would now be,
1
2
(4 1) / 2 2 nk m m = = or, ( 2 0. m 5 ). So, for ( ), three values of
duty ratio, as given earlier, are obtained. Similarly, for any other odd harmonic ( ),
the duty ratios can be computed. It may also be observed that, for the duty ratio of (
3 n =
k 2 1 n m = +
1
2
0.5( ) k = ),
the magnitudes of the output voltage at all odd harmonics are maximum.
Now, for even harmonics ( 2 n m = ), the duty ratios for which the magnitude of the
component of output voltage is maximum, are obtained. For second harmonic ( 2 n = ), two
values of duty ratio obtained using the formula (
1
2
2 2 k m = ) are,
3 1
4 4
0.25( ) & 0.75( ) k = , as . If these two values of are substituted, the results obtained,
using the ascending order, are
1.0 k < k
sin ( / 2) 1 = and
sin (3 / 2) sin ( / 2) 1 = = . For fourth harmonic ( 4 n = ), the duty ratios obtained are,
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3 5 1
8 8 8
0.125( ), 0.375( ), 0.625( ) & 0.875( ) k =
7
8
, as 1.0 k < . Similarly, for the rms value of any other
even harmonic to be maximum (highest), the duty ratios can be computed. To obtain the
maximum value of average or dc component as per formula given earlier, the duty ratio is
( ), it being an ideal one. In this case, the switch or the device is always ON in the time
period ( ), with the output voltage being constant, and also same as the average value, which
is equal to the input (source) voltage. In the ideal case, no harmonic component, including
fundamental one, is present in the output voltage. But the duty ratio in normal case, for buck
converter (dcdc) or stepdown chopper (thyristor) circuit is (
1.0 k =
0 T
1.0 k ), due to the turnoff time
requirement of the switching device used. For this case, the rms and average values are nearly
equal, but the rms value is slightly higher than the average value. Both the above values are also
nearly maximum. The ripple content is very low, with the rms values of the harmonic
components, starting from fundamental, also being very low. All these can be checked from the
formula.
To eliminate a given harmonic or a set of harmonics in the output voltage waveform, the
condition to be satisfied is, 0 sin = k n , for which the value of the angle is m k n = , or
. The case of even ( ) harmonics, starting from second ( ), is taken up first.
The duty ratio required is , as
m k n = 2 n = m 2 n =
5 . 0 = k 1.0 k < , for the elimination of second harmonic
component. To eliminate fourth ( 4 n = ) harmonic component, two more values of duty ratio
(
3 1
4
0.25( ) & 0.75( ) k =
4
), including the earlier one ( 5 . 0 = k ), as 1.0 k < , are required. It may be
noted that, with the duty ratio ( , all even harmonic components are eliminated. To make
the average value or dc component zero (0), the duty ratio required is ( ). But this is an
ideal case, in which the switch or the device is OFF. In normal case, duty ratio required is very
small ( ), due to requirement of both turnon and turnoff times of the switching device
used. For this case, the rms and average values are nearly equal, but the rms value is slightly
higher than the average value. Both the above values are also nearly minimum. The ripple
content is very low, with the rms values of the harmonic components, starting from fundamental,
also being very low. All these can be checked from the formula. Now, the case of the elimination
of odd ( ) harmonic components is described. If third (
0.5 k = )
1
0.0 k =
0.0 k
2 n m = + 3 n = ) harmonic is to be
eliminated, two values of duty ratios required are (
1 2
3 3
0.333( ) & 0.667( ) k = ), as 1.0 k < .
Similarly, for any other (odd or even) harmonic component to be eliminated, the duty ratios can
be computed.
The rms value of the n
th
harmonic component of the output (load) current is,
( )
n
n
n
Z
c
I
2 /
= , where the load impedance for n
th
harmonic is
2 2
) ( L n R Z
n
+ = .
As stated earlier, the rms value of the harmonic components of the output voltage decreases and
also is inversely proportional to n, as the order of the harmonic (n) is increased. The impedance
at the harmonic frequency ( ) increases, and also is nearly proportional to n, if the load
resistance (R) is assumed to be much smaller than the inductive reactance (
f n
L f n 2 ), as the
order of the harmonic is increased. So, the rms value of the n
th
harmonic component of the output
current decreases at a faster rate, and also can be stated as being inversely proportional (nearly)
to , with the increase in the order of the harmonic. If R is very small, and can be neglected, as
compared to the inductive reactance, the rms value of the n
2
n
th
harmonic component of the output
current is inversely proportional to , i.e. proportional to ( ).
2
n
2
/ 1 n
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The harmonic content of the output voltage waveform is the ac ripple voltage ( ), which
can be easily computed as shown here, without computing the harmonic components. Its rms
value is defined as
r
V
2
0
2
0
) ( ) ( V V V
r r
= , the other symbols having been defined earlier. The
average value of the output voltage ( ) is shown in Fig. 18.2b. If the Xaxis is shifted to the
average value, the remaining part is the ac ripple voltage, having both positive and negative
values in a cycle. The expression for ac ripple voltage is obtained as, after substituting the
expressions of two voltages given earlier,
0
V
2 2 2 2
) ( ) ( k k V V k V k V
s s s r
= =
The ripple factor (RF) is defined as the ratio of ac ripple voltage to the average value, and is
obtained as,
RF
k
k
V
V
r
= =
1
0
It may be noted that the ac ripple voltage, in terms of rms values of all harmonic components,
may also be computed as,
( )
=
=
= =
1
2
2
1
1
2
) ( ) 2 / (
n
n
n
n r
c c V
This value is same as computed by the expression given earlier.
In this lesson the second one in this module, the analysis of the analysis of the buck
converter (dcdc) or stepdown chopper circuit, using thyristor as a switching device, with
inductive (RL) and battery (or back emf = E) load, is presented in detail The procedure for the
derivation of following expressions the maximum and minimum output (load) currents,
assuming continuous conduction, the duty ratio for the limit of continuous conduction, the
average value and the ripple factor, of the output current, and the harmonic components of the
output voltage waveform, are described in detail. Starting with the next lesson the third one in
this module, the operation of the additional circuits needed for commutation in thyristorbased
choppers, with relevant waveforms, will be taken up in detail.
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Module
3
DC to DC Converters
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Lesson
19
Commutation of
ThyristorBased Circuits
PartI
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This lesson provides the reader the following:
(i) Requirements to be satisfied for the successful turnoff of a SCR
(ii) The turnoff groups as per the General Electric classification
(iii) The operation of the turnoff circuits
(iv) Design of a SCR commutation circuit
A thyristor can be turned ON by applying a positive voltage of about a volt or a current of a
few tens of milliamps at the gatecathode terminals. However, the amplifying gain of this
regenerative device being in the order of the 10
8
, the SCR cannot be turned OFF via the gate
terminal. It will turnoff only after the anode current is annulled either naturally or using forced
commutation techniques. These methods of turnoff do not refer to those cases where the anode
current is gradually reduced below Holding Current level manually or through a slow process.
Once the SCR is turned ON, it remains ON even after removal of the gate signal, as long as a
minimum current, the Holding Current, I
h
, is maintained in the main or rectifier circuit.
Fig. 3.1 Turnoff dynamics of the SCR
In all practical cases, a negative current flows through the device. This current returns to zero
only after the reverse recovery time t
rr
, when the SCR is said to have regained its reverse
blocking capability. The device can block a forward voltage only after a further t
fr
, the forward
recovery time has elapsed. Consequently, the SCR must continue to be reversebiased for a
minimum of t
fr
+t
rr
=t
q
, the rated turnoff time of the device. The external circuit must therefore
reverse bias the SCR for a time t
off
>t
q
. Subsequently, the reapplied forward biasing voltage must
rise at a dv/dt <dv/dt (reapplied) rated. This dv/dt is less than the static counterpart. General
Electric has suggested six classification methods for the turnoff techniques generally adopted
for the SCR. Others have chosen different classification rules.
SCRs have turnoff times rated between 8  50 secs. The faster ones are popularly
known as 'Inverter grade' and the slower ones as 'Converter grade' SCRs. The latter are available
at higher current levels while the faster ones are expectedly costlier.
Classification of forced commutation methods
The six distinct classes by which the SCR can be turned off are:
Class A Self commutated by a resonating load
Class B Self commutated by an LC circuit
Class C C or LC switched by another load carrying SCR
Class D C or LC switched by an auxiliary SCR
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Class E An external pulse source for commutation
Class F AC line commutation
These examples show the classes as choppers. The commutation classes may be used in practice
in configurations other than choppers.
Class A, Self commutated by resonating the load
Fig. 3.2 A resonant load commutated SCR and the corresponding waveforms
When the SCR is triggered, anode current flows and charges up C with the dot as positive. The
LCR form a second order underdamped circuit. The current through the SCR builds up and
completes a half cycle. The inductor current will then attempt to flow through the SCR in the
reverse direction and the SCR will be turned off.
The current may be expressed as
Rs Ls LRCs
RCs
V
RCs
R
Ls s
V s I
+ +
+
=
+
+
=
2 3
1
)
1
(
1
) (
The solution of the above equation is of the form
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=
= = = =
+ =
1 ) sin(
1
) (
2 tan , 1 , ,
2
1
,
) sin(
1
1
1 ) (
2
2
2
1 2
2
2
t e V t v
and
RC
C
L
C
L
R
where
wt e
R
V
t i
RC t n
n n
RC t n
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The capacitor voltage is at its peak when the SCR turns off and the capacitor discharges into
the resistance in an exponential manner. The SCR is reversebiased till the capacitor voltages
returns to the level of the supply voltage V.
Class B, Self commutated by an LC circuit
The Capacitor C charges up in the dot as positive before a gate pulse is applied to the
SCR. When SCR is triggered, the resulting current has two components.
The constant load current I
load
flows through R  L load. This is ensured by the large
reactance in series with the load and the freewheeling diode clamping it. A sinusoidal current
flows through the resonant LC circuit to chargeup C with the dot as negative at the end of the
half cycle. This current will then reverse and flow through the SCR in opposition to the load
current for a small fraction of the negative swing till the total current through the SCR becomes
zero. The SCR will turn off when the resonantcircuit (reverse) current is just greater than the
load current.
The SCR is turned off if the SCR remains reversed biased for t
q
>t
off
, and the rate of rise
of the reapplied voltage <the rated value.
Fig. 3.3 Class B, LC turnoff
Problem #1
A Class B turnoff circuit commutates an SCR. The load current is constant at 10 Amps.
Dimension the commutating components L and C. The supply voltage is 100VDC.
Soln # 1
The commutating capacitor is charged to the supply voltage =100 V
The peak resonant current is,
L
C
V i
peak
=
Assuming,
load peak
I i . 5 . 1 ~
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0225 . 0 )
100
15
(
2
= =
L
C
The SCR commutates when the total current through it reaches zero.This corresponds to 0.73
rads after the zero crossing of the resonant current. The capacitor voltage at that instant is 75
volts. After the SCR turns off, the capacitor is charged linearly by the load current.
If the SCR is to commutate at twice this load current, for a rated "Inverter grade' SCR turn
off time of 20 secs,
C t I
load
. 75 ). . 2 ( =
F
75
20 . 20
= C
F 15 33 . 15 =
700 667
0225 . 0
= =
C
L
H
33 . 1
15
20
= =
dt
dV The reapplied forward voltage has a volts/sec rise.
It can be observed that if the peak of the commutating current is just equal to the load
current, the turnoff time would be zero as the capacitor would not be able to impress any
negative voltage on the SCR.
Class C, C or LC switched by another loadcarrying SCR
This configuration has two SCRs. One of them may be the main SCR and the other auxiliary.
Both may be load current carrying main SCRs. The configuration may have four SCRs with the
load across the capacitor, with the integral converter supplied from a current source. Assume
SCR
2
is conducting. C then charges up in the polarity shown. When SCR
1
is triggered, C is
switched across SCR
2
via SCR
1
and the discharge current of C opposes the flow of load current
in SCR
2
.
Fig. 3.4 Class C turnoff, SCR switched off by another loadcarring SCR
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Class D, LC or C switched by an auxiliary SCR
Example 1
The circuit shown in Figure 3.3 (Class C) can be converted to Class D if the load current is
carried by only one of the SCRs, the other acting as an auxiliary turnoff SCR. The auxiliary
SCR would have a resistor in its anode lead of say ten times the load resistance.
Fig. 3.5 Class D turnoff. Class D commutation by a C (or LC) switched by an
Auxiliary SCR.
Example 2
SCR
A
must be triggered first in order to charge the upper terminal of the capacitor as
positive. As soon as C is charged to the supply voltage, SCR
A
will turn off. If there is substantial
inductance in the input lines, the capacitor may charge to voltages in excess of the supply
voltage. This extra voltage would discharge through the diodeinductorload circuit.
When SCR
M
is triggered the current flows in two paths: Load current flows through the
load and the commutating current flows through C SCR
M
LD network. The charge on C is
reversed and held at that level by the diode D. When SCR
A
is retriggered, the voltage across C
appears across SCR
M
via SCR
A
and SCR
M
is turned off. If the load carries a constant current as
in Fig. 3.4, the capacitor again charges linearly to the dot as positive.
Problem #2
A Class D turnoff circuit has a commutating capacitor of 10 F. The load consists of a clamped
inductive load such that the load current is reasonably constant at 25 amperes. The 'Inverter
grade' SCR has a turnoff time of 12 secs. Determine whether the SCR will be satisfactorily
commutated. Also dimension the commutating inductor. The supply voltage is 220 VDC.
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Soln #2
The capacitor is initially charged to the supply voltage 220 V at the end of the conduction period
of SCR
A
.
When SCR
M
is triggered, the 25 Amps load current and the LC ringing current flows
through it. Peak current through SCR is
Amps
L
C
i
peak
220 25+ =
Selecting L such that i
peak
~1.5 . load current,
mH L
L
C
1 . 3
0568 . 0
220 . 2
25
=
= =
Assuming that the capacitor charges to 70% of its original charge because of losses in the
C SCR
M
LD network, and it charges linearly when SCR
A
is again triggered,
( )
s t
t I
q
load
q
sec 6 . 61 25 / 1540
10 . 1540 10 220 . 7 . 0 10 .
6 6
= =
= =
The SCR can therefore be successfully commutated.
The maximum current that can be commutated with the given Capacitor at the 220 V
supply voltage is
For the 25 Amps load current the capacitor just enough would have a rating of
Amps I
load
128 12 / 1540 = =
F t I C
q load
0 . 2 95 . 1 154 / ) 12 . 25 ( ) 220 . 7 . 0 /( . = = =
If the supply voltage is reduced by a factor K, the required capacitor rating
increases by the same factor K for the same load current.
Class E External pulse source for commutation
The transformer is designed with sufficient iron and air gap so as not to saturate. It is capable of
carrying the load current with a small voltage drop compared with the supply voltage.
When SCR1 is triggered, current flows through the load and pulse transformer. To turn SCR
1
off
a positive pulse is applied to the cathode of the SCR from an external pulse generator via the
pulse transformer. The capacitor C is only charged to about 1 volt and for the duration of the
turnoff pulse it can be considered to have zero impedance. Thus the pulse from the transformer
reverses the voltage across the SCR, and it supplies the reverse recovery current and holds the
voltage negative for the required turnoff time.
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Fig. 3.6 Class E, External pulse commutation
LOAD
SCR
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Class F, AC line commutated
Fig. 3.7 Class F, natural commutation by supply voltage
If the supply is an alternating voltage, load current will flow during the positive half
cycle. With a highly inductive load, the current may remain continuous for some time till the
energy trapped in the load inductance is dissipated. During the negative half cycle, therefore, the
SCR will turn off when the load current becomes zero 'naturally'. The negative polarity of the
voltage appearing across the outgoing SCR turns it off if the voltage persists for the rated turn
off period of the device. The duration of the half cycle must be definitely longer than the turn
off time of the SCR.
The rectifier in Fig.3.6 is supplied from an single phase AC supply. The commutation
process involved here is representative of that in a three phase converter. The converter has an
input inductance L
s
arising manly out of the leakage reactance of the supply transformer.
Initially, SCRs Th
1
and Th
1'
are considered to be conducting. The triggering angle for the
converter is around 60
0
. The converter is operating in the continuous conduction mode aided by
the highlyinductive load.
When the incoming SCRs, Th
2
and Th
2'
are triggered, the current through the incoming
devices cannot rise instantaneously to the load current level. A circulating current I
sc
builds up in
the shortcircuited path including the supply voltage, V
s
L
s
Th
1'
 Th
2
and V
s
 L
s
Th
2'
Th
1
paths.
This current can be described by:
cos
) cos(
cos
) 90 sin(
0
s
s
s
s
s
s
s
s
sc
L
V
L
t V
L
V
L
t V
I + = +
=
where the triggering angle and I
sc
and V
s
as shown in Fig. 3.6.
This expression is obtained with the simplifying assumption that the input inductance
contains no resistances. When the current rises in the incoming SCRs, which in the outgoing
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ones fall such that the total current remains constant at the load current level. When the current in
the incoming ones reach load current level, the turnoff process of the outgoing ones is initiated.
The reverse biasing voltage of these SCRs must continue till they reach their forward blocking
state. As is evident from the above expression, the overlap period is a function of the triggering
angle. It is lowest when ~90
0
. These SCRs being 'Converter grade', they have a larger turnoff
time requirement of about 3050 secs.
The period when both the devices conduct is known as the 'overlap period'. Since all
SCRs are in conduction, the output voltage for this period is zero. If the 'fullycontrolled'
converter in Fig. 3.7 is used as an inverter with triggering angles >90
0
, the converter triggering
can be delayed till the 'margin angle' which includes the overlap angle and the turnoff time of
the SCR  both dependent on the supply voltages.
Rate of rise of forward voltage, dv/dt
The junctions of any semiconductor exhibit some unavoidable capacitance. A changing
voltage impressed on this junction capacitance results in a current, I =C dv/dt. If this current is
sufficiently large a regenerative action may occur causing the SCR to switch to the on state. This
regenerative action is similar to that which occurs when gate current is injected. The critical rate
of rise of offstate voltage is defined as the maximum value of rate of rise of forward voltage
which may cause switching from the offstate to the onstate.
Since dv/dt turnon is nondestructive, this phenomenon creates no problem in applications in
which occasional false turnon does not result in a harmful affect at the load. Heater application
is one such case. However, at large currents where dv/dt turnon is accompanied by partial turn
on of the device area a high di/dt occurs which then may be destructive.
The majority of inverter applications, however, would result in circuit malfunction due to
dv/dt turnon. One solution to this problem is to reduce the dv/dt imposed by the circuit to a
value less than the critical dv/dt of the SCR being used. This is accomplished by the use of a
circuit similar to those in Figure 3.8 to suppress excessive rate of rise of anode voltage. Z
represents load impedance and circuit impedance. Variations of the basic circuit is also shown
where the section of the network shown replaces the SCR and the RC basic snubber.
Since circuit impedances are not usually well defined for a particular application, the values
of R and C are often determined by experimental optimization. A technique can be used to
simplify snubber circuit design by the use of nomographs which enable the circuit designer to
select an optimized RC snubber for a particular set of circuit operating conditions.
Another solution to the dv/dt turnon problem is to use an SCR with higher dv/dt turnon
problem is to use an SCR with higher dv/dt capability. This can be done by selecting an SCR
designed specially for high dv/dt applications, as indicated by the specification sheet. Emitter
shorting is a manufacturing technique used to accomplish high dv/dt capability.
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Questions
Fig. 3.8 dv/dt supression circuits
#1 For a Class D turnoff SCR, the load consists of a resistance only. If the supply voltage and
SCR turnoff ratings are as in Problem #1 calculate the required value of the commutating
capacitor.
Ans: (Hints): The capacitor would now charge in an exponential manner. The time it takes to
discharge from its reverse charged state once SCR
A
is triggered is the circuit turnoff time which
must be in excess of the rated 12 secs.
#2 For a Class F converter, will the overlap period rise with the leakage inductance of the
converter? What happens to the output voltage?
Ans: Yes. The overlap time is directly related to the commutating inductance. The output
voltage decreases. In fact, this inductor limits the maximum output current of the converter. The
input current maximum would be as for a shorted network with the leakage inductance only
present.
#3 Can the output DC voltage be controlled in the above circuits?
Ans: Yes. Most of the above circuits are also called 'forced commutated' DCDC chopper
circuits.
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Module
3
DC to DC Converters
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Lesson
20
Commutation of
ThyristorBased Circuits
PartII
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This lesson provides the reader the following:
(i) Practical significance of commutation
(ii) Limitations of line commutation
(iii) Ability to determine commutation interval
(iv) Insight to different methods of commutation
(v) Consequences of the commutating methods on device stresses
20.1 Introduction
The commutation process plays an important role in the operation and control of both
naturally commutated (or line commutated) and forced commutated SCR based converters.
These converters may be either ACDC, DCDC or DCAC converters. The ACDC Phase
Angle Converter, (PAC) continues to be used in much high power and very high power
converters where the application is noncritical or the nonstateoftheart is preferred for
operational advantages. The following section discusses commutation with respect to this
application.
Fig. 20.1 Top: A threephase Phase Angle Converter; bottom: The input
threephase voltage waveforms
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20.2 Commutation in PAC
A three phase PAC is shown in Fig. 20.1. Nominally balanced three phase voltages V
R
,
V
Y
and V
B
are connected to the three legs of the converter via three inductances LS, which can
be considered to represent the leakage reactance of the supply transformer. At any instant, two
devices are conducting, say SCR
1
and SCR
6
at the time instant indicated by the dashed line in
Fig, 20.1, bottom. At that instant, phase voltage V
R
is most positive and V
B
most negative.
Fig. 20.2 Significant voltage and current waveforms of a single phase converter
highlighting the overlap instants and the corresponding converter terminal and
output voltages
Subsequently, at the crossover point, V
Y
becomes most negative and SCR
2
is more forward
biased with respect to SCR
6
. The incoming SCR does not take the full load current I
L
, nor does
the outgoing SCR turnoff immediately. There ensues an overlap period when three SCRs
conduct for a transient period. It is evident that with the simultaneous conduction of SCR
2
and
SCR
6
there is a short circuit at the converter terminals with the short circuit current I
SC
being
limited by the perphase series inductances L
S.
Line voltage V
YB
drives this current. With no
delay in triggering (as if the SCRs are all replaced by diodes) the SCRs, they would be triggered
60
0
after the zero crossing of the corresponding line voltage. The triggering on this line voltage is
delayed by the trigger angle from this 60
0
point.
There are a few significant effects of the commutation process when three devices
conduct. The voltage waveforms at the output and at the converter input terminals reflect the
commutation process. AllSCR (fullycontrolled) converters, which are capable of operating with
trigger angles between 0
0
to 180
0
ideally, are restricted in the inverter mode to operate within
the marginangle. This angle is of the order of 160
0
and the output voltage is limited.
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20.3 Input voltage waveform distortion
A singlephase converter, Fig 20.2 is considered to illustrate this. A fourSCR fullycontrolled
converter operates into a load, which draws a constant current. The AC source includes the series
(leakage) inductance L
S
. Waveforms are shown for (i) no overlap case (when L
S
= 0) and (ii) for
a finite value of L
S
causing an overlap. It is evident from waveforms of I
SCR 1,1
I
SCR 2,2
that they
take a finite time to rise and fall. In the intervening period all four SCRs are ON. The current in
the incoming device rises till it equals the load current I
L
while that in the out going one falls to
zero. All conducting SCRs can be considered to be short circuits and consequently the output
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