Академический Документы
Профессиональный Документы
Культура Документы
= ) (
] 1 )[ ( ) (
L P
C R
t
SS DD CL
e V V t V
=
The energy required to charge the capacitor is
dt t V t i E
CL CL C
= ) ( ) (
2
) (
2
1
SS DD L
V V C =
The above equation only depends on C
L
and not on R
P
. The current through and voltage
across the pull up resistor are
) ( ) ( t i t i
CL P
=
L P
C R
t
P
Ve t V
= ) (
The energy required to charge the capacitor is
dt t V t i E
p p R
= ) ( ) (
2
) (
2
1
SS DD L
V V C =
Once again the value of Rp (pull-up resistance) drops from energy formula
The energy consumed in discharging the capacitor can be calculated in same way and is
2
) (
2
1
SS DD L
V V C =
The total charging and discharging cycle consumes
2
) (
SS DD L
V V C
Therefore, the power consumed by the circuit depends on frequency of output changes
The clock frequency is f=1/t. so the total power consumption is
2
) (
SS DD L
V V fC
Therefore, power consumption is depends on clock frequency because must power is
consumed while the outputs are changing
Speed power product (power-delay product)
o Ignore leakage current and consider speed and power for single inverter transisiton
o SP/SPP = 1/f *P = CV
2
o This result suggests an important method for power consumption reduction is by
reducing the power supply voltage
Voltage scaling
o The power consumption is reduced by reducing the power supply voltage and adding
parallel logic gates
o In this method, the power consumption shrinks quickly than the circuit delay so
voltage scaling is a powerful technique
Yield:
chips of number Total
wafer on chips good of Number
Y =
Depends on
o Technology
o Chip area
o Layout
Seeds model
o
AD
e Y
= Where A Chip area, D Defect density
o This model is used for large chips and yields less than 30%
Murphys model
o
2
1
(
=
AD
e
Y
AD
o This model is used for small chips and yields greater than 30%
Recent generalized model
o
i
C
N
i j
ij i j
P D A Y
=
|
|
\
|
+ =
1
1
Where i i
th
type of defect
j j
th
module
P
ij
Probability of i
th
defect to cause a fault in j
th
area
C
i
Constant relating to the density of i
th
type of defect
Yield decreases dramatically as the area of chip is increased
Yield enhancements
Space out wires to reduce risk of short circuits and to reduce capacitance
At least two vias for every connection to avoid open circuits
Use wider-than-min transistors
Avoid non rectangular shapes ( angle, circles)