VLSI Design For Testability VLSI Design For Testability

Lecture 2: Fault Models, Detection and Lecture 2: Fault Models, Detection and
Simulation Simulation
Instructor: Shianling Wu
Director,
NE USA, European, & Asian Operations
SynTest Technologies, Inc.
Fall 2005
Acknowledgement to Contributors:
V. Agrawal (Auburn Univ), M. Bushnell (Rutgers Univ), C. Stroud (Auburn Univ.)
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Outline
l Fault Modeling
l Simulation (Logic, True Value)
l Fault Simulation
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Fault Modeling
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Defects, Faults and Failures
l Defects : Imperfection or flaw that occurs
within silicon.
l Faults : Representation of a defect.
l Failures : Non-performance of the intended
functions of the system.
l Example :
A physical short is considered a Defect.
A physical short resulting in stuck-at
behavior might be modeled as a stuck-at-
1/0 Fault.
Non-performance of the system due to
error is Failure.
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l Why model faults?
l Some real defects in VLSI and PCB
l Common fault models
l Stuck-at faults
l Single stuck-at faults
l Fault equivalence
l Fault dominance and checkpoint theorem
l Classes of stuck-at faults and multiple faults
l Transistor faults
l Summary
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Why Model Faults?
l Model the effect of a defect
l Real defects (often mechanical) too numerous and
often not analyzable
l Easier to compute than Real Defects
A fault model identifies targets for testing
A fault model makes analysis possible
Effectiveness measurable by experiments
Required for deterministic Automatic Test Pattern
Generation (ATPG)
l I/O function tests inadequate for manufacturing
(functionality versus component and interconnect
testing)
l Figure of merit quality
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Fault models Considerations
Permanent vs. Temporary
Single vs. Multiple
Combinational vs. Sequential
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Some Real Defects in Chips
Processing defects
Missing contact windows
Parasitic transistors
Oxide breakdown
. . .
Material defects
Bulk defects (cracks, crystal imperfections)
Surface impurities (ion migration)
. . .
Time-dependent failures
Dielectric breakdown
Electromigration
. . .
Packaging failures
Contact degradation
Seal leaks
. . .
Ref .: M. J . How es and D. V. Mor gan, Reliability and Degradation -
Semiconductor Devices and Circuits, Wi l ey, 1981.
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Observed Printed Circuit Board
(PCB) Defects
Def ec t c l asses
Shor t s
Opens
Mi ssi ng c omponent s
Wr ong c omponent s
Rever sed c omponent s
Bent l eads
Anal og spec i f i c at i ons
Di gi t al l ogi c
Per f or manc e (t i mi ng)
Oc c ur r enc e f r equenc y (%)
51
1
6
13
6
8
5
5
5
Ref .: J . Bat eson, In-Circuit Testing, Van Nost r and Rei nhol d, 1985.
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Common Fault Models
l Single stuck-at faults
l Transistor open and short faults
l Memory faults
l PLA faults (stuck-at, cross-point, bridging)
l Functional faults (processors)
l Delay faults (transition, path)
l Analog faults
l For more examples, see Section 4.4 (p. 60-70) of
the book,
l Etc.
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Single Stuck-at Fault
l Three properties define a single stuck-at fault
l Only one line is faulty
l The faulty line is permanently set to 0 or 1
stuck-at-0 (s-a-0) or stuck-at-1 (s-a-1)
l The fault can be at an input or output of a gate or circuit
element
l Has been proven effective in finding defects over
the years
l Requires a test pattern to detect the stuck-at
voltage and propagate the difference to the
primary output
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Gate Level Stuck-at Fault Model
l Gate inputs or outputs can be:
Stuck-at-0 (sa0)
l as if input or output were disconnected and tied low to Vss
Stuck-at-1 (sa1)
l as if input or output were disconnected and tied high to Vdd
fault site denoted by X with sa0/sa1
l Note: there is no feedback of fault value from fault site!
A
B
Z
x
sa1
A
B
Z
x
sa0
A Z
x
sa0
A Z
x
sa1
A
B
Z
Vdd
A
B
Z
Vss
A Z
Vss
A Z
Vdd
Input stuck-at-1 Input stuck-at-0 Output stuck-at-1 Output stuck-at-0
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Single Stuck-at Fault
l Example: An AND gate has 3 fault sites ( ) and 6
single stuck-at faults
s-a-0
Among 4 vec t or s (pat t er ns),
w hi c h t est vec t or DETECTS z s-a-0 f aul t ?
Good c i r c ui t val ue
1
(0)
Faul t y c i r c ui t val ue
1
0
0
0
0
1
1
1
a
b
z X
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Single Stuck-at Fault
l Example: XOR circuit has 12 fault sites ( ) and
24 single stuck-at faults
1
0(1)
1
a
b
c
d
e
f
g
h
i
j
k
z
s-a-0
1
0
What t est vec t or det ec t s h s-a-0 f aul t ?
Good c i r c ui t val ue
1
Faul t y c i r c ui t val ue
(0)
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Multiple Stuck-at Faults
l A multiple stuck-at fault means that any set of
lines is stuck-at some combination of (0,1)
values Simultaneously.
l The total number of single and multiple stuck-at
faults in a circuit with k single fault sites is 3
k
-1.
l A single fault test can fail to detect the target
fault if another fault is also present, however,
such masking of one fault by another is rare.
l Statistically, single fault tests cover a very large
number of multiple faults.
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Stuck-at Fault Model Single vs. Multiple
l A circuit with n nodes
has :
2n single stuck-at
faults
3^n - 1 multiple
stuck-at faults
l Example : when n = 9
# of single stuck-at
faults = 18
# of multiple stuck-at
faults = 19,682
a
b
c
d
f
h
g
j
k
Fault-free Model
a
b
c
d
f
h
g
j
k
Stuck-at fault Model
g stuck-at-0
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Why single stuck-at fault model
l Logic fault model
l Computationally manageable
l Covers most multiple stuck-at faults
l opens, shorts, floating nodes cannot be
modeled as stuck-at faults but may be tested
by stuck-at test sets
l Some of the above Non-classical faults may
not be detected by a stuck-at fault test
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Fault Equivalence
l Number of fault sites in a Boolean gate circuit =
#PI + #gates + # (fanout branches).
l Fault equivalence: Two faults f1 and f2 are
equivalent if all tests that detect f1 also detect f2.
l If faults f1 and f2 are equivalent then the
corresponding faulty functions are identical.
l Fault collapsing: All single faults of a logic circuit
can be divided into disjoint equivalence subsets,
where all faults in a subset are mutually
equivalent. A collapsed fault set contains one
fault from each equivalence subset.
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Gate Level Equivalent Faults and
Fault Collapsing
Collapsed fault set
Z sa0 = A sa0 = B sa0
Z sa1
A sa1
B sa1
AB Z Asa0 Asa1 Bsa0 Bsa1 Zsa0 Zsa1
0 0 0 0 0 0 0 0 1
0 1 0 0 1 0 0 0 1
1 0 0 0 0 0 1 0 1
1 1 1 0 1 0 1 0 1
AND
Collapsed fault set
Z sa1 = A sa1 = B sa1
Z sa0
A sa0
B sa0
AB Z Asa0 Asa1 Bsa0 Bsa1 Zsa0 Zsa1
0 0 0 0 1 0 1 0 1
0 1 1 1 1 0 1 0 1
1 0 1 0 1 1 1 0 1
1 1 1 1 1 1 1 0 1
OR
A Z Asa0 Asa1 Zsa0 Zsa1
0 1 1 0 0 1
1 0 1 0 0 1
INVERTER
Collapsed fault set
Z sa1 = A sa0
Z sa0 = A sa1
A
B
Z
sa0
x
sa1
sa0
x
sa1
sa1
x
sa0
A
B
Z
sa1
x
sa0
sa1
x
sa0
sa0
x
sa1
A Z
sa1
x
sa0
sa0
x
sa1
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Structural Equivalent Faults and
Fault Collapsing
Z
sa0
x
sa1
sa1
x
sa0
A
sa1
x
sa0
sa0
x
sa1
Only 2 collapsed faults for inverter chain (Z sa0 & Z sa1)
Cannot collapse faults at fan-out stem since
it would violate single stuck-at fault model
Fan-out stem sa1 = K sa1 & J sa1
Fan-out stem sa0 = K sa0 & j sa0
D
Z
sa0
x
sa1
sa0
x
sa1
sa1
x
sa0
C
Z
sa1
x
sa0
sa1
x
sa0
sa0
x
sa1
sa0
x
sa1
sa1
x
sa0
A
B
sa0
x
sa1
sa0
x
sa1
sa1
x
sa0
Fan-out Stem
K
J
# collapsed faults = 12
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Equivalence Example
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
Faul t s i n bl ue
r emoved by
equi val enc e
c ol l apsi ng
20
Col l apse r at i o = ----- = 0.625
32
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Fault Dominance
l If all tests of some fault F1 detect another fault F2, then F2
is said to dominate F1.
l Dominance fault collapsing: If fault F2 dominates F1, then
F2 is removed from the fault list.
l When dominance fault collapsing is used, it is sufficient to
consider only the input faults of Boolean gates. See the
next example.
l In a tree circuit (without fanouts) PI faults form a
dominance collapsed fault set. (How realistic is this?)
l If two faults dominate each other then they are equivalent.
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Dominance Example
s-a-1
F1
s-a-1
F2
001
110 010
000
101
100
011
Al l t est s of F2
Onl y t est of F1
s-a-1
s-a-1
s-a-1
s-a-0
A domi nanc e c ol l apsed f aul t set
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Checkpoints Insufficient for
Sequential Circuits
l Primary inputs and fanout branches of a combinational
circuit are called checkpoints.
l Checkpoint theorem: A test set that detects all single
(multiple) stuck-at faults on all checkpoints of a
combinational circuit, also detects all single (multiple)
stuck-at faults in that circuit.
Tot al f aul t si t es = 16
Chec k poi nt s ( ) = 10
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Redundant Faults
l Faults for which no static test exists are called redundant
faults
l Here, Z stuck-at-0 cannot be detected, so its redundant
l Often present due to
Consensus (hazard avoidance)
Drive strength (duplicated gates)
Re-convergent fan-out
Design or synthesis errors
Z s-a-0 A
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An Example A Redundant Fault
l Redundancy sometimes introduced to avoid hazards
l Output (Q) produces term BC, which is not logically required
l Without Gate G, static hazard when input changes from 111 to 011, results
in spurious 0-pulse
l Could be visible as a glitch, but impossible to detect on tester
l Fault Q s-a-0 is undetectable
A
B
C
R
Q
P
s-a-0
Z G
A
BC
A
0
1
1 1
1 1
11 00 01 10
) ( ) ( C A AB C A BC AB Z + = + + =
P
C
B
A
A
R
Z with Gate G
Q
Z without Gate G
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Common Fault Models
l Circuit level (Inductive Fault Analysis)
Shorts
Opens
l Switch level
Stuck-on
Stuck-open
l Gate level
Stuck-at
Bridging
Delay
l Memory faults
l PLA faults (stuck-at, cross-point, bridging)
l Functional faults (processors)
l Higher level
Register transfer level
Behavioral level
Architectural level
l For more examples, see Section 4.4 (p. 60-70) of the book.
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Bridging Faults
l Bridging faults are caused by shorts
between two or more normally
unconnected lines
l Model depends on technology
Wired AND
Wired OR
Resistive
Voting
l Capacitive loads
l Transistor sizing, etc.
l Recent studies have shown that
many manufacturing defects can be
modeled as bridging faults
l Largely ignored by test generation
software but no longer necessary
for 90 nanometer (0.9)
Input Bridging Fault (BF)
BF
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Bridging Fault Models
l Two current models for wires shorted together:
Wired-AND/Wired-OR fault model
l Shorted wires perform logical AND or OR
Dominant fault model
l Stronger driving gate dominates the short
l For N nets, # pair-wise bridging faults = N
2
-N (either model)
l No fault equivalence no fault collapsing
A
B
Low
resistance
short
A
B
A
B
A
B
A dominates B model
A
B
A
B
B dominates A model
A
B
A
B
Wired-AND fault model
A
B
A
B
Wired-OR fault model
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Transistor (Switch) Faults
l MOS transistor is considered an ideal switch
and two types of faults are modeled:
l Stuck-open -- a single transistor is permanently stuck in the
open state.
l Stuck-short -- a single transistor is permanently shorted
irrespective of its gate voltage.
l Detection of a stuck-open fault requires two
vectors.
l Detection of a stuck-short fault requires the
measurement of quiescent current (I
DDQ
).
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Stuck-OPEN Faults
l Exhibits sequential behavior
l p-part will be open due to
input vector
l n-part will be open due to
stuck-open fault
l Results in sequential
behavior (retaining previous
state)
l Need two-pattern or multi-
pattern tests to detect stuck-
OPEN faults
l may be invalidated under
timing skews
l Need robust test patterns to
be generated
V
DD
A
B
A B
Gnd
AB=01
Open
V
out =
Previous State
B A f + =
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Stuck-Open Example
Two-vector s-op test
can be constructed by
ordering two s-at tests
A
B
V
DD
C
pMOS
FETs
nMOS
FETs
St uc k-
open
1
0
0
0
0 1(Z)
Good c i r c ui t st at es
Faul t y c i r c ui t st at es
Vec t or 1: t est f or A s-a-0
(I ni t i al i zat i on vec t or )
Vec t or 2 (t est f or A s-a-1)
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Stuck-ON (Short) Faults
l Stuck-ON faults are caused
by shorts or transistor
permanently being ON
l Consider pMOS transistor
corresponding to input A
l V
out
depends on the
resistances of the transistors
l Which makes it hard to
detect using logic testing
l I
DDQ
(current) testing detects
the fault due to elevated I
DDQ
values
V
DD
R
on
R
pB
R
nB
R
nA
A
B
A B
Gnd
B A f + =
nA pB on
nA
DD out
R R R
R
V V
+ +
=
AB=10
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Stuck-Short Example
A
B
V
DD
C
pMOS
FETs
nMOS
FETs
St uc k-
shor t
1
0
0 (X)
Good c i r c ui t st at e
Faul t y c i r c ui t st at e
Test vec t or f or A s-a-0
I
DDQ
pat h i n
f aul t y c i r c ui t
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I
DDQ
Testing
l Gate oxide shorts caused by
manufacturing defects are hard to
detect with logic testing
l I
DDQ
testing detects gate oxide
shorts and various other defects
resulting in strengthened I
DDQ
l Vector AB = 01 results in elevated
IDDQ
l I
DDQ
is the IEEE symbol for the
quiescent power supply current in
an IC
l Perfect CMOS circuits have I
DDQ
values typically less than 100 nA -
There is no direct conducting path
between V
DD
and V
SS
l Many CMOS IC defects elevate
I
DDQ
several orders of magnitude
greater than non-defective circuit
l Therefore, I
DDQ
testing is a highly
sensitive way to detect some of the
CMOS defects
V
DD
A
B
A B
Gnd
AB=01
Gate oxide short
B A f + =
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I
DDQ
- Detecting Defects
+V
DD
V
SS
(Ground)
V
out
V
in
I
DD
CMOS Inverter
Ex. Gate-Oxide
Short Circuit (V
gd
)
(high resistance)
V
in
V
out
I
DDQ
I
DDT
Defect
I
DDQ
Measure
No Defect
Failure Analysis by Measuring Power Supply Current
Source: K. T. Cheng
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Delay Faults
l Ensures IC operates within timing spec.
l Screens manufacturing defects that cause performance
degradation
l Requires the application of a two-pattern set to create a
transition to excite and propagate a fault
Combinational
circuit
PIs POs
Time
Force
PIs
Initialization
Force
PIs
Measure
POs
Time
T
Circuit stabilizes for
a time > T
Transition
T = time
period
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Transition Delay Fault Model
l Models large delay defects in circuits
l Behaves as a stuck-at fault for a brief period of time
l Includes the slow-to-rise fault model, which models an internal
node that is slow to change from 0 to 1
l Includes the slow-to-fall fault model, which models an internal
node that is slow to change from 1 to 0
l Requires two test patterns for detection : initialization vector and
transition vector
Initialization vector places initial transition value at the point of
the fault
Transition vector, which is same as vector for detecting stuck-at
fault, places the final transition value at the point of the fault
Treats faults on clock lines as stuck-at faults
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Transition Delay Fault Slow to
Rise
Combinational Logic
FF
Input
Output
A
FF
FF
FF
x
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Path Delay Fault Model
l Places slow-to-rise and slow-to-fall faults on
paths in a circuit
l Propagates a transition from source of path
to destination of path
l In transition has occurred at time of strobe,
circuit is declared fault-free. If not, a fault
exists.
l Requires two-pattern testing to initialize the
path and propagate a transition
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Path Delay Fault
Combinational Logic
FF
Input
Output
A
FF
FF
FF
x
x
The entire red path
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Toggle Fault Model
l Ensures that a node can be driven to both a
logical 0 and a logical 1
l Includes 0 and 1 faults on design cell input
pins, design cell output pins, and external
pins
l Is detected when the opposite binary value of
the fault is placed at the fault site
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A Basic Question
If defect may not affect circuit logical behavior,
Why bother??
Three reasons, at least:
1. Defect may indicate a latent reliability problem
2. Additional current drain for low-power devices
3. Indication of processing problem
Source: K. T. Cheng
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Summary
l Fault models are analyzable approximations of
defects and are essential for a test methodology.
l For digital logic, single stuck-at fault model offers
best advantage of tools and experience.
l Many other faults (bridging, stuck-open and
multiple stuck-at) are largely covered by stuck-at
fault tests.
l Stuck-short and delay faults and technology-
dependent faults require special tests.
l Memory and analog circuits need other
specialized fault models and tests.
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Logic Simulation
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l What is simulation?
l Design verification
l Circuit modeling
l True-value simulation algorithms
l Compiled-code simulation
l Event-driven simulation
l Summary
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Simulation Defined
l Definition: Simulation refers to modeling of a design, its
function and performance.
l A software simulator is a computer program; an emulator
is a hardware simulator.
l Simulation is used for design verification:
l Validate assumptions
l Verify logic
l Verify performance (timing)
l Types of simulation:
l Logic or switch level
l Timing
l Circuit
l Fault
Other types: Behavior, Register Transfer Level (RTL), gate level,
transistor level simulation, etc.
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Simulation for Verification
True-value
simulation
Specification
Design
(netlist)
Input stimuli
Computed
responses
Response
analysis
Synthesis
Design
changes
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Modeling for Simulation
l Modules, blocks or components described by
l Input/output (I/O) function
l Delays associated with I/O signals
l Examples: binary adder, Boolean gates, FET, resistors and
capacitors
l Interconnects represent
l ideal signal carriers, or
l ideal electrical conductors
l Netlist: a format (or language) that describes a
design as an interconnection of modules.
Netlist may use hierarchy: Think of this as an inverted tree
l Leaves layers of sub-modules, nested modules, and
l Root a single chip-top module.
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Example: A Full-Adder
HA;
inputs: a, b;
outputs: c, f;
AND: A1, (a, b), (c);
AND: A2, (d, e), (f);
OR: O1, (a, b), (d);
NOT: N1, (c), (e);
a
b
c
d
e
f
HA
FA;
inputs: A, B, C;
outputs: Carry, Sum;
HA: HA1, (A, B), (D, E);
HA: HA2, (E, C), (F, Sum);
OR: O2, (D, F), (Carry);
HA1
HA2
A
B
C
D
E F
Sum
Carry
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C
a
Logic Model of MOS Circuit
C
c
C
b
V
DD
a
b
c
pMOS FETs
nMOS FETs
C
a
, C
b
and C
c
are
parasitic capacitances
D
c
D
a
c
a
b
D
a
and D
b
are
interconnect or
propagation delays
D
c
is inertial delay
of gate
D
b
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Options for Inertial Delay
(simulation of a NAND gate)
b
a
c (CMOS)
Time units
0
5
c (zero delay)
c (unit delay)
c (multiple delay)
c (minmax delay)
I
n
p
u
t
s
L
o
g
i
c

s
i
m
u
l
a
t
i
o
n
min =2, max =5
rise=5, fall=5
Transient
region
Unknown (X)
X
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Signal States
l Two-states (0, 1) can be used for purely
combinational logic with zero-delay.
l Three-states (0, 1, X) are essential for timing
hazards and for sequential logic initialization.
l Four-states (0, 1, X, Z) are essential for MOS
devices. See example below.
l Analog signals are used for exact timing of
digital logic and for analog circuits.
0
0
Z
(hold previous value)
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Modeling Levels
Circuit
description
Programming
language-like HDL
Connectivity of
Boolean gates,
flip-flops and
transistors
Transistor size
and connectivity,
node capacitances
Transistor technology
data, connectivity,
node capacitances
Tech. Data, active/
passive component
connectivity
Signal
values
0, 1
0, 1, X
and Z
0, 1
and X
Analog
voltage
Analog
voltage,
current
Timing
Clock
boundary
Zero-delay
unit-delay,
multiple-
delay
Zero-delay
Fine-grain
timing
Continuous
time
Modeling
level
Function,
behavior, RTL
Logic
Switch
Timing
Circuit
Application
Architectural
and functional
verification
Logic
verification
and test
Logic
verification
Timing
verification
Digital timing
and analog
circuit
verification
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True-Value Simulation Algorithms
l Compiled-code simulation
l Applicable to zero-delay combinational logic
l Also used for cycle-accurate synchronous sequential circuits for
logic verification
l Efficient for highly active circuits, but inefficient for low-activity
circuits
l High-level (e.g., C language) models can be used
l Event-driven simulation
l Only gates or modules with input events are evaluated (event
means a signal change)
l Delays can be accurately simulated for timing verification
l Efficient for low-activity circuits
l Can be extended for fault simulation
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Compiled-Code Algorithm
l Step 1: Levelize combinational logic and encode in a
compilable programming language
l Step 2: Initialize internal state variables (flip-flops)
Circuit signals are variables (Boolean, integer, etc.)
Gates are programming operators
Flip-flops, unlike gates, as data variables capable of retaining
values over time.
High level functions as subroutines
l Step 3: For each input vector
Set primary input variables
Repeat (until steady-state or max. iterations)
l Execute compiled code
Report or save computed variables
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Time Wheel (Circular Stack) for Event
Scheduling
t=0
1
2
3
4
5
6
7
max
Current
time
pointer
Event link-list
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Event-Driven Algorithm
(Example)
Gate
Delay =
2
2
4
2
a =1
b =1
c =1
d = 0
e =1
f =0
g =1
Time, t
0 4
8
g
Scheduled
events
c = 0
Activity
list
d, e t = 0
1
2
3
4
5
6
7
8
T
i
m
e

s
t
a
c
k
0
d = 1, e = 0
f, g
g = 0
f = 1
g
g = 1
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Efficiency of Event-driven
Simulator
l Simulates events (value changes) only
l Speed up over compiled-code can be ten times
or more; in large logic circuits about 0.1 to 10%
gates become active for an input change
Large logic
block without
activity
Steady 0
0 to 1 event
Steady 0
(no event)
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Summary
l Logic or true-value simulators are essential tools
for design verification.
l Verification vectors and expected responses are
generated (often manually) from specifications.
l A logic simulator can be implemented using
either compiled-code or event-driven method.
l Per vector complexity of a logic simulator is
approximately linear in circuit size.
l Modeling level determines the evaluation
procedures used in the simulator.
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Fault Simulation
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l Problem and motivation
l Fault simulation algorithms
l Serial
l Parallel
l Deductive
l Concurrent
l Differential
l Random Fault Sampling
l Summary
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Problem and Motivation
l Fault simulation Problem: Given
A circuit
A sequence of test vectors
A fault model
Determine
Fault coverage - fraction (or percentage) of modeled
faults detected by test vectors
Set of undetected faults
l Motivation
Determine test quality and in turn product quality
Find undetected fault targets to improve tests
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Fault Detection
l Fault detection requires:
observation of an error (from fault) at a primary output
l observability of the fault site
the ease at which we can observe the fault behavior
input stimuli that creates an error as a result of fault
l controllability of the fault site
the ease at which we can control the fault behavior
l controllability of path from fault site to primary output
typically considered part of observability
l Testability controllability & observability
l Any given fault may be:
Detectable
Undetectable
Potentially detectable
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Gate Level Fault Detection - Path
Sensitization
1. At fault site, assign logic value opposite that of stuck-at
fault
2. From fault site, choose a path to a PO assigning non-
controlling values to all other inputs to gates in that path
1 = non-controlling value for AND/NAND gates
0 = non-controlling value for OR/NOR gates
3. For all assigned values, back-trace to PIs selecting input
values that will produce the assigned values
4. If there is a conflict, repeat Steps 2 & 3 choosing new
paths and/or values in Step 3
If no path can be found without conflict, the fault may be
undetectable, otherwise values at PIs form test vector
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Undetectable Faults
l No test vector can detect the fault
usually difficult to prove a fault is undetectable
l Undetectable faults due to:
Re-convergent fan-out, and
Redundant logic
x
sa0
A
B
Z
S
0
1
1/0
1/0
0
1
1
1
0
1
0
1
1
conflict
Good ckt/Faulty ckt
response
Hazard-free multiplexer
has undetectable faults
due to re-convergent
fanout and redundancy
0 0 1 1
0 1 1 0
AB
00 01 11 10
S 0
1
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Undetectable Faults (cont.)
l Minimize circuit to remove redundancy & these faults
undetectable fault may not effect circuit operation
l wasted area
undetectable fault slows down fault simulation
l all test vectors are simulated (no trip on mismatch)
l Sometimes undetectable faults are unavoidable
hazard-free circuits
l glitch-free clock multiplexing
initialization circuitry
l power-up presets
l global resets
use these ckts sparingly to minimize undetectable faults
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Potentially Detected Faults
l Due to undefined logic values (U,2,X)
an artifact of logic simulation
l can be a 0 or a 1 but simulator doesnt know
l used for un-initialized logic
faults preventing initialization produce U,2,X
l Potential detect fault if good ckt = 1/0 & faulty ckt =
U,2,X
potential detect faults may be detected by other vectors
probability of detect of a fault # potential detects
l for high data activity, otherwise probability = 0.5
in real circuit, fault may/may not be detected
l depends on power-up value
in simulation, PDFs also show up as undetected faults
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Potentially Detected Faults (cont.)
Examples of potentially detected
fault
l Select input to MUX stuck-at-0
flip-flop cannot be initialized
l Clock stuck-at-0 and stuck-at-1
flip-flop cannot be initialized
l 3 potentially detected faults
high detection probability for
l high data activity on Sel & Din
l high clock frequency
otherwise these may not be
detected
0
1
Din
Sel
Clk
x
sa0
D Q
Dout
x
sa0/sa1
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Fault Simulation
l Fault simulator emulates faults and compares
resultant response to known good circuit output
responses
l Fault simulation long for large fault lists - speed-up:
simulation of a given faults ends on detection
parallel flt simulation emulates 1 flt/bit (computer word)
statistical fault sampling (>1000 samples = good estimate)
Circuit
Netlist
Test
Vectors
Fault
Emulator
Output
Responses
Compare
Undetected
Faults
Detected
Faults
Fault
List
mismatch
no mismatch
Fault Simulator
Potentially
Detected Faults
?
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Fault Coverage/Grading
l Given a set of test vectors, each fault in fault set can be:
D = detected faults
l Targeted faults and faults accidentally detected
X = undetectable faults (aka untestable faults)
l There are NO vectors that can detect these faults
U = undetected faults
l Could not find vector to detect fault (but there could be
one)
P = potentially detected faults (PDF)
l Also included in U
T = total faults = D + X + U
l Fault coverage = (D+P/2) / T
Detectable FC = (D+P/2) / (T - X)
l Note: assumes PDF detection probability = 0.5
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Fault simulator in a VLSI Design
Process
Ver i f i ed desi gn
net l i st
Ver i f i c at i on
i nput st i mul i
Faul t si mul at or Test vec t or s
Model ed
f aul t l i st
Test
gener at or
Test
c ompac t or
Faul t
c over age
?
Remove
tested faults
Delete
vectors
Add vectors
Low
Adequate
Stop
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Classes of Stuck-at Faults
l Following classes of single stuck-at faults are
identified by fault simulators:
l Potentially-detectable fault -- Test produces an unknown (X)
state at primary output (PO); detection is probabilistic, usually
with 50% probability.
l Initialization fault -- Fault prevents initialization of the faulty
circuit; can be detected as a potentially-detectable fault.
l Hyperactive fault -- Fault induces much internal signal activity
without reaching PO.
l Redundant fault -- No test exists for the fault.
l Untestable fault -- Test generator is unable to find a test.
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Fault Simulation Scenario
l Circuit model: mixed-level
l Mostly logic with some switch-level for high-impedance (Z) and
bidirectional signals
l High-level models (memory, etc.) with pin faults
l Signal states: logic
l Two (0, 1) or three (0, 1, X) states for purely Boolean logic
circuits
l Four states (0, 1, X, Z) for sequential MOS circuits
l Timing:
l Zero-delay for combinational and synchronous circuits
l Mostly unit-delay for circuits with feedback
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Fault Simulation Scenario
(continued)
l Faults:
l Mostly single stuck-at faults
l Sometimes stuck-open, transition, and path-delay faults;
analog circuit fault simulators are not yet in common use
l Equivalence fault collapsing of single stuck-at faults
l Fault-dropping -- a fault once detected is dropped from
consideration as more vectors are simulated; fault-dropping
may be suppressed for diagnosis
l Fault sampling -- a random sample of faults is simulated when
the circuit is large
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Fault Simulation Algorithms
l Serial
l Parallel
l Deductive
l Concurrent
l Differential
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Serial Algorithm
l Algorithm: Simulate fault-free circuit and save
responses. Repeat following steps for each fault
in the fault list:
l Modify netlist by injecting one fault
l Simulate modified netlist, vector by vector, comparing
responses with saved responses
l If response differs, report fault detection and suspend
simulation of remaining vectors
l Advantages:
l Easy to implement; needs only a true-value simulator, less
memory
l Most faults, including analog faults, can be simulated
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Serial Algorithm (Cont.)
l Disadvantage: Much repeated computation; CPU time
prohibitive for VLSI circuits
l Alternative: Simulate many faults together
Test vec t or s Faul t -f r ee c i r c ui t
Ci r c ui t w i t h f aul t f 1
Ci r c ui t w i t h f aul t f 2
Ci r c ui t w i t h f aul t f n
Compar at or f 1 det ec t ed?
Compar at or f 2 det ec t ed?
Compar at or f n det ec t ed?
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Parallel Fault Simulation
l Compiled-code method; best with two-states (0,1)
l Exploits inherent bit-parallelism of logic operations on
computer words
l Storage: one word per line for two-state simulation
l Multi-pass simulation: Each pass simulates w-1 new
faults, where w is the machine word length
l Speed up over serial method ~ w-1
l Not suitable for circuits with timing-critical and non-
Boolean logic
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Parallel Fault Sim. Example
a
b
c
d
e
f
g
1 1 1
1 1 1 1 0 1
1 0 1
0 0 0
1 0 1
s-a-1
s-a-0
0 0 1
c s-a-0 detected
Bi t 0: f aul t -f r ee c i r c ui t
Bi t 1: c i r c ui t w i t h c s-a-0
Bi t 2: c i r c ui t w i t h f s-a-1
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Deductive Fault Simulation
l One-pass simulation
l Each line k contains a list L
k
of faults detectable on k
l Following true-value simulation of each vector, fault
lists of all gate output lines are updated using set-
theoretic rules, signal values, and gate input fault lists
l PO fault lists provide detection data
l Limitations:
l Set-theoretic rules difficult to derive for non-Boolean gates
l Gate delays are difficult to use
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Deductive Fault Sim.
Example
a
b
c
d
e
f
g
1
1
1
0
1
{a
0
}
{b
0
, c
0
}
{b
0
}
{b
0
, d
0
}
L
e
= L
a
U L
c
U {e
0
}
= {a
0
, b
0
, c
0
, e
0
}
L
g
= (L
e
L
f
) U {g
0
}
= {a
0
, c
0
, e
0
, g
0
}
U
{b
0
, d
0
, f
1
}
Not at i on: L
k
i s f aul t l i st f or l i ne k
k
n
i s s-a-n f aul t on l i ne k
Faul t s det ec t ed by
t he i nput vec t or
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Concurrent Fault Simulation
l Event-driven simulation of fault-free circuit and only those
parts of the faulty circuit that differ in signal states from the
fault-free circuit.
l A list per gate containing copies of the gate from all faulty
circuits in which this gate differs. List element contains fault
ID, gate input and output values and internal states, if any.
l All events of fault-free and all faulty circuits are implicitly
simulated.
l Faults can be simulated in any modeling style or detail
supported in true-value simulation (offers most flexibility.)
l Faster than other methods, but uses most memory.
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Conc. Fault Sim. Example
a
b
c
d
e
f
g
1
1
1
0
1
1
1
1
1
0
1
1 0
0
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0 1
0 1 1 1
a
0
b
0
c
0
e
0
a
0
b
0
b
0
c
0
e
0
d
0
d
0
g
0
f
1
f
1
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Roths Test-Detect Algorithm
l D-Calculus
D means 1/0 (Good Machine is 1 but Bad Machine is 0)
D means 0/1 (Good Machine is 0 but Bad Machine is 1)
1
1
1
0
0
1
1
s-a-1
_
D
D
D
D
Fault detected.
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Roths Test-Detect Algorithm
l D-Calculus
D means 1/0 (Good Machine is 1 but Bad Machine is 0)
D means 0/1 (Good Machine is 0 but Bad Machine is 1)
1
1
1
0
0
1
1
s-a-1
Fault undetected.
_
D
_
D
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Roths Test Detect Algorithm:
l D-Calculus
l For each fault, refresh entire circuit back to the
original fault-free (true value) circuit
Differential Fault Simulator:
l No D-Calculus
l Partial refresh
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Differential Fault Simulation Algorithm
1. Select 1
st
test vector
2. Do true-value (fault free) simulation of the vector
Save golden Primary Output (PO) values in a list.
3. Pick a fault, inject opposite to fault value, simulate
the from good to bad event
If s-a-0, simulate 10 event, for example
4. Continue even-driven wheel until no more events.
5. Compare primary output (PO) value against golden
PO value
6. If no more faults to pick, done. Advance to next test
vector, go to 2
7. Else pick next fault by placing 2 parallel events
Event#1: From previous fault site, refresh (on need basis)
back to fault-free values
Event#2: From the current fault site, simulate fault effect
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Fault Sampling
l A randomly selected subset (sample) of
faults is simulated.
l Measured coverage in the sample is used to
estimate fault coverage in the entire circuit.
l Advantage: Saving in computing resources
(CPU time and memory.)
l Disadvantage: Limited data on undetected
faults.
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Motivation for Sampling
l Complexity of fault simulation depends on:
l Number of gates
l Number of faults
l Number of vectors
l Complexity of fault simulation with fault
sampling depends on:
l Number of gates
l Number of vectors
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Random Sampling Model
Al l f aul t s w i t h
a f i x ed but
unk now n
c over age
Det ec t ed
f aul t
Undet ec t ed
f aul t
Random
pi c k i ng
N
p
= t ot al number of f aul t s
(popul at i on si ze)
C = f aul t c over age (unk nown)
N
s
= sampl e si ze
N
s
<< N
p
c = sampl e c over age
(a r andom var i abl e)
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Probability Density of Sample
Coverage, c
(x--C )
2
-- ------------
1 2
2
p (x ) = Pr ob(x < c < x +dx ) = -------------- e
(2 )
1/2
p

(
x
)
C
C +3 C -3 1.0
x
Sampl e c over age
C (1 - C)
Variance,
2
= ------------
N
s
Mean = C
Sampl i ng
er r or

x
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Sampling Error Bounds
C (1 - C )
| x - C | = 3 [ -------------- ]
1/2
N
s
Sol vi ng t he quadr at i c equat i on f or C, we get t he
3-si gma (99.7% c onf i denc e) est i mat e:
4.5
C
3
= x ------- [ 1 + 0.44 N
s
x (1 - x )]
1/2
N
s
Wher e N
s
i s sampl e si ze and x i s t he measur ed f aul t
c over age i n t he sampl e.
Ex ampl e: A c i r c ui t wi t h 39,096 f aul t s has an ac t ual
f aul t c over age of 87.1%. The measur ed c over age i n
a r andom sampl e of 1,000 f aul t s i s 88.7%. The above
f or mul a gi ves an est i mat e of 88.7% 3%. CPU t i me f or
sampl e si mul at i on was about 10% of t hat f or al l f aul t s.

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Summary
l Fault simulator is an essential tool for test development.
l Concurrent or differential fault simulation algorithm offers
the best choice.
l For restricted class of circuits (combinational and
synchronous sequential with only Boolean primitives),
differential algorithm can provide better speed and
memory efficiency (Section 5.5.6.)
l For large circuits, the accuracy of random fault sampling
only depends on the sample size (1,000 to 2,000 faults)
and not on the circuit size. The method has significant
advantages in reducing CPU time and memory needs of
the simulator. (However, certain products demand exact
fault coverage figure and analysis.)