MSP 430 G 2231

M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
www.ti.com SLAS694J FEBRUARY 2010REVISED FEBRUARY 2013
M I X E D S I G N A L M I C R O C O N T R O L L E R
1 FE A T UR E S
L ow S upply-Voltage R ange: 1 .8 V to 3 .6 V 1 6-Bit T imer_A With T wo C apture/C ompare
R egisters
Ultra-L ow P ower C onsumption
Universal S erial I nterface (US I ) S upporting S P I
A ctive M ode: 2 2 0 A at 1 M Hz, 2 .2 V
and I 2 C (S ee T able 1)
S tandby M ode: 0 .5 A
Brownout D etector
O ff M ode (R A M R etention): 0 .1 A
1 0 -Bit 2 0 0 -ksps A /D C onverter With I nternal
Five P ower-S aving M odes
R eference, S ample-and-Hold, and A utoscan
Ultra-Fast Wake-Up From S tandby M ode in
(S ee T able 1 )
L ess T han 1 s
S erial O nboard P rogramming,
1 6-Bit R I S C A rchitecture, 62 .5-ns I nstruction
N o E x ternal P rogramming Voltage N eeded,
C ycle T ime
P rogrammable C ode P rotection by S ecurity
Basic C lock M odule C onfigurations
Fuse
I nternal Frequencies up to 1 6 M Hz With
O n-C hip E mulation L ogic With S py-Bi-Wire
O ne C alibrated Frequency
I nterface
I nternal Very L ow P ower L ow-Frequency
For Family M embers D etails, S ee T able 1
(L F) O scillator
A vailable in 1 4 -P in P lastic S mall-O utline T hin
3 2 -kHz C rystal
P ackage (T S S O P ) (P W), 1 4 -P in P lastic D ual
E x ternal D igital C lock S ource I nline P ackage (P D I P ) (N ), and 1 6-P in QFN
P ackage (R S A )
For C omplete M odule D escriptions, S ee the
MSP430x2xx Family Users Guide (S L A U1 4 4 )
D E S C R I P T I O N
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s.
The MSP430G2x21/G2x31 series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer
and ten I/O pins. The MSP430G2x31 family members have a 10-bit A/D converter and built-in communication
capability using synchronous protocols (SPI or I2C). For configuration details, see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20102013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
SLAS694J FEBRUARY 2010REVISED FEBRUARY 2013 www.ti.com
T able 1 . A vailable O ptions
(1 )
Flash R A M A D C 1 0 P ackage
D evice BS L E E M T imer_A US I C lock I /O
(KB) (B) C hannel T ype
(2 )
MSP430G2231IRSA16 16-QFN
MSP430G2231IPW14 - 1 2 128 1x TA2 1 8 LF, DCO, VLO 10 14-TSSOP
MSP430G2231IN14 14-PDIP
MSP430G2221IPW14 - 1 2 128 1x TA2 1 - LF, DCO, VLO 10 14-TSSOP
MSP430G2131IPW14 - 1 1 128 1x TA2 1 8 LF, DCO, VLO 10 14-TSSOP
MSP430G2121IPW14 - 1 1 128 1x TA2 1 - LF, DCO, VLO 10 14-TSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2 Submit Documentation Feedback Copyright 20102013, Texas Instruments Incorporated
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P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
1 DVCC
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9 P1.7/SDI/SDA/TDO/TDI
10 RST/NMI/SBWTDIO
11 TEST/SBWTCK
12 XOUT/P2.7
13 XIN/P2.6/TA0.1
14 DVSS
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
P1.4/SMCLK/TCK
P1.5/TA0.0/SCLK/TMS
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
D evice P inout, M S P 4 3 0 G 2 x 2 1
N O R P W P A C KA G E
(T O P VI E W)
NOTE: See port schematics in Application Information for detailed I/O information.
R S A P A C KA G E
(T O P VI E W)
Copyright 20102013, Texas Instruments Incorporated Submit Documentation Feedback 3
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11 XOUT/P2.7
12 XIN/P2.6/TA0.1
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P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREF-
1 DVCC
2
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8 P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK
9 P1.7/A7/SDI/SDA/TDO/TDI
10 RST/NMI/SBWTDIO
11 TEST/SBWTCK
12 XOUT/P2.7
13 XIN/P2.6/TA0.1
14 DVSS
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
P1.5/TA0.0/A5/SCLK/TMS
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
D evice P inout, M S P 4 3 0 G 2 x 3 1
N O R P W P A C KA G E
(T O P VI E W)
R S A P A C KA G E
(T O P VI E W)
Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
SMCLK
ACLK
MDB
MAB
Port P1
8 I/O
Interrupt
capability
pull-up/down
resistors
P1.x
8
Spy-Bi
Wire
XIN XOUT
RAM
128B
Flash
2kB
1kB
ADC
10-Bit
8 Ch.
Autoscan
1 ch DMA
P2.x
Port P2
2 I/O
Interrupt
capability
pull-up/down
resistors
2
USI
Universal
Serial
Interface
SPI, I2C
Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
SMCLK
ACLK
MDB
MAB
Port P1
8 I/O
Interrupt
capability
pull-up/down
resistors
P1.x
8
Spy-Bi
Wire
XIN XOUT
RAM
128B
Flash
2KB
1KB
P2.x
Port P2
2 I/O
Interrupt
capability
pull-up/down
resistors
2
USI
Universal
Serial
Interface
SPI, I2C
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
Functional Block D iagram, M S P 4 3 0 G 2 x 2 1
Functional Block D iagram, M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T able 2 . T erminal Functions
T E R M I N A L
N O . I /O D E S C R I P T I O N
N A M E
N , P W R S A
P1.0/ General-purpose digital I/O pin
TA0CLK/ Timer0_A, clock signal TACLK input
2 1 I/O
ACLK/ ACLK signal output
A0 ADC10 analog input A0
(1)
TA0.0/ 3 2 I/O Timer0_A, capture: CCI0A input, compare: Out0 output
(1)
TA0.1/ 4 3 I/O Timer0_A, capture: CCI1A input, compare: Out1 output
(1)
ADC10CLK/ ADC10, conversion clock output
(1)
5 4 I/O
A3/ ADC10 analog input A3
(1)
VREF-/VEREF ADC10 negative reference voltage
(1)
SMCLK/ SMCLK signal output
A4/ 6 5 I/O ADC10 analog input A4
(1)
VREF+/VEREF+/ ADC10 positive reference voltage
(1)
TCK JTAG test clock, input terminal for device programming and test
TA0.0/ Timer0_A, compare: Out0 output
A5/ 7 6 I/O ADC10 analog input A5
(1)
SCLK/ USI: clock input in I2C mode; clock input/output in SPI mode
TMS JTAG test mode select, input terminal for device programming and test
TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output
(1)
8 7 I/O
SDO/ USI: Data output in SPI mode
SCL/ USI: I2C clock in I2C mode
TDI/TCLK JTAG test data input or test clock input during programming and test
(1)
SDI/ 9 8 I/O USI: Data input in SPI mode
SDA/ USI: I2C data in I2C mode
TDO/TDI
(2)
JTAG test data output terminal or test data input during programming and test
XIN/ Input terminal of crystal oscillator
P2.6/ 13 12 I/O General-purpose digital I/O pin
TA0.1 Timer0_A, compare: Out1 output
XOUT/ Output terminal of crystal oscillator
(3)
12 11 I/O
P2.7 General-purpose digital I/O pin
RST/ Reset
NMI/ 10 9 I Nonmaskable interrupt input
SBWTDIO Spy-Bi-Wire test data input/output during programming and test
TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
11 10 I
SBWTCK Spy-Bi-Wire test clock input during programming and test
DVCC 1 15, 16 NA Supply voltage
DVSS 14 13, 14 NA Ground reference
QFN Pad - Pad NA QFN package pad connection to V
SS
recommended.
(1) MSP430G2x31 only
(2) TDO or TDI is selected via JTAG instruction.
(3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
Program Counter PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
General-Purpose Register R4
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
S HO R T -FO R M D E S C R I P T I O N
C P U
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
I nstruction S et
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
T able 3 . I nstruction Word Formats
I N S T R UC T I O N FO R M A T S YN T A X O P E R A T I O N
Dual operands, source-destination ADD R4,R5 R4 + R5 ---> R5
Single operands, destination only CALL R8 PC -->(TOS), R8--> PC
Relative jump, un/conditional JNE Jump-on-equal bit = 0
T able 4 . A ddress M ode D escriptions
(1 )
A D D R E S S M O D E S D S YN T A X E X A M P L E O P E R A T I O N
Register MOV Rs,Rd MOV R10,R11 R10 -- --> R11
Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) -- --> M(6+R6)
Symbolic (PC relative) MOV EDE,TONI M(EDE) -- --> M(TONI)
Absolute MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT)
Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6)
M(R10) -- --> R11
Indirect autoincrement MOV @Rn+,Rm MOV @R10+,R11
R10 + 2-- --> R10
Immediate MOV #X,TONI MOV #45,TONI #45 -- --> M(TONI)
(1) S = source, D = destination
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
O perating M odes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
DCO's dc generator is disabled if DCO not used in active mode
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc generator remains enabled
ACLK remains active
CPU is disabled
DCO's dc generator is disabled
ACLK remains active
CPU is disabled
ACLK is disabled
DCO's dc generator is disabled
Crystal oscillator is stopped
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
I nterrupt Vector A ddresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
T able 5. I nterrupt S ources, Flags, and Vectors
S YS T E M WO R D
I N T E R R UP T S O UR C E I N T E R R UP T FL A G P R I O R I T Y
I N T E R R UP T A D D R E S S
Power-Up PORIFG
External Reset RSTIFG
Watchdog Timer+ WDTIFG Reset 0FFFEh 31, highest
Flash key violation KEYV
(2)
PC out-of-range
(1)
NMI NMIIFG (non)-maskable
Oscillator fault OFIFG (non)-maskable 0FFFCh 30
Flash memory access violation ACCVIFG
(2) (3)
(non)-maskable
0FFFAh 29
0FFF8h 28
0FFF6h 27
Watchdog Timer+ WDTIFG maskable 0FFF4h 26
Timer_A2 TACCR0 CCIFG
(4)
maskable 0FFF2h 25
Timer_A2 TACCR1 CCIFG, TAIFG
(2) (4)
maskable 0FFF0h 24
0FFEEh 23
0FFECh 22
ADC10
(5)
ADC10IFG
(4) (5)
maskable 0FFEAh 21
USI USIIFG, USISTTIFG
(2) (4)
maskable 0FFE8h 20
I/O Port P2 (two flags) P2IFG.6 to P2IFG.7
(2) (4)
maskable 0FFE6h 19
I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7
(2) (4)
maskable 0FFE4h 18
0FFE2h 17
0FFE0h 16
See
(6)
0FFDEh to
15 to 0, lowest
0FFC0h
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) MSP430G2x31 only
(6) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
S pecial Function R egisters (S FR s)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
L egend rw: Bit can be read and written.
rw-0 ,1 : Bit can be read and written. It is reset or set by PUC.
rw-(0 ,1 ): Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
T able 6. I nterrupt E nable R egister 1 and 2
A ddress 7 6 5 4 3 2 1 0
0 0 h A C C VI E N M I I E O FI E WD T I E
rw-0 rw-0 rw-0 rw-0
WD T I E Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
O FI E Oscillator fault interrupt enable
N M I I E (Non)maskable interrupt enable
A C C VI E Flash access violation interrupt enable
A ddress 7 6 5 4 3 2 1 0
0 1 h
T able 7. I nterrupt Flag R egister 1 and 2
A ddress 7 6 5 4 3 2 1 0
0 2 h N M I I FG R S T I FG P O R I FG O FI FG WD T I FG
rw-0 rw-(0) rw-(1) rw-1 rw-(0)
WD T I FG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on V
CC
power-on or a reset condition at the RST/NMI pin in reset mode.
O FI FG Flag set on oscillator fault.
P O R I FG Power-On Reset interrupt flag. Set on V
CC
power-up.
R S T I FG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V
CC
power-up.
N M I I FG Set via RST/NMI pin
A ddress 7 6 5 4 3 2 1 0
0 3 h
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
M emory O rganization
T able 8. M emory O rganization
M S P 4 3 0 G 2 0 2 1 M S P 4 3 0 G 2 1 2 1 M S P 4 3 0 G 2 2 2 1
M S P 4 3 0 G 2 0 3 1 M S P 4 3 0 G 2 1 3 1 M S P 4 3 0 G 2 2 3 1
Memory Size 512B 1kB 2kB
Main: interrupt vector Flash 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0
Main: code memory Flash 0xFFFF to 0xFE00 0xFFFF to 0xFC00 0xFFFF to 0xF800
Information memory Size 256 Byte 256 Byte 256 Byte
Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h
RAM Size 128B 128B 128B
027Fh to 0200h 027Fh to 0200h 027Fh to 0200h
Peripherals 16-bit 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h
8-bit 0FFh to 010h 0FFh to 010h 0FFh to 010h
8-bit SFR 0Fh to 00h 0Fh to 00h 0Fh to 00h
Flash M emory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
P eripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
O scillator and S ystem C lock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1s. The basic
clock module provides the following clock signals:
Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
T able 9. D C O C alibration D ata
(P rovided From Factory I n Flash I nformation M emory S egment A )
C A L I BR A T I O N
D C O FR E QUE N C Y S I ZE A D D R E S S
R E G I S T E R
CALBC1_1MHZ byte 010FFh
1 MHz
CALDCO_1MHZ byte 010FEh
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
D igital I /O
There is one 8-bit I/O port implementedport P1and two bits of I/O port P2:
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull-up/pull-down resistor.
WD T + Watchdog T imer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T imer_A 2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
T able 1 0 . T imer_A 2 S ignal C onnections D evice With A D C 1 0
I N P UT P I N N UM BE R M O D UL E O UT P UT P I N N UM BE R
D E VI C E I N P UT M O D UL E M O D UL E
O UT P UT
S I G N A L I N P UT N A M E BL O C K
P W, N R S A P W, N R S A
S I G N A L
2 - P1.0 1 - P1.0 TACLK TACLK
ACLK ACLK
Timer NA
SMCLK SMCLK
2 - P1.0 1 - P1.0 TACLK INCLK
3 - P1.1 2 - P1.1 TA0 CCI0A 3 - P1.1 2 - P1.1
ACLK (internal) CCI0B 7 - P1.5 6 - P1.5
CCR0 TA0
VSS GND
VCC VCC
4 - P1.2 3 - P1.2 TA1 CCI1A 4 - P1.2 3 - P1.2
8 - P1.6 7 - P1.6 TA1 CCI1B 8 - P1.6 7 - P1.6
CCR1 TA1
VSS GND 13 - P2.6 12 - P2.6
VCC VCC
US I
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
A D C 1 0 (M S P 4 3 0 G 2 x 3 1 only)
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
P eripheral File M ap
T able 1 1 . P eripherals With Word A ccess
R E G I S T E R
M O D UL E R E G I S T E R D E S C R I P T I O N O FFS E T
N A M E
A D C 1 0 (M S P 4 3 0 G 2 x 3 1 only) ADC data transfer start address ADC10SA 1BCh
ADC control 0 ADC10CTL0 01B0h
ADC control 1 ADC10CTL0 01B2h
ADC memory ADC10MEM 01B4h
T imer_A Capture/compare register TACCR1 0174h
Capture/compare register TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control TACCTL1 0164h
Capture/compare control TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash M emory Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
Watchdog T imer+ Watchdog/timer control WDTCTL 0120h
T able 1 2 . P eripherals With Byte A ccess
R E G I S T E R
N A M E
A D C 1 0 (M S P 4 3 0 G 2 x 3 1 only) ADC analog enable ADC10AE0 04Ah
ADC data transfer control 1 ADC10DTC1 049h
ADC data transfer control 0 ADC10DTC0 048h
US I USI control 0 USICTL0 078h
USI control 1 USICTL1 079h
USI clock control USICKCTL 07Ah
USI bit counter USICNT 07Bh
USI shift register USISR 07Ch
Basic C lock S ystem+ Basic clock system control 3 BCSCTL3 053h
Basic clock system control 2 BCSCTL2 058h
Basic clock system control 1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
P ort P 2 Port P2 resistor enable P2REN 02Fh
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T able 1 2 . P eripherals With Byte A ccess (continued)
R E G I S T E R
N A M E
P ort P 1 Port P1 resistor enable P1REN 027h
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
S pecial Function SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Legend:
16 MHz
S
y
s
t
e
m

F
r
e
q
u
e
n
c
y

-

M
H
z
12 MHz
6 MHz
1.8 V
Supply Voltage - V
3.3 V
2.7 V 2.2 V
3.6 V
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
A bsolute M ax imum R atings
(1 )
Voltage applied at V
CC
to V
SS
0.3 V to 4.1 V
Voltage applied to any pin
(2)
0.3 V to V
CC
+ 0.3 V
Diode current at any device pin 2 mA
Unprogrammed device 55C to 150C
Storage temperature range, T
stg
(3)
Programmed device 55C to 150C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
. The JTAG fuse-blow voltage, V
FB
, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
R ecommended O perating C onditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25C (unless otherwise noted)
M I N N O M M A X UN I T
During program execution 1.8 3.6
V
CC
Supply voltage V
During flash programming 2.2 3.6
V
SS
Supply voltage 0 V
T
A
Operating free-air temperature I version 40 85 C
V
CC
= 1.8 V,
dc 6
Duty cycle = 50% 10%
V
CC
= 2.7 V,
f
SYSTEM
Processor frequency (maximum MCLK frequency)
(1) (2)
dc 12 MHz
V
CC
= 3.3 V,
dc 16
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V
CC
of 2.2 V.
Figure 1 . S afe O perating A rea
0.0
1.0
2.0
3.0
4.0
5.0
1.5 2.0 2.5 3.0 3.5 4.0
V
CC
Supply Voltage V
A
c
t
i
v
e

M
o
d
e

C
u
r
r
e
n
t
m
A
f
DCO
= 1 MHz
f
DCO
= 8 MHz
f
DCO
= 12 MHz
f
DCO
= 16 MHz
0.0
1.0
2.0
3.0
4.0
0.0 4.0 8.0 12.0 16.0
f
DCO
DCO Frequency MHz
A
c
t
i
v
e

M
o
d
e

C
u
r
r
e
n
t
m
A
T
A
= 25 C
T
A
= 85 C
V
CC
= 2.2 V
V
CC
= 3 V
T
A
= 25 C
T
A
= 85 C
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
E lectrical C haracteristics
A ctive M ode S upply C urrent I nto V
C C
E x cluding E x ternal C urrent
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) (2)
P A R A M E T E R T E S T C O N D I T I O N S T
A
V
C C
M I N T YP M A X UN I T
f
DCO
= f
MCLK
= f
SMCLK
= 1 MHz, 2.2 V 220
f
ACLK
= 32768 Hz,
Program executes in flash,
Active mode (AM)
I
AM,1MHz
BCSCTL1 = CALBC1_1MHZ, A
current (1 MHz)
3 V 300 370
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
(1) All inputs are tied to 0 V or to V
CC
. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
T ypical C haracteristics A ctive M ode S upply C urrent (I nto V
C C
)
Figure 2 . A ctive M ode C urrent vs V
C C
, T
A
= 2 5C Figure 3 . A ctive M ode C urrent vs D C O Frequency
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
-40
I
L
o
w
-
P
o
w
e
r

M
o
d
e

C
u
r
r
e
n
t
A
L
P
M
3
Vcc = 3.6 V
T Temperature C
A
Vcc = 1.8 V
Vcc = 3 V
Vcc = 2.2 V
-20 0 20 40 60 80
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
-40
I
L
o
w
-
P
o
w
e
r

M
o
d
e

C
u
r
r
e
n
t
A
L
P
M
4
Vcc = 3.6 V
T Temperature C
A
Vcc = 1.8 V
Vcc = 3 V
Vcc = 2.2 V
-20 0 20 40 60 80
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
L ow-P ower M ode S upply C urrents (I nto V
C C
) E x cluding E x ternal C urrent
(1) (2)
A
V
C C
f
MCLK
= 0 MHz,
f
SMCLK
= f
DCO
= 1 MHz,
f
ACLK
= 32768 Hz,
Low-power mode 0
I
LPM0,1MHz
BCSCTL1 = CALBC1_1MHZ, 25C 2.2 V 65 A
(LPM0) current
(3)
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
f
MCLK
= f
SMCLK
= 0 MHz,
f
DCO
= 1 MHz,
f
ACLK
= 32768 Hz,
Low-power mode 2
I
LPM2
BCSCTL1 = CALBC1_1MHZ, 25C 2.2 V 22 A
(LPM2) current
(4)
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
f
DCO
= f
MCLK
= f
SMCLK
= 0 MHz,
Low-power mode 3 f
ACLK
= 32768 Hz,
I
LPM3,LFXT1
25C 2.2 V 0.7 1.5 A
(LPM3) current
(4)
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
f
DCO
= f
MCLK
= f
SMCLK
= 0 MHz,
Low-power mode 3 f
ACLK
from internal LF oscillator (VLO),
I
LPM3,VLO
25C 2.2 V 0.5 0.7 A
current, (LPM3)
(4)
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
f
DCO
= f
MCLK
= f
SMCLK
= 0 MHz, 25C 2.2 V 0.1 0.5 A
Low-power mode 4 f
ACLK
= 0 Hz,
I
LPM4
(LPM4) current
(5)
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
85C 2.2 V 0.8 1.5 A
OSCOFF = 1
(1) All inputs are tied to 0 V or to V
CC
. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
T ypical C haracteristics L ow-P ower M ode S upply C urrents
Figure 4 . L P M 3 C urrent vs T emperature Figure 5. L P M 4 C urrent vs T emperature
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
S chmitt-T rigger I nputs P orts P x
P A R A M E T E R T E S T C O N D I T I O N S V
C C
0.45 V
CC
0.75 V
CC
V
IT+
Positive-going input threshold voltage V
3 V 1.35 2.25
0.25 V
CC
0.55 V
CC
V
IT
Negative-going input threshold voltage V
3 V 0.75 1.65
V
hys
Input voltage hysteresis (V
IT+
V
IT
) 3 V 0.3 1 V
For pullup: V
IN
= V
SS
R
Pull
Pullup/pulldown resistor 3 V 20 35 50 k
For pulldown: V
IN
= V
CC
C
I
Input capacitance V
IN
= V
SS
or V
CC
5 pF
L eakage C urrent P orts P x
C C
M I N M A X UN I T
I
lkg(Px.y)
High-impedance leakage current
(1) (2)
3 V 50 nA
(1) The leakage current is measured with V
SS
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
O utputs P orts P x
C C
V
OH
High-level output voltage I
(OHmax)
= 6 mA
(1)
3 V V
CC
0.3 V
V
OL
Low-level output voltage I
(OLmax)
= 6 mA
(1)
3 V V
SS
+ 0.3 V
(1) The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined should not exceed 48 mA to hold the maximum voltage drop
specified.
O utput Frequency P orts P x
C C
Port output frequency
f
Px.y
Px.y, C
L
= 20 pF, R
L
= 1 k
(1) (2)
3 V 12 MHz
(with load)
f
Port_CLK
Clock output frequency Px.y, C
L
= 20 pF
(2)
3 V 16 MHz
(1) A resistive divider with 2 0.5 k between V
CC
and V
SS
is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% V
CC
at the specified toggle frequency.
V
OH
High-Level Output Voltage V
25
20
15
10
5
0
0 0.5 1 1.5 2 2.5
V
CC
= 2.2 V
P1.7
T
A
= 25C
T
A
= 85C
O
H
I
T
y
p
i
c
a
l

H
i
g
h
-
L
e
v
e
l

O
u
t
p
u
t

C
u
r
r
e
n
t
m
A
V
OH
High-Level Output Voltage V
50
40
30
20
10
0
0 0.5 1 1.5 2 2.5 3 3.5
V
CC
= 3 V
P1.7
T
A
= 25C
T
A
= 85C
O
H
I
T
y
p
i
c
a
l

H
i
g
h
-
L
e
v
e
l

O
u
t
p
u
t

C
u
r
r
e
n
t
m
A
V
OL
Low-Level Output Voltage V
0
5
10
15
20
25
30
0 0.5 1 1.5 2 2.5
V
CC
= 2.2 V
P1.7
T
A
= 25C
T
A
= 85C
O
L
I
T
y
p
i
c
a
l

L
o
w
-
L
e
v
e
l

O
u
t
p
u
t

C
u
r
r
e
n
t
m
A
V
OL
0
10
20
30
40
50
0 0.5 1 1.5 2 2.5 3 3.5
V
CC
= 3 V
P1.7
T
A
= 25C
T
A
= 85C
O
L
I
T
y
p
i
c
a
l

L
o
w
-
L
e
v
e
l

O
u
t
p
u
t

C
u
r
r
e
n
t
m
A
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T ypical C haracteristics O utputs
T YP I C A L L O W-L E VE L O UT P UT C UR R E N T T YP I C A L L O W-L E VE L O UT P UT C UR R E N T
vs vs
L O W-L E VE L O UT P UT VO L T A G E L O W-L E VE L O UT P UT VO L T A G E
Figure 6. Figure 7.
T YP I C A L HI G H-L E VE L O UT P UT C UR R E N T T YP I C A L HI G H-L E VE L O UT P UT C UR R E N T
vs vs
HI G H-L E VE L O UT P UT VO L T A G E HI G H-L E VE L O UT P UT VO L T A G E
Figure 8. Figure 9.
0
1
t
d(BOR)
V
CC
V
(B_IT)
V
hys(B_IT)
V
CC(start)
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
P O R , BO R
(1 ) (2 )
C C
V
CC(start)
See Figure 10 dV
CC
/dt 3 V/s 0.7 V
(B_IT)
V
V
(B_IT)
See Figure 10 through Figure 12 dV
CC
/dt 3 V/s 1.35 V
V
hys(B_IT)
See Figure 10 dV
CC
/dt 3 V/s 140 mV
t
d(BOR)
See Figure 10 2000 s
Pulse duration needed at RST/NMI pin to
t
(reset)
2.2 V, 3 V 2 s
accepted reset internally
(1) The current consumption of the brownout module is already included in the I
CC
current consumption data. The voltage level V
(B_IT)
+
V
hys(B_IT)
is 1.8 V.
(2) During power up, the CPU begins code execution following a period of t
d(BOR)
after V
CC
= V
(B_IT)
+ V
hys(B_IT)
. The default DCO settings
must not be changed until V
CC
V
CC(min)
, where V
CC(min)
is the minimum supply voltage for the desired operating frequency.
Figure 1 0 . P O R and BO R vs S upply Voltage
V
CC
0
0.5
1
1.5
2
V
CC(drop)
t
pw
t
pw
Pulse Width s
V
C
C
(
d
r
o
p
)
V
3 V
0.001 1 1000 t
f
t
r
t
pw
Pulse Width s
t
f
= t
r
Typical Conditions
V
CC
= 3 V
V
CC(drop)
V
CC
3 V
t
pw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1 ns 1 ns
t
pw
Pulse Width s
V
C
C
(
d
r
o
p
)
V
t
pw
Pulse Width s
V
CC
= 3 V
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T ypical C haracteristics P O R and BO R
Figure 1 1 . V
C C (drop)
L evel With a S quare Voltage D rop to G enerate a P O R or BO R S ignal
Figure 1 2 . V
C C (drop)
L evel With a T riangle Voltage D rop to G enerate a P O R or BO R S ignal
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
average
DCO(RSEL,DCO) DCO(RSEL,DCO+1)
32 f f
f =
MOD f + (32 MOD) f
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
M ain D C O C haracteristics
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter S
DCO
.
Modulation control bits MODx select how often f
DCO(RSEL,DCO+1)
is used within the period of 32 DCOCLK
cycles. The frequency f
DCO(RSEL,DCO)
is used for the remaining cycles. The frequency is an average equal to:
D C O Frequency
C C
RSELx < 14 1.8 3.6 V
V
CC
Supply voltage RSELx = 14 2.2 3.6 V
RSELx = 15 3 3.6 V
f
DCO(0,0)
DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3 V 0.06 0.14 MHz
f
DCO(0,3)
DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3 V 0.12 MHz
f
DCO(1,3)
f
DCO(2,3)
f
DCO(3,3)
f
DCO(4,3)
f
DCO(5,3)
f
DCO(6,3)
f
DCO(7,3)
f
DCO(8,3)
f
DCO(9,3)
f
DCO(10,3)
f
DCO(11,3)
f
DCO(12,3)
f
DCO(13,3)
f
DCO(14,3)
f
DCO(15,3)
f
DCO(15,7)
DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3 V 21 MHz
Frequency step between
S
RSEL
S
RSEL
= f
DCO(RSEL+1,DCO)
/f
DCO(RSEL,DCO)
3 V 1.35 ratio
range RSEL and RSEL+1
Frequency step between
S
DCO
S
DCO
= f
DCO(RSEL,DCO+1)
/f
DCO(RSEL,DCO)
3 V 1.08 ratio
tap DCO and DCO+1
Duty cycle Measured at SMCLK output 3 V 50 %
DCO Frequency MHz
0.10
1.00
10.00
0.10 1.00 10.00
D
C
O

W
a
k
e
T
i
m
e
s
RSELx = 0...11
RSELx = 12...15
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
C alibrated D C O Frequencies T olerance
A
V
C C
BCSCTL1= CALBC1_1MHz,
1-MHz tolerance over
DCOCTL = CALDCO_1MHz, 0C to 85C 3 V -3 0.5 +3 %
temperature
(1)
calibrated at 30C and 3 V
1-MHz tolerance over V
CC
DCOCTL = CALDCO_1MHz, 30C 1.8 V to 3.6 V -3 2 +3 %
1-MHz tolerance overall DCOCTL = CALDCO_1MHz, -40C to 85C 1.8 V to 3.6 V -6 3 +6 %
(1) This is the frequency change from the measured frequency at 30C over temperature.
Wake-Up From L ower-P ower M odes (L P M 3 /4 ) E lectrical C haracteristics
C C
DCO clock wake-up time from BCSCTL1= CALBC1_1MHz,
t
DCO,LPM3/4
3 V 1.5 s
LPM3/4
(1)
DCOCTL = CALDCO_1MHz
1/f
MCLK
+
t
CPU,LPM3/4
CPU wake-up time from LPM3/4
(2)
t
Clock,LPM3/4
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
T ypical C haracteristics D C O C lock Wake-Up T ime From L P M 3 /4
Figure 1 3 . D C O Wake-Up T ime From L P M 3 vs D C O Frequency
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
C rystal O scillator, X T 1 , L ow-Frequency M ode
(1 )
C C
LFXT1 oscillator crystal
f
LFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz
frequency, LF mode 0, 1
LFXT1 oscillator logic level
f
LFXT1,LF,logic
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 1.8 V to 3.6 V 10000 32768 50000 Hz
LF mode
XTS = 0, LFXT1Sx = 0,
500
f
LFXT1,LF
= 32768 Hz, C
L,eff
= 6 pF
Oscillation allowance for
OA
LF
k
LF crystals
XTS = 0, LFXT1Sx = 0,
200
f
LFXT1,LF
= 32768 Hz, C
L,eff
= 12 pF
XTS = 0, XCAPx = 0 1
XTS = 0, XCAPx = 1 5.5
Integrated effective load
C
L,eff
pF
capacitance, LF mode
(2)
XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 11
XTS = 0, Measured at P2.0/ACLK,
Duty cycle, LF mode 2.2 V 30 50 70 %
f
LFXT1,LF
= 32768 Hz
Oscillator fault frequency,
f
Fault,LF
XTS = 0, XCAPx = 0, LFXT1Sx = 3
(4)
2.2 V 10 10000 Hz
LF mode
(3)
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
I nternal Very-L ow-P ower L ow-Frequency O scillator (VL O )
P A R A M E T E R T
A
V
C C
f
VLO
VLO frequency -40C to 85C 3 V 4 12 20 kHz
df
VLO
/d
T
VLO frequency temperature drift -40C to 85C 3 V 0.5 %/C
df
VLO
/dV
CC
VLO frequency supply voltage drift 25C 1.8 V to 3.6 V 4 %/V
T imer_A
C C
Internal: SMCLK, ACLK
f
TA
Timer_A input clock frequency External: TACLK, INCLK f
SYSTEM
MHz
t
TA,cap
Timer_A capture timing TA0, TA1 3 V 20 ns
V
OL
0.0
1.0
2.0
3.0
4.0
5.0
0.0 0.2 0.4 0.6 0.8 1.0
V
CC
= 2.2 V
T
A
= 25C
O
L
I
L
o
w
-
L
e
v
e
l

O
u
t
p
u
t

C
u
r
r
e
n
t
m
A
T
A
= 85C
V
OL
0.0
1.0
2.0
3.0
4.0
5.0
0.0 0.2 0.4 0.6 0.8 1.0
V
CC
= 3 V
T
A
= 25C
O
L
I
L
o
w
-
L
e
v
e
l

O
u
t
p
u
t

C
u
r
r
e
n
t
m
A
T
A
= 85C
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
US I , Universal S erial I nterface
C C
External: SCLK,
f
USI
USI clock frequency Duty cycle = 50% 10%, f
SYSTEM
MHz
SPI slave mode
USI module in I2C mode, V
SS
V
OL,I2C
Low-level output voltage on SDA and SCL 3 V V
SS
V
I
(OLmax)
= 1.5 mA + 0.4
T ypical C haracteristics US I L ow-L evel O utput Voltage on S D A and S C L
Figure 1 4 . US I L ow-L evel O utput Voltage vs O utput C urrent Figure 1 5. US I L ow-L evel O utput Voltage vs O utput C urrent
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
1 0 -Bit A D C , P ower S upply and I nput R ange C onditions (M S P 4 3 0 G 2 x 3 1 O nly)
(1)
A
V
C C
V
CC
Analog supply voltage V
SS
= 0 V 2.2 3.6 V
All Ax terminals, Analog inputs
V
Ax
Analog input voltage
(2)
3 V 0 V
CC
V
selected in ADC10AE register
f
ADC10CLK
= 5.0 MHz,
ADC10ON = 1, REFON = 0,
I
ADC10
ADC10 supply current
(3)
25C 3 V 0.6 mA
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
f
ADC10CLK
= 5.0 MHz,
ADC10ON = 0, REF2_5V = 0, 0.25
REFON = 1, REFOUT = 0
Reference supply current,
I
REF+
25C 3 V mA
reference buffer disabled
(4)
f
ADC10CLK
= 5.0 MHz,
ADC10ON = 0, REF2_5V = 1, 0.25
REFON = 1, REFOUT = 0
f
ADC10CLK
= 5.0 MHz,
Reference buffer supply ADC10ON = 0, REFON = 1,
I
REFB,0
25C 3 V 1.1 mA
current with ADC10SR = 0
(4)
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
f
ADC10CLK
= 5.0 MHz,
Reference buffer supply ADC10ON = 0, REFON = 1,
I
REFB,1
25C 3 V 0.5 mA
current with ADC10SR = 1
(4)
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
Only one terminal Ax can be selected
C
I
Input capacitance 25C 3 V 27 pF
at one time
R
I
Input MUX ON resistance 0 V V
Ax
V
CC
25C 3 V 1000
(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range V
R+
to V
R
for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter I
ADC10
.
(4) The internal reference current is supplied via terminal V
CC
. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
1 0 -Bit A D C , Built-I n Voltage R eference (M S P 4 3 0 G 2 x 3 1 O nly)
C C
I
VREF+
1 mA, REF2_5V = 0 2.2
Positive built-in reference
V
CC,REF+
V
analog supply voltage range
I
VREF+
1 mA, REF2_5V = 1 2.9
I
VREF+
I
VREF+
max, REF2_5V = 0 1.41 1.5 1.59
Positive built-in reference
V
REF+
3 V V
voltage
I
VREF+
I
VREF+
max, REF2_5V = 1 2.35 2.5 2.65
Maximum VREF+ load
I
LD,VREF+
3 V 1 mA
current
I
VREF+
= 500 A 100 A,
Analog input voltage V
Ax
0.75 V, 2
REF2_5V = 0
VREF+ load regulation 3 V LSB
I
VREF+
= 500 A 100 A,
Analog input voltage V
Ax
1.25 V, 2
REF2_5V = 1
I
VREF+
= 100 A900 A,
V
REF+
load regulation V
Ax
0.5 VREF+,
3 V 400 ns
response time Error of conversion result 1 LSB,
ADC10SR = 0
Maximum capacitance at
C
VREF+
I
VREF+
1 mA, REFON = 1, REFOUT = 1 3 V 100 pF
pin VREF+
ppm/
TC
REF+
Temperature coefficient I
VREF+
= const with 0 mA I
VREF+
1 mA 3 V 100
C
Settling time of internal
I
VREF+
= 0.5 mA, REF2_5V = 0,
t
REFON
reference voltage to 99.9% 3.6 V 30 s
REFON = 0 1
VREF
I
VREF+
= 0.5 mA,
Settling time of reference
t
REFBURST
REF2_5V = 1, REFON = 1, 3 V 2 s
buffer to 99.9% VREF
REFBURST = 1, ADC10SR = 0
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
1 0 -Bit A D C , E x ternal R eference
(1 )
(M S P 4 3 0 G 2 x 3 1 O nly)
C C
VEREF+ > VEREF,
1.4 V
CC
SREF1 = 1, SREF0 = 0
Positive external reference input
VEREF+ V
voltage range
(2)
VEREF VEREF+ V
CC
0.15 V,
1.4 3
(3)
Negative external reference input
VEREF VEREF+ > VEREF 0 1.2 V
voltage range
(4)
Differential external reference
VEREF input voltage range, VEREF+ > VEREF
(5)
1.4 V
CC
V
VEREF = VEREF+ VEREF
0 V VEREF+ V
CC
,
3 V 1
I
VEREF+
Static input current into VEREF+ A
0 V VEREF+ V
CC
0.15 V 3 V,
3 V 0
(3)
I
VEREF
Static input current into VEREF 0 V VEREF V
CC
3 V 1 A
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C
I
, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current I
REFB
. The current consumption can be limited to the sample and conversion period with REBURST = 1.
(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
1 0 -Bit A D C , T iming P arameters (M S P 4 3 0 G 2 x 3 1 O nly)
C C
ADC10SR = 0 0.45 6.3
ADC10 input clock For specified performance of
f
ADC10CLK
3 V MHz
frequency ADC10 linearity parameters
ADC10SR = 1 0.45 1.5
ADC10 built-in ADC10DIVx = 0, ADC10SSELx = 0,
f
ADC10OSC
3 V 3.7 6.3 MHz
oscillator frequency f
ADC10CLK
= f
ADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
3 V 2.06 3.51
f
ADC10CLK
= f
ADC10OSC
t
CONVERT
Conversion time s
13
f
ADC10CLK
from ACLK, MCLK, or SMCLK,
ADC10DIV
ADC10SSELx 0
1/f
ADC10CLK
Turn-on settling time
t
ADC10ON
(1)
100 ns
of the ADC
(1) The condition is that the error in a conversion started after t
ADC10ON
is less than 0.5 LSB. The reference and input signal are already
settled.
1 0 -Bit A D C , L inearity P arameters (M S P 4 3 0 G 2 x 3 1 O nly)
C C
E
I
Integral linearity error 3 V 1 LSB
E
D
Differential linearity error 3 V 1 LSB
E
O
Offset error Source impedance R
S
< 100 3 V 1 LSB
E
G
Gain error 3 V 1.1 2 LSB
E
T
Total unadjusted error 3 V 2 5 LSB
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
1 0 -Bit A D C , T emperature S ensor and Built-I n V
M I D
(M S P 4 3 0 G 2 x 3 1 O nly)
C C
Temperature sensor supply REFON = 0, INCHx = 0Ah,
I
SENSOR
3 V 60 A
current
(1)
T
A
= 25C
TC
SENSOR
ADC10ON = 1, INCHx = 0Ah
(2)
3 V 3.55 mV/C
Sample time required if channel ADC10ON = 1, INCHx = 0Ah,
t
Sensor(sample)
3 V 30 s
10 is selected
(3)
Error of conversion result 1 LSB
I
VMID
Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh 3 V
(4)
A
ADC10ON = 1, INCHx = 0Bh,
V
MID
V
CC
divider at channel 11 3 V 1.5 V
V
MID
0.5 V
CC
Sample time required if channel ADC10ON = 1, INCHx = 0Bh,
t
VMID(sample)
3 V 1220 ns
11 is selected
(5)
Error of conversion result 1 LSB
(1) The sensor current I
SENSOR
is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, I
SENSOR
is included in I
REF+
. When REFON = 0, I
SENSOR
applies during conversion of the temperature sensor
input (INCH = 0Ah).
(2) The following formula can be used to calculate the temperature sensor output voltage:
V
Sensor,typ
= TC
Sensor
(273 + T [C] ) + V
Offset,sensor
[mV] or
V
Sensor,typ
= TC
Sensor
T [C] + V
Sensor
(T
A
= 0C) [mV]
(3) The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time t
SENSOR(on)
.
(4) No additional current is needed. The V
MID
is used during sampling.
(5) The on-time t
VMID(on)
is included in the sampling time t
VMID(sample)
; no additional on time is needed.
Flash M emory
P A R A M E T E R T E S T
V
C C
C O N D I T I O N S
V
CC(PGM/ERASE)
Program and erase supply voltage 2.2 3.6 V
f
FTG
Flash timing generator frequency 257 476 kHz
I
PGM
Supply current from V
CC
during program 2.2 V, 3.6 V 1 5 mA
I
ERASE
Supply current from V
CC
during erase 2.2 V, 3.6 V 1 7 mA
t
CPT
Cumulative program time
(1)
2.2 V, 3.6 V 10 ms
t
CMErase
Cumulative mass erase time 2.2 V, 3.6 V 20 ms
Program/erase endurance 10
4
10
5
cycles
t
Retention
Data retention duration T
J
= 25C 100 years
t
Word
Word or byte program time
(2)
30 t
FTG
t
Block, 0
Block program time for first byte or word
(2)
25 t
FTG
Block program time for each additional byte or
t
Block, 1-63
(2)
18 t
FTG
word
t
Block, End
Block program end-sequence wait time
(2)
6 t
FTG
t
Mass Erase
Mass erase time
(2)
10593 t
FTG
t
Seg Erase
Segment erase time
(2)
4819 t
FTG
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the Flash Controller's state machine (t
FTG
= 1/f
FTG
).
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
R A M
P A R A M E T E R T E S T C O N D I T I O N S M I N M A X UN I T
V
(RAMh)
RAM retention supply voltage
(1)
CPU halted 1.6 V
(1) This parameter defines the minimum supply voltage V
CC
when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JT A G and S py-Bi-Wire I nterface
C C
f
SBW
Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
t
SBW,Low
Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 s
Spy-Bi-Wire enable time
t
SBW,En
2.2 V, 3 V 1 s
(TEST high to acceptance of first clock edge
(1)
)
t
SBW,Ret
Spy-Bi-Wire return to normal operation time 2.2 V, 3 V 15 100 s
2.2 V 0 5 MHz
f
TCK
TCK input frequency
(2)
3 V 0 10 MHz
R
Internal
Internal pulldown resistance on TEST 2.2 V, 3 V 25 60 90 k
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t
SBW,En
time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) f
TCK
may be restricted to meet the timing requirements of the module selected.
JT A G Fuse
(1 )
P A R A M E T E R T E S T C O N D I T I O N S M I N M A X UN I T
V
CC(FB)
Supply voltage during fuse-blow condition T
A
= 25C 2.5 V
V
FB
Voltage level on TEST for fuse blow 6 7 V
I
FB
Supply current into TEST during fuse blow 100 mA
t
FB
Time to blow fuse 1 ms
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
To Module
From Timer
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxSEL.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
A P P L I C A T I O N I N FO R M A T I O N
P ort P 1 P in S chematic: P 1 .0 to P 1 .3 , I nput/O utput With S chmitt T rigger M S P 4 3 0 G 2 x 2 1
T able 1 3 . P ort P 1 (P 1 .0 to P 1 .3 ) P in Functions M S P 4 3 0 G 2 x 2 1
C O N T R O L BI T S /S I G N A L S
P I N N A M E (P 1 .x ) x FUN C T I O N
P 1 D I R .x P 1 S E L .x
P1.0/ P1.0 (I/O) I: 0; O: 1 0
TA0CLK/ 0 TA0CLK 0 1
ACLK ACLK 1 1
P1.1/ P1.1 (I/O) I: 0; O: 1 0
TA0.0 1 TA0.CCI0A 0 1
TA0.0 1 1
P1.2/ P1.2 (I/O) I: 0; O: 1 0
TA0.1 2 TA0.CCI1A 0 1
TA0.1 1 1
P1.3 3 P1.3 (I/O) I: 0; O: 1 0
To Module
From Module
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxSEL.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
From JTAG
To JTAG
P1.4/SMCLK/TCK
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
P ort P 1 P in S chematic: P 1 .4 , I nput/O utput With S chmitt T rigger M S P 4 3 0 G 2 x 2 1
T able 1 4 . P ort P 1 (P 1 .4 ) P in Functions M S P 4 3 0 G 2 x 2 1
C O N T R O L BI T S / S I G N A L S
(1 )
P 1 D I R .x P 1 S E L .x JT A G M ode
P1.4/ P1.x (I/O) I: 0; O: 1 0 0
SMCLK/ 4 SMCLK 1 1 0
TCK TCK X X 1
(1) X = don't care
To Module
From USI
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
From JTAG
To JTAG
P1.5/TA0.0/SCLK/TMS
PxSEL.y or
USIPE5
PxSEL.y
From USI
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
P ort P 1 P in S chematic: P 1 .5, I nput/O utput With S chmitt T rigger M S P 4 3 0 G 2 x 2 1
T able 1 5. P ort P 1 (P 1 .5) P in Functions M S P 4 3 0 G 2 x 2 1
(1 )
P 1 D I R .x P 1 S E L .x US I P .x JT A G M ode
P1.5/ P1.x (I/O) I: 0; O: 1 0 0 0
TA0.0/ TA0.0 1 1 0 0
5
SCLK/ SCLK X X 1 0
TMS TMS X X 0 1
(1) X = don't care
To Module
From Module
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
From JTAG
To JTAG
P1.6/TA0.1/SDO/SCL/TDI
PxSEL.y or
USIPE6
PxSEL.y
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
(1 )
P1.6/ P1.x (I/O) I: 0; O: 1 0 0 0
TA0.1/ TA0.1 1 1 0 0
6 TA0.CCI1B 0 1 0 0
SDO/SCL/ SDO/SCL X X 1 0
TDI/TCLK TDI/TCLK X X 0 1
(1) X = don't care
To Module
From USI
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
USIPE7
0
1
From JTAG
To JTAG
P1.7/SDI/SDA/TDO/TDI
PxSEL.y or
USIPE7
PxSEL.y
From JTAG
To JTAG
From USI
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
(1 )
P I N N A M E (P (1 .x ) x FUN C T I O N
P1.7/ P1.x (I/O) I: 0; O: 1 0 0 0
SDI/SDA/ 7 SDI/SDA X X 1 0
TDO/TDI TDO/TDI X X 0 1
(1) X = don't care
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
To Module
ACLK
PxOUT.y
DV
SS
DV
CC
1
Bus
Keeper
EN
1
0
PxIN.y
PxSEL.y
PxREN.y
1
0
INCHx
To ADC10
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
ADC10AE0.y
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
P ort P 1 P in S chematic: P 1 .0 to P 1 .2 , I nput/O utput With S chmitt T rigger M S P 4 3 0 G 2 x 3 1
T able 1 8. P ort P 1 (P 1 .0 to P 1 .2 ) P in Functions M S P 4 3 0 G 2 x 3 1
(1 )
A D C 1 0 A E .x
(I N C H.y = 1 )
P1.0/ P1.x (I/O) I: 0; O: 1 0 0
TA0CLK/ TA0.TACLK 0 1 0
0
ACLK/ ACLK 1 1 0
A0 A0 X X 1 (y = 0)
P1.1/ P1.x (I/O) I: 0; O: 1 0 0
TA0.0/ TA0.0 1 1 0
1
TA0.CCI0A 0 1 0
A1 A1 X X 1 (y = 1)
P1.2/ P1.x (I/O) I: 0; O: 1 0 0
TA0.1/ TA0.1 1 1 0
2
TA0.CCI1A 0 1 0
A2/ A2 X X 1 (y = 2)
(1) X = don't care
To Module
ADC10CLK
PxOUT.y
DV
SS
DV
CC
1
Bus
Keeper
EN
1
0
PxIN.y
EN
D
PxSEL.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
INCHx = y
To ADC10
To ADC10 VREF-
1
0
VSS
SREF2
ADC10AE0.y
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T able 1 9. P ort P 1 (P 1 .3 ) P in Functions M S P 4 3 0 G 2 x 3 1
(1 )
A D C 1 0 A E .x
(I N C H.x = 1 )
P1.3/ P1.x (I/O) I: 0; O: 1 0 0
ADC10CLK/ ADC10CLK 1 1 0
A3/ 3 A3 X X 1 (y = 3)
VREF-/ VREF- X X 1
VEREF- VEREF- X X 1
(1) X = don't care
To Module
SMCLK
PxOUT.y
DV
SS
DV
CC
1
Bus
Keeper
EN
1
0
PxIN.y
PxSEL.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
INCHx = y
To ADC10
ToADC10 VREF+
ADC10AE0.y
From JTAG
To JTAG
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
Bus
Keeper
EN
P1.5/TA0.0/A5/TMS
To Module
From Module
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxSEL.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
From JTAG
To JTAG
INCHx
To ADC10
ADC10AE0.y
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T able 2 0 . P ort P 1 (P 1 .4 ) P in Functions M S P 4 3 0 G 2 x 3 1
(1 )
A D C 1 0 A E .x JT A G
(I N C H.x = 1 ) M ode
P1.4/ P1.x (I/O) I: 0; O: 1 0 0 0
SMCLK/ SMCLK 1 1 0 0
A4/ A4 X X 1 (y = 4) 0
4
VREF+/ VREF+ X X 1 0
VEREF+/ VEREF+ X X 1 0
TCK TCK X X 0 1
(1) X = don't care
Bus
Keeper
EN
P1.6/TA0.1/SDO/SCL/A6/TDI
To Module
From USI
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxSEL.y or
USIPE6
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
USIPE6
0
1
From JTAG
To JTAG
INCHx
To ADC10
ADC10AE0.y
from USI
PxSEL.y
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T able 2 1 . P ort P 1 (P 1 .5) P in Functions - M S P 4 3 0 G 2 x 3 1
(1 )
P 1 D I R .x P 1 S E L .x US I P .x
P1.5/ P1.x (I/O) I: 0; O: 1 0 0 0 0
TA0.0/ TA0.0 1 1 0 0 0
A5/ 5 A5 X X X 1 (y = 5) 0
SCLK/ SCLK X X 1 0 0
TMS TMS X X 0 0 1
(1) X = don't care
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T able 2 2 . P ort P 1 (P 1 .6) P in Functions - M S P 4 3 0 G 2 x 3 1
(1 )
P1.6/ P1.x (I/O) I: 0; O: 1 0 0 0 0
TA0.1/ TA0.1 1 1 0 0 0
TA0.CCR1B 0 1 0 0 0
6
A6/ A6 X X 0 1 (y = 6) 0
SDO/ SDO X X 1 0 0
TDI/TCLK TDI/TCLK X X 0 0 1
(1) X = don't care
Bus
Keeper
EN
P1.7/SDI/SDA/A7/TDO/TDI
To Module
From USI
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
USIPE7
0
1
From JTAG
To JTAG
INCHx
To ADC10
ADC10AE0.y
from USI
PxSEL.y
PxSEL.y or
USIPE7
PxSEL.y
From JTAG
To JTAG
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
T able 2 3 . P ort P 1 (P 1 .7) P in Functions M S P 4 3 0 G 2 x 3 1
(1 )
P1.7/ P1.x (I/O) I: 0; O: 1 0 0 0 0
A7/ A7 X X 0 1 (y = 7) 0
7
SDI/SDO SDI/SDO X X 1 0 0
TDO/TDI TDO/TDI X X 0 0 1
(1) X = don't care
XIN/P2.6/TA0.1
1
0
XOUT/P2.7
LF off
LFXT1CLK
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
To Module
from Module
PxOUT.y
DV
SS
DV
CC
1
Bus
Keeper
EN
1
0
PxIN.y
PxSEL.6
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.6
0
1
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
P ort P 2 P in S chematic: P 2 .6, I nput/O utput With S chmitt T rigger M S P 4 3 0 G 2 x 2 1 and
M S P 4 3 0 G 2 x 3 1
T able 2 4 . P ort P 2 (P 2 .6) P in Functions M S P 4 3 0 G 2 x 2 1 and M S P 4 3 0 G 2 x 3 1
(1 )
P 2 D I R .x P 2 S E L .6 P 2 S E L .7
XIN XIN 0 1 1
P2.6 6 P2.x (I/O) I: 0; O: 1 0 X
TA0.1 TA0.1
(2)
1 1 X
(1) X = don't care
(2) BCSCTL3.LFXT1Sx = 11 is required.
XIN/P2.6/TA0.1
1
0
XOUT/P2.7
LF off
LFXT1CLK
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
To Module
from Module
PxOUT.y
DV
SS
DV
CC
1
Bus
Keeper
EN
1
0
PxIN.y
PxSEL.7
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.7
0
1
from P2.6/XIN
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
P ort P 2 P in S chematic: P 2 .7, I nput/O utput With S chmitt T rigger M S P 4 3 0 G 2 x 2 1 and
M S P 4 3 0 G 2 x 3 1
T able 2 5. P ort P 2 (P 2 .7) P in Functions M S P 4 3 0 G 2 x 2 1 and M S P 4 3 0 G 2 x 3 1
(1 )
P 2 D I R .x P 2 S E L .6 P 2 S E L .7
XOUT XOUT 1 1 1
7
P2.7 P2.x (I/O) I: 0; O: 1 X 0
(1) X = don't care
M S P 4 3 0 G 2 x 3 1
M S P 4 3 0 G 2 x 2 1
R E VI S I O N HI S T O R Y
R E VI S I O N D E S C R I P T I O N
SLAS694 Limited Product Preview release
Updated Product Preview release.
SLAS694A
Changes throughout for sampling.
SLAS694B Updated Product Preview release
SLAS694C Production Data release
Updated Table 12, Table 15, Table 16, Table 17, Table 19, Table 20, Table 21, Table 24, Table 25.
SLAS694D
Updated MSP430G2x31 port schematics: P1.0 to P1.3, P1.5, P1.6, P1.7.
Updated Table 20, Table 21, Table 24.
SLAS694E
Updated MSP430G2x31 port schematics: P1.3, P1.4.
Corrected TA0.1 signal description in Table 2.
Added ADC10SA register to Table 11.
SLAS694F
Added ADC10DTC1 and ADC10DTC0 registers to Table 12.
Corrected control bits in Table 13.
Corrected control bits in Table 25.
SLAS694G Changed T
stg
, Programmed device, to -40C to 150C in Absolute Maximum Ratings.
Changed T
stg
, Programmed device, to -55C to 150C in Absolute Maximum Ratings.
SLAS694H
Changed f
SYSTEM
MAX at V
CC
= 1.8 V from 4.15 to 6 MHz in Recommended Operating Conditions.
SLAS694I Corrected all port schematics (added buffer after PxOUT.y mux) in APPLICATION INFORMATION
Recommended Operating Conditions, Added test conditions for typical values.
SLAS694J
POR, BOR, Added note (2).
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (C) Top-Side Markings
(4)
Samples
MSP430G2121IN14 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2121
MSP430G2121IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 G2121
MSP430G2121IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM G2121
MSP430G2121IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR M430G
2121
MSP430G2121IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS
& no Sb/Br)
2121
(RoHS)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
2131
& no Sb/Br)
2131
(RoHS)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
2221
& no Sb/Br)
2221
(RoHS)
CU NIPDAU Level-1-260C-UNLIM MSP430G2231
& no Sb/Br)
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (C) Top-Side Markings
(4)
Samples
& no Sb/Br)
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G
2231
& no Sb/Br)
2231

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF MSP430G2231 :
Addendum-Page 3
Enhanced Product: MSP430G2231-EP

NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications

TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
MSP430G2121IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MSP430G2121IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2121IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430G2121IPW14R TSSOP PW 14 2000 367.0 367.0 35.0
MSP430G2121IRSA16R QFN RSA 16 3000 367.0 367.0 35.0
MSP430G2121IRSA16T QFN RSA 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Oct-2013
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
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Enhanced Product: MSP430G2231-EP

Enhanced Product - Supports Defense, Aerospace and Medical Applications

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