Ece6372 Chapter1

Embedded Systems Design: A Unified
Hardware/SoftwareIntroduction Hardware/Software Introduction

Chapter 1: Introduction Chapter 1: Introduction
1
Outline
Embedded systems overview y
What are they?
Design challenge optimizing design metrics g g p g g
Technologies
Processor technologies
IC technologies
Design technologies
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
2
Computing systems are everywhere p g y y
Most of us think of desktop computers
PCs
Laptops
Mainframes
Servers
But theres another type of computing system
Far more common...
3
Embedded computing systems p g y
Computing systems embedded within
electronic devices
Computers are in here...
and here...
Hard to define. Nearly any computing
system other than a desktop computer
Billionsof unitsproducedyearly versus
and even here...
Billions of units produced yearly, versus
millions of desktop units
Perhaps 50 per household and per
automobile
Lots more of these,
though they cost a lot
less each.
4
A short list of embedded systems y
Anti-lock brakes
Auto-focus cameras
Automatic teller machines
Modems
MPEG decoders
Network cards
Automatic toll systems
Automatic transmission
Avionic systems
Battery chargers
Camcorders
Cell phones
C ll h b i
Network switches/routers
On-board navigation
Pagers
Photocopiers
Point-of-sale systems
Portable video games
P i Cell-phone base stations
Cordless phones
Cruise control
Curbside check-in systems
Digital cameras
Disk drives
Electroniccardreaders
Printers
Satellite phones
Scanners
Smart ovens/dishwashers
Speech recognizers
Stereo systems
Teleconferencingsystems Electronic card readers
Electronic instruments
Electronic toys/games
Factory control
Fax machines
Fingerprint identifiers
Home security systems
Teleconferencing systems
Televisions
Temperature controllers
Theft tracking systems
TV set-top boxes
VCRs, DVD players
Video game consoles
And the list goes on and on
Life-support systems
Medical testing systems
Video phones
Washers and dryers
5
g
Some common characteristics of embedded
systems systems
Traditionally Single-functioned y g
Executes a single program, repeatedly
Tightly-constrained g y
Low cost, low power, small, fast, etc.
Reactive and real-time
Continually reacts to changes in the systems environment
Must compute certain results in real-time without delay
6
An embedded system example -- a digital
camera camera
Digital camera chip
CCD preprocessor Pixel coprocessor
A2D
D2A
g p
lens
CCD
Microcontroller J PEG codec
DMA controller Display ctrl
Multiplier/Accum
Memory controller ISA bus interface UART LCD ctrl
Single-functioned -- always a digital camera
Tightly-constrained -- Low cost, low power, small, fast
Reactiveandreal time onlytoasmall extent
7
Reactive and real-time -- only to a small extent
Obvious design goal: g g
Construct an implementation with desired functionality
Key design challenge: y g g
Simultaneously optimize numerous design metrics
Design metric
A measurable feature of a systems implementation
Optimizing design metrics is a key challenge
8
Common metrics
Unit cost: the monetary cost of manufacturing each copy of the system,
excluding NRE cost
NRE cost (Non Rec rringEngineeringcost): Th i NRE cost (Non-Recurring Engineering cost): The one-time
monetary cost of designing the system
Size: the physical space required by the system
Performance: the execution time or throughput of the system
Power: the amount of power consumed by the system
l ibili Flexibility: the ability to change the functionality of the system without
incurring heavy NRE cost
9
Common metrics (continued) ( )
Time-to-prototype: the time needed to build a working version of the
system
Timeto market: h i i d d l h i h i Time-to-market: the time required to develop a system to the point that it
can be released and sold to customers
Maintainability: the ability to modify the system after its initial release
Correctness, safety, many more
10
Design metric competition -- improving one
mayworsenothers may worsen others
Expertise with both software
Power
and hardware is needed to
optimize design metrics
Not just ahardwareor
Size Performance
Not just a hardware or
software expert, as is common
A designer must be
comfortablewithvarious
NRE cost
comfortable with various
technologies in order to choose
the best for a given application
and constraints
CCD preprocessor Pixel coprocessor
A2D
D2A
Digital camera chip
lens
CCD
Microcontroller J PEG codec
DMA controller
Memory controller ISA bus interface UART LCD ctrl
Display ctrl
Multiplier/Accum
Hardware
Software
11
Time-to-market: a demanding design metric g g
Time required to develop a
product to the point it can be
sold to customers
Market window Market window
Period during which the
product would have highest
sales
R
e
v
e
n
u
e
s

(
$
)
sales
Average time-to-market
constraint is about 8 months
Time (months)
Delays can be costly
12
Losses due to delayed market entry y y
Simplified revenue model
Product life =2W, peak at W
Timeof market entrydefinesa
Peak revenue
Peak revenue from
(
$
)
Time of market entry defines a
triangle, representing market
penetration
Triangleareaequalsrevenue
delayed entry
Market rise
Market fall
On-time
Delayed
R
e
v
e
n
u
e
s

(
Triangle area equals revenue
Loss
The difference between the on- W 2W
D
Delayed
time and delayed triangle areas On-time Delayed
entry entry
Time
13
Losses due to delayed market entry (cont.) y y( )
Area=1/2* base* height Area 1/2 base height
On-time =1/2 * 2W * W
Delayed =1/2 * (W-D+W)*(W-D)
Peak revenue
Peak revenue from
(
$
)
Percentage revenue loss =
(D(3W-D)/2W
2
)*100%
Trysomeexamples
delayed entry
Market rise
Market fall
On-time
Delayed
R
e
v
e
n
u
e
s

(
Try some examples
W 2W
D
Delayed
Lifetime 2W=52 wks, delay D=4 wks
(4*(3*26 4)/2*26^2) =22%
Lifetime2W=52wks delayD=10wks
On-time Delayed
entry entry
Time
Lifetime 2W=52 wks, delay D=10 wks
(10*(3*26 10)/2*26^2) =50%
Delays are costly!
14
NRE and unit cost metrics
Costs:
Unit cost: the monetary cost of manufacturing each copy of the system,
excluding NRE cost
NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of
designingthesystem designing the system
total cost = NRE cost + unit cost * # of units
per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost ( f )
Example
NRE=$2000, unit=$100
For 10 units
total cost =$2000 +10*$100 =$3000
per-product cost =$2000/10 +$100 =$300
Amortizing NRE cost over the units results in an
dd l $200
15
additional $200 per unit
NRE and unit cost metrics
Compare technologies by costs -- best depends on quantity p g y p q y
Technology A: NRE=$2,000, unit=$100
Technology B: NRE=$30,000, unit=$30
TechnologyC: NRE $100000 unit $2
$160,000
$200,000
A
B
C
$160
$200
A
B
C
0
0
)
o
s
t
Technology C: NRE=$100,000, unit=$2
$40,000
$80,000
$120,000
$40
$80
$120
t
o
t
a
l

c
o
s
t

(
x
1
0
p
e
r

p
r
o
d
u
c
t

c
o
$0
0 800 1600 2400
$0
0 800 1600 2400
Number of units (volume)
Number of units (volume)
But, must alsoconsider time-to-market
16
But, must also consider timeto market
The performance design metric p g
Widely-used measure of system, widely-abused
Clock frequency, instructions per second not good measures
Digital camera example a user cares about how fast it processes images, not
clock speed or instructions per second
L t ( ti ) Latency (response time)
Time between task start and end
e.g., Cameras A and B process images in 0.25 seconds
Th h t Throughput
Tasks per second, e.g. Camera A processes 4 images per second
Throughput can be more than latency seems to imply due to concurrency, e.g.
CameraB mayprocess8imagesper second(bycapturinganewimagewhile Camera B may process 8 images per second (by capturing a new image while
previous image is being stored).
Speedup of B over S = Bs performance / As performance
Throughput speedup=8/4=2
17
Throughput speedup 8/4 2
Three key embedded system technologies y y g
Technology gy
A manner of accomplishing a task, especially using technical
processes, methods, or knowledge
Three key technologies for embedded systems
Processor technology
C h l IC technology
Design technology
18
Processor technology gy
The architecture of the computation engine used to implement a
d i df i li systems desired functionality
Processor does not have to be programmable
Processor not equal to general-purpose processor q g p p p
Registers
Custom
Datapath Controller
Control logic
and State
register
Datapath Controller
Control
logic
State
index
total
+
Register
file
Datapath Controller
Control
logic and
State register
ALU
Program memory
Data
memory
IR PC
register
Data
memory
+
IR PC
General
ALU
Program Data g y
Assembly code
for:
total =0
for i =1 to
g
memory
Assembly code
for:
total =0
for i =1 to
memory
19
Application-specific Single-purpose (hardware) General-purpose (software)
Processor technology gy
Processors vary in their customization for the problem at hand
total =0
for i =1 to N loop
total +=M[i]
end loop
Desired
functionality
General-purpose
processor
Single-purpose
processor
Application-specific
processor
20
General-purpose processors p p p
Programmable device used in a variety of
applications
Datapath Controller
applications
Also known as microprocessor
Features
Register
file
p
Control
logic and
State register
Program memory
General datapath with large register file and
general ALU
IR PC
General
ALU
User benefits
Low time-to-market and NRE costs
High flexibility
Program
memory
Assembly code
for:
Data
memory
g y
Pentium the most well-known, but
there are hundreds of others
total =0
for i =1 to
21
Single-purpose processors g p p p
Digital circuit designed to execute exactly
Datapath Controller
one program
a.k.a. coprocessor, accelerator or peripheral
Features
Datapath Controller
Control
logic
State
index
total
Features
Contains only the components needed to
execute a single program
N
State
register
Data
+
No program memory
Benefits
Fast
memory
Low power
Small size
22
Application-specific processors pp p p
Programmable processor optimized for a
Datapath Controller
particular class of applications having
common characteristics
Compromisebetweengeneral-purposeand
Registers
Custom
Control
logic and
State register
Compromise between general purpose and
single-purpose processors
Features
P
IR PC
ALU
Program
Data
memory
Program memory
Optimized datapath
Special functional units
Program
memory
Assembly code
for:
memory
Benefits
Some flexibility, good performance, size and
power
total =0
for i =1 to
23
power
IC technology gy
The manner in which a digital (gate-level) g (g )
implementation is mapped onto an IC
IC: Integrated circuit, or chip
IC technologies differ in their customization to a design
ICs consist of numerous layers (perhaps 10 or more)
IC t h l i diff ith t t h b ild hl d IC technologies differ with respect to who builds each layer and
when
source drain channel
oxide
gate
Siliconsubstrate
IC package IC
24
Silicon substrate
IC technology gy
Three types of IC technologies yp g
Full-custom/VLSI
Semi-custom ASIC (gate array and standard cell)
PLD (Programmable Logic Device)
25
Full-custom/VLSI
All layers are optimized for an embedded systems y p y
particular digital implementation
Placing transistors
Sizing transistors
Routing wires
Benefits
Excellent performance, small size, low power
D b k Drawbacks
High NRE cost (e.g., $300k), long time-to-market
26
Semi-custom
Lower layers are fully or partially built y y p y
Designers are left with routing of wires and maybe placing
some blocks
Benefits
Good performance, good size, less NRE cost than a full-
customimplementation(perhaps$10kto$100k) custom implementation (perhaps $10k to $100k)
Drawbacks
Still requireweekstomonthstodevelop Still require weeks to months to develop
27
PLD (Programmable Logic Device) ( g g )
All layers already exist y y
Designers can purchase an IC
Connections on the IC are either created or destroyed to
implement desired functionality
Field-Programmable Gate Array (FPGA) very popular
B fit Benefits
Low NRE costs, almost instant IC availability
Dra backs Drawbacks
Bigger, expensive (perhaps $30 per unit), power hungry,
slower
28
sowe
Moores law
The most important trend in embedded systems p y
Predicted in 1965 by Intel co-founder Gordon Moore
IC transistor capacity has doubled roughly every 18 months
for the past several decades
10,000
1,000
100
10
1
01
Logic transistors
per chip
(in millions)
0.1
0.01
0.001
Note:
logarithmic scale
29
Moores law
Wow
This growth rate is hard to imagine, most people
underestimate
Howmanyancestorsdoyouhavefrom20generationsago How many ancestors do you have from 20 generations ago
i.e., roughly how many people alive in the 1500s did it take to make
you?
2
20 =
morethan1 million people 2 more than 1 million people
(This underestimation is the key to pyramid schemes!)
30
Graphical illustration of Moores law p
1981 1984 1987 1990 1993 1996 1999 2002
10,000
transistors
150,000,000
transistors
Leading edge
chip in 1981
Leading edge
chip in 2002
Something that doubles frequently grows more quickly
th t l li ! than most people realize!
A 2002 chip can hold about 15,000 1981 chips inside itself
31
Design Technology g gy
The manner in which we convert our concept of p
desired system functionality into an implementation
Compilation/
Synthesis
Libraries/
IP
Test/
Verification
System
specification
Behavioral
specification
Compilation/Synthesis:
Automates exploration and
insertion of implementation
details for lower level.
System
synthesis
Behavior
synthesis
Hw/Sw/
OS
Cores
Model simulat./
checkers
Hw-Sw
cosimulators
Libraries/IP: Incorporates pre-
designed implementation from
lower abstraction level into
higher level.
specification
RT
specification
synthesis
RT
synthesis
RT
components
cosimulators
HDL simulators
Logic
specification
Tofinal implementation
Test/Verification: Ensures correct
functionality at each level, thus
reducing costly iterations
between levels.
Logic
synthesis
Gates/
Cells
Gate
simulators
32
To final implementation
Design productivity exponential increase g p y p
100,000
10,000
1,000
100
i
v
i
t
y
a
f
f

M
o
.
10
1
P
r
o
d
u
c
t
i
(
K
)

T
r
a
n
s
.
/
S
t
a
0.1
0.01
1
9
8
3
1
9
8
7
1
9
8
9
1
9
9
1
1
9
9
3
1
9
8
5
1
9
9
5
1
9
9
7
1
9
9
9
2
0
0
1
2
0
0
3
2
0
0
5
2
0
0
7
2
0
0
9
Exponential increase over the past few decades
33
The co-design ladder g
In the past:
Sequential program code (e.g., C, VHDL)
Hardware and software
design technologies were
very different
Assembly instructions
Register transfers
Compilers
(1960's,1970's)
Behavioral synthesis
(1990's)
RT synthesis
Recent maturation of
synthesis enables a unified
view of hardware and
y
Machineinstructions
Assemblers, linkers
(1950's, 1960's)
RT synthesis
(1980's, 1990's)
Logic synthesis
(1970's, 1980's)
Logic equations / FSM's
software
Hardware/software
codesign
Implementation
Machine instructions
( , )
Microprocessor plus VLSI, ASIC, or PLD
Logic gates
codesign
program bits: software implementation: hardware
The choice of hardware versus software for a particular function is simply a tradeoff among various
design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no
fundamental difference between what hardware or software can implement
34
fundamental difference between what hardware or software can implement.
Independence of processor and IC
technologies technologies
Basic tradeoff
General vs. custom
With respect to processor technology or IC technology
Thetwotechnologiesareindependent The two technologies are independent
General-
purpose
processor
ASIP
Single-
purpose
processor
General, Customized,
processor processor
providing improved: providing improved:
Power efficiency
Performance
Size
Flexibility
Maintainability
NRE cost
Semi-custom PLD Full-custom
Size
Cost (high volume)
Time- to-prototype
Time-to-market
Cost (low volume)
35
Semi custom PLD Full custom
Design productivity gap g p yg p
While designer productivity has grown at an impressive rate
over the past decades, the rate of improvement has not kept
pace with chip capacity
10,000
1,000
100
10
Logic transistors
per chip
100,000
10,000
1000
100
Productivity
Gap
10
1
0.1
0.01
per chip
(in millions)
100
10
1
0.1
y
(K) Trans./Staff-Mo.
IC capacity
productivity
0.001 0.01
36
Design productivity gap g p yg p
1981 leading edge chip required 100 designer months
10,000 transistors / 100 transistors/month
2002 leading edge chip requires 30,000 designer months
150,000,000 / 5000 transistors/month , ,
Designer cost increase from $1M to $300M
10,000 100,000
1,000
100
10
1
01
Logic transistors
per chip
(in millions)
10,000
1000
100
10
1
Productivity
(K) Trans./Staff-Mo.
IC capacity
Gap
0.1
0.01
0.001
1
0.1
0.01
productivity
37
The mythical man-month y
The situation is even worse than the productivity gap indicates
In theory, adding designers to team reduces project completion time
In reality, productivity per designer decreases due to complexities of team management
and communication
I h f i k h hi l h (B k 1975) In the software community, known as the mythical man-month (Brooks 1975)
At some point, can actually lengthen project completion time! (Too many cooks)
60000
15
Team
1 i 1
20000
30000
40000
50000
60000
24
19
16
15
16
18
23
Months until completion
1M transistors, 1
designer=5000 trans/month
Each additional designer
reduces for 100 trans/month
10 20 30 40 0
10000
20000
43
Individual
p
Number of designers
So 2 designers produce 4900
trans/month each
38
Number of designers
Summaryy
Embedded systems are everywhere
Key challenge: optimization of design metrics
Design metrics compete with one another
A ifi d i f h d d ft i t A unified view of hardware and software is necessary to
improve productivity
Three key technologies y g
Processor: general-purpose, application-specific, single-purpose
IC: Full-custom, semi-custom, PLD
D i C il ti / th i lib i /IP t t/ ifi ti Design: Compilation/synthesis, libraries/IP, test/verification
39

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Embedded Systems Design: A Unified

Hardware/SoftwareIntroduction Hardware/Software Introduction

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