Active Power Filter Control Algorithm Based on

Filter Banks
K. P. Sozanski, Member, IEEE, and Z. Fedyczak, Member, IEEE
Abstract - This paper describes the proposed active power filter (APF)
with a new control circuit based on an algorithm using a filter bank and a
harmonic predictor. The control circuit was realized using the digital
signal processor ADSP-21065L and FPGA circuit. In the proposed circuit
transient performance of APF is improved. The active power filter circuit
has been built and tested, and some illustrative, experimental results are
also presented in the paper.
Index Terms digital filters, digital signal processors, active filters,
harmonic analysis, harmonic distortion
I. INTRODUCTION
O suppress power line harmonics, an active power-
harmonic-compensation filter can be used. The active
power filter (APF) can be connected in series or in parallel
with the supply network. The series APF is suitable for the
harmonic compensation of a large capacity diode rectifier with
a DC link capacitor. The parallel APF (shunt active power
filter) permits compensation of the harmonics and
asymmetries of the mains currents caused by nonlinear loads.
The parallel APF without feedback, as shown in Fig. 1 (with
unity gain), was chosen because of its greater stability in use.
Nonlinear
Load
E
s

Z
S

i
S
i
L

Z
L
Control
Circuit
i
C

Active Power Filter Power System

Fig. 1. Harmonic compensation circuit with current-fed active power filter
without feedback (with unity gain)
The shunt active power filter injects AC power current i
C

to cancel out the main AC harmonic content. The line current
i
S
is the result of summing the load current i
L
and the
compensating current i
C


K. P. Sozaski, University of Zielona Gra, Institute of Electrical
Engineering, ul. Podgrna 50, 65 246 Zielona Gra, Poland, tel.: +4868-
3282567, fax: +4868-3254615, (e-mail: K.Sozanski@iee.uz.zgora.pl).
Z. Fedyczak, University of Zielona Gra, Institute of Electrical Engineering,
ul. Podgrna 50, 65 246 Zielona Gra, Poland, tel.: +4868-3282528,
fax: +4868-3254615, (e-mail:Z.Fedyczak@iee.uz.zgora.pl).

C L S
i i i + = . (1)
A simplified diagram of the conventional parallel APF
circuit with nonlinear load consists of a thyristor power
controller in which the resistive load is depicted in Fig. 2.
Active Power Filter
L1
C2
L2 L3
C1
Q1
Q4
Q2
Q5
Q3
Q6
IC1 IC2 IC3
Power Controller
IPM
N1
V1
U1
W1
IS1
IS2
IS3
IL1
IL2
IL3
R1
R2
R3
AC Mains
3x380V
Cf1
Cf2 Cf3 3F 3F
3F
0.5mH 0.5mH
0.5mH
4.8mF
4.8mF
ADSP-
21065L &
FPGA
A/D
Converter
A/D
Converter
PLL
Program
EPROM
Q1Q6
Control Circuit
iL1iL3
uC1, uC2
iC1iC3
u1,u2,u3
u1,u2,u3

Fig. 2. Three-phase active power filter test circuit
Experimental waveforms of the APF circuit in steady-state
are shown in Fig. 3. The APF control current dynamics is
dependent on the inverter output time constant consisting of
APF output inductance and resultant impedance of load and
mains.
When the value of load current changes rapidly as in
current i
L
in Fig. 3 the APF transient response is too slow
[1], [5] and the line current i
S
suffers from dynamic distortion.
This distortion causes an increase of harmonic content in the
line current, which is dependent on a time constant. In the
APF shown in Fig. 2 the THD ratio is increased by about 10%.
The loads can be divided into two main categories:
predictable loads and noise-like loads. Most loads belong to
the first category. For this reason it is possible to predict
current values in subsequent periods, after a few periods of
observation. It is also possible to predict the current spectrum
as a function of time [2], [3], [4].
In this paper a new control algorithm with filter banks and
predictive harmonics compensation is presented. For analysis
and synthesis signal filter banks will be used.
T
0-7803-7967-5/03/$17.00 2003 IEEE
Paper accepted for presentation at 2003 IEEE Bologna Power Tech Conference, June 23th-26th, Bologna, Italy
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-20
0
20
40
-40
-20
0
20
40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-40
-20
0
20
40

Fig. 3. Experimental waveforms of an active power filter in steady-state with
the resistive load: load current i
L1
(blue), compensating current i
C1
(green),
line current i
S1
(red)
II. FILTER BANKS
Analysis filter banks decompose signal spectra into
a number of directly adjacent frequency bands and recombine
the signal spectra by means of synthesis filter banks. In most
cases signals are separated into more than two subband signals
[6], [7]. By cascading two-channel filter banks into a tree
structure it is possible to obtain a uniform M-channel filter
bank with M equalling 2. If the two-channel filter bank
provides perfect reconstruction then this also holds for the tree
structure filter bank. One disadvantage is that the tree structure
filter bank possesses high computational complexity. This is
why another filter bank has become more popular, i.e., the
uniform parallel-structured filter bank, depicted in Fig. 4.
The general form of the M-channel filter banks is shown in
Fig. 4, where M is the number of subbands. The output signal
of filter banks Y(z) can be calculated by the equation
( ) ( ) ( ) ( ) z G z H z X z Y
k
M
k
k

=
=
1
0
. (2)
It is possible to simplify this equation to
( ) ( ) ( ) z X z F z Y = , (3)
where F(z) denotes the quality of signal reconstruction.
If |F(e
j
| = 1 for all frequencies, the filter bank is without
amplitude distortion. If F(e
j
) has linear phase (constant group
delay), the filter bank is without phase distortion. When F(z) is
pure delay, the filter bank is called perfect reconstruction
(PR). A filter bank with amplitude and/or phase distortion
which can be kept arbitrarily small is called a filter bank with
almost perfect reconstruction (APR) [6].
Another function important for the discussed filter banks is
power complementary. This ensures representation of whole
input signal spectrum in subbands. For an M-channel power
complementary filter bank the square sum of transfer functions
H
k
(z) module is equal to one
( ) 1
1
0
2
=

=
M
k
k
z H
. (4)
The typical frequency responses of M-channel overlapping
uniform band analysis and synthesis filter banks are shown in
Fig. 5.

H0(z)
X(z)
Y0(z)
Analysis Filter Bank Synthesis Filter Bank
W
1
(z)=X(z)H
1
(z) Y
1
(z)
Y(z)
+
YM-1(z)
....
....
W0(z)=X(z)H0(z)
WM-1(z)=X(z)HM-1(z)
H1(z)
HM-1(z)
G0(z)
G1(z)
GM-1(z)

Fig. 4. An M-channel uniform band analysis and synthesis filter bank
III. CONTROL ALGORITHM
The control algorithm for the proposed APF is based on
filter banks with predictive harmonic compensation.
A simplified block diagram for the active power filter control
algorithm is depicted in Fig. 6.
The algorithm realized using the digital signal processor
ADSP-21065L and Field Programmable Gate Array (FPGA)
circuit is divided into two parts: the first one has sampling rate
f
p1
, and the second has sampling rate f
p2
. The digital signal
processor is synchronized with the mains voltage and the
algorithm is performed N times per mains period. For the
mains voltage frequency of f
s
=50 Hz and the number of
samples chosen to N=256 and R=8, the sampling periods is
equal T
p1
=78.125 s, T
p2
=7.766 s and the sampling rate is
equal to f
p1
=12800 samples/s f
p2
=102400 samples/s.
Three phase current signals i
L1
(nT
p1
), i
L2
(nT
p1
) i
L3
(nT
p1
) are
divided into M-subbands by analysis filter banks. In the next
stage harmonic amplitudes and phases are controlled by
predictive harmonic compensation circuits. In synthesis filter
banks harmonic signals are synthesized to current
compensating signals i
CR1
(nT
p1
), i
CR2
(nT
p1
), i
CR3
(nT
p1
). In the
next step the output compensation reference current signals
i
CR1
(nT
p1
), i
CR2
(nT
p1
) i
CR3
(nT
p1
) are interpolated with
oversampling ratio R=8, to signals i
CR1
(nT
p2
), i
CR2
(nT
p2
)
i
CR3
(nT
p2
). The chosen polyphase interpolator is based on an
FIR filter with periodically time-varying coefficients [1].
Finally, the output compensation reference current signals
are transformed to transistor controlling pulses by a current
controller. In the proposed circuit a current delta sigma
modulator (CDSM) is employed to control current, realized
using the digital signal processor ADSP-21065L [1, 4] and
FPGA.

i
L

[A]
i
C

[A]
i
S

[A]
t [s]
2
M
f
s
2
M
f
s
2
2
M
f
s
2
3
M
f
s
2
4
( )
M
f M
s
2
2 ( )
M
f M
s
2
1
2
s
f
( ) z H
0
( ) z H
1
( ) z H
2
( ) z H
3
( ) z H
M 2
( ) z H
M 1
Magnitude
Frequency

Fig. 5. Frequency responses of M-channel uniform band analysis and synthesis filter banks


i
L1
(nT
p1
)
i
L3
(nT
p1
)
sin(2n/N)

E
m1
sin(
S
t),
E
m2
sin(
S
t-2/3),
E
m3
sin(
S
t-4/3)
U
C
(nT
p1
)
i
L2
(nT
p1
)
sin(2n/N)

Synchronization Circuit
DC Voltage Controller
U
C
(nT
p1
)
U*
C
=700 V
_
U
C2
(nT
p1
)
_
U
C1
(nT
p1
)
dU
C
(nT
p1
)
U
C
(nT
p1
)
i
C1
(nT
p1
)
dU
C
(nT
p1
)
1
3
1
3 3
1

z a
z b b
1
2
1
2 2
1

z a
z b b

Analysis
F. Bank
Interpolator
R=8
Current
Controller
A/D
Converter
i
C2
(t)
i
C2r
(nT
p2
)
+
x
+
+
+
+
+
+
Lowpass Filters
f
p1
= f
s
/N
f
p2
= f
s
/(N*R)
sin(2n/N-2/(3N))

sin(2n/N-4/(3N))

Harmonic
Predictor
Sythesis
F. Bank
i
C2
(nT
p1
) Analysis
F. Bank
x
+
Harmonic
Predictor
Sythesis
F. Bank
i
C3
(nT
p1
) Analysis
F. Bank
x
+
Harmonic
Predictor
Sythesis
F. Bank
Interpolator
R=8
Current
Controller
A/D
Converter
i
C1
(t)
i
C1r
(nT
p2
)
Interpolator
R=8
Current
Controller
A/D
Converter
i
C3
(t)
i
C3r
(nT
p2
)
U
C
(nT
p1
)
U
C
(nT
p1
)
dU
C
(nT
p1
)
dU
C
(nT
p1
)
PLL

Fig. 6. Simplified block diagram for the active power filter control algorithm
For the APF control circuit a 64-channel almost perfect
reconstruction power complementary filter bank has been
chosen. Between filter banks there is placed a harmonics
predictor for predicting harmonics occurring in predictable
loads, as in Fig. 3. Amplitudes of current harmonics separated
by the analysis filter bank are stored in DSP memory and are
used to predict harmonic contents in subsequent periods. If
load current is changed during mains periods the harmonics
predictive algorithm is switch off. The algorithm waits for a
steady-state and when detected it once again switches on.
In the proposed solution the user can select which
harmonics are most important in the active power filtration
process. This is very important, especially when several APFs
are working in parallel or cascaded connection.
IV. RESULTS
A prototype of the three-phase active power filter was
built and tested in our laboratory. To model the nonlinear load
a thyristor power controller with resistive loads was used as
depicted in Fig. 2.
Oscillogram records of the various waveforms of the test
circuit are shown in Fig. 3, 7. The experimental waveforms of
the active power filter in steady-state with the resistive load
are presented in Fig. 3, 7: without predictive harmonics
compensation (Fig. 3), with predictive harmonics
compensation (Fig. 7). Depicted are the following waveforms:
load currents i
L1
, compensating currents i
C1
, line currents i
S1
.
The harmonic spectrum of the line current i
S1
for a circuit
without predictive harmonic compensation is depicted in
Fig. 8a, and with predictive harmonic compensation, in
Fig. 8b.
Using the new control algorithm with predictive harmonic
compensation it is possible to decrease the harmonic contents
in power line currents as shown in Fig. 8.
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20
40
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0
20
40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
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0
20
40

Fig. 7. Experimental waveforms of an active power filter in steady-state with
the resistive load with predictive harmonics compensation: load current i
L1

(blue), compensating current i
C1
(green), line current i
S1
(red)
-60
-40
-20
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
-60
-40
-20
0

Fig. 8. Harmonic spectrum of experimental waveforms of active power filter
in steady-state with resistive load: (a) without predictive harmonics
compensation, line current i
S1
(red), (b) with predictive compensation, line
current i
S1
(blue)
V. AN ALTERNATIVE TO FILTER BANKS
As a corollary to the solution for filter banks and harmonic
predictor the authors propose a simple alternative. In this
solution, for predictable loads it is possible to use a circuit with
non-causal current compensation. This compensation is
dependent on the inverter output time constant. Current
samples i
C
(nT
p1
) are stored in DSP memory and subsequent
periods of mains current are compared with present samples,
and if respective sample differences are less than assumed
values the non-causal current compensation algorithm is
switched on. Previous current compensation signal samples
i
C
(nT
p1
) are stored in memory, and are sent to present output in
advance. In Fig. 9 are depicted transient response of APF
current compensating signal i
C
(nT
p1
) and inverter output
current I
C
for causal case (Fig. 9a), and for non-causal case
(Fig. 9b). In the experimental circuit the timing T
A
was about
several hundred microseconds in advance. Because the time
constant is dependent on load parameter an adaptive algorithm
to calculate time ahead was employed. Block diagram of such
compensation is depicted in Fig. 10.


t
t
Amplitude
i
C
(nT
p
)
Amplitude
I
C

t
t
Amplitude
i
C
(nT
p
)
Amplitude
I
C

T
A

(a)
(b)

Fig. 9. Transient response of APF current compensating signal i
C
(nT
p
) and
inverter output current I
C
(a) causal case, (b) non-causal case

iL(nTp1)
i
C
(nT
p1
) Low-pass
Filter
Phase
Comp.
Non-causal
Compen.

Fig. 10. Simplified block diagram of harmonics compensation with non-causal
circuit
VI. CONCLUSIONS
This paper describes the proposed active power filter with a
new control circuit using a filter bank and harmonics
predictive control algorithm. The new active power filter for a
power supply of 75 kVA has been built and tested. Some
illustrative, experimental results have also been presented in
the paper. The proposed technique makes the compensation
process instantaneous, it allows optimal filtering and
cancelling of permanent errors. The new algorithm shows a
reduction in the harmonic content of line current in
comparison with classical algorithms. The control algorithm of
the proposed APF is implemented in the floating-point digital
signal processor ADSP-21065L and FPGA.
i
L

[A]
i
C

[A]
i
S

[A]
t [s]
f [Hz]
Magnitude
[dB]
(a) without predictive harmonics compensation
(b) with predictive compensation
VII REFERENCES
1. K. Sozaski, R. Strzelecki, A. Kempski, Digital Control Circuit for Active
Power Filter with Modified Instantaneous Reactive Power Control
Algorithm IEEE 33rd Annual IEEE Power Electronics Specialists
Conference - PESC '02: Conference proceedings. Cairns, Australia, 2002
.- Piscataway.
2. S. Mariethoz, A. Rufer, Open Loop and Closed Loop Spectral Frequency
Active Filtering, IEEE Transactions on Power Electronics, Vol.17, N0 4,
July 2002.
3. J. Marks, T. Green, Predictive Transient-Following Control of Shunt,
IEEE Transactions on Power Electronics, Vol.17, N0 4, July 2002.
4. M. Kazimierkowski, L. Malesani, Current Control Techniques for Three-
Phase Voltage-Source Converters: A Survey, IEEE Transactions on
Industrial Electronics Vol.45 N0 5, October 1998
5. K. Sozaski, R. Strzelecki, Aplikacyjny ukad sterowania filtrem
hybrydowym z zastosowaniem procesora sygnaowego, Sterowanie w
Energoelektronice i Napdzie Elektrycznym, Politechnika dzka, d,
1995 (in Polish).
6. N. Flige, "Multirate Digital Signal Processing", John Wiley & Sons, 1994.
7. Vaidyanathan P. P., Multirate Systems and Filter Banks, Prentice Hall Inc.,
Engelwood Cliffs, New Jersey 1992.


VIII BIOGRAPHIES
Krzysztof Sozaski (M1997) was born in
Czerwiesk, Poland, on July 25, 1957. He
received the MSc degree in electrical
engineering from the Institute of Industrial
Engineering from the Technical University of
Zielona Gra, Poland, in 1981. In 1999 he
received his PhD degree in
telecommunications from the Institute of
Electronics and Telecommunications at
Pozna University of Technology, Pozna
Poland. He is an Associate Professor at the
Institute of Electrical Engineering, University
of Zielona Gra. His current research interests
are in digital signal processing, implementation of digital signal processing
methods in digital signal processors, power electronics, and active power
filters. He is author or coauthor of more then 50 periodical and conference
papers and 1 patent.

Zbigniew Fedyczak (M1999) was born
in Zielona Gra, Poland on August 26, 1952.
He received the B.Sc. and the M.Sc. degrees
in automation and metrology from Higher
School of Engineering in Zielona Gra (at
present University of Zielona Gra), Poland,
in 1976 and 1982 respectively, and the
Ph.D.(with honors) degree in electrical
engineering from Warsaw Technical
University, Warsaw, Poland in 1996. He
worked in LUMEL, Zielona Gra, Poland as a
Design Engineer, from April 1983 to October
1992. He was involved in a AC/AC thyristor
controller design program. He joined the Institute of Electrical Engineering in
University of Zielona Gra, Poland in 1992, where he is an Associate
Professor. His research interests include power electronics, AC/AC
transforming circuits, especially topology and modeling of PWM AC line
matrix and matrix-reactance choppers, and active power filters. He is author or
coauthor of more then 60 periodical and conference papers and 10 patents. He
is a member of EPE.