MPMC Notes

PRAGATI ENGINEERING COLLEGE :: SURAMPALEM
MICROPROCESSORS & MICROCONTROLLERS

1

Introduction:
A digital computer is an interconnection of different digital modules.
Processor is the one which do operations.
Control unit issues the required control signals to perform specific task.
Processor combined with control unit often referred to as CPU (Central Processing Unit) or a CPU enclosed in a small
integrated circuit package is known as microprocessor.

Fig: Block diagram of a digital computer

Number System:
Numbers can be expressed to any base.
- If base is 2 then those numbers are known as binary numbers. In these numbers individual digits are 0 & 1.
- If base is 8 then those numbers are known as octal numbers. In these numbers individual digits vary from 0 to 7.
- If base is 10 then those numbers are known as decimal numbers. In these numbers individual digits vary from 0 to
9.
- If base is 16 then those numbers are known as hexa decimal numbers. In these numbers individual digits vary from
0 to 9, A,B,C,D,E OR F.
Any number in baser system can be converted to decimal using the formula
a
n
r
n
+ a
n-1
r
n-1
+ a
n-2
r
n-2
+ ..+ a
1
r
1
+ a
0
+ a-
1
r
-1
+ a
-2
r
-2
+ ..

Each HEX digit can be represented in binary using four bits.

Decimal Hex Binary
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111

Processor

Control Unit

Memory

Output
devices

Input
devices
2

Evolution of Microprocessors:
- Worlds first microprocessor released by Intel Corporation is 4004. It is a 4-bit microprocessor. It can address to a
memory of 4096 memory locations, each of 4- bits size. It has 45 instructions in its instruction set.
Note:
4-bit microprocessor means it can transfer 4-bits of information in parallel at a time. In other words its data bus is
of size 4-bits(D0-D3).
It can address to a memory of 4096 memory locations means its address bus is of size 12 bits(A0-A11).
- The evolution of 4-bit microprocessor ended when Intel released 4040, an updated version of 4004.
- In 1971, Intel Corporation released 8008 -an extended 8-bit version of 4004.The 8008 can address to a memory of 16K
bytes or it has 48 instructions in its instruction set.
- Small size, slow speed and limited instruction set are the general limitations in older version of microprocessors. Intel
recognized these limitations and in 1973, Intel released the first modern 8-bit p-8080.
- About 6 months after Intel recognized 8080, Motorola released MC6800 p. Some other companies like Zilog,
Rockwell also started manufacturing their own versions of ps. Zilog still manufacturers of ps, but remained in
background, concentrating on microcontrollers and embedded controllers instead of general-purpose ps. Rockwell
abandoned p development in favor of modem circuitry.
- In 1977, Intel released updated version of 8080-the 8085. This was the last general purpose p developed by Intel.
Intel has sell over 100 million copies of 8085 ps and is the most successful general purpose 8-bit p .
- In 1978, Intel released the 8086 p. It is the first 16-bit general purpose p which can address upto 1M bytes of
memory. Concept of memory segmentation was introduced in 8086 p.
- In 1979 Intel released 8088 microprocessor, which has 8-bit data bus and which can address 1M byte of memory.
- In 1983, Intel released 80286, which has the combined features of both 8086 OR 8088. It can address 16 M bytes of
memory. The clock speed of 80286 is increased sothat it can execute instructions in 250ns (4.0 MIPS) with original
8.0 MHz clock.
- Applications demand faster p speeds, more memory and wider data paths. This led to 80386 in 1986. 80386 was
Intels first practical 32-bit p which has 32-bit data bus OR 32-bit address bus. It can address upto 4G bytes of
memory.
- In 1989, Intel released 80486 p. It has an 80386-like microprocessor and an 80387-like numeric co-processor and an
8K byte cache memory system into one integrated circuit package. 80486 was available in 50 MHZ version.
Note:

Concept of Cache memory is introduced from 80486.
Cache memory is placed between main memory and CPU. It can be accessed by the CPU at a faster rate than the
main memory. It is very costly.

- In 1993 Intel introduced Pentium, which was similar to 80386 and 80486.The two introductory versions of Pentium
are available with a clock frequency of 60 MHZ and 66 MHZ and at a speed of 110 MIPS , with higher frequency of
100 MHZ that operated at 150 MIPS.
The most important feature of Pentium is its dual integer processors. Pentium executes two instructions, which are
independent on each other simultaneously. Because it contain two independent internal integer processors, called
Superscalar technology.

- Later Intel Corporation released Pentium pro, Pentium-II, Pentium-II Xeon, Pentium-III and Pentium-IV
microprocessors. These processors have 64 bit data bus width and 64GB addressable memory.
-

Microprocessors
Year of
Introduction
Word
Length
Memory
Addressing
Pins Clock Remarks
4004
1971
4 bits
1KB 16 750KHz
Intels 1st P
8008 1972 8 bits 16KB 18 800KHz
Mark-8 used this;
1st computer for the home
8080 1973 8 bits 64KB 40 2 MHz
6000trs, Altair-1st PC
8085A 1976 8 bits 64KB 40 3-6 MHz
Popular
8086 1978 16 bits 1 MB 40 5-10 MHz
IBM PC, Intel became
one of fortune 500
companies.
8088 1980 8/16 bits 1MB 40 5-8MHz
PC/XT
80186 1982 16 bits 1 MB 68 5-8MHz
More a Microcontroller
3

80286 1982 16 bits
16 MB real,
4GBv
68
60-
12.5MHz
PC/AT, 15 million PCs
sold in 6 years
80386DX 1985 32 bits
4GB real,
64TBv
132
PGA
20-
33MHz
2,75,000 transistors
80386SX 1988 16/32 bits
16MB real,
64TBv
100 20MHz
32b int
16b ext
80486DX 1989 32 bits
4 GB real,
64TBv
168
PGA
25-
66MHz
Flaot pt cop, Common
line to point and click
Pentium 1993 64 bits
4 GB, 16
KB cache
237
PGA
60-200
MHz
2 intr. At a time, Process
real world data like
sound, hand written and
photo images.
Pentium Pro 1995
64 bits
64Gb,
256K/512K
L2 Cache
387
PGA
150MHz Speedy CAD
Pentium II 1997 64 bits 64Gb 242 400MHz
Capture, edit & share
digital photos via Internet
Pentium II Xeon
1998

64 bits
512k/1M/2
M L2 cache
528 pins
LGA
400MHz
Workstations thriving on
business applications
Pentium III Xeon 1999 64 bits
16 k L1 data
+ 16 k L1
instr; 512
kB/1 MB/2
MB L2
370
PGA
1GHz e-commerce applications
Pentium IV 2000 64 bits 514,864 KB
423
PGA
1.3 -
2GHz
1.5 GHz, Professional
quality movies, rendering
3D graphics.
Xeon 2001 64 bits
8 MB iL3
cache
3.33 GHz
Choice of operating
system
Itanium 2001 64 bits
2MB/ 4MB
L3 cache
418 pins
FCPGA
800 MHz
Enabling e-commerce
security transactions
Itanium 2 2002 64 bits
1.5 9MB
L3 cache
611 pins
FCPGA
200 MHz Business applications
Centrino mobile 2003 64 bits

Mobile specific, increased
battery life.
Pentium 4 processor
extreme
2003 64 bits
2 MB L2
cache
423 pins
PGA
3.80 GHz
Hyper threading
technology, games
Centrino M (mobile) 2004 64 bits

90nm,2MB L2
cache400MHz power-
system optimized system
bus

Fig(a) 80486 DX Fig (b) Pentium
CPU
Coprocessor
8K L1 Cache
CPU1
CPU2 Coprocessor
16K L1 cache
4

Fig(c) Pentium Pro Fig (d) Pentium II, Pentium III, Pentium IV
***

Memory Segmentation:

The memory in an 8086/8088 based system is organized as segmented as segmented memory. In this scheme , the
complete physically available memory may be divided into a number of logical segments. Each segment is 64k bytes in size
OR is addressed by one of the segment registers. The 16-bit contents of the segment register actually point to the starting
location of a particular segment. To address a specific memory location within a segment , we need an offset address. The
offset address is also 16-bit long so that the maximum offset value can be FFFFH, OR the maximum size of any segment is
thus 64K locations.
The CPU 8086 is able to address 1 Mbytes of physical memory . The complete 1 Mbytes memory can be divided
into 16 segments , each of 64Kbytes size. The address of the segments may be assigned as 0000H to F00H respectively. The
offset address values are from 0000H to FFFFH so that the physical addresses range from 00000H to FFFFFH.
The main advantages of the segmented memory are
1. Allows the memory capacity to be 1Mbytes although the actual addresses to be handled are of 16-bit size.
2. Allows the placing of code, data and stack portions of the same program in different parts (segments) of
memory ,for data and code protection.
3. Permits a program and/or its data to be put into different areas of memory each time the program is executed
,i.e. provision for relocation is done.

Physical Address:
The 20- bit address of any memory location in 1MB of memory, which can be addressed by 8086 is called Physical
address.

Offset Address:
Displacement of any memory location from the starting of the segment is called Offset address

Effective Address:
Effective Address = Offset Address + Displacement, if any

Segment Base:
The most significant 16-bits of the starting address of any Segment is called Segment Base.
Note:
1. Code Segment register contain Code Segment base.
2. Data Segment register contain Data Segment base.
3. Extra Segment register contain Extra Segment base.
4. Stack Segment register contain Stack Segment base.

Calculation of Starting Address of a Segment:
To get Starting Address of any Segment, append 4-binary zeros (or) one HEX zero as least significant digit to the Segment
Base .

Therefore, Physical address= Starting address of the Segment + Effective address
16K L1 Cache
256K L2 Cache

C
P
U
1

C
P
U
3

C
O
P
R
O

16
K
L1
Cac
he

C
P
U
2
32K L1 Cache
256K (or) 512K L2 Cache
C
P
U
1

C
P
U
2

C
P
U
3

C
0
P
R
o
1

5

Fig: One way of positioning four 64-Kbyte segments within the 1-Mbyte address space of 8086

In the Overlapped Area Locations, Physical Address = CS1+IP1 = CS2+IP2 ,where + indicates the procedure of physical
address formation.

5FFFFH
70000H
7FFFFH
FFFFFH
PHYSICAL
ADDRESS
MEMORY
EXTRA SEGMENT BASE
ES=7000H
HIGHEST ADDRESS
TOP OF EXTRA SEGMENT
STACK SEGMENT BASE
SS = 5000H
TOP OF CODE SEGMENT
TOP OF STACK SEGMENT
CODE SEGMENT BASE
CS=348AH
TOP OF DATA SEGMENT
BOTTOM OF DATA SEGMENT
64K
64K
64K
64K
50000H
4489FH
348A0H
2FFFFH
20000H
6

Fig: Addition of IP to CS to produce the physical address of the code byte

Fig : Non-overlapped Segments

Fig : Overlapped Segments
348A0H
38AB4H
4489FH
PHYSICAL
ADDRESS
MEMORY
CODE BYTE
TOP OF CODE SEGMENT
START OF CODE SEGMENT
CS=348AH
IP=4214H
7

Generation of Physical address:
The 8086 microprocessor has 20 bit address pins. These are capable of addressing 2
20
= 1Mega Byte memory. To generate
this 20 bit physical address from 2 sixteen bit registers, the following procedure is adopted.
The 20 bit address is generated from two 16-bit registers. The first 16-bit register is called the segment base register. These
are code segment registers to hold programs, data segment register to keep data, stack segment register for stack operations
and extra segment register to keep strings of data. The contents of the segment registers are shifted left four times with
zeroes (0s) filling on the right hand side. This is similar to multiplying four hex numbers by the base 16. This
multiplication process takes place in the adder and thus a 20 bit number is generated. This is called the base address. To
this a 16-bit offset is added to generate the 20-bit physical address.

Segmentation helps in the following way. The program is stored in code segment area. The data is stored in data segment
area. In many cases the program is optimized and kept unaltered for the specific application. Normally the data is variable.
So in order to test the program with a different set of data, one need not change the program but only have to alter the data.
Same is the case with stack and extra segments also, which are only different type of data storage facilities.

Generally, the program does not know the exact physical address of an instruction. The assembler, a software which
converts the Assembly Language Program (MOV, ADD etc.) into machine code (3EH, 4CH etc) takes care of address
generation and location.

Example1:
Segment base value in CS = 348AH
20- bit starting address of code segment = 348A0H
(It is shifted by one position OR LSB is loaded with zeros)
16 -bit EA or offset in IP = 4214H
The 20- bit physical address of 38AB4H is quite often represented in segment based, offset form as 348A:4214, as this from
clearly indicate the segment base value OR the EA.

In an 8086 based system , the 1Mbyte of memory organized as odd bank and even bank , each of 512k bytes ,addressed
in parallel by the processor .Byte data with even address is transferred on D7-D0, while the byte data with odd address is
transferred on D15-D8 bus lines. The processor provides two enable signals, BHE and A0 for selection of either even or
odd or both the banks.

In referring word data , the BIU requires one or two memory cycles, depending upon whether the starting byte is located
at an even or odd address .It is always better to locate the word data at an even address. To read or write a complete word
from/or to memory, if it is located at an even address , only one read or write cycle is required . If the word is located at an
odd address , The first cycle is required for accessing the lower byte while the second one is required for accessing the upper
byte. Thus two bus cycles are required , if a word is located at an odd address.

8086 Memory Addressing :
The 8086 memory address space can be viewed as a sequence of one million bytes in which any byte may contain an 8-
bit data element and any two consecutive bytes may contain a 16-bit data element. There is no constraint on byte or word
address boundaries. The address space is physically connected to a 16-bit data bus by dividing the address space into two 8-
bit banks of up to 512K bytes each.
One bank is connected to the lower half of the 16-bit data bus (D0 D7) and contains even address bytes. i.e., when A0
bit is low, the bank is selected. The other bank is connected to the upper half of the data bus (D8 - D15) and contains odd
address bytes. i.e., when A0 is high and BHE (Bus High Enable) is low, the odd bank is selected. A specific byte within
each bank is selected by address lines A1-A19.

8

Higher
Address
Bank
(512K x 8)
ODD
Lower
Address
Bank
(512K x 8)
EVEN
A1-A19
Address Bus
Data Bus (D0 - D15)
D8-D15
D0-D7
BHE
A0

Fig. Organization of 1 Mega byte of memory in 8086
Data can be accessed from the memory in four different ways. They are:
8 - bit data from Lower (Even) address Bank.
8 - bit data from Higher (Odd) address Bank.
16 - bit data starting from Even Address.
16 - bit data starting from Odd Address.
8-bit data from Even address Bank :

A1-A19
D0-D15
BHE = 1
D8-D15 D0-D7
A0 = 0
x
x + 2
x + 4
x + 1
x + 3
x + 5
Odd Bank Even Bank

Fig. 8-bit data access from an even address
To access memory bytes from Even address, information is transferred over the lower half of the data bus (D0- D7).
The A0 is output LOW and BHE is output HIGH enabling only the even address bank. It is illustrated in fig. 6.

Example: Consider loading a byte of data into CH register (higher order 8-bits of CX register) from the memory location with
an even address. The data will be accessed from the even bank via the (D0 - D7) DATA BUS. Although this data is
transferred into the 8086 over the lower 8-bit lines, the 8086 automatically redirects the data to the higher 8-bits of its internal
16-bit data path and hence to the CH-register. This capability allows bytes input - output transfer via the AL register to access
I/O device connected to either the upper half of the data bus or the lower half of the 16-bit data bus.

8-bit Data from Odd Address Bank:
To access memory byte from an odd address information, is transferred over the higher half of the data bus (D8 -
D15). The BHE output low enables the upper memory bank. A0 is output high to disable the lower memory bank. It is
shown in the following figure.
A1-A19
D0-D15
BHE =0 A0 = 1
x
x + 2
x + 1
x + 3
Odd Bank Even Bank
D8-D15
D0-D7

9

Fig. 8-bit data access from an Odd address
16-bit Data Access starting from Even Address:

A1-A19
D0-D15
BHE =0
A0 = 0
x
x + 2
x + 1
x + 3
Odd Bank Even Bank
D8-D15
D0-D7

Fig. 16-bit data access from an Odd address
16-bit data from an even address is accessed in a single bus cycle. Address lines A1 - A19 select the appropriate
byte within each bank. A0 low and BHE low enables both banks simultaneously. This is shown in the above figure.
16-bit Data Access starting from Odd Address:
A 16-bits word located at an odd address (two consecutive bytes with the least significant byte at an odd byte
address) is accessed using two bus cycles. During the first bus cycle the lower byte (with the odd address 0005H ) is
accessed.
A1-A19
Odd Bank
Even Bank
D8-D15
D0-D7
A1-A9
0005
0007
0009
0004
0006
0008
A1-A19
Odd Bank
Even Bank
D8-D15
D0-D7
A1-A9
0005
0007
0009
0004
0006
0008
(a) First Access from Odd Address (b) Next Access from Even Address

Fig.

During the second bus cycle, the upper byte (with the even address 0006H as in fig. 9 (b)) is accessed. During the
first bus cycle, A1 - A19 address bus specifies the address and A0 as 1 and BHE is low. Therefore the even memory bank is
disabled and odd memory bank is enabled. During the second bus cycle, the address is incremented. Therefore A0 is zero
and BHE is made high. The even memory bank is enabled and the odd memory bank is disabled.

ADDRESS

DATATYPE

BHE

A0

BUS CYCLES

DATALINES
USED

0000

0000

0001

0001

BYTE

WORD

BYTE

WORD

1

0

0

0

1

0

0

1

1

0

ONE

ONE

ONE

FIRST

SECOND

D0-D7

D0-D15

D7-D15

D7-D15

D0-D7

1. Certain locations in memory are reserved for specific CPU operations. The many locations from FFFF0H to FFFFFH are
reserved for operations including jump to initialization
2. The locations 00000H to 003FFH are reserved for interrupt vector table.
10

***
Addressing Modes of 8086:
Different ways of addressing the operands to access the data, which is required to execute the instructions are known
as addressing modes.
I. Immediate addressing mode:
Ex: MOV AX, 1234H
Above instruction copies the immediate word 1234H into the register AX.
In the above instruction, source operand is specified using Immediate addressing mode.
II. Register addressing mode:
Ex: MOV AX, BX
Above instruction copies the word in BX to the register AX.
In the above instruction, source and destination operands are specified using Register addressing mode.
III. Memory Addressing mode:
a) Direct Memory addressing:
If the offset address of the memory location is specified directly in the instruction itself then it is called Direct
Memory addressing.
Ex: MOV AX, [1234H]
Above instruction copies the word from the memory location whose offset address is 1234H into the register AX.
In the above instruction, source operand is specified using Direct memory addressing mode.

b) Indirect Memory addressing:
If the offset address of the memory location is specified in an indirect way then it is called Indirect Memory
addressing.
(i) Register Indirect addressing:
If the offset address of the memory location is specified using a register then it is called Register Indirect
Memory addressing.
Ex: MOV AX, [BX]
Above instruction copies the word from the memory location whose offset address is content of BX to the register
AX.
In the above instruction, source operand is specified using Register Indirect memory addressing.
(ii) Based addressing with displacement:
If the offset address of the memory location is specified using one of the base register and displacement
then it is called Based addressing with displacement.
Ex: MOV AX, 1234H[BX]
Above instruction copies the word from the memory location whose offset address is [BX] + 1234 H into the
register AX.
In the above instruction, source operand is specified using Based addressing with displacement mode of
addressing.
(iii) Indexed addressing with displacement:
If the offset address of the memory location is specified using one of the Index register and displacement
then it is called Indexed addressing with displacement.
Ex: MOV AX, 1234H[SI]
Above instruction copies the word from the memory location whose offset address is [SI] + 1234 H into the
register AX.
In the above instruction, source operand is specified using Indexed addressing with displacement mode of
addressing.
(iv) Based Indexed addressing:
If the offset address of the memory location is specified using one of the Base register and one of the
Index register then it is called Based Indexed addressing.
Ex: MOV AX, [BP][DI]
Above instruction copies the word from the memory location whose offset address is [BP] + [DI] to the register
AX.
In the above instruction, source operand is specified using Based Indexed addressing.
(v) Based Indexed addressing with addressing:
If the offset address of the memory location is the sum of the content of one of the Base register,one
of the Index register and displacement then it is called Based Indexed addressing with displacement.
Ex: MOV AX, 1234H[BX][DI]
Above instruction copies the word from the memory location whose offset address is [BX] + [DI]+ 1234 H to the
register AX.
In the above instruction, source operand is specified using Based Indexed addressing with displacement.
IV. I/O Port addressing:
a) Fixed Port addressing:
If Port address is specified directly in IN/OUT instruction, then it is called Fixed Port addressing.
Ex: IN AL,55H
Above instruction reads a byte from the port whose address is 55H to AL.
11

b) Variable Port addressing:
If Port address is specified using DX register in IN/OUT instruction, then it is called Variable Port addressing.
Ex: OUT DX,AX
Above instruction writes a word in AX to the port whose address is the content of DX.

***

Architecture of 8086:

8086 CPU is divided into two independent functional parts, the Bus Interface Unit (BIU), and the Execution Unit
(EU). Dividing the work between these two units speeds up processing.

The BIU sends out addresses, fetches instructions from memory, reads data from ports and memory, and writes data
to ports and memory. In other words, the BIU handles all transfers of data and addresses on the buses for the execution unit.

The execution unit of the 8086 tells the BIU where to fetch instructions or data from, decodes instructions, and
executes instructions.

Bus Interface Unit (BIU):
The BIU sends out addresses, fetches instructions from memory, reads data from memory and ports, and writes data
to ports and memory. In other words the BIU handles all transfers of data and addresses on the buses for the execution unit.
The BIU has
1. An instruction queue
2. An Instruction pointer
3. Segment registers
12

The Bus Interface Unit consists of segment registers, adder to generate 20 bit address and instruction pre-fetch and
queue. Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and they fill a First In
First Out 6- byte long queue.

The Queue:

While the EU is decoding an instruction or executing an instruction which does not require use of the buses, the BIU
fetches up to six instruction bytes for the following instructions. The BIU stores these pre fetched bytes in a first-in first- out
register set called a queue. When the EU is ready for its next instruction, it simply reads for its next instruction, it simply
reads the instruction bytes for the instruction from the queue.

To speed up program execution, the BIU fetches as many as 6 insturction bytes ahead of time from memory. The
prefetched instruction bytes are held for the EU in a first-in-first-out group of register called a queue. The EU decodes an
instruction or executes an instruction which does not require the buses. When the EU is ready for its next instruction, it
simply reads the instruction from the queue in the BIU. Fetching the
next instruction while the current instruction executes, is called pipelining.
Note: The 8088 microprocessor has only a 4-byte queue.
Instruction Pointer (IP):
The Instruction Pointer is a 16-bit register. This register is always used as the effective memory address, and is
added to the Code segment with a displacement of four bits to obtain the physical address of the opcode. The code segment
cannot be changed by the move instruction. The instruction pointer is incremented after each opcode fetch
to point to the next instruction.
Segment Registers:
The 8086 / 8088 microprocessor has 20-bit address lines. All the registers in 8086 / 8088 are 16-bits in length.
Hence to obtain 20-bit addresses from the available 16-bit registers, all 8086 / 8088 memory addresses are computed by
summing the contents of a segment register and effective memory address. The effective memory address is computed via a
variety of addressing modes. The process of adding, to obtain 20-bit address is as follows:
The selected segment register contents are shifted-left four bits (i.e., the contents are multiplied by 16 decimal), and
then added to the effective memory address to generate the actual physical address output.

Segment Register value
i.e., Segment Base
( CS, DS, ES or SS)

x x x x x x x x x x x x x x x x
Starting address of the segment x x x x x x x x x x x x x x x x 0 0 0 0
Effective Memory Address y y y y y y y y y y y y y y y y
Physical Address wwww wwww wwww wwww wwww
Table
The table shows 16-bits of the segment registers CS, DS, ES or SS displaced by 4-bits to the left. The effective
address is calculated depending on the type of addressing mode. The effective address is shown as yyyy yyyy yyyy yyyy.
The 20-bit physical address wwww wwww wwww wwww wwww is obtained after adding the segment register value and
effective address. The physical address is 20-bits wide.
To understand how the segmentation is used, it is required to know the memory structure of the 8086 / 8088
microprocessor.
The memory in an 8086/8088 system is a sequence of up to 2
20
= one million bytes. A word is any two consecutive
bytes in memory (word alignment is not required). Words are stored in memory with the most significant byte at the higher
memory address. These bytes are stored sequentially from byte 00000 to byte FFFFF hex.
Programs view memory space as a group of segments defined by the application. A segment is a logical unit of
memory that may be up to 64K bytes long. Each segment is made up of contiguous memory locations and is an independent,
separately addressable unit. Each segment is assigned a base address, which is its starting location in the memory space. All
segments start on 16-bit memory boundaries. Segments may be adjacent, disjoint, partially overlapped, or fully overlapped.
It is as shown in figure below.
The segment registers point to the four immediately addressable segments. The four segment registers are
Code Segment register [points to the instruction opcode]
Data Segment register [points to the data memory]
Stack Segment register [points to the Stack memory]
Extra Segment register [points to the data memory]
13

0 10000h 20000h 30000h
Segment A Segment B
Segment C
Segment D
Segment E
Contiguous memory
Fully overlap
Disjoint
Partial overlaped

The segment registers and their default offsets are given below.
Segment Register Default Offset
CS IP (Instruction Pointer)
DS SI, DI
SS SP, BP
ES DI

FFFFFH
A
B
C
D
E
F
G
I
H
J
00000H
CS
DS
SS
ES

Above figure shows the segment registers pointing to the various memory segments. Since logical addresses are 16-
bits wide, up to 64K (65536) bytes in a given segment can be addressed.
Each time the CPU need to generate a memory address, one of the segment registers is automatically chosen and its
contents added to a logical address.
For an instruction fetch, the code segment register is automatically added to the logical address (in this case, the
contents of the instruction pointer) to compute the value of the instruction address.
For stack referencing the stack segment register is automatically added to the logical address (the SP or BP register
contents) to compute the value of the stack address.
For data reference operations, where either the data or extra segment register is chosen as the base, the logical
address can be made up of many different types of values: it can be simply the immediate data value contained in the
instruction, or it can be the sum of an immediate data value and a base register, plus an index register. Generally, the
selection of the DS or ES register is made automatically, though provisions do exist to override this selection. Thus any
memory location may be addressed without changing the value of the segment base register. In systems that use 64K or
fewer bytes of memory for each memory area (code, stack, data and extra), the segment registers can be initialized to zero at
the beginning of the program and then ignored, since zero plus a 16-bit offset yields a 16-bit address. In a system where the
total amount of memory is 64K bytes or less, it is possible to set all segments equal and have fully overlapping segments.
Segment registers are also very useful for large programming tasks, which require isolation of program code from
the data area, or isolation of module data from the stack information etc.
Segmentation makes it easy to build re-locatable and reentrant programs. In many cases, the task of relocating a
program (relocation means having the ability to run the same program in several different areas of memory without changing
addresses in the program itself) simply requires moving the program code and then adjusting the code segment register to
point to the base of the new code area. Since programs can be written for the 8086 / 8088 in which all branches and jumps
are relative to the instruction pointer, it does not matter what value is kept in the code segment register. Every application
will define and use segments differently. The currently addressable segment override provide, a generous workspace: 64K
bytes for code, 64K bytes stack and 128K bytes of data storage.
14

Solved Problems
1. If a physical branch address is 5A230 H when (CS) = 5200 H, what will it be if the (CS) are changed to 7800 H.
CS: 52 0 0
Offset: XXXX
Physical add. 5A2 3 0 H
Hence Offset = Physical add - (Segment address displaced by 4-bits)
Offset = 5A230 - 52000 = 8230 H
If the CS is changed to 7800 H the Physical address will be 78000 + 8230 = 80230
2. Given that the EA of a datum is 2359 H OR the DS = 490B H, what is the physical address of the datum?
DS: 490B0 H
EA: 2359 H
Physical add. 4B409H

Execution Unit (EU):
The execution unit consists of
1. General Registers
2. Arithmetic Logic Unit
3. Control unit
4. Flag Registers
The execution unit and the Bus Interface unit operate asynchronously. The EU waits for the instruction object code
to be fetched from the memory by the BIU.
The BIU fetches or pre-fetches the object code (16-bits at a time) and loads it into the six bytes queue. Whenever
the EU is ready to execute a new instruction, it fetches the instruction object code from the front of the instruction queue and
executes the instruction in specified number of clock periods.
If memory or Input/output devices must be accessed in the course of executing an instruction, then the EU informs
the BIU of its needs. The BIU completes its operation code (opcode) fetch cycle, if in progress, and executes an appropriate
external access machine cycle in response to the EU demand.
The BIU is independent of the EU and attempts to keep the six-bytes queue filled with instruction object codes. If
two or more of these six bytes are empty, then the BIU executes instruction fetch machine cycles as long as the EU does not
have an active request for the bus access pending. If the EU issues a request for the bus access while the BIU is in the middle
of an instruction fetch machine cycle, then the BIU will complete the instruction fetch machine cycle before honoring the EU
bus access request.
The EU does not use machine cycles; it executes instructions in some number of clock periods that are not subjected
to any type of machine cycles. The only time clock periods are grouped is clock when the bus control logic wishes to access
memory or I/O devices.

General Registers
The CPU has eight 16-bit general registers. They are divided into two files of four registers each. They are:
(a) The data register file and
(b) The pointer and index register file

AX
BX
CX
DX
AL AH
BL BH
CL
CH
DL
DH

Fig. Data Register File
AX, BX, CX OR DX registers are the data registers. The upper and lower halves of the data registers are
individually addressable. AX register can be addressed as AL and AH registers, BX register can be addressed as BL and BH
register, CX register can be addressed as CL and CH register, DX register can be addressed as DL and DH.
The data registers can be used in most arithmetic and logic operations. Some instructions however require these
registers for specific use. This implicit register usage allows a more compact instruction encoding. Fig.1.4 shows the data
registers specific one. The index register file consists of the Stack Pointer (SP), the Base Pointer (BP), Source Index (SI) and
Destination Index (DI) registers all are of 16-bits. They can also be used in most arithmetic and logic operations. These
registers are usually used to hold offset addresses for addressing within a segment. Offset addressing reduces program size by
eliminating the need for each instruction to specify frequently used addresses.
The pointer and index register files are further divided into the pointer sub-file (containing the Stack Pointer and the
Base Pointer registers) and the index sub-file (containing the Source index and Destination index registers). The Pointer
registers are used to access the current stack segment. The index registers are used to access the current data. (Stack segment
and data segment are specific areas of memory. Their application will be explained in later chapters). Unless otherwise
specified in the instruction, stack pointer registers refer to the current stack segment while index register refers to the current
data segment.
15

The BP and SP registers are both used to point to the stack, a linear array in the memory used for subroutine
parameters, subroutine return addresses, and the data temporarily saved during execution of a program
The implicit register usage is as follows:
AX Register Word Multiplication
Word Division and
Word I/O Operation.
AL Register Byte Multiplication
Byte Division
Byte I/O
Translate, and
Decimal Arithmetic
AH Register Byte Multiplication
Byte Division.
BX Register Base Register
Translate
CX Register String Operations
CL Register Variable Shift OR Rotate
DX Register Word Multiplication, Word
Division,
Indirect I/O.
Fig.
Most microprocessors have a single stack pointer register called the SP. 8086 / 8088 has an additional pointer into
the stack called the BP register. While the SP is used similar to the stack pointer in other machine (for pointing to subroutine
and interrupt return addresses), the BP register is used to hold an old stack pointer value, or it can mark a place in the
subroutine stack independent of the SP register. Using the BP register to mark the stack saves the juggling of a single stack
pointer to reference subroutine parameters OR addresses.
SI OR DI are both 16-bits wide and are used by string manipulation instructions and in building some of the more
powerful 8086/8088 data structures and addressing modes. Both the SI and the DI registers have auto incrementing and auto-
decrementing capabilities.

IP
SR
DI
SI
BP
SP
DX
CX
AX
BX
ES
SS
DS
CS
Instruction Pointer
Code Segment Register
Data Segment Register
Stack Segment Register
Extra Segment Register
AH
Stack Pointer Register
AL
BE BL
CE CL
DH DL
Break Pointer Register
Source Index Register
Destination Index Register
Status Register

Code Segment (64Kb)

Data Segment (64Kb)

Stack Segment (64Kb)

Extra Segment (64Kb)

FFFFF
16

000000
16

8086/8088 MPU

MEMORY

16

Arithmetic Logic Unit (ALU)
ALU is 16-bits wide. It can do the following 16-bits arithmetic operations
(i) Addition
(ii) Subtraction
(iii) Multiplication
(iv) Division

Arithmetic operations may be performed on four types of numbers
Unsigned binary numbers
Signed binary numbers (Integers)
Unsigned packed decimal numbers
Unsigned unpacked decimal numbers
The ALU can also perform logical operations such as
(i) AND
(ii) OR
(iii) NOT
(iv) EXCLUSIVE OR
(v) TEST
The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The results of these operations can
affect the condition flags.
Control Circuitry:

Generation of 20-bit Physical Address:

Flag Register:
A flag is a flip-flop which indicates some condition produced by the execution of an instruction or controls certain operations
of the EU
The six conditional flags in the flag register are
Carry flag(CF)
Parity flag(PF)
Auxiliary Carry flag(AF)
Zero flag(ZF)
Sign flag(SF)
Overflow flag(OF)

The three remaining flags in the flag register are control certain operations of the processor.
The three control flags are the trap flag(TF), which is used for single stepping through a program; the
interrupt flag(IF),which is used to allow or prohibit the interruption of a program; and the Direction flag(DF), which is used
with string instructions.

LOGICAL ADDRESS
SEGMENT REGISTER 0000
ADDER
20 BIT PHYSICAL MEMORY ADDRESS
17

Conditional Flags:
Carry Flag (CF)
This flag will be set to one if the addition of two 16-bit binary numbers produces a carry out of the most significant
bit position or if there is a borrow to the MSB after subtraction. This flag is also affected when other arithmetic and logical
instruction are executed.

Parity Flag (PF)
This flag is set, if the result of the operation has an even number of 1's (in the lower 8 bits of the result). This flag
can be used to check for data transmission error.

Auxiliary Carry Flag (AF)
This flag is set, when there is a carry out of the lower nibble to the higher nibble or a borrow from the higher nibble
to the lower. The auxiliary carry flag is used for decimal adjust operation. The AF flag is of significance only for byte
operations during which the lower order byte of the 16-bit word is used.

Zero Flag (ZF)
This flag is set when the result of an operation is zero. The flag is reset when the result is not zero.

Overflow Flag (OF)
This flag is set, when an arithmetic overflow occurres. Overflow means that the size of the result exceeded the
storage capacity of the destination, and a significant digit has been lost.

(a) : CARRY FLAG SET BY CARRY OUT OF MSB
(b) : PARITY FLAG SET IF RESULT HAS EVEN PARITY
(c) : AUXILIARY CARRY FLAG FOR BCD
(d) : ZERO FLAG SET IF RESULT = 0
(e) : SIGN FLAG = MSB OF RESULT
(f) : SINGLE STEP TRAP FLAG
(g) : INTERRUPT ENABLE FLAG
(h) : STRING DIRECTION FLAG
(i) : OVERFLOW FLAG
(i)
(h)
(g)
(f)
(e)
(d)
(b)
(c)
(a)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
U U U U 0F
DF
IF TF SF ZF U
AF
U PF U
CF
U= UNDEFINED
BIT
18

Sign Flag (SF)
This flag is set, when an MSB bit of the result is high after an arithmetic operation. When this flag is set the data in
assumed to be negative and when this flag is zero it is assumed to be positive.
Control Flags:
Control flags are used to control certain operations of the processor. The application of these flags are different
from that of six conditional flags. The conditional flags are set or reset by the EU on the basis of the result of some
arithmetic or logic operations. The control flags are deliberately set or reset with specific instructions included in the
program.

Trap flag (TF)
This is used for single stepping through a program. It is used for debugging the programs. (Discusses with
interrupts).
Interrupt Flag (IF)
It is used to allow / prohibit the interruption of a program. When the flag set, it enables the interrupt from INTR.
When the flag is reset (0), it disables the interrupt.
Direction Flag (DF)
It is used for string instructiion (Discussed with the specific instructions later inthe book). If the direction flag is
set, the pointers are decremented else the pointers areincremented.
There are three internal buses, namely A bus, B bus and C bus, which interconnect the various blocks inside 8086.
The execution of instruction in 8086 is as follows:
The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and fetches the first instruction of a
program from the memory. Subsequent addresses are sent out and the queue is filled upto 6 bytes. The instructions are
decoded and further data (if necessary) are fetched from memory. After the execution of the instruction, the results may go
back to memory or to the output peripheral devices as the case may be.

Instruction Set of 8086:
I. Data Transfer Instructions: MOV,PUSH,PUSHF,POP,POF,XCHG,XLAT,LEA,LDS,LES,LAHF,SAHF,IN & OUT
II. (a) Arithmetic Instructions: ADD, ADC, INC ; SUB,SBB,CMP,NEG ; MUL,IMUL ; DIV, IDIV ; CBW, CWD
(b) Logical Instructions: AND, OR, NOT, XOR, TEST
(c) Shift Instructions: SAL/SHL, SAR, SHR
(d) Rotate Instructions: ROL, ROR, RCL, RCR
(e) String Instructions:
MOVS/MOVSB/MOVSW, CMPS/CMPSB/CMPSW, SCAS/SCASB/SCASW, LODS/LODSB/LODSW,
STOS/STOSB/STOSW
(f) Repeat : REP/REPE(or)REPZ/REPNE (or) REPNZ

III. Program Control Instructions:
(a) Unconditional Jump Instructions: JMP,CALL, RET
(b) Conditional Jump Instructions:
JAE/JNB, JA/JNBE, JB/JNAE, JBE/JNA,
JGE/JNL, JG/JNLE, JL/JNGE, JLE/JNG,
JC,JNC,JP/JPE,JNP/JPO,JE/JZ,JNE/JNZ, JS,JNS,JO,JNO
(c) Iteration Control Instructions:
LOOP/LOOPE (or) LOOPZ/ LOOPNE (or) LOOPNZ, JCXZ

IV. Some other Instructions:
(a) Flag set/Reset Instructions: STC,CLC,CMC ; STD,CLD ; STI,CLI
(b) External Hardware Synchronization Instructions: LOCK, WAIT, HLT, NOP
(c) Decimal Adjust Instructions: AAA,AAS,AAM,AAD,DAA

***

19

I. Data Transfer Instructions: MOV,PUSH,PUSHF,POP,POF,XCHG,XLAT,LEA,LDS,LES,LAHF,SAHF,IN & OUT

MOV (Copy a byte/ word)
MOV Destination, Source
MOV instruction is used to copy a byte/word from the specified source to the specified destination. Source can be an
immediate number (or) a register (or) a memory location that can be addressed by anyone of the 24 addressing modes.
Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressing modes.
Note:
1. Both Source and Destination should not be two memory locations.
PUSH
PUSH Source
PUSH instruction decrements the Stack Pointer (SP) register by two and it pushes the word from the specified source to the
memory location(s) now pointed to by SP. Source can be a register (or) a memory location that can be addressed by anyone
of the 24 addressing modes.
Note:
1. Stack: Stack is a section of memory set aside to store data and addresses while a subprogram is executing.
2. Top of the Stack: It is the memory location in stack, where a word was most recently stored.

PUSHF (Push the Flag Register on the stack)
PUSHF
PUSHF instruction decrements the Stack Pointer (SP) register by two OR it pushes the current status of the Flag register to
the memory location(s) now pointed to by SP.

POP:
POP Destination
POP instruction copies the word from the top of the stack to the specified destination OR it increments the Stack Pointer(SP)
register by two. Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressing
modes.

POPF(POP word from the top of the stack to the Flag register)
POPF
POF instruction copies the word from the top of the stack to the Flag register and it increments the Stack Pointer(SP) register
by two.

XCHG:
XCHG Destination, Source
XCHG instruction interchanges the contents of the specified source and the specified destination. Source can be a register
(or) a memory location that can be addressed by anyone of the 24 addressing modes. Destination can be a register (or) a
memory location that can be addressed by anyone of the 24 addressing modes.
Note: 1. Both Source and Destination should not be two memory locations.
XLAT/ XLATB (Translate a byte in AL)
XLATB
XLATB instruction translates a byte in AL from one code to another code. This instruction replaces the byte in AL with a
byte pointed to by BX in a lookup table in memory. Before the XLATB instruction can be executed, the lookup table
containing the values for the new code must be put in memory. It copies the byte from the address pointed to by [BX]+[AL]
back into AL.

LEA (Load Effective Address)
LEA Register, Source
LEA instruction determines the offset address of a variable or memory location named as source and puts this offset address
into the specified register.

LES (Load Register OR ES with words from Memory)
LES Register, Memory address of First Word)
LES instruction copies a word from the two memory locations into the register specified in the instruction. It then copies the
word from next two memory locations into ES register.
Note: 1.LES can be used to point DI and ES at the start of a string before a string instruction is to be executed.

LDS:
LDS Register, Memory address of First Word)
LDS instruction copies a word from the two memory locations into the register specified in the instruction. It then copies the
word from next two memory locations into DS register.
Note: 1.LDS can be used to point SI and DS at the start of a string before a string instruction is to be executed.
2. LDS BX,[4326] instruction copies the byte from the memory at a displacement 4326H in DS into BL, byte from 4327H
into BH. Then it copies the content at a displacement of 4328H and 4329H in DS into DS register
3. Unlike all other instructions, LDS and LES instructions copies two words.

20

LAHF (Copy Low byte of Flag register into AH)
LAHF
The lower byte of 8086 flag register is same as the flag byte for 8085. LAHF instruction copies the low byte of 8086 flag
register into AH.

SAHF(Copy AH register into Low byte of Flag register)
SAHF
SAHF instruction replaces the low byte of 8086 flag register with AH.

IN (Copy data from a Port)
IN Accumulator, Port
IN instruction copies the data from a port to the AL or AX register. If an 8-bit port is read, the data will go to AL. If a 16-bit
port is read, the data will go to AX.

Note:
1. IN instruction has two possible formats, Fixed Port and Variable Port.
-If Port address is directly specified in the instruction itself then it is called Fixed port addressing.
-If port address is loaded into DX register before IN instruction and that DX is specified in IN instruction then it is called
Variable port addressing.
2. Variable port addressing is useful where we need to compute the port address dynamically during the execution of
instructions.
3. Using DX register, 65,536 ports can be addressed in this Variable Port addressing.

OUT (Output a byte or word to a port)
OUT Port, Accumulator
OUT instruction copies a byte from AL or word from AX to the specified port.
Note:
1. OUT instruction has two possible formats, Fixed Port and Variable Port.
-If Port address is directly specified in the instruction itself then it is called Fixed port addressing.
-If port address is loaded into DX register before IN instruction and that DX is specified in OUT instruction then it is called
Variable port addressing. Here the content from AL or AX will be copied to the port whose address is in DX.
2. Variable port addressing is useful where we need to compute the port address dynamically during the execution of
instructions.
3. Using DX register, 65,536 ports can be addressed in this Variable Port addressing.

II.a) Arithmetic Instructions:
ADD (Add)
ADC (Add with Carry)
ADD/ADC Destination, Source
ADD instruction adds the content of the specified source to the content of the specified destination and result will be stored in
the specified destination.
ADC instruction adds the content of the specified source to the content of the specified destination along with the status of
the Carry and result will be stored in the specified destination.
Source can be an immediate number (or) a register (or) a memory location that can be addressed by anyone of the 24
addressing modes. Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressing
modes. Both Source and Destination should not be two memory locations.
CF, PF, AF, ZF, SF and OF will be effected by these instructions.

INC (Increment)
INC Destination
INC instruction adds 1 to the content of the specified destination. Destination can be a register (or) a memory location that
can be addressed by anyone of the 24 addressing modes.
PF, AF, ZF, SF and OF are updated by this instruction Note that CF is not affected.
Note:
1.If an 8-bit destination containing FFH (or) a 16-bit destination containing FFFFH is attempted to increment, result will be
all 0s with no carry.

SUB (Subtract)
SBB (Subtract with Borrow)
SUB/SBB Destination, Source
SUB instruction subtracts the number in the specified source from the number in the specified destination and put the result
in the specified destination.
21


Note:
1 .In all subtraction operations, Carry Flag acts like Borrow Flag.

SBB instruction subtracts the content of the specified source and the content of CF from the content of the specified
destination and result is put in the specified destination.

CMP (Compare Byte/Word)
CMP Destination, Source
CMP instruction compares a byte/word from the specified source with a byte/word from the specified destination.
Comparison is actually done internally using Subtraction, but result will not be stored in either of the operands. But based
on the result flags will be effected.
In the example, CMP AX,BX

CF ZF SF
[AX] > [BX] 0 0 0

[AX] = [BX] 0 1 0

[AX] < [BX] 1 0 1

NEG (Form 2s complement)
NEG Destination
NEG instruction replaces the number in the specified destination with the 2s complement of that number. Destination can be
a register (or) a memory location that can be addressed by anyone of the 24 addressing modes.

MUL (Multiplication of unsigned numbers)
MUL Source
MUL instruction multiplies an unsigned byte from some source with an unsigned byte in AL register (or) an unsigned word
from some source with an unsigned word in AX. Source can be register (or) a memory location, which can be addressed by
any one of the 24-addressing modes.
- When a byte is multiplied by the byte in AL, result is a word and is stored in AX.
- When a word is multiplied by the word in AX, result is as long as 32-bits( double word) . The most significant
word of that double word is put in DX and least significant word of that double word is put in AX.
Note:
1. AF, PF, SF and ZF are undefined after MUL instruction.
2. If a byte is to be multiplied by the word, convert the byte to word and fill the upper byte of the word with all zeros.

IMUL (Multiplication of signed numbers)
IMUL Source
IMUL instruction multiplies the signed byte from some source with the signed byte in AL register (or) signed word from
some source with the signed word in AX. Source can be register (or) a memory location, which can be addressed by any one
of the 24-addressing modes.
- When a signed byte is to be multiplied by the signed byte in AL, result is a signed word and it will be stored in AX.
- When a signed word is multiplied by the signed word in AX, result is as long as 32-bitsb(signed double word) . The
most significant word of that signed double word will be stored in DX and least significant word of that double word
will be stored in AX.
Note:
1. AF, PF, SF and ZF are undefined after MUL instruction.
2. If a signed byte in AL is to be multiplied by signed word, convert the signed byte in AL to signed word by filling the
AH register with the sign of the byte in AL.

CBW (Convert Signed Byte to Signed Word)
CBW instruction converts the signed byte in AL to signed word OR it will be stored in AX. It copies the sign of the byte in
AL to all the bits of AH. AH is said to be the sign extension of AL. CBW affects no flags.

CWD (Convert Signed Word to Signed Double word)
CWD instruction converts the signed word in AX to signed Double word and it will be stored in DX & AX. It copies the sign
of the byte in AX to all the bits of DX. In other words, it extends the sign of AX to all the bits of DX.

22

DIV (Unsigned divide)
DIV Source
DIV instruction is used to divide an unsigned word by a byte (or) to divide an unsigned DW by a word.
- When a word is divided by a byte, the word must be in AX register. Divisor can be in a register or a memory location
that can be addressed by anyone of the 24 addressing modes. After division, AL contains an 8-bit result (quotient) & AH
will contain the 8-bit remainder.
- When a double word is divided by a word, the double word must be in DX and AX registers. Divisor can be in a register
or a memory location that can be addressed by anyone of the 24 addressing modes. After division, AX contains an 16-bit
result (quotient) & DX will contain the 16-bit remainder.
- If an attempt is made to divide by zero (or) if the quotient is too large to fit in AL, 8086 will automatically do Type-0
interrupt.
Note:
1. For DIV instruction, dividend(numerator) must be in AX (or) DX OR AX

IDIV (Divide by Signed byte/word)
IDIV Source
IDIV instruction is used to divide a signed word by a signed byte (or) to divide an signed DW by a signed word.
- When a signed word is divided by a signed byte, the signed word must be in AX register. Divisor can be in a register or a
memory location that can be addressed by anyone of the 24 addressing modes. After division, AL contains an 8-bit result
(quotient) & AH will contain the 8-bit remainder.
- When a signed double word is divided by a signed word, the signed double word must be in DX and AX registers.
Divisor can be in a register or a memory location that can be addressed by anyone of the 24 addressing modes. After
division, AX contain an16-bit result (quotient) & DX will contain the 16-bit remainder.
- If an attempt is made to divide by zero (or) if the quotient is too large to fit in AL, 8086 will automatically do Type-0
interrupt.
Note:
1. If we want to divide a signed byte by another signed byte, we must first put the dividend byte in AL and fill AH with
copies of the sign bit from AL.
2. If AL is +ve (sign bit=0), AH will be filled with all 0s.
If AL is -ve (sign bit=1), AH will be filled with all 1s.

Logical Instructions:
AND (AND corresponding bits of the two operands)
AND Destination, Source
AND instruction ANDs the corresponding bits of specified source or specified destination. After execution, result will be
stored in the specified destination.

OR (OR corresponding bits of the two operands)
OR Destination, Source
OR instruction ORs the corresponding bits of specified source or specified destination. After execution, result will be stored
in the specified destination.

NOT (Invert each bit of the operands)
NOT destination
NOT instruction inverts each bit (forms 1s complement) of the specified destination.

XOR (XOR corresponding bits of the two operands)
XOR Destination, Source
XOR instruction XORs the corresponding bits of specified source or specified destination. After execution, result will be
stored in the specified destination.

TEST ( AND corresponding bits of the operands to update flags)
TEST Destination, Source
TEST instruction ANDs the corresponding bits of specified source or specified destination. After execution, result will not be
stored in either of the operands, But based on the result flags will be effected.
23


Note:
1.TEST instruction is often used to set flags before a Conditional Jump instruction.

Shift Instructions:
SAL/SHL (Shift the bits of the operand left; Put zeros in LSB(s) )
SAL Destination, Count
CF MSB LSB 0

SAL/SHL instruction shifts each bit in the specified destination some number of bit positions to the left. As a bit shifted out
of LSB bit position, a 0 is put in LSB position.
In case of multiple bit shifts, the desired number of shifts is loaded in CL register or CL is put in count position of the
instruction.
Note;
1. SAL/SHL instruction is used to multiply an unsigned binary number by a power of 2.

SAR (Shift the bits of the operand right; New MSB= Old MSB)
SAR Destination, Count
MSB MSB LSB CF
SAR instruction shifts each bit in the specified destination some number of bit positions to the right. As a bit shifted out of
MSB bit position, a copy of old MSB is copied to the new MSB position.
instruction.
Note;
1. SAR instruction is used to divide a signed binary number by a power of 2.

SHR(Shift the bits of the operand right; Put Zero(s) in MSB(s))
SHR Destination, Count
0 MSB LSB CF
SHR instruction shifts each bit in the specified destination some number of bit positions to the right. As a bit shifted out of
MSB bit position, a 0 is put in LSB position.
instruction.
Note;
1. SHR instruction is used to divide an unsigned binary number by a power of 2.

Rotate Instructions:
ROL (Rotate all bits of the operand left; MSB to LSB)
ROL Destination, Count

CF MSB LSB

ROL instruction rotate all bits in the specified destination to the left some number of bit positions. The data bit rotated out of
MSB position is also copied into CF during ROL.
In case of multiple bit rotates, the desired number of rotates is loaded in CL register or CL is put in count position of the
instruction.

ROR (Rotate all bits of the operand right; LSB to MSB)
ROR Destination, Count
ROR instruction rotates all bits in the specified destination to the right some number of bit positions. The data bit rotated out
of LSB position is also copied into CF during ROR.
instruction.

CF MSB LSB
24

RCL (Rotate all bits of the operand left through Carry)
RCL Destination, Count

CF MSB LSB

The middle letter of the mnemonic C indicate that CF is also in the loop.
RCL instruction rotate all bits in the specified destination through Carry to the left some number of bit positions.
instruction.

RCR (Rotate all bits of the operand right through Carry)
RCR Destination, Count
RCR instruction rotates all bits in the specified destination through Carry to the right some number of bit positions.
instruction.

CF MSB LSB

Note:

1. Rotate instructions effect only CF & OF.
- If MSB is changed by a single bit rotate, OF will be 1
- CF will contain the last most recently rotated out of the MSB/LSB.

String Instructions:
MOVS/MOVSB/MOVSW
25

26

27

28

IV (c) BCD Arithmetic:

The microprocessor allows manipulation of BCD OR ASCII data
BCD used in Cash registers OR ASCII used by many programs

There are two instructions
DAA decimal adjust after addition
DAS decimal adjust after subtraction
Both instructions correct the result. The BCD number is stored as packed form 2 digits/byte OR if unpacked form means 1
digit/byte it functions with AL only.
DAA decimal adjust after addition
The result is in AL
The Logic of this instruction

If lower nibble>9 or AF=1 add 06
After adding 06 if upper nibble>9 or CF=1 add 60
DAA instruction follows ADD or ADC
Example1

ADD AL,CL
DAA
Let AL=53 OR CL=29
AL=53+29
AL=7C
AL=7C+06 (as C>9)
AL=82

Example 2

Let AL=73 CL=29
AL=9C
AL=9C+06 (as C>9)
AL=A2
AL=A2+60=02 OR CF=1
The instruction affects AF,CF,PF OR ZF
Example3

MOV DX,1234H
MOV BX,3099H
MOV AL,BL
ADD AL,DL
DAA
MOV AL,BH
ADC AL,DH
DAA
MOV CH,AL

BL=99H DL=34H
99+34=CD
AL=CD+6(D>9)
AL=D3
AL=D3+60(D>9)
AL=33 OR CF=1

BH=30 DH=12
AL=30+12+CF
AL=43
DAA does not do anything
The result is placed in CX=4333

DAS instruction follows subtraction
The result is in AL
Logic of this instruction

If lower nibble>9 or AF=1 subtract 06
29

After subtracting 06 if upper nibble>9 or CF=1 add 60
The instruction affects AF,CF,PF OR ZF

Example1
SUB AL,BH
DAS
Let AL=75 BH=46
AL=75-46=2F AF=1

AL=2F-6(F>9)
AL=29

Example 2

SUB AL,CH
DAS
AL=38 CH=61
AL=38-61=D7 CF=1(borrow)
AL=D7-60(D>9)
AL=77 CF=1(borrow)

Example 3

MOV DX,1234H
MOV BX,3099H
MOV AL,BL
SUB AL,DL
DAS
MOV CL,AL
MOV AL,BH
SBB AL,DH
DAS
MOV CH,AL
AL=99-34=65
DAS will not have affect
AL=30-12=1E
AL=1E-06(E>9)
AL=18
The result is 1865 placed in CX

ASCII Arithmetic

Functions with ASCII coded numbers
The numbers range from 30-39H for 0-9
AAA
AAD
AAM
AAS use AX as source OR destination

AAA
Example
add 31H OR 39H the result is 6AH it should have been 10 decimal which is 31H OR 30H
AAA is used to correct the answer
Converts resulting contents of AL to unpacked decimal digits
AAA instruction examines the lower 4 bits of AL for valid BCD numbers OR checks AF=0 sets the 4 high order bits to 0
AH cleared before addition
If lower digit of AL is between 0-9 OR AF=1 06 is added
The upper 4 digits are cleared OR incremented by 1
If the lower value of the lower nibble is greater than 9 then increment AL by 06 AH by 1
AF OR CF set
The higher 4 bits of AL are cleared to 0
AH modified
To get the exact sum add 3030H to AX
AAS
Correct result in AL after subtracting two unpacked ASCII operORs
30

The result is in unpacked decimal format
If the lower 4 bits of AL are>9 or if AF=1 then AL=AL-6 OR AH=AH-1 CF OR AF set
otherwise CF OR AF set to 0 no correction

result the upper nibble of AL is 00 OR the lower nibble may be any number from 0-9

AAM
Follows multiplication instruction after multiplying two unpacked BCD numbers
Converts the product available in AL into unpacked BCD
Lower byte of result is in AL OR upper in AH

Example
let the product is 5D in AL
D>9 so add 6 =13H
LSD of 13H is lower unpacked byte
Increment AH, AH=5+1=6 upper unpacked byte
After execution AH=06 OR AL=03
MOV AL,5
MOV CL,5
MUL CL
AAM
Accomplishes conversion by dividing AX by 10
Benefit of AAM converts from binary to unpacked BCD
use of AAM for conversion
XOR DX,DX
MOV CX,100
DIV CX
AAM
ADD AX,3030H
XCHG AX,DX
AAM
ADD AX,3030H

AAD
Appears before division
requires AX to contain two digit unpacked BCD number(not ASCII) before executing
After adjusting AX with AAD it is divided by an unpacked BCD number to generate a single digit result in AL with
remainder in AH
Example
.MODEL
.CODE
.STARTUP
MOV AL,48H
MOV AH,0
AAM
ADD AX,3030H
MOV DL,AH
MOV AH,2
PUSH AX
INT 21H
POP AX
MOV DL,AL
INT 21H
.EXIT
END

MACHINE CODE GENERATION:

The 8086 instruction sizes vary from one to six bytes. The OP code occupies six bytes OR it defines the operation to be
carried out by the instruction.
Register Direct bit (D) occupies one bit. It defines whether the register operOR in byte 2 is the source or destination operOR.
D=1 Specifies that the register operOR is the destination operOR.
D=0 indicates that the register is a source operOR.
31

Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data

W=0 indicates 8 bit operation
W=1 indicates 16 bit operation

The second byte of the instruction usually identifies whether one of the operORs is in memory or whether both are registers.
This byte contains 3 fields. These are the mode (MOD) field, the register (REG) field OR the Register/Memory (R/M) field.

MOD (2 bits) Interpretation
00 Memory mode with no displacement follows except for 16 bit displacement when
R/M=110
01 Memory mode with 8 bit displacement
10 Memory mode with 16 bit displacement
11 Register mode (no displacement)

Register field occupies 3 bits. It defines the register for the first operOR which is specified as source or destination by the D
bit.

REG W=0 W=1
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI
The R/M field occupies 3 bits. The R/M field along with the MOD field defines the second operOR as shown below.

MOD 11
R/M W=0 W=1
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

Effective Address Calculation
R/M MOD=00 MOD 01 MOD 10
000 (BX) + (SI) (BX)+(SI)+D8 (BX)+(SI)+D16
001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16
010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16
011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D10
100 (SI) (SI) + D8 (SI) + D16
101 (DI) (DI) + D8 (DI) + D16
110 Direct address (BP) + D8 (BP) + D16
111 (BX) (BX) + D8 (BX) + D16

In the above, encoding of the R/M field depends on how the mode field is set. If MOD=11 (register to register mode), this
R/M identifies the second register operOR.
32

MOD selects memory mode, then R/M indicates how the effective address of the memory operOR is to be calculated. Bytes
3 through 6 of an instruction are optional fields that normally contain the displacement value of a memory operOR OR / or
the actual value of an immediate constant operOR.

Example 1 : MOV CH, BL
This instruction transfers 8 bit content of BL

Into CH
The 6 bit Opcode for this instruction is 100010
2
D bit indicates whether the register specified by the REG field of byte 2 is a
source or destination operOR.
D=0 indicates BL is a source operOR.
W=0 byte operation
In byte 2, since the second operOR is a register MOD field is 11
2
.
The R/M field = 101 (CH)
Register (REG) field = 011 (BL)
Hence the machine code for MOV CH, BL is
10001000 11 011 101
Byte 1 Byte2
= 88DD16

Example 2 : SUB Bx, (DI)
This instruction subtracts the 16 bit content of memory location addressed by DI OR DS from Bx. The 6 bit Opcode for SUB
is 001010
2
.
D=1 so that REG field of byte 2 is the destination operOR. W=1 indicates 16 bit operation.
MOD = 00
REG = 011
R/M = 101
The machine code is 0010 1011 0001 1101
2 B 1 D
2B1D
16

Summary of all Addressing Modes
Example 3 : Code for MOV 1234 (BP), DX
Here we have specify DX using REG field, the D bit must be 0, indicating the DX is the source register. The REG field must
be 010 to indicate DX register. The W bit must be 1 to indicate it is a word operation. 1234 [BP] is specified using MOD
value of 10 OR R/M value of 110 OR a displacement of 1234H. The 4 byte code for this instruction would be 89 96 34 12H.

Opcode D W MOD REG R/M LB displacement HB displacement
100010 0 1 10 010 110 34H 12H

Example 4 : Code for MOV DS : 2345 [BP], DX
Here we have to specify DX using REG field. The D bit must be o, indicating that Dx is the source register. The REG field
must be 010 to indicate DX register. The w bit must be 1 to indicate it is a word operation. 2345 [BP] is specified with
MOD=10 OR R/M = 110 OR displacement = 2345 H.
MOD / R/M Memory Mode (EA Calculation) Register Mode
00 01 10 W=0 W=1
000 (BX)+(SI) (BX)+(SI)+d8 (BX)+(SI)+d16 AL AX
001 (BX) + (DI) (BX)+(DI)+d8 (BX)+(DI)+d16 CL CX
010 (BP)+(SI) (BP)+(SI)+d8 (BP)+(SI)+d16 DL DX
011 (BP)+(DI) (BP)+(DI)+d8 (BP)+(DI)+d16 BL BX
100 (SI) (SI) + d8 (SI) + d16 AH SP
101 (DI) (DI) + d8 (DI) + d16 CH BP
110 d16 (BP) + d8 (BP) + d16 DH SI
111 (BX) (BX) + d8 (BX) + d16 BH DI
33

Whenever BP is used to generate the Effective Address (EA), the default segment would be SS. In this example, we want the
segment register to be DS, we have to provide the segment override prefix byte (SOP byte) to start with. The SOP byte is
001 SR 110, where SR value is provided as per table shown below.

SR Segment register
00 ES
01 CS
10 SS
11 DS
To specify DS register, the SOP byte would be 001 11 110 = 3E H. Thus the 5 byte code for this instruction would be 3E 89
96 45 23 H.

SOP Opcode D W MOD REG R/M LB disp. HD disp.
3EH 1000 10 0 1 10 010 110 45 23
Suppose we want to code MOV SS : 2345 (BP), DX. This generates only a 4 byte code, without SOP byte, as SS is already
the default segment register in this case.

Example 5 :
Give the instruction template OR generate code for the instruction ADD OFABE [BX], [DI], DX (code for ADD instruction
is 000000)

ADD OFABE [BX] [DI], DX
Here we have to specify DX using REG field. The bit D is 0, indicating that DX is the source register. The REG field must
be 010 to indicate DX register. The w must be 1 to indicate it is a word operation. FABE (BX + DI) is specified using MOD
value of 10 OR R/M value of 001 (from the summary table). The 4 byte code for this instruction would be
Opcode D W MOD REG R/M 16 bit disp.
=01 91 BE FAH
000000 0 1 10 010 001 BEH FAH
Example 6 :
Give the instruction template OR generate the code for the instruction MOV AX, [BX]
(Code for MOV instruction is 100010)
AX destination register with D=1 OR code for AX is 000 [BX] is specified using 00 Mode OR R/M value 111
It is a word operation

Opcode D W Mod REG R/M
=8B 07H
100010 1 1 00 000 111

Segment Over Ride Prefix

SOP is used when a particular offset register is not used with its default base segment register, but with a different base
register. This is a byte put before the OPCODE byte.
0 0 1 S R 1 1 0

SR Segment Register
00 ES
01 CS
10 SS
11 DS
Here SR is the new base register. To use DS as the new register 3EH should be prefix.
OperOR Register Default With over ride prefix
34

IP (Code address) CS Never
SP(Stack address) SS Never
BP(Stack Address) SS BP+DS or ES or CS
SI or DI(not including Strings) DS ES, SS or CS
SI (Implicit source Address for
strings)
DS
DI (Implicit Destination Address for
strings)
ES Never
Examples: MOV AX, DS: [BP], LODS ES: DATA1
S
4
S
3
Indications
0 0 Alternate data
0 1 Stack
1 0 Code or none
1 1 Data

Bus High Enable / Status
BHE
A
0
Indications
0 0 Whole word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 none

Assembler Directives:
Assembler converts Assembly Language Program into Machine UnderstORable
Language. For doing this conversion, the directions given to the assembler are known as
Assembler Directives.
Assembler directives are classified into
I) Data definition OR Storage allocation directives:
DB, DW, DD, DQ, DT, STRUCT, RECORD
II) Program Organization directives:
SEGMENT, ENDS, ASSUME, GROUP
III) Alignment directives:
EVEN, ORG
IV) Program End directive:
END
V) Value returning attribute directives:
LENGTH, SIZE, OFFSET, SEG,TYPE
VI) Procedure definition directives:
PROC, ENDP
VII) Macro definition directives:
EQU, MACRO, ENDM
35

VIII) Data Control directives:
PUBLIC, EXTRN, PTR
IX) Branch Displacement directives:
SHORT, LABEL
X) Header file Inclusion directive:
INCLUDE
ASSEMBLER DIRECTIVES:

Also called as pseudo operations that control the assembly process.
They indicate how an operOR or section of a program to be processed by the assembler.
They generate OR store information in the memory.

Assembler Memory models

Each model defines the way that a program is stored in the memory system.
Tiny: data fits into one segment written in .COM format
Small: has two segments data OR memory.
There are several other models too.

Directive for string data in a memory segment

DB define byte
DW define word
DD define double word
DQ define 10 bytes
Example
Data1 DB 10H,11H,12H
Data2 DW 1234H

SEGMENT: statement to indicate the start of the program OR its symbolic name.
Example
Name SEGMENT
Variable_name DB .
Variable_name DW .
Name ENDS

Data SEGMENT
Data1 DB .
Data2 DW .
Data ENDS

Code SEGMENT
START: MOV AX,BX

Code ENDS

Similarly the stack segment is also declared.

For small models
.DATA

ENDS

The ENDS directive indicates the end of the segment.
36

Memory is reserved for use in the future by using a ? as an operOR for DB DW or DD directive. The assembler sets
aside a location OR does not initialize it to any specific value (usually stores a zero). The DUP (duplicate) directive
creates an array OR stores a zero.
Example
Data1 DB 5 DUP(?)
This reserves 5 bytes of memory for a array data1 OR initializes each location with 05H

ALIGN: memory array is stored in word boundaries.
Example
ALIGN 2 means storing from an even address

Address 0 XX
Address 1 YY
Address 2 XX

The data XX is aligned to the even address.
ASSUME, EQU, ORG
ASSUME tells the assembler what names have been chosen for Code, Data Extra OR Stack segments. Informs the
assembler that the register CS is to be initialized with the address allotted by the loader to the label CODE OR DS is
similarly initialized with the address of label DATA.
Example
ASSUME CS: Name of code segment
ASSUME DS: Name of the data segment

ASSUME CS: Code1, DS: Data1

EQU: Equates a numeric, ASCII(American StORard Code for Information Interchange) or label to another label.
Example
Data SEGMENT
Num1 EQU 50H
Num2 EQU 66H
Data ENDS

Numeric value 50H OR 66H are assigned to Num1 OR Num2

ORG: Changes the starting offset address of the data in the data segment
Example
ORG 100H
100 data1 DB 10H
it can be used for code too.
PROC & ENDP: indicate the start OR end of the procedure. They require a label to indicate the name of the procedure.
NEAR: the procedure resides in the same code segment. (Local)
FAR: resides at any location in the memory.
Example
Add PROC NEAR
ADD AX,BX
MOV CX,AX
RET
Add ENDP

PROC directive stores the contents of the register in the stack.
EXTRN, PUBLIC informs the assembler that the names of procedures OR labels declared after this directive have been
already defined in some other assembly language modules.
Example
If you want to call a Factorial procedure of Module1 from Module2 it must be declared as
PUBLIC in Module1.

Example
A sample for full segment definition

Data SEGMENT
Num1 DB 10H
Num2 DB 20H
Num3 EQU 30H
37

Data ENDS

ASSUME CS:Code,DS:Data
Code SEGMENT
START: MOV AX,Data
MOV DS,AX
MOV AX,Num1
MOV CX,Num2
ADD AX,CX
Code ENDS

Example
A sample for small model

. MODEL SMALL

.Data
Num1 DB 10H
Num2 DB 20H
Num3 EQU 30H

.Code
HERE: MOV AX,@Data
MOV DS,AX
MOV AX,Num1
MOV CX,Num2
ADD AX,CX

Assembly Language Program Development Tools:

For all assembly language programs , you will probably want to use some type of microcomputer development
system(MDS) OR program development tools to make your work easier.
Editor
An editor is a program which allows you to create a file containing the assembly language statements for your
program. Examples of suitable editors are PC Write, Word star, OR the editor that comes with some assemblers.
As we type in your program, the editor stores the ASCII codes for the letters OR numbers in successive RAM
locations. If we make a typing error, the editor will let you back up OR correct it. If you leave out a program statement, the
editor will let you move everything down OR insert the line. This is much easier than working with pencil OR paper, even if
we type as slowly as I do.
Assembler
An assembler program is used to translate the assembly language mnemonics for instructions to the corresponding
binary codes
The assembler generates two files on the floppy or hard disk. The first file, called the object file is given the
extension. OBJ. The object file contains the binary codes for the instructions. The second file generated by the assembler is
called the assembler list file OR is given the extension.
A linker or locator will be used to assign the physical starting addresses for the segments
Linker
A Linker is a program used to join several object files into one large object file. When writing large programs, it is
usually much more efficient to divide the large program into smaller modules. Each module can be individually written,
tested, OR debugged. Then when all modules work their object modules can be linked together to form a large, functioning
program.
The linker produces a link file which contains the binary codes for all the combined modules. The linker also
produces a link map file which contains the address information about the linked files. The linker, however does not assign
absolutes addresses to the program. The linkers which come with the TASM or MASM assemblers produce link with the
.EXE extension.
Locator
A locator is a program used to assign the specific addresses of the segments of object code are to be loaded into the
memory.
Debugger
38

A debugger is a program which allows you to load your object code program into system debug it. The debugger
allows you to look at the contents of registers OR memory locations after your program runs. It allows you to change the
contents of some debuggers allow you to stop execution after each instruction so that you can check or alter memory OR
register contents. A debugger also allows you to set a break point at any point in your program. If you insert a breakpoint, the
debugger will run the program up to the instruction where you put the breakpoint OR then stop execution. You can then
examine register OR memory contents to see whether the results are correct, you can move the break point to a later point in
the program. If the results are not correct ,you can check the program up to that point to find out why they are not correct.

Emulator
An emulator is a mixture of hardware OR software. It is usually used to test OR debug the hardware of an external
system, such as the prototype of a microprocessor-based instrument. Part of the hardware of an emulator is a multi wire cable
which connects the host system in place of its microprocessor. Through this connection the software of the emulator allows
you to download your object code program into RAM in the system being tested OR run it. Like a debugger , an emulator
allows you to load OR run programs, examine OR change the contents of memory locations, OR insert breakpoints in the
program. The emulator stores this trace data, as it is called, in a large RAM.
Another powerful feature of an emulator is the ability to use either system memory or the memory on the prototype
for the program you are debugging.

39

Pin Diagram of 8086:
8086
AD15
Vcc 40
39
38 A16/S3
A17/S4 37
36 A18/S5
A19/S6 35
BHE/S7 34
MN/MX
RD
RG GT0 / (HOLD)
RQ GT1 / (HLDA)
LOCK WR ( )
S2 I0 (M/ )
S1 R (DT/ )
S0 DEN ( )
QS0 (ALE)
QS1 ( ) INTA
TEST
READY
RESET
33
32
31
30
29
28
27
26
25
24
23
22
21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1 GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND

Classification OR Description of Pins of 8086:

8086 is a 40 pin DIP using MOS technology. It has 2 GNDs as circuit complexity demORs a large amount of current
flowing through the circuits, OR multiple grounds help in dissipating the accumulated heat etc. 8086 works on two modes of
operation namely, Maximum Mode OR Minimum Mode.

(i) Power Connections

GND Pin no. 1, 20
Ground
V
CC
Pin no. 40
V
CC
: +5V power supply pin

CLK Pin no. 19 Type I
Clock: provides the basic timing for the processor OR bus controller. It is asymmetric with a 33% duty cycle to provide
optimized internal timing.
40

CLK (I): Clock
Clock provides the basic timing for the processor OR bus controller. It is asymmetric with 33% duty cycle to
provide optimized internal timing. Minimum frequency of 2 MHz is required, since the design of 8086 processors
incorporates dynamic cells. The maximum clock frequencies of the 8086-4, 8086 OR 8086-2 are

Vcc
R
F/C
X1
X2
CLK
RESET
SYSTEM RESET
8086 p
AEN1
AEN2
8
2
8
4
READY
PCLK
OSC
Csync
RDY1
RDY2

Fig..4
4MHz, 5MHz OR 8MHz respectively. Since the 8086 does not have on-chip clock generation circuitry, OR 8284 clock
generator chip must be connected to the 8086 clock pin. The crystal connected to 8284 must have a frequency 3 times the
8086 internal frequency. The 8284 clock generation chip is used to generate READY, RESET OR
CLK. It is as shown in fig..4

(v) Interrupts

NMI Pin no. 17 Type I
Non Maskable Interrupt: an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an
interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a
LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.

NMI (I): Non-Muskable Interrupt
An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt vector look up table
located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH on this
pin initiates the
interrupt at the end of the current instruction. This input is internally synchronized.

INTR Pin No. 18 Type I
Interrupt Request: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if
the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup
table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally
synchronized. This signal is active HIGH.

41

INTR (I): Interrupt Request
It is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector look up
table located in system memory. It can be internally masked by software resetting the interrupt enable bit
INTR is internally synchronized. This signal is active HIGH.
(ii) Address/ Data Lines

Pin Description
AD
15
-AD
0
Pin no. 2-16, 39 Type I/O

Address Data bus: These lines constitute the time multiplexed memory/ IO address (T1) OR data (T
2
, T
3
, T
W
, T
4
) bus. A
0
is
analogous to BHE for the lower byte of of the data bus, pins D
7
-D
0
. It iss low when a byte is to be transferred on the lower
portion of the bus in memory or I/O operations. Eight bit oriented devices tied to the lower half would normally use A
0
to
condition chip select functions. These lines are active HIGH OR float to 3-state OFF during interrupt acknowledge OR local
bus hold acknowledge.
(iii) Address Lines

42

AD0 - AD15 (I/O): Address Data Bus
These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1) OR data during T2, T3
OR T4 clock cycles. A0 is analogous to BHE for the lower byte of the data bus, pins D0-D7. A0 bit is Low during T1 state
when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. 8-bit oriented devices tied to the
lower half would normally use A0 to condition chip select functions. These lines are active high OR float to tri-state during
interrupt acknowledge OR local bus "Hold acknowledge". Fig. 2 shows the timing of AD
0
AD
15
lines to access data OR
address.
AD0 - AD15 Address Data
T4 T1 T2 T3 T4

Fig. .2

A
19
/S
6
, A
18
/S
5
, A
17
/S
4
, A
16
/S
3
Pin no. 35-38 Type O
Address / Status: During T
1
these are the four most significant address lines for memory operations. During I/O operations
these lines are low. During memory OR I/O operations, status information is available on these lines during T
2
, T
3
, T
W
OR
T
4
. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. A
17
/S
4
OR A
16
/S
3
are
encoded as shown.
A
17
/S
4
A
16
/S
3
Characteristics
0 (LOW) 0 Alternate Data
0 1 Stack
1(HIGH) 0 Code or None
1 1 Data
S
6
is 0 (LOW)
This information indicates which relocation register is presently being used for data accessing.
These lines float to 3-state OFF during local bus hold acknowledge.

A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status
During T1 state these lines are the four most significant address lines for memory operations. During I/O operations
these lines are low. During memory OR I/O operations, status information is available on these lines during T2, T3, OR
T4 states.
S5: The status of the interrupt enable flag bit is updated at the beginning of each cycle. The status of the flag is
indicated through this bus.
S6: When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock period, the 8086
tri-states the S6 pin OR thus allows another bus master to take control of the status bus.

S3 & S4: Lines are decoded as follows:

Table 1
After the first clock cycle of an instruction execution, the A17/S4 OR A16/S3 pins specify which segment register
generates the segment portion of the 8086 address. Thus by decoding these lines OR using the decoder outputs as chip selects
A17/S4 A16/S3 Function
0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access
43

for memory chips, up to 4 Megabytes (one Mega per segment) of memory can be accesses. This feature also provides a
degree of protection by preventing write operations to one segment from erroneously overlapping into another segment OR
destroying information in that segment.

S4 S3 Indications
0 0 Alternate data
0 1 Stack
1 0 Code or none
1 1 Data

----- Value of Interrupt Enable flag

----- Always low (logical) indicating 8086 is on the bus. If it is tristated another
bus master has taken control of the system bus.
----- Used by 8087 numeric coprocessor to determine whether the CPU is a 8086
or 8088

BHE /S7 (O): Bus High Enable/Status
During T1 state the BHE should be used to enable data onto the most significant half of the data bus, pins D15 -
D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to control chip select functions.
BHE is Low during T1 state of read, write OR interrupt acknowledge cycles when a byte is to be transferred on the high
portion of the bus.
The S7 status information is available during T2, T3 OR T4 states. The signal is active Low OR floats to 3-state
during "hold" state. This pin is Low during T1 state for the first interrupt acknowledge cycle.

7
/S BHE - Pin No. 34 Type O
Bus High Enable / Status: During T
1
the Bus High Enable signal ( BHE )should be used to enable data onto the most
significant half of the data bus, pins D
15
-D
8
. Eight bit oriented devices tied to the upper half of the bus would normally use
BHE to condition chip select functions. BHE is LOW during T
1
for read, write, OR interrupt acknowledge cycles when a
byte is to be transferred on the high portion of the bus. The S
,7
status information is available during T
2
, T
3
OR T
4
. The signal
is active LOW OR floats to 3-state OFF in hold. It is LOW during T
1
for the first interrupt acknowledge cycle.
BHE
A
0
Characteristics
0 0 Whole word
0 1 Upper byte from / to odd address
1 0 Lower byte from / to even address
1 1 None

MX MN/ - Pin no. 33 Type - I
Minimum / Maximum: indicates what mode the processor is to operate in.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next clock.
5
S
6
S
7
S
44

2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with
condition number 1 already satisfied.
MN/ MX (I): Maximum / Minimum
This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself generates all bus
control signals. In maximum mode the three status
signals are to be decoded to generate all the bus control signals.

RD - Pin no. 32, Type O
Read: Read strobe indicates that the processor is performing a memory of I/O read cycle, depending on the state of the S
2
pin.
This signal is used to read devices which reside on the 8086 local bus. RD is active LOW during T
2
, T
3
OR T
W
of any read
cycle, OR is guaranteed to remain HIGH in T
2
until the 8086 local bus has floated.
This signal floats to 3-state OFF in hold acknowledge.
RD (O): READ
The Read strobe indicates that the processor is performing a memory or I/O read cycle. This signal is active low during T2
OR T3 states OR the Tw states of any read cycle.
This signal floats to tri-state in "hold acknowledge cycle".
RESET Pin no. 21 Type I
Reset: causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four
clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is
internally synchronized.
Reset (I)
Reset causes the processor to immediately terminate its present activity. To be recognised, the signal must be active
high for at least four clock cycles, except after power-on which requires a 50 Micro Sec. pulse. It causes the 8086 to
initialize registers DS, SS, ES, IP OR flags to all zeros. It also initializes CS to FFFF H. Upon removal of the RESET signal
from the RESET pin, the 8086 will fetch its next instruction from the 20 bit physical address FFFF0H. The reset signal to
8086 can be generated by the 8284. (Clock generation chip). To guarantee reset from power-up, the reset input must remain
below 1.5 volts for 50 Micro sec. after Vcc has reached the minimum supply voltage of 4.5V. The RES input of the 8284 can
be driven by a simple RC circuit as shown in fig.3.

+5V
R
Normal
Reset Key
RES
F/C
X1
X2
CLK
CLK
RESET RESET
SYSTEM RESET
8086 p
C
8284

Fig. .3
The value of R OR C can be selected as follows:
Vc (t) = V (1 - e
-t /RC
) t = 50 Micro sec.
V = 4.5 volts, Vc = 1.05V OR RC = 188 Micro sec.
C = 0.1 Micro F; R = 1.88 K ohms.
CPU component Contents
Flags Cleared
Instruction Pointer 0000H
CS register FFFFH
DS register 0000H
SS register 0000H
ES register 0000H
Queue Empty
Table .2 System Registers after Reset
45

8086/88 RESET line provide an orderly way to start an executing system. When the processor detects the positive-going
edge of a pulse on RESET, it terminates all activities until the signal goes low, at which time it initializes the system as
shown in table .2.
READY Pin no. 22, Type I
READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The
READY signal from memory / IO is synchronized by the 8284A Clock Generator to form READY. This signal is active
HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup OR hold times are not
met.
synchronized internally during each clock cycle on the leading edge of CLK.
Ready (I)
Ready is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The
READY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This signal is active
HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup OR hold times are not
met.

TEST - Pin No 23 Type I
TEST : input is examined by the Wait instruction. If the TEST input is LOW execution continues, otherwise the processor
waits in an idle state. This input is synchronized internally during each clock cycle on the leading edge of CLK.
TEST(I)
TESTpin is examined by the "WAIT" instruction. If the TESTpin is Low, execution continues. Otherwise the
processor waits in an "idle" state. This input is

(VI) Common Signals in Minimum Mode OR Maximum Mode:

46

MODES OF OPERION OF 8086:
8086 Basic System Concepts
8086 can be used either in a minimum mode system or a maximum mode system. The fig. 10 OR fig. 11 shows
minimum OR maximum modes with groups of ICs to generate address bus, data bus OR control bus signals. Using these
buses, the CPU can be connected to ROM, RAM, PORTS OR other devices to form a complete system.

BASIC 8086 Minimum mode System
8282 I/O ports are used to latch the addresses from the 8086 Microprocessor Data/Address bus. By using three 8282,
A0-A15, BHE , A16-A19 lines are latched during T1 state. OE(Output Enable) input of the 8288 I/O ports are grounded;
the bus will therefore, never be floated. ALE signal from 8286 is used to strobe the addresses into the 8282 I/O latches.
Since the Data Bus is bi-directional, 8286 bi-directional bus transceivers are used, in order to create a separate Data
Bus from the 8086 Address/data Bus. The DT/ R OR DEN outputs from 8086 are used for 8286 "T" signal OR OEinputs
respectively.
Maximum Mode Configuration
When MN/ MX pin is strapped to GND, the 8086 treats pin 24 through 31 to be in maximum mode. An 8288 bus
controller interprets status information coded into S0, S1 OR S2 to generate bus timing OR control signals compatible. DEN,
DT/ R OR ALE control outputs, are now generated by the 8288 bus controller. The DEN from 8288 is inverted OR given to
8286 transceiver to enable the output. The output enable of 8282 latch is grounded. As in minimum mode the address-data
lines are latched through 8282 latch. The ALE signal from the 8288 bus controller latches the address during the T
1
state of
the microprocessor. The DEN signal is used to enable the transceiver either to transmit or receive data from I/O devices OR
memory. The DT/ R signal is used to transmit or receive the data as the need may be.

Pins Description:
The following pin function descriptions are for the microprocessor 8086 in either minimum or maximum mode. The 8086
pins signals are TTL compatible.

Minimum Mode Pins
The following 8 pins function descriptions are for the 8086 in minimum mode; MN/ MX = 1. The corresponding 8
pins function descriptions for maximum mode is explained later.

Pin Description:

47

HOLD, HLDA Pin no. 31, 30 Type I/O
HOLD: indicates that another master is requesting a local bus hold. To be acknowledged, HOLD must be active HIGH.
The processor receiving the hold request will issue HLDA (HIGH) as an acknowledgement in the middle of a T
1
clock
cycle. Simultaneous with the issuance of HLDA the processor will float the local bus OR control lines. After HOLD is
detected as being LOW, the processor will LOWer the HLDA, OR when the processor needs to run another cycle, it will
again drive the local bus OR control lines.
The same rules as GT / RQ apply regarding when the local bus will be released.
HOLD is not an asynchronous input. External synchronization should be provided if the system can not otherwise guarantee
the setup time.

HOLD & HLDA (I/O): Hold OR Hold Acknowledge

Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged, HOLD must be active
HIGH. The processor receiving the "HOLD " request will issue HLDA (HIGH) as an acknowledgement in the middle of the
T1-clock cycle. Simultaneous with the issue of HLDA, the processor will float the local bus OR control lines. After "HOLD"
is detected as being Low, the processor will lower the HLDA OR when the processor needs to run another cycle, it will again
drive the local bus OR control lines.

WR - Pin no. 29 Type O
Write: indicates that the processor is performing a write memory or write I/O cycle, depending on the state of the O M/I
signal. WR is active for T
2
, T
3
OR T
W
of any write cycle. It is active LOW, OR floats to 3-state OFF in local bus hold
acknowledge.
WR(O): Write
Indicates that the processor is performing a write memory or write IO cycle, depending on the state of the M
/ IOsignal. WR is active for T2, T3 OR Tw of any write cycle. It is active LOW, OR floats to 3-state OFF during
local bus "hold
acknowledge ".
O M/I - Pin no. 28 type O
Status line: logically equivalent to S
2
in the maximum mode. It is used to distinguish a memory access from an I/O access.
O M/I becomes valid in the T
4
preceding a bus cycle OR remains valid until the final T
4
of the cycle (M=HIGH), IO=LOW).
O M/I floats to 3-state OFF in local bus hold acknowledge.
M/ IO (O): Status line
This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it accesses I/O OR when
high it access memory. M / IO becomes valid in the T4 state preceding a bus cycle OR remains valid until the final T4 of
the cycle. M/ IO
floats to 3 - state OFF during local bus "hold acknowledge".
R DT/ -Pin no. 27 Type O
Data Transmit / Receive: needed in minimum system that desires to use an 8286/8287 data bus transceiver. It is used to
control the direction of data flow through the transceiver. Logically R DT/ is equivalent to
1
S in the maximum mode, OR its
timing is the same as for O M/I . (T=HIGH, R=LOW). This signal floats to 3-state OFF in local bus hold acknowledge.
48

DT/ R (O): DATA Transmit/Receive
In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the direction of data
flow through the transceiver. This signal floats to tri-state off during local bus "hold acknowledge".

DEN - Pin no. 26 Type O
Data Enable: provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. DEN is
active LOW during each memory OR I/O access OR for INTA cycles. For a read or INTA cycle it is active from the middle
of T
2
until the middle of T
4
, while for a write cycle it is active from the beginning of T
2
until the middle of T
4
. DEN floats to
3-state OFF in local bus hold acknowledge.
DEN (O): Data Enable
It is provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. DEN is
active LOW during each memory OR IO access. It will be low beginning with T2 until the middle of T4, while for a write
cycle, it is active from the beginning of T2 until the middle of T4. It floats to tri-state off during local bus "hold
acknowledge".

ALE Pin no. 25 Type O
Address Latch Enable: provided by the processor to latch the address into the 8282/8283 address latch. It is a HIGH pulse
active during T
1
of any bus cycle. Note that ALE is never floated.
ALE (O): Address Latch Enable
ALE is provided by the processor to latch the address into the 8282/8283 address
latch. It is an active high pulse during T1 of any bus cycle. ALE signal is never floated.

INTA - Pin no. 24 Type O
INTA is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T
2
, T
3
OR T
W
of each interrupt
acknowledge cycle.

INTA (O): Interrupt Acknowledge
It is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3, OR T4 of each
interrupt acknowledge cycle.

Maximum Mode of operation of 8086:
Maximum Mode

The following pins function descriptions are for the 8086/8088 systems in maximum mode (i.e.. MN/ MX= 0).
Only the pins which are unique to maximum mode are described below.
.

49

Pin Description:
0
GT / RQ ,
1
GT / RQ - Pin no. 30, 31 Type I/O
Request /Grant: pins are used by other local bus masters to force the processor to release the local bus at the end of the
processors current bus cycle. Each pin is bidirectional with
0
GT / RQ having higher priority than
1
GT / RQ . GT / RQ has an
internal pull up resistor so may be left unconnected. The request/grant sequence is as follows:
1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (hold) to the 8086 (pulse 1)
2. During a T
4
or T
1
clock cycle, a pulse 1 CLK wide from the 8086 to the requesting master (pulse 2), indicates that
the 8086 has allowed the local bus to float OR that it will enter the hold acknowledge state at the next CLK. The
CPUs bus interface unit is disconnected logically from the local bus during hold acknowledge.
3. A pulse 1 CLK wide from the requesting master indicates to the 8086 (pulse 3) that the hold request is about to
end OR that the 8086 can reclaim the local bus at the next CLK.
Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one dead CLK cycle after each bus
exchange. Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it will release the local bus during T
4
of the cycle when
all the following conditions are met:
1. Request occurs on or before T
2
.
2. Current cycle is not the low byte of a word (on an odd address)
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
RQ/
0
GT OR RQ/
1
GT (I/O): Request/Grant
These pins are used by other processors in a multi processor organization. Local bus masters of other processors
force the processor to release the local bus at the end of the processors current bus cycle. Each pin is bi-directional OR has
an internal pull up
resistors. Hence they may be left un-connected.

LOCK- Pin no. 29 Type O
50

LOCK: output indicates that other system bus masters are not to gain control of the system bus while LOCKis active
LOW. The LOCKsignal is activated by the LOCK prefix instruction OR remains active until the completion of the next
instruction. This signal is active LOW, OR floats to 3-state OFF in hold acknowledge.
LOCK (O)
It indicates to another system bus master, not to gain control of the system bus while LOCKis active Low. The
LOCKsignal is activated by the "LOCK" prefix instruction OR remains active until the completion of the instruction. This
signal is active
Low OR floats to tri-state OFF during 'hold acknowledge".
Example:
LOCK XCHG reg., Memory ; Register is any register OR memory
0
GT
; is the address of the semaphore.

QS
1
, QS
0
Pin no. 24, 25 Type O
Queue Status: the queue status is valid during the CLK cycle after which the queue operation is performed.
QS
1
OR QS
0
provide status to allow external tracking of the internal 8086 instruction queue.

QS
1
QS
0
Characteristics
0(LOW) 0 No operation
0 1 First Byte of Op Code from Queue
1 (HIGH) 0 Empty the Queue
1 1 Subsequent byte from Queue

QS0, QS1 (O): Queue Status
Queue Status is valid during the clock cycle after which the queue operation is performed. QS0, QS1 provide
status to allow external tracking of the internal 8086
instruction queue. The condition of queue status is shown in table 4.
Queue status allows external devices like In-circuit Emulators or special instruction set extension co-processors to track the
CPU instruction execution. Since instructions are executed from the 8086 internal queue, the queue status is presented each
CPU clock cycle OR is not related to the bus cycle activity. This mechanism allows
(1) A processor to detect execution of a ESCAPE instruction which directs the co-processor to perform a specific
task OR
(2) An in-circuit Emulator to trap execution of a specific memory location.
QS1 QS1 Characteristics
0 0 No operation
0 1 First byte of opcode from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
Table 4

51

S2, S1, S0 (O): Status Pins
These pins are active during T4, T1 OR T2 states OR is returned to passive state (1,1,1 during T3 or Tw (when ready is
inactive). These are used by the 8288 bus controller to generate all memory OR I/O operation) access control signals. Any
change by S2, S1, S0 during T4 is used to indicate the beginning of a bus cycle. These status lines are encoded as shown in
table 3.

S2 S1 S0 Characteristics
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive State
Table 3

(iv) Status Pins S
0
- S
7

2
S ,
1
S ,
0
S - Pin no. 26, 27, 28 Type O

Status: active during T
4
, T
1
OR T
2
OR is returned to the passive state (1,1,1) during T
3
or during T
W
when READY is HIGH.
This status is used by the 8288 Bus Controller to generate all memory OR I/O access control signals. Any change by
2
S ,
1
S
or
0
S during T
4
is used to indicate the beginning of a bus cycle OR the return to the passive state in T
3
or T
W
is used to
indicate the end of a bus cycle.
These signals float to 3-state OFF in hold acknowledge. These status lines are encoded as shown.
2
S
1
S
0
S
Characteristics
0(LOW) 0 0 Interrupt acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1(HIGH) 0 0 Code Access
52

1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive

Status Details

Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive

2
S
1
S
0
S
53

Minimum Mode of operation of 8086:
Block Diagram of 8086 in Minimum Mode

8
0
8
6

C
P
U
F/C
AEN1
AEN2
Clock
generator
+5V
RES
Wait-State
Generator
CLK
READY
RESET
M/IO
INTA
RD
WR
PCLK
MN/MX +5V
STB
OE
8282
Latch
ALE
AD0-AD15
A16-A19
BHE BHE
D0 - D15
8286
DT/R
DEN
T
OE
16
A0 - A19
Address Bus
Control
Bus

A minimum mode of 8086 configuration depicts a stOR alone system of computer where no other processor is connected.
This is similar to 8085 block diagram with the following difference.
The Data transceiver block which helps the signals traveling a longer distance to get boosted up. Two control signals data
transmit/ receive are connected to the direction input of transceiver (Transmitter/Receiver) OR DEN* signal works as enable
for this block.
Read Cycle Timing Diagram for Minimum Mode

In the bus timing diagram, data transmit / receive signal goes low (RECEIVE) for Read operation. To validate the data,
DEN* signal goes low. The Address/ Status bus carries A16 to A19 address lines during BHE* (low) OR for the remaining
time carries Status information. The Address/Data bus carries A0 to A15 address information during ALE going high OR for
54

the remaining time it carries data. The RD* line going low indicates that this is a Read operation. The curved arrows indicate
the relationship between valid data OR RD* signal.
The T
W
is Wait time needed to synchronize the fast processor with slow memory etc. The Ready pin is checked to see
whether any peripheral needs more time for data transmission.

Write Cycle Timing Diagram for Minimum Operation

This is the same as Read cycle Timing Diagram except that the DT/R* line goes high indicating it is a Data Transmission
operation for the processor to memory / peripheral. Again DEN* line goes low to validate data OR WR* line goes low,
indicating a Write operation.

Bus Request & Bus Grant Timings in Minimum Mode System

The HOLD OR HLDA timing diagram indicates in Time Space HOLD (input) occurs first OR then the processor outputs
HLDA (Hold Acknowledge).

55

Maximum Mode of operation of 8086:

Block Diagram of 8086 in Maximum Mode:
8
0
8
6

C
P
U
Clock
generator
Wait-State
Generator
CLK
READY
RESET
MN/MX
AD0-AD15
A16-A19
BHE
STB
OE
8282
Latch
A0 - A19
Address Bus
+5V
RES
S0
S1
S2
CLK
S0
S1
S2
DATA
8286
Transceiver
T
OE
ALE
Gnd
DEN
DT/R
MRDC
MWTC
IORC
IOWC
AIOWC
AMWC
INTA
8
2
8
8
B
u
s

C
o
n
t
r
o
l
l
e
r

In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the type 8087 or another processor is
interfaced with 8086. The Memory, Address Bus, Data Buses are shared resources between the two processors. The control
signals for Maximum mode of operation are generated by the Bus Controller chip 8788. The three status outputs S0*, S1*,
S2* from the processor are input to 8788. The outputs of the bus controller are the Control Signals, namely DEN, DT/R*,
IORC*, IOWTC*, MWTC*, MRDC*, ALE etc. These control signals perform the same task as the minimum mode
operation. However the DEN is an active HIGH signal which has to be converted to active LOW by means of an inverter.
Memory Read Timing in Maximum Mode

Here MRDC* signal is used instead of RD* as in case of Minimum Mode S0* to S2* are active OR are used to generate
control signal.
56

Memory Write Timing in Maximum Mode

Here the maximum mode write signals are shown. Please note that the T states correspond to the time during which DEN* is
LOW, WRITE Control goes LOW, DT/R* is HIGH OR data output in available from the processor on the data bus.
GT / RQ
Timings in Maximum Mode

Request / Grant pin may appear that both signals are active low. But in reality, Request signal goes low first (input to
processor), OR then the processor grants the request by outputting a low on the same pin.
Bus Read Machine Cycle
Fig- 12 shows the timing diagram of 8086 read machine cycle with WAIT state. The clock (CLK) signal is obtained
from the clock-generator 8284. Each cycle of the clock is referred to as a state. Minimum number of states to access a data
is four. They are T1, T2, T3, OR T4 states.
During T1 state of a read machine cycle an 8086 first asserts the M/ IO signal. It will assert this signal high if it is
going to read from memory during memory read cycle OR it will assert M/ IO low if it is going to do a read from an Input
port during its read cycle. The timing diagram in fig. 12 shows two lines for the M/ IOsignal, because the signal may be
going LOW or going HIGH for a read cycle. The point where the two lines cross indicate the time at which the signal
becomes valid for this machine cycle.
After asserting M/ IO, the 8086 sends out a high on the address latch enable signal, ALE. The microprocessor
sends out on AD0-AD15, A16 through A19 OR BHE lines, the address of the memory location that it wants to read. Since
the latches are enabled by ALE being high, this address information passes through the latches to their outputs. The 8086
57

then makes the ALE output low. This disables the latches (8282) OR holds the address information latched on the latch
outputs. The address information latched on the latch outputs can now be used to select the desired memory or port location.
In the timing diagram, the first point at which the two (AD
0

AD
15
) cross represents the time at which the 8086 has
put a valid address on these lines. Two lines DO NOT indicate that all 16 lines are going high or going low at this point. The
crossed lines indicate the time at which a valid address is on the bus.

T1 T2 T3 Twait T4
CLK
AD0-AD15
BHE
ALE
S2 S0 -
M/IO
RD
READY
DT/R
DEN
WR

Fig. 12 Read Timing Diagram
Since the address information is now held on the latch, the 8086 does not need to send it out any more. As shown in
fig. 12 the 8086 floats the AD0 - AD15 lines so that they can be used to input data from memory or from a port. At about
the same time the 8086 also remove the BHE OR A16-A19 information from the upper lines OR sends out some status
information on these lines.
The 8086 is now ready to read data from the addressed memory locations or port. During T2-state the 8086 asserts
its RDsignal low. This signal is used to enable the addressed memory device or port device.
At the end of T3 state the microprocessor makes the RDsignal high OR reads the data available on the data bus,
provided the READY input signal is high. It is the duty of the external circuit to see that valid data is made available on the
data bus.
If the READY input pin is not high at the sampled time in a machine cycle, the 8086 will insert one or more WAIT
states between T3 OR T4 states in that machine cycle. An external hardware device is set up to pulse READY low before the
rising edge of the clock in T2 state. After the 8086 finishes T3 of the machine cycle, it enters a WAIT state.
If the READY input is still low at the end of a WAIT state, then the 8086 will insert another WAIT state. The 8086
will continue inserting WAIT states until the READY input is sampled high again. If the READY input is sampled high
again during T3 or during the WAIT state, the microprocessor comes out of the WAIT state OR will initiate T4 of the
machine cycle.
The DENsignal is used to enable bi-directional buffers on the data bus. The data enable signal, DEN, from the
8086 will enable the data buffer when it is asserted LOW. The data transmit / receive signal DT/ R from the 8086 is used to
specify the direction in which the buffers are enabled. When DT/ R is asserted high, the buffers will, if enabled byDEN,
transmit data from the 8086 to Memory or I/O ports. When DT/ R is asserted low, the buffers, if enabled by DEN, will
allow data to be received from Memory or I/O ports of the 8086. DT/ R is asserted during T1 of the machine cycle. The
DENis asserted after the 8086 finishes using the data bus to send the lower 16 address bits.

BUS Write Machine Cycle
The 8086 write operation is very similar to the read cycle. During T1 of a write machine cycle the 8086 asserts
M/ IOlow if the write is going to a port OR it asserts M/ IO high if the write is going to memory. At about the same time
the 8086 raises ALE
high to enable the address latches. The 8086 then assert BHE OR on the lines AD0 - AD19, it output the address that it will
be writing to. When writing to a port, line A16 - A19 will always be low, because the 8086 only sends out 16-bits port
addresses. The 8086 brings ALE low again to latch the address on the outputs of the latches. In addition to holding the
58

address, the latches also function as buffers for the address lines. After the address information is latched, the 8086 remove
the address information from AD0 - AD15 OR outputs the desired data on these lines.

Fig 13 Write Timing Diagram
If the READY input is sampled LOW by the 8086 before or during T2 of the machine cycle, the 8086 will insert a
WAIT state after T3. If the READY input is sampled high before the end of the WAIT state, the 8086 will go on with state
T4 as soon as it completes the WAIT state. The 8086 will continue to insect wait states for as long
as the READY is sampled low just before the end of each WAIT state.

59

INTERRUPTS:

Introduction:
Normal program flow can be interrupted because of a variety of reasons.
When the interrupt occurs OR is recognized, the values of the Flag register, CS OR IP registers are saved on the
stack OR the control is transferred from the executing program to an associated Interrupt Service Routine (ISR).
After completing the ISR control returns to the interrupted program.
Thus, this mechanism is similar to yet different from Far Call. CALL is always an instruction in the program. The
mechanism of calling & returning from ISR is some what different from normal CALL mechanism.
The concept of an interrupt vis--vis a far call is illustrated in the following figure:
DIAGRAM:

(ISR; Interrupt Service Procedure; Interrupt HORler All mean the same)
Interrupt can be because of:
An external interrupt signal at the pins NMI or INTR . These are called Hardware interrupts (studied in a
later session).
A Software interrupt instruction.
Internal causes resulting from execution of other instructions etc, like Interrupt on Divide Error.
(sometimes called exceptions)
Whatever be the source of interrupt:
An interrupt instruction has an associated numeric operOR called interrupt type code;
a number in the range of 0 to 255 (00H to FFH). (Thus we can have a total of 256 type codes)
The interrupt type code:
Is provided by external hardware like Interrupt Controller (in the case of external interrupts).
Is specified as part of instruction in the case of Software Interrupts.
Is implicit in the case exceptions like Divide Error.

Whatever be the source of interrupt & what ever be the type code:
For an ISR, both CS OR IP are specified.
To this extent, an ISR is like a far procedure.
CS OR IP of an ISR together constitute the Interrupt Vector. Thus an interrupt vector is 2 + 2 = 4 bytes
long.
One interrupt vector is required for each interrupt type code. We have 256 possible interrupt type codes OR
thus 256 possible interrupt vectors. Consequently, to specify all these interrupt vectors, we need 256 x 4 =
1024 bytes of memory.
Interrupt Vector Table: A table of 1024 bytes containing the 256 interrupt vectors. Address range is 00000H (0:0)
to 003FFH (0:03FFH). This is a memory block of 1KB starting from 00000H
Interrupt vector corresponding to interrupt type code n starts at location 4 x n.
60

Example: Interrupt type code = 20H Corresponding interrupt vector starts at 20H x 4 = 80H. (In locations 80H,
81H, we have IP OR in locations 82H, 83H, we have CS)
Another Example: Interrupt type code = 00H Corresponding interrupt vector starts at 00H x 4 = 00H. (00H, 01H:
IP ; 02H, 03H: CS)
Interrupt type codes:
Some have predefined meaning;
Some are reserved for future use; OR
Remaining interrupt type codes are free for user definitions.
This scheme is shown in the following Interrupt Vector Table:

Interrupt Type Number Function Address
0 Divide by Zero 00H-03H
1 Single Step 04H-07H
2 NMI 08H-0BH
3 Break Point 0CH-0FH
4 Interrupt on Overflow 10H-13H
5-1FH Reserved 14H-7FH
20H-FFH User defined 80H-3FFH

Interrupt Processing:
When an interrupt is to be processed:
Flags, CS OR IP are pushed on to the stack.
(Note that no automatic pushing of Flags occurs with far Call!)
T OR I flags are cleared (disabling Single Step OR External Interrupts)
Control is transferred to the new CS : IP specified in the Interrupt Vector. (ISR begins execution.)
Return from ISR:
To return from the ISR, the interrupt return (IRET) instruction is used.
Executing IRET pops IP, CS OR Flags from the stack.
In particular, the status of T OR I flags is restored.
Now, control returns to the interrupted program.

I Flag:
I flag is cleared disabling recognition of external interrupts. To enable them within the ISR, programmer can enable
them using STI (Set Interrupt Flag) instruction.
CLI (Clear Interrupt Flag) instruction also clears the I flag disabling recognition of interrupts from INTR pin.
The use of these instructions is studied in detail in a later session.
61

T Flag:
Setting the T flag enables Single Step. The, after the execution of every instruction, an interrupt of type 1 is
generated. This feature is quite useful for debugging. (The ISR can display Register values & other useful
information.)
Evidently, within the ISR, Single Step should not be in effect! So T is cleared. On return from ISR, the value of T is
restored.
This concept is illustrated in the following figure:

TRAP DIAGRAM:

Software Interrupt Instructions (INT n):
These instructions appear as regular instructions in the program code.
INT 3 is 1 Byte long. (The only special case). Rest of INT n instructions are all 2 Byte long.
These instructions are commonly used to access system procedures. Example: INT 21H to access DOS services.
A software interrupt instruction is more convenient than far call. It occupies less memory as it needs only 1 or 2
bytes as against the 5 bytes required for a far Call. Further, there is no need to remember the CS:IP values. These
values are obtained from the Interrupt Vector Table.
The software instruction format is as shown below:

INT 3 Instruction:

Only INT n instruction that is 1 Byte long! Rest are 2 Byte long.
This is often used to effect a breakpoint in the program. The breakpoint service routine can provide Register
values OR other information useful for debugging. Any INT n can be used for implement a breakpoint. However, as
INT 3 is only 1-byte long, it is comparatively easier to insert this instruction into the program.
INTO Instruction:
This instruction causes an Interrupt on Overflow. Thus if the O flag = 1, an interrupt is generated as Interrupt
Vector 4. OR if the O flag = 0 , this instruction results in no operation.
This instruction is placed in the program usually after arithmetic instructions that may lead to overflow condition.
(Recall that JO instruction also detects overflow condition.)

Interrupts in PC:
Type codes 0 to 4 are used in the stORard way.
Several interrupt type codes are dedicated to interrupts from hardware devices like key board, mouse etc. Examples:
9 for Keyboard; 17H for Parallel Port.
Software interrupt instructions commonly used in Assembly Language Programs are:
opcode type code
62

INT 21H : DOS Services
INT 27H : Terminate OR Stay Resident (TSR)
INT 1AH : Clock Service etc.

Symbol ASCII

Symbol ASCII

Symbol ASCII

Symbol ASCII

Symbol ASCII

Symbol ASCII
(space) 20 0 30 @ 40 P 50 ` 60 p 70
! 21 1 31 A 41 Q 51 a 61 q 71
" 22 2 32 B 42 R 52 b 62 r 72
# 23 3 33 C 43 S 53 c 63 s 73
$ 24 4 34 D 44 T 54 d 64 t 74
% 25 5 35 E 45 U 55 e 65 u 75
& 26 6 36 F 46 V 56 f 66 v 76
' 27 7 37 G 47 W 57 g 67 w 77
( 28 8 38 H 48 X 58 h 68 x 78
) 29 9 39 I 49 Y 59 i 69 y 79
* 2A : 3A J 4A Z 5A j 6A z 7A
+ 2B ; 3B K 4B [ 5B k 6B { 7B
, 2C < 3C L 4C \ 5C l 6C | 7C
- 2D = 3D M 4D ] 5D m 6D } 7D
. 2E > 3E N 4E ^ 5E n 6E ~ 7E
/ 2F ? 3F O 4F _ 5F o 6F 7F

Branch Displacement Directives: SHORT, LABEL
Blank 20H
A Z - 41H-5AH
a-z - 61H -7AH
0-9 - 30H-39H

63

Bus Structure of 8086:

Fig: Bus Structure of 8086

System Bus: System bus comprises of address bus, data bus OR control bus.

64

Demultiplexing of 8086:

There are 21-multiplexed pins in 8086.

65

Buffering of 8086:

66

Minimum Mode of Operation of 8086:

Timing Diagrams in Minimum Mode of operation of 8086:
a) Read Machine Cycle:

67

b) Write Machine Cycle:

Maximum Mode of Operation of 8086:

68

a) Read Machine Cycle:

b) Write Machine Cycle:

69

8255:

Modes of operation of 8255:
I.Bit Set Reset Mode (BSR Mode)

70

2. I/O Mode:

Interfacing an ADC with 8086 using 8255:

Interfacing DAC with 8086 using 8255:

71

DMA Controller (8257):

72

PPI(8259A):

CommOR Words of 8259A:
1. Initialization CommOR Words: ICW1, ICW2, ICW3, ICW4
2. Operation CommOR Words: OCW1, OCW2, OCW3

Initialization CommOR Words:
ICW1:

73

ICW2:

ICW3:

ICW4:

Operation CommOR Words:
OCW1:

74

OCW2:

OCW3:

75

Cascading of 8259As:

76

Stepper Motor Interfacing:

77

USART (8251A):

Mode word of 8251A:

78

CommOR Word of 8251A:

Status word of 8251A:

79

IEEE-488 Bus:

Fig(a): Pin Diagram of IEEE-488 Bus

Fig(b): Bus Structure of IEEE-488 Bus
80

Microcontrollers:
8051:

81

Memory Interfacing:

82

8051 Ports:

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