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Term End Examination - May 2013

Course : EEE597 - Low Power IC Design

Slot: E2
Class NBR :

2325
Time : Three Hours

Max.Marks:100
Answer ALL Questions
1. Compute the switching activity () and the transition density (D) at the output of a
AND gate with 2 inputs a and b for the following cases, given that they are
implemented using static CMOS style. Also assume that the total possible events for
each of the following cases occur over a reference time frame of 1 sec.
a) Uncorrelated inputs with uniform probability distribution.
b) Temporal correlation in the inputs: Every 0 applied to input a is immediately
followed by a 1, while every 1 applied to input b is immediately followed by a
0.
c) Spatial correlation among inputs: only patterns 00 and 11 can be applied to the
inputs and both are equally likely.
d) Spatio-temporal correlation: changes exactly when b changes value.
[15]
2.(a) i. Consider the system shown in the fig below, where all blocks are assumed to be
identical. Let us assume that each block in the system has a critical path of 1 time
unit when the system is operated with a supply voltage of 3V. The threshold voltage
of the technology, V
th
, is known to be 0.5V. Assume a maximum of 3 supply voltage
to be available. Also assume that the minimum supply voltage to be 1.33V. Use
multiple supply voltage to obtain the least power consumption without altering the
system latency of 6 u.t. Neglect loading effects.

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ii) Develop hardware for time multiplexed bus sharing for the fig shown below.


[2]









[OR]
[10]
2.(b) Consider the following different implementations of the logic functions=(abc+def)
using the characteristics cells of a low area 0.8m library, listed in the table-1 below.
i. Implementation 1: Using NOR and inverter cells.
ii. Implementation 2: Using NOR, NAND and inverter cells.
Assume a load capacitance of 0.2 pf. Determine which of the above implementations is
power efficient, by computing the power cost, if the inputs are uniformly distributed
and uncorrelated.
Table-1:
Gate type Output capacitance (fF) Input capacitance (fF)
Inverter 35 13
NAND2 60 13
NAND3 65 13
NOR2 62 13
NOR3 69 13


3. Get the transfer characteristics of a CMOS inverter and find the short circuit current
and sketch the dependencies of short-circuit current on the following parameters
i) SSC variations with output load capacitance and how to get the optimized design.
ii) SSC variations with different input slopes and how to get the optimized design.
[10]
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4. Mention the significance of software level power analysis. Consider a sample program
execution profile described in the table below. The base current cost and the number of
cycles for each instruction of an INTEL 486DX2 processor is listed alongside. The
measured current cost for this sequence is 332.8 mA. Hence determine the following:
a) Base cost energy and power cost for the program.
b) Energy cost and power cost due to the circuit state overhead.
Assume that the processor operates with a supply voltage of 3.3V with a clock of
80Mhz. Further assume that there are no instruction stalls and cache misses. The
sample program goes as follows:
ADD
DLOAD
LOAD; MULT
ADD
[10]

Instruction Base Cost(PJ) Circuit State effect (PJ) Cycles
Load Dload Add Mult Load;
Add
Load
;Mult
LOAD
DLAOD
ADD
MULT
LOAD;ADD
LOAD;MULT
1.98
2.37
0.99
1.19
2.10
2.25
0.13

0.15
0.17
1.19
1.19
0.26
0.92
0.92
0.53
0.66
1.25
1.32
0.86
0.79
0.40
1.06
1.06
0.99
0.96
0.53
0.79
1
1
2
3
3
3
I
sw
V
DD
GND

V
in
I
sc
I
lk
V
out
C

I
lk
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5. Design a Low Power Full adder circuit in the transistor level using the following
methods:
a) XOR-XOR Based Full adder
b) XNOR-XNOR based Full adder.
Compare their efficiency with conventional full adders in the aspect of number of
transistor used, delay and power.
[10]
6. a) Develop a BDD diagram for the function was expressed as y = x3 + x1 (x2 + x3).
b) Describe the three power saver modes in the system level.
[10]
7.(a) Draw the direct FORM-I structure of a 8-tap FIR filter. Assume the propagation delay
of a multiplier to be thrice that of an adder. For power calculation purposes, further
assume that the total capacitance of a multiplier is 10 times that of an adder.
Draw an alternate FIR filter structure whose critical path delay is exactly half of the
previous version. If the latter filter structure is to be operated at the same sampling rate
as that of the former, then estimate the following.
i. the supply voltage for the alternate filter structure and
ii. the savings in power consumptions expressed as a percentage of the original filter.
Assume Vt=0.5V and V
dd
for the original filter is 4V.
[15]
[OR]

7.(b) i. Consider a static 2-input NOR gate and assume that only one input transition is
possible during a clock cycle and also assume that the inputs to the NOR gate have a
uniform input distribution of high and low levels. This means that the four possible
states for inputs A and B (00, 01, 10, 11) are equally likely.
I. Find the probability that the output is 0.
II. Find the probability that the output is 1.
III. Find the 0 to 1transition probability.
Draw the state transition diagram and annotate with transition probability.
ii. Consider the example in which the multiplication by a constant is optimized by
decomposing into a shift and add operation using a CSD representation. Consider the
two topology shown below for the function using the Associativity and
commutativity law Transformation, comment which topology give me the less
number of transition probability.
[7]






[8]
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Fig (a) Fig (b)
8. Design a 6-T SRAM cell with reduced bit line swing and pulsed word line and discuss
various way of reducing power dissipation in the cell.
[10]
9. Derive the expression for energy dissipation in a transistor channel using an RC model.
Also highlight the framework for an energy recovery circuit design.
[10]