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UNDERSTANDING VIA EFFECTS
DR. ZHEN MU, MENTOR GRAPHI CS
Understanding Via Effects
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2
As the demand for fast computation and information transmission has increased dramatically in recent years, many
designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs are targeting
over 10 Gbps data rates while the SERDES standard is moving toward 25-28 Gbps. With the signal speed changes
come the new challenges of solving design issues never seen before. The electrical components of signal paths on
boards and interconnects present problems, such as significant dielectric loss or impedance discontinuity from
non-trace portion, which used to be ignored at lower signal speed.
For a typical SERDES channel (Figure 1), the discontinuity contribution comes from the vias for signal switching
layers, connectors enabling multi-board connections, and packages. To PCB designers, only via configurations are
under their control in these discontinuity contributors.
Figure 1a: The general signal
path from chip to chip is shown
with the critical path in red.
Figure 1b: This is a typical
channel representation for
simulation.
Understanding Via Effects
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Lets take a look at a single via through a standard PCB stackup. When the signal going through the via has lower
speed (more precisely, with longer rise/fall times), via effects are not significant at all. However, when we have a
faster signal edge rate (rise-fall time is reduced to about 100ps), via causes noticeable delay and signal degradation
(Figure 2). This is the typical discontinuity effects on signal integrity (SI) from a true 3D structure.
Figure 2a: Here is a simple net
topology with a single signal
via .
Figure 2b: Via effects can be
ignored with lower signal speed.
Figure 2c: Via effects cannot be
ignored for higher signal speeds
(data rates in the multi-Gbps
range.)
Understanding Via Effects
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For channel analyses, differential vias are used on signal paths. They also cause signal degradation with the way
they are configured. The most important part is the via stub. Long via stubs can interrupt signal transmission
completely at certain frequencies. Figure 3 shows a pair of differential vias on a 16 layer board. It compares the
S-parameters of the configurations with and without stubs. Clearly, via stubs create un-wanted resonance peaks
(around 8 GHz in this example). At those frequencies, signal components of the spectrum cannot be transmitted.
Therefore, a smaller eye opening in the eye diagram of the case with stubs is observed at receiving end.
Figure 3b: Comparing
S-parameters with and without
via stubs. (Pink and Red: with
stubs; Yellow and White: stubs
removed)
.
Figure 3a: Illustrated here are A
pair of differential vias with long
stubs.
Understanding Via Effects
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Considering that differential signals on a channel have normally one entering layer and one exiting layer, there
would be many via pads left unused. Those pads also can cause SI problems. Figure 4 shows the configuration of a
pair of vias going through a board stackup of 26 layers. If a designer leaves all these non-functional pads intact, he
can get significant resonance peaks at lower frequencies. Removing those pads helps pushing such peaks toward
the higher frequency range therefore benefiting signal transmission. This design method is useful when it is not
practical to remove long via stubs through back-drilling techniques
Figure 3c: Comparing eye
diagrams with and without via
stubs.
Figure 4a: Shown are a pair of
differential vias with unused
pads in both 3D and 2D
representation..
Figure 4b: Comparing
S-parameters with and without
unused pads (Pink has unused
pads; Red with unused pads
removed).
Understanding Via Effects
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A via is the means of signal routing by moving the signal to different layers. The return current path will be
interrupted when layer switching occurs. As the result, the trace impedance will be affected. To avoid the reflection
caused by the impedance change (or discontinuity) at vias, stitching (or ground) vias are recommended in multi-
Gbps designs to keep the current return path for signals. Considering that these extra vias take up precious space
on board, designers often need to know when stitching vias are absolutely necessary, and when a design still works
without using stitching vias. Simulating and understanding the stitching via effect help make such decisions. Figure
5 shows the results of via configurations with and without stitching vias, and the distance changes from the signal
vias. Designers can learn in this case that stitching vias need to be placed closer to the signal vias; if the budget
allows a 0.5dB loss from the via discontinuity, they do not need to use stitching vias here.
When the routing space is restricted, designers will also need to know the exact number of stitching vias required.
The selection depends on the frequency range designers are interested in. Figure 6 gives another example on
effects with different numbers of stitching vias. In this 6 layer design, the number of stitching vias does not matter
up to about 14 Ghz, while the insertion loss difference is 0.3 dB at 20 GHz whether placing 4 stitching vias or 1
stitching via around the single via. Again, designers should choose the right number of stitching vias based on
noise budget, or the design tolerance.
Figure 5a: A pair of differential
vias with 2 stitching vias.
Figure 5b: Comparing insertion
loss using S-parameters
(Yellow: with stitching vias closely
placed. Pink: with stitching vias
placed far away. Green: without
stitching vias)
.
Figure 6a: This structure will be
used for our design example
varying the number of stiching
vias.
Understanding Via Effects
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So far, we have discussed single via (or pair) behavior. Vias can also create coupling noise to a signal net through
plane cavities if two signal vias go through the same plane pair. Lets examine the example in Figure 7. The channel
under testing carries a PCIExpress signal. There are several DDR2 signals routed on the same board. Though the
DDR signals are far from the PCIExpress channel (no trace coupling), the vias on both signals pass through the same
plane layers. When the DQ net of the DDR bus switches, noise is generated in the plane cavity and travels towards
the vias on the PCIExpress channel and is picked up. It then influences the eye diagram at the receiving end. The
eye opening is reduced because of the via coupling noise.
Figure 6b: Comparison of
insertion loss with different
numbers of stitching vias on the
design example shown in FIgure
6a.
Figure 7a: This is the design for
the example simulation shown in
Figures 7b and 7c..
Understanding Via Effects
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In summary, the discontinuity effects from vias on signal path can cause significant degradation on eye diagrams of
a multi-Gbps channel. The old assumption to ignore those effects, or using simple models estimating the effects
are no longer acceptable. Designers need to understand the contributions from different parts of a via and the
severity of their impact on signal quality. Then, they can use 3D modeling and analysis functions in an SI tool to
determine how a design should be modified.
Figure 7b: Plan noise indusced by
via coupling when the DQ signal
switches: 86 mV..
Figure 7c: Comparing eye
diagrams and time-domain
waveforms. (Blue has no via
crosstalk, while red shows via
crosstalk.