antenna diode vlsi operation positive charge

Here are some Questions.........

Explain why & how a MOSFET works
Draw Vds!ds "ur#e $or a MOSFET. %ow& show how this "ur#e "han'es (a) with in"reasin'
V's (*) with in"reasin' transistor width (") "onsiderin' +hannel ,en'th Modulation
Explain the #arious MOSFET +apa"itan"es & their si'ni$i"an"e
Draw a +MOS !n#erter. Explain its trans$er "hara"teristi"s
Explain si-in' o$ the in#erter
How do you si-e %MOS and .MOS transistors to in"rease the threshold #olta'e/
0hat is %oise Mar'in/ Explain the pro"edure to determine %oise Mar'in
1i#e the expression $or +MOS swit"hin' power dissipation
0hat is 2ody E$$e"t/
Des"ri*e the #arious e$$e"ts o$ s"alin'
1i#e the expression $or "al"ulatin' Delay in +MOS "ir"uit
0hat happens to delay i$ you in"rease load "apa"itan"e/
0hat happens to delay i$ we in"lude a resistan"e at the output o$ a +MOS "ir"uit/
0hat are the limitations in in"reasin' the power supply to redu"e delay/
How does 3esistan"e o$ the metal lines #ary with in"reasin' thi"kness and in"reasin'
len'th/
4ou ha#e three ad5a"ent parallel metal lines. Two out o$ phase si'nals pass throu'h the
outer two metal lines. Draw the wa#e$orms in the "enter metal line due to inter$eren"e.
%ow& draw the si'nals i$ the si'nals in outer metal lines are in phase with ea"h other
0hat happens i$ we in"rease the num*er o$ "onta"ts or #ia $rom one metal layer to the
next/
Draw a transistor le#el two input %6%D 'ate. Explain its si-in' (a) "onsiderin' Vth (*) $or
e7ual rise and $all times
,et 6 & 2 *e two inputs o$ the %6%D 'ate. Say si'nal 6 arri#es at the %6%D 'ate later
than si'nal 2. To optimi-e delay& o$ the two series %MOS inputs 6 & 2& whi"h one would
you pla"e near the output/
Draw the sti"k dia'ram o$ a %O3 'ate. Optimi-e it
For +MOS lo'i"& 'i#e the #arious te"hni7ues you know to minimi-e power "onsumption
0hat is +har'e Sharin'/ Explain the +har'e Sharin' pro*lem while samplin' data $rom a
2us
0hy do we 'radually in"rease the si-e o$ in#erters in *u$$er desi'n/ 0hy not 'i#e the
output o$ a "ir"uit to one lar'e in#erter/
!n the desi'n o$ a lar'e in#erter& why do we pre$er to "onne"t small transistors in parallel
(thus in"reasin' e$$e"ti#e width) rather than lay out one transistor with lar'e width/
1i#en a layout& draw its transistor le#el "ir"uit. (! was 'i#en a 8 input 6%D 'ate and a 9
input Multiplexer. 4ou "an expe"t any simple 9 or 8 input 'ates)
1i#e the lo'i" expression $or an 6O! 'ate. Draw its transistor le#el e7ui#alent. Draw its
sti"k dia'ram
0hy don:t we use 5ust one %MOS or .MOS transistor as a transmission 'ate/
For a %MOS transistor a"tin' as a pass transistor& say the 'ate is "onne"ted to VDD& 'i#e
the output $or a s7uare pulse input 'oin' $rom ; to VDD
Draw a <T S36M +ell and explain the 3ead and 0rite operations
Draw the Di$$erential Sense 6mpli$ier and explain its workin'. 6ny idea how to si-e this
"ir"uit/ (+onsider +hannel ,en'th Modulation)
0hat happens i$ we use an !n#erter instead o$ the Di$$erential Sense 6mpli$ier/
Draw the S36M 0rite +ir"uitry
6pproximately& what were the si-es o$ your transistors in the S36M "ell/ How did you
arri#e at those si-es/
How does the si-e o$ .MOS .ull =p transistors ($or *it & *it lines) a$$e"t S36M:s
per$orman"e/
0hat:s the "riti"al path in a S36M/
Draw the timin' dia'ram $or a S36M 3ead. 0hat happens i$ we delay the ena*lin' o$
+lo"k si'nal/
1i#e a *i' pi"ture o$ the entire S36M ,ayout showin' your pla"ements o$ S36M +ells& 3ow
De"oders& +olumn De"oders& 3ead +ir"uit& 0rite +ir"uit and 2u$$ers
!n a S36M layout& whi"h metal layers would you pre$er $or 0ord ,ines and 2it ,ines/
0hy/
How "an you model a S36M at 3T, ,e#el/
0hat:s the di$$eren"e *etween Testin' & Veri$i"ation/
For an 6%DO3 implementation o$ a two input Mux& how do you test $or Stu"k6t; and
Stu"k6t> $aults at the internal nodes/ (4ou "an expe"t a "ir"uit with some redundant
lo'i")
0hat is ,at"h =p/ Explain ,at"h =p with "ross se"tion o$ a +MOS !n#erter. How do you
a#oid ,at"h =p/
1) How transition time is going to effect your delay?
delay increases with transistion time.
2) If load is more, would delay increase or decrease?
why?
Delay increases with load. It requires more time to cahrge high loads.
3) How skew is goint to effect your setu and hold?
!ill it hel the setu?
setu time increases with skew.
") If skew is more, how it is going to effect your
design?
#he seed goes down with skew.
$) If hase delay is more, how it is going to effect
your design?
hase delay effects the frequency of oeration due to hase distortion.
%) !hy we need to fi& the ma& transition 'efore setu
and hold?
this effects delay.
() !hat is meant 'y false ath? !hen can we call
selection line of multile&er as a false ath? and
when not?
......
How we will decide the ath as a false ath? )an
you tell 'y taking mu& as an e&amle?
....
*) !hy we need to fi& hold after )#+ only?
1.,&lain multi cycle ath with e&amle and wa-eform
2.How is ower consumtion effected with shrinking technology?
3.!hat are the different tyes of lacements?
".How will u know whether to do a #iming Dri-en lacement or
)ongestion Dri-en lacement?
$.!hat does timing li'rary consist of?
%..ook u ta'les?
(.how to calculate die si/e?
0.how to calculate the no of 1DD and 1++ ads?
*.)on-ert 2 i2 mu& to in-erter?
13.what is 4set inut delay4 in sdc file?
11.During I56 usi/ing and downsi/ing,what are usi/ed or
downsi/ed,778s or )om'i logic? !hy?
12.,&lain setu and hold with e&amle and wa-eforms
-isit the site9
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+# micro electronic question aer +# ;I)<6,.,)#<6=I)+
<6>=D 1
?ue9 );6+ working, 6eration.
?ue9 .atch@ >
?ue9 #iming +lack, +etu, Hold, How to calculate the slack.
?ue9 Hot carrier effect?
?ue9 5ass transistor concet?
?ue9 How 'uffer minimi/es skew as gate delays is more than
roagation or transition
Delays?
<6>=D2
?ue9 Difference 'etween 77 A .atch
?ue9 <acing 5ro'lem, what is it and where it occurs in 77 or in latch?
?ue9 Block diag. 6f latch.
?ue9 +lack
?ue9 +etu A Hold time? How is it effected?
?ue9 How to form ca in ;6+? If Drain and source is shorted how will it
'eha-e
.ike a caacitor? !hich tye of ca is it?
?ue9 ,quation of 1# ? where 5.D. is more , where the gain is high?
<6>=D C 3 D= Eggarwal)
?ue9 How will 'e )harging occur for the following )ur-e.
?ue9 How ;os de-ice works?
?ue9 How );6+ In-erter works. How the = ;6+25;6+ works in
different region ie. )ut@off, saturation, linear.
?ue9 ,quation of ID+ in different region.
?ue9 ,lectro migration )alculation
?ue9 Entenna effect, from where the charge comes?
?ue9 where will we ut the diode, nearer to gate or far from gate, A
why?
?ue9 How layer hoing reduces the rocess Entenna effect?
?ue9 why distance 'etween diffusion contacts?
<6>=D "
?ue9 cross section of ;6+?
?ue9 cut it in halfF how the -iew looks like?
?ue9 Guard <ing, secondary guard ring? !hy is it always as ring?
?ue9 If u cut guard ring how will it look like?
?ue9 .atch >?
?ue9 Entenna ,ffect?
?ue9 In the following figure what will haen if u run the metal1 5ower
suly 23- o-er
the oly.
?ue9 !hat were the ro'lems u faced while doing layout?
?ue9 #ell a'out following fig. !hat actually it is?
1$ in the following diagram? ?ue9 Is it ossi'le to get H"3 - if its
suly is $
?ue9 In diffusion region why multile contact, what will haen if we
ut a 'ig contact?
;,;6<I G<6>5
<6>=D1
?ue9 ,lectro migration, A How will u o-ercome this A at what le-el u
see it DIn
5rocessing or after a chi is manufactured?)
?ue9 How will u calculate ,lectro migration A what r the data u need to
calculate
,.;.? How fingering effects the ,.;.?
?ue9 !hat is Entenna effect A How metal hoing imro-es antenna
effects? D5ositi-e
)harge gets collected on the metal, from where this charge comes?)
?ue9 ,&lain .atch u? How the 1dd -alue will come down to 3.* if it is
$1 earlier?
?ue9 How more su'strate contact reduces H-e resistance and also well
contact?
?ue9 How 5 ta 2 =ta imro-es latch u?
?ue9 !hen does the ,+D occurs? In rocessing or in oeration?
?ue9 when does the ,lectro migration occurs? In rocessing or in
6eration?
<6>=D2
?ue9 How will u calculate the ower strie width?
?ue9 How will u imro-e I< dro effect?
?ue9 <) ckt. D.ow ass 7ilter), o2 cur-e
?ue9 If u increase 1dd, what will 'e the effect on the su' threshold
current?
?ue9 !hat kind of )aacitor is there in ;6+? ;6+ de-ice ca cur-e?
1alue of )
+u'strate?
?ue9 D7; rule?
?ue9 How e-en no. of fingering is 'etter than odd no. of fingering? How
does it effect the
quality of layout?
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simle logic questions that in-ol-ed using gates to imlement 'oolean
equations, the only one I remem'er is B J 2KE
@ write -hdl code for fli fli with synchronous reset
@ imlement 2 'it counter using a fsm, draw the circuit using D fli
flos
@ define setu time, hold time and clock skew, use a diagram
@ Gi-en a circuit with 2 d fli flos where the outut of one fli flo
goes through some com'inational logic and ties into the inut of the
second fli flo, and the same clock is used for 'oth fli flos. Deri-e
the ma&imum clock frequency for the circuit. Deri-e the minimum hold
time allowed for the circuit. If the hold time
@ ,&lain the oeration of a n@channel or @channel );6+ transistor at
the de-ice le-el using a diagram
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htt922asic.co.in2
1.+I
1. ,&lain why A how a ;6+7,# works.
2. Draw 1ds@Ids cur-e for a ;6+7,#. =ow, show how this cur-e
changes Da) with increasing 1gs D') with increasing transistor width Dc)
considering )hannel .ength ;odulation
3. ,&lain the -arious ;6+7,# )aacitances A their significance
". Draw a );6+ In-erter. ,&lain its transfer characteristics
$. ,&lain si/ing of the in-erter
%. How do you si/e =;6+ and 5;6+ transistors to increase the
threshold -oltage?
(. !hat is =oise ;argin? ,&lain the rocedure to determine =oise
;argin
0. Gi-e the e&ression for );6+ switching ower dissiation
*. !hat is Body ,ffect?
13. Descri'e the -arious effects of scaling
11. Gi-e the e&ression for calculating Delay in );6+ circuit
12. !hat haens to delay if you increase load caacitance?
13. !hat haens to delay if we include a resistance at the outut of a
);6+
circuit?
1". !hat are the limitations in increasing the ower suly to reduce
delay?
1$. How does <esistance of the metal lines -ary with increasing
thickness and increasing length?
1%. Iou ha-e three ad:acent arallel metal lines. #wo out of hase
signals ass through the outer two metal lines. Draw the wa-eforms in
the center metal line due to interference. =ow, draw the signals if the
signals in outer metal lines are in hase with each other
1(. !hat haens if we increase the num'er of contacts or -ia from
one metal layer to the ne&t?
10. Draw a transistor le-el two inut =E=D gate. ,&lain its si/ing Da)
considering 1th D') for equal rise and fall times
1*. .et E A B 'e two inuts of the =E=D gate. +ay signal E arri-es at
the =E=D gate later than signal B. #o otimi/e delay, of the two series
=;6+ inuts E A B, which one would you lace near the outut?
23. Draw the stick diagram of a =6< gate. 6timi/e it
21. 7or );6+ logic, gi-e the -arious techniques you know to minimi/e
ower consumtion
22. !hat is )harge +haring? ,&lain the )harge +haring ro'lem while
samling data from a Bus
23. !hy do we gradually increase the si/e of in-erters in 'uffer design?
!hy not gi-e the outut of a circuit to one large in-erter?
2". In the design of a large in-erter, why do we refer to connect small
transistors in arallel Dthus increasing effecti-e width) rather than lay
out one transistor with large width?
2$. Gi-en a layout, draw its transistor le-el circuit. DI was gi-en a 3
inut E=D gate and a 2 inut ;ultile&er. Iou can e&ect any simle 2
or 3 inut gates)
2%. Gi-e the logic e&ression for an E6I gate. Draw its transistor le-el
equi-alent. Draw its stick diagram
2(. !hy donLt we use :ust one =;6+ or 5;6+ transistor as a
transmission gate?
20. 7or a =;6+ transistor acting as a ass transistor, say the gate is
connected to 1DD, gi-e the outut for a square ulse inut going from
3 to 1DD
2*. Draw a %@# +<E; )ell and e&lain the <ead and !rite oerations
33. Draw the Differential +ense Emlifier and e&lain its working. Eny
idea how to si/e this circuit? D)onsider )hannel .ength ;odulation)
31. !hat haens if we use an In-erter instead of the Differential
+ense Emlifier?
32. Draw the +<E; !rite )ircuitry
33. Ero&imately, what were the si/es of your transistors in the +<E;
cell? How did you arri-e at those si/es?
3". How does the si/e of 5;6+ 5ull > transistors Dfor 'it A 'it@ lines)
affect +<E;Ls erformance?
3$. !hatLs the critical ath in a +<E;?
3%. Draw the timing diagram for a +<E; <ead. !hat haens if we
delay the ena'ling of )lock signal?
3(. Gi-e a 'ig icture of the entire +<E; .ayout showing your
lacements of +<E; )ells, <ow Decoders, )olumn Decoders, <ead
)ircuit, !rite )ircuit and Buffers
30. In a +<E; layout, which metal layers would you refer for !ord
.ines and Bit .ines? !hy?
3*. How can you model a +<E; at <#. .e-el?
"3. !hatLs the difference 'etween #esting A 1erification?
"1. 7or an E=D@6< imlementation of a two inut ;u&, how do you test
for +tuck@Et@3 and +tuck@Et@1 faults at the internal nodes? DIou can
e&ect a circuit with some redundant logic)
"2. !hat is .atch >? ,&lain .atch > with cross section of a );6+
In-erter. How do you a-oid .atch >?
htt922www.-lsichidesign.com2
1. Gi-e two ways of con-erting a two inut =E=D gate to an
in-erter
2. Gi-en a circuit, draw its e&act timing resonse. DI was gi-en a
5seudo <andom +ignal GeneratorF you can e&ect any sequential
ckt)
3. !hat are set u time A hold time constraints? !hat do they
signify? !hich one is critical for estimating ma&imum clock
frequency of a circuit?
". Gi-e a circuit to di-ide frequency of clock cycle 'y two
$. Design a di-ide@'y@3 sequential circuit with $3M duty circle.
DHint9 Dou'le the )lock)
%. +uose you ha-e a com'inational circuit 'etween two registers
dri-en 'y a clock. !hat will you do if the delay of the
com'inational circuit is greater than your clock signal? DIou canLt
resi/e the com'inational circuit transistors)
(. #he answer to the a'o-e question is 'reaking the com'inational
circuit and ielining it. !hat will 'e affected if you do this?
0. !hat are the different Edder circuits you studied?
*. Gi-e the truth ta'le for a Half Edder. Gi-e a gate le-el
imlementation of the same.
13. Draw a #ransmission Gate@'ased D@.atch.
11. Design a #ransmission Gate 'ased N6<. =ow, how do you
con-ert it to N=6<? D!ithout in-erting the outut)
12. How do you detect if two 0@'it signals are same?
13. How do you detect a sequence of 411314 arri-ing serially
from a signal line?
1". Design any 7+; in 1HD. or 1erilog.
1$. ,&lain <) circuitOPQRSQTPs charging and discharging.
1%. ,&lain the working of a 'inary counter.
1(. Descri'e how you would re-erse a singly linked list.
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x86 interview questions
#hese inter-iew questions test the knowledge of &0% Intel architecture
and 030% microrocessor secifically.
1. What is a Microprocessor? @ ;icrorocessor is a rogram@
controlled de-ice, which fetches the instructions from memory,
decodes and e&ecutes the instructions. ;ost ;icro 5rocessor are
single@ chi de-ices.
2. Give examples for 8 / 16 / 3 !it Microprocessor? @ 0@'it
5rocessor @ 030$ 2 U03 2 %033F 1%@'it 5rocessor @ 030% 2 %0333 2
U0333F 32@'it 5rocessor @ 0330% 2 03"0%.
3. Wh" 8#8$ processor is called an 8 !it processor? @ Because
030$ rocessor has 0 'it E.> DErithmetic .ogic <e-iew). +imilarly
030% rocessor has 1% 'it E.>.
". What is 1st / nd / 3rd / %th generation processor? @ #he
rocessor made of 5;6+ 2 =;6+ 2 H;6+ 2 H);6+ technology is
called 1st 2 2nd 2 3rd 2 "th generation rocessor, and it is made
u of " 2 0 2 1% 2 32 'its.
$. &efine '(M)*? @ High@density n@ tye )omlimentary ;etal
6&ide +ilicon field effect transistor.
%. What does microprocessor speed depend on? @ #he
rocessing seed deends on DE#E B>+ !ID#H.
(. +s the address !us unidirectional? @ #he address 'us is
unidirectional 'ecause the address information is always gi-en
'y the ;icro 5rocessor to address a memory location of an
inut 2 outut de-ices.
0. +s the data !us is ,i-directional? @ #he data 'us is Bi@
directional 'ecause the same 'us is used for transfer of data
'etween ;icro 5rocessor and memory or inut 2 outut de-ices
in 'oth the direction.
*. What is the disadvantage of microprocessor? @ It has
limitations on the si/e of data. ;ost ;icrorocessor does not
suort floating@oint oerations.
13. What is the difference !etween microprocessor and
microcontroller? @ In ;icrorocessor more o@codes, few 'it
handling instructions. But in ;icrocontroller9 fewer o@codes,
more 'it handling Instructions, and also it is defined as a de-ice
that includes micro rocessor, memory, A inut 2 outut signal
lines on a single chi.
11. What is meant !" ./0('? @ .atch is a D@ tye fli@flo
used as a temorary storage de-ice controlled 'y a timing signal,
which can store 3 or 1. #he rimary function of a .atch is data
storage. It is used in outut de-ices such as .,D, to hold the data
for dislay.
12. Wh" does microprocessor contain 1)M chips? @
;icrorocessor contain <6; chi 'ecause it contain instructions
to e&ecute data.
13. What is the difference !etween primar" 2 secondar"
storage device? @ In rimary storage de-ice the storage
caacity is limited. It has a -olatile memory. In secondary
storage de-ice the storage caacity is larger. It is a non-olatile
memory. 5rimary de-ices are9 <E; 2 <6;. +econdary de-ices
are9 7loy disc 2 Hard disk.
1". &ifference !etween static and d"namic 1/M? @ +tatic
<E;9 =o refreshing, % to 0 ;6+ transistors are required to form
one memory cell, Information stored as -oltage le-el in a fli
flo. Dynamic <E;9 <efreshed eriodically, 3 to " transistors are
required to form one memory cell, Information is stored as a
charge in the gate to su'strate caacitance.
1$. What is interrupt? @ Interrut is a signal send 'y e&ternal
de-ice to the rocessor so as to request the rocessor to erform
a articular work.
1%. What is cache memor"? @ )ache memory is a small high@
seed memory. It is used for temorary storage of data A
information 'etween the main memory and the )5> Dcenter
rocessing unit). #he cache memory is only in <E;.
1(. What is called 3*cratch pad of computer3? @ )ache
;emory is scratch ad of comuter.
10. Which transistor is used in each cell of 451)M? @
7loating .gate E-alanche In:ection ;6+ D7E;6+) transistor is
used in each cell of ,5<6;.
1*. &ifferentiate !etween 1/M and 1)M? @ <E;9 <ead 2
!rite memory, High +eed, 1olatile ;emory. <6;9 <ead only
memory, .ow +eed, =on 1oliate ;emory.
23. What is a compiler? @ )omiler is used to translate the
high@le-el language rogram into machine code at a time. It
doesn.t require secial instruction to store in a memory, it stores
automatically. #he ,&ecution time is less comared to
Interreter.
21. Which processor structure is pipelined? @ Ell &0%
rocessors ha-e ielined structure.
22. What is flag? @ 7lag is a fli@flo used to store the
information a'out the status of a rocessor and the status of the
instruction e&ecuted most recently
23. What is stac6? @ +tack is a ortion of <E; used for sa-ing
the content of 5rogram )ounter and general urose registers.
2". (an 1)M !e used as stac6? @ <6; cannot 'e used as
stack 'ecause it is not ossi'le to write to <6;.
2$. What is 78-1/M? @ =on-olatile <ead !rite ;emory, also
called 7lash memory. It is also know as shadow <E;.
VBack to #o
+ntel interview questions
#he following questions are used for screening the candidates during
the first inter-iew. #he questions aly mostly to fresh college grads
ursuing an engineering career at Intel.
1. Ha-e you studied 'uses? !hat tyes?
2. Ha-e you studied ielining? .ist the $ stages of a $ stage
ieline. Essuming 1 clock er stage, what is the latency of an
instruction in a $ stage machine? !hat is the throughut of this
machine ?
3. How many 'it com'inations are there in a 'yte?
". 7or a single comuter rocessor comuter system, what is the
urose of a rocessor cache and descri'e its oeration?
$. ,&lain the oeration considering a two rocessor comuter
system with a cache for each rocessor.
%. !hat are the main issues associated with multirocessor caches
and how might you sol-e them?
(. ,&lain the difference 'etween write through and write 'ack
cache.
0. Ere you familiar with the term ;,+I?
*. Ere you familiar with the term snooing?
13. Descri'e a finite state machine that will detect three
consecuti-e coin tosses Dof one coin) that results in heads.
11. In what cases do you need to dou'le clock a signal 'efore
resenting it to a synchronous state machine?
12. Iou ha-e a dri-er that dri-es a long signal A connects to
an inut de-ice. Et the inut de-ice there is either o-ershoot,
undershoot or signal threshold -iolations, what can 'e done to
correct this ro'lem?
13. !hat are the total num'er of lines written 'y you in )2)H
H? !hat is the most comlicated2-alua'le rogram written in
)2)HH?
1". !hat comiler was used?
1$. !hat is the difference 'etween J and JJ in )?
1%. Ere you familiar with 1HD. and2or 1erilog?
1(. !hat tyes of );6+ memories ha-e you designed? !hat
were their si/e? +eed?
10. !hat work ha-e you done on full chi )lock and 5ower
distri'ution? !hat rocess technology and 'udgets were used?
1*. !hat tyes of I26 ha-e you designed? !hat were their
si/e? +eed? )onfiguration? 1oltage requirements?
23. 5rocess technology? !hat ackage was used and how did
you model the ackage2system? !hat arasitic effects were
considered?
21. !hat tyes of high seed );6+ circuits ha-e you
designed?
22. !hat transistor le-el design tools are you roficient with?
!hat tyes of designs were they used on?
23. !hat roducts ha-e you designed which ha-e entered high
-olume roduction?
2". !hat was your role in the silicon e-aluation2roduct ram?
!hat tools did you use?
2$. If not into roduction, how far did you follow the design
and why did not you see it into roduction?
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<ead more at #echInter-iews.com
4m!edded s"stems interview questions
1. )an structures 'e assed to the functions 'y -alue?
2. !hy cannot arrays 'e assed 'y -alues to functions?
3. Ed-antages and disad-antages of using macro and inline
functions?
". !hat haens when recursion functions are declared inline?
$. +coe of static -aria'les?
%. Difference 'etween o':ect oriented and o':ect 'ased languages?
(. ;ultile inheritance @ o':ects contain howmany multily inherited
ancestor?
0. !hat are the " different tyes of inheritance relationshi?
*. How would you find out the no of instance of a class?
13. Is :a-a a ure o':ect oriented language? !hy?
11. 6rder of constructor and destructor call in case of multile
inheritance?
12. )an u ha-e inline -irtual functions in a class?
13. !hen you inherit a class using ri-ate keyword which
mem'ers of 'ase class are -isi'le to the deri-ed class?
1". !hat is the outut of rintfD4Wna'W'cdWref4)F @X ef
1$. Ydefine catD&,y) &YYy concatenates & to y. But
catDcatD1,2),3) does not e&and 'ut gi-es rerocessor warning.
!hy?
1%. )an you ha-e constant -olatile -aria'le? Ies, you can ha-e
a -olatile ointer?
1(. HHKi increments what? it increments what i oints to
10. 6erations in-ol-ing unsigned and signed Z unsigned will
'e con-erted to signed
1*. aHHH' @X DaHH)H'
23. mallocDsi/eofD3)) will return Z -alid ointer
21. mainD) [forkD)FforkD)FforkD)FrintfD4hello world4)F \ Z will
rint 0 times.
22. Erray of ts to functions Z -oid DKftr]13^)D)
23. !hich way of writing infinite loos is more efficient than
others? there are 3ways.
2". Y error Z what it does?
2$. How is function itoaD) written?
2%. !ho to know wether systemuses 'ig endian or little endian
format and how to con-ert among them?
2(. !hat is interrut latency?
20. !hat is forward reference w.r.t. ointers in c?
2*. How is generic list maniulation function written which
accets elements of any kind?
33. !hat is the difference 'etween hard real@time and soft
real@time 6+?
31. !hat is interrut latency? How can you recuce it?
32. !hat is the differnce 'etween em'edded systems and the
system in which rtos is running?
33. How can you define a structure with 'it field mem'ers?
3". !hat are the features different in +6+ and -&!orks?
3$. How do you write a function which takes 2 arguments @ a
'yte and a field in the 'yte and returns the -alue of the field in
that 'yte?
3%. !hat are the different storage classes in )?
3(. !hat are the different qualifiers in )?
30. !hat are the different B+D and +1<" communication
mechanisms
VBack to #o
(omputer architecture and design interview questions
1. !hat is ielining?
2. !hat are the fi-e stages in a D.N ieline?
3. 7or a ieline with _nL stages, whatLs the ideal throughut? !hat
re-ents us from achie-ing this ideal throughut?
". !hat are the different ha/ards? How do you a-oid them?
$. Instead of :ust $@0 ie stages why not ha-e, say, a ieline with
$3 ie stages?
%. !hat are Branch 5rediction and Branch #arget Buffers?
(. How do you handle recise e&cetions or interruts?
0. !hat is a cache?
*. !hatLs the difference 'etween !rite@#hrough and !rite@Back
)aches? ,&lain ad-antages and disad-antages of each.
13. )ache +i/e is %"`B, Block si/e is 32B and the cache is #wo@
!ay +et Essociati-e. 7or a 32@'it hysical address, gi-e the
di-ision 'etween Block 6ffset, Inde& and #ag.
11. !hat is 1irtual ;emory?
12. !hat is )ache )oherency?
13. !hat is ;,+I?
1". !hat is a +nooing cache?
1$. !hat are the comonents in a ;icrorocessor?
1%. !hat is E)B7DHe&) di-ided 'y 1%?
1(. )on-ert %$DHe&) to Binary
10. )on-ert a num'er to its twoLs comliment and 'ack
1*. #he )5> is 'usy 'ut you want to sto and do some other
task. How do you do it?
'ardware design interview questions
1. Gi-e two ways of con-erting a two inut =E=D gate to an
in-erter
2. Gi-en a circuit, draw its e&act timing resonse. DI was gi-en a
5seudo <andom +ignal GeneratorF you can e&ect any sequential
ckt)
3. !hat are set u time A hold time constraints? !hat do they
signify? !hich one is critical for estimating ma&imum clock
frequency of a circuit?
". Gi-e a circuit to di-ide frequency of clock cycle 'y two
$. Design a di-ide@'y@3 sequential circuit with $3M duty circle.
DHint9 Dou'le the )lock)
%. +uose you ha-e a com'inational circuit 'etween two registers
dri-en 'y a clock. !hat will you do if the delay of the
com'inational circuit is greater than your clock signal? DIou canLt
resi/e the com'inational circuit transistors)
(. #he answer to the a'o-e question is 'reaking the com'inational
circuit and ielining it. !hat will 'e affected if you do this?
0. !hat are the different Edder circuits you studied?
*. Gi-e the truth ta'le for a Half Edder. Gi-e a gate le-el
imlementation of the same.
13. Draw a #ransmission Gate@'ased D@.atch.
11. Design a #ransmission Gate 'ased N6<. =ow, how do you
con-ert it to N=6<? D!ithout in-erting the outut)
12. How do you detect if two 0@'it signals are same?
13. How do you detect a sequence of 411314 arri-ing serially
from a signal line?
1". Design any 7+; in 1HD. or 1erilog.
1$. ,&lain <) circuit.s charging and discharging.
1%. ,&lain the working of a 'inary counter.
1(. Descri'e how you would re-erse a singly linked list.
18. Insights of an inverter. Explain the working?
19. Insights of a 2 input NOR gate. Explain the working?
20. Insights of a 2 input NN! gate. Explain the working?
21. I"ple"ent #$ not %&'(!) using (*O+ gates?
22. Insights of a pass gate. Explain the working?
2,. -h. /o we nee/ 0oth 1*O+ an/ N*O+ transistors to i"ple"ent a pass gate?
22. -hat /oes the a0ove 3o/e s.nthesi4e to?
25. (ross se3tion of a 1*O+ transistor?
26. (ross se3tion of an N*O+ transistor?
27. -hat is a !8lat3h? -rite the 9:!; (o/e for it?
28. !ifferen3es 0etween !8;at3h an/ ! flip8flop?
29. I"ple"ent ! flip8flop with a 3ouple of lat3hes? -rite a 9:!; (o/e for a ! flip8flop?
,0. -hat is lat3hup? Explain the "etho/s use/ to prevent it?
,1. -hat is 3harge sharing?
,2. -hile using logi3 /esign< explain the various steps that r followe/ to o0tain the /esira0le /esign in a well
/efine/ "anner?
,,. -h. is OO1+ 3alle/ OO1+? %('')
,2. -hat is a linke/ list? Explain the 2 fiel/s in a linke/ list?
,5. I"ple"ent a 2 I=1 an/ gate using >ran gates?
,6. Insights of a 20it a//er=+u0 (ir3uit?
,7. #or f $ &'(! if & is +8a81< what r the test ve3tors nee/e/ to /ete3t the fault?
,8. Explain various a//ers an/ /iff 0etween the"?
,9. Explain the working of 280it ?p=/own (ounter?
20. 3ir3uit has 1 input @ an/ 2 outputs an/ &. If @ $ :IA: for 2 3lo3k ti3ks< $ 1. If @ $ ;O- for 2 3lo3k ti3ks<
& $ 1. !raw a state /iagra" for this +pe3?
21. /vantages an/ /isa/vantages of *eal. an/ *oore?
22. I/ vs. 9/s (hara3teristi3s of N*O+ an/ 1*O+ transistors?
2,. Explain the operation of a 6>8+R* 3ell?
22. !ifferen3es 0etween !R* an/ +R*?
25. I"ple"ent a fun3tion with 0oth ratioe/ an/ /o"ino logi3 an/ "erits an/ /e"erits of ea3h logi3?
26. Aiven a 3ir3uit an/ aske/ to tell the output voltages of that 3ir3uit?
27. :ow 3an .ou 3onstru3t 0oth 1*O+ an/ N*O+ on a single su0strate?
28. -hat happens when the gate oxi/e is ver. thin?
29. -hat is setup ti"e an/ hol/ ti"e?
50. -rite a pseu/o 3o/e for sorting the nu"0ers in an arra.?
51. -hat is pipelining an/ how 3an we in3rease throughput using pipelining?
52. Explain a0out stu3k at fault "o/els< s3an /esign< &I+> an/ I!!B testing?
5,. -hat is +1I(E?
52. !ifferen3es 0etween IR+I* an/ +1I(E?
55. !ifferen3es 0etween netlist of :+1I(E an/ +pe3tre?
56. -hat is #1A?
57. !raw the (ross +e3tion of an Inverter? (learl. show all the 3onne3tions 0etween *1 an/ pol.< *1 an/ /iffusion
la.ers et3?
58. !raw the ;a.out of an Inverter?
59. If the 3urrent thru the pol. is 20n an/ the 3onta3t 3an take a "ax 3urrent of 10n how woul/ u over3o"e the
pro0le"?
60. I"ple"ent # $ &'( using (*O+ gates?
61. -orking of a 28stage O1*1?
62. 68> @OR gate?
6,. !ifferen3es 0etween 0lo3king an/ Non80lo3king state"ents in 9erilog?
62. !ifferen3es 0etween +ignals an/ 9aria0les in 9:!;? If the sa"e 3o/e is written using +ignals an/ 9aria0les
what /oes it s.nthesi4e to?
65. !ifferen3es 0etween fun3tions an/ 1ro3e/ures in 9:!;?
66. -hat is 3o"ponent 0in/ing?
67. -hat is pol."orphis"? %('')
68. -hat is hot ele3tron effe3t?
69. !efine threshol/ voltage?
70. #a3tors affe3ting 1ower (onsu"ption on a 3hip?
71. Explain (lo3k +kew?
72. -h. /o we use a (lo3k tree?
7,. Explain the various (apa3itan3es asso3iate/ with a transistor an/ whi3h one of the" is the "ost pro"inent?
72. Explain the 9arious steps in +.nthesis?
75. Explain +I( !esign #low?
76. Explain (usto" !esign #low?
77. -h. is Extra3tion perfor"e/?
78. -hat is ;9+< !R(?
79. -ho provi/es the !R( rules?
80. -hat is vali/ation?
81. -hat is (ross >alk?
82. !ifferent wa.s of i"ple"enting a 3o"parator?
8,. -hat r the pheno"enon whi3h 3o"e into pla. when the /evi3es are s3ale/ to the su08"i3ron lengths?
82. -hat is 3lo3k fee/ through?
85. I"ple"ent an Inverter using a single transistor?
86. -hat is #owler8Nor/hei" >unneling?
87. Insights of a >ri8state inverter?
88. If an=ap $ 0.5< an=ap $ 1< an=ap $ ,< for , inverters /raw the transfer 3hara3teristi3s?
89. !ifferen3es 0etween rra. an/ &ooth *ultipliers?
90. Explain the 3on3ept of a (lo3k !ivi/er (ir3uit? -rite a 9:!; 3o/e for the sa"e?
91. -hi3h gate is nor"all. preferre/ while i"ple"enting 3ir3uits using (*O+ logi3< NN! or NOR? -h.?
92. Insights of a >ri8+tate Inverter?
9,. &asi3 +tuff relate/ to 1erl?
92. :ave .ou stu/ie/ 0uses? -hat t.pes?
95. :ave .ou stu/ie/ pipelining? ;ist the 5 stages of a 5 stage pipeline. ssu"ing 1 3lo3k per stage< what is the
laten3. of an instru3tion in a 5 stage "a3hine? -hat is the throughput of this "a3hine ?
96. :ow "an. 0it 3o"0inations are there in a 0.te?
97. #or a single 3o"puter pro3essor 3o"puter s.ste"< what is the purpose of a pro3essor 3a3he an/ /es3ri0e its
operation?
98. Explain the operation 3onsi/ering a two8pro3essor 3o"puter s.ste" with a 3a3he for ea3h pro3essor.
99. -hat are the "ain issues asso3iate/ with "ultipro3essor 3a3hes an/ how "ight .ou solve the"?
100. Explain the /ifferen3e 0etween write through an/ write 0a3k 3a3he.
101. re .ou fa"iliar with the ter" *E+I?
102. re .ou fa"iliar with the ter" snooping?
10,. !es3ri0e a finite state "a3hine that will /ete3t three 3onse3utive 3oin tosses %of one 3oin) that results in hea/s.
102. In what 3ases /o .ou nee/ to /ou0le 3lo3k a signal 0efore presenting it to a s.n3hronous state "a3hine?
105. Cou have a /river that /rives a long signal D 3onne3ts to an input /evi3e. t the input /evi3e there is either
overshoot< un/ershoot or signal threshol/ violations< what 3an 0e /one to 3orre3t this pro0le"?
106. -hat are the total nu"0er of lines written 0. .ou in (=(''? -hat is the "ost 3o"pli3ate/=valua0le progra"
written in (=(''?
107. -hat 3o"piler was use/?
108. -hat is the /ifferen3e 0etween $ an/ $$ in (?
109. re .ou fa"iliar with 9:!; an/=or 9erilog?
110. -hat t.pes of (*O+ "e"ories have .ou /esigne/? -hat were their si4e? +pee/?
111. -hat work have .ou /one on full 3hip (lo3k an/ 1ower /istri0ution? -hat pro3ess te3hnolog. an/ 0u/gets
were use/?
112. -hat t.pes of I=O have .ou /esigne/? -hat were their si4e? +pee/? (onfiguration? 9oltage reEuire"ents?
11,. 1ro3ess te3hnolog.? -hat pa3kage was use/ an/ how /i/ .ou "o/el the pa3kage=s.ste"? -hat parasiti3 effe3ts
were 3onsi/ere/?
112. -hat t.pes of high spee/ (*O+ 3ir3uits have .ou /esigne/?
115. -hat transistor level /esign tools are .ou profi3ient with? -hat t.pes of /esigns were the. use/ on?
116. -hat pro/u3ts have .ou /esigne/ whi3h have entere/ high volu"e pro/u3tion?
117. -hat was .our role in the sili3on evaluation=pro/u3t ra"p? -hat tools /i/ .ou use?
118. If not into pro/u3tion< how far /i/ .ou follow the /esign an/ wh. /i/ not .ou see it into pro/u3tion?